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authorAdrian Betschart <adrian.betschart@cinemaone.ch>2026-09-11 17:13:14 +0200
committerAlex Deucher <alexander.deucher@amd.com>2026-10-01 17:18:05 -0400
commit106b4a2a78b2a2f14885604891957b84bba502db (patch)
tree5d40eef2428fb1a4791ab46a4b19091a5910eac2 /drivers/base/regmap/regmap-fsi.c
downloadlinux-stable-106b4a2a78b2a2f14885604891957b84bba502db.tar.gz
linux-stable-106b4a2a78b2a2f14885604891957b84bba502db.zip
drm/amd/display: Try RGB before YCbCr 4:4:4 in stream validationgrafted
amdgpu_dm_create_validate_stream_for_sink() walks encoding_order[] and uses the first encoding that validates. YCbCr 4:4:4 is listed before RGB, so an HDMI sink that advertises 4:4:4 gets YCbCr 4:4:4 whenever the "color format" property is left at AUTO, even though RGB fits the same link. That contradicts the documented AUTO behaviour for HDMI in enum drm_connector_color_format (RGB, falling back to YCbCr 4:2:0 only when the bandwidth is not available or the mode is 4:2:0-only), which the amdgpu implementation of the property also describes. It also leaves the "Broadcast RGB" property without effect on such sinks, since the quantization range it selects only applies to RGB output. Try RGB first. The mask still holds every encoding the sink supports, so a mode that cannot carry RGB falls back exactly as before. For reference, v7.2 picked RGB here unless YCbCr 4:4:4 was forced through debugfs, while earlier kernels picked YCbCr 4:4:4 for any HDMI sink that advertised it. Fixes: 0b0ff65d3ca1 ("drm/amd/display: Refactor stream validation") Suggested-by: Adolfo Rodrigues <adolfotregosa@gmail.com> Assisted-by: Claude Code:claude-fable-5-1 Signed-off-by: Adrian Betschart <adrian.betschart@cinemaone.ch> Reviewed-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Adolfo Rodrigues <adolfotregosa@gmail.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 7de432bc753133764dc40d37f9388da56de251e7)
Diffstat (limited to 'drivers/base/regmap/regmap-fsi.c')
-rw-r--r--drivers/base/regmap/regmap-fsi.c231
1 files changed, 231 insertions, 0 deletions
diff --git a/drivers/base/regmap/regmap-fsi.c b/drivers/base/regmap/regmap-fsi.c
new file mode 100644
index 000000000..3d2f3cb31
--- /dev/null
+++ b/drivers/base/regmap/regmap-fsi.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Register map access API - FSI support
+//
+// Copyright 2022 IBM Corp
+//
+// Author: Eddie James <eajames@linux.ibm.com>
+
+#include <linux/fsi.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#include "internal.h"
+
+static int regmap_fsi32_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ u32 v;
+ int ret;
+
+ ret = fsi_slave_read(context, reg, &v, sizeof(v));
+ if (ret)
+ return ret;
+
+ *val = v;
+ return 0;
+}
+
+static int regmap_fsi32_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ u32 v = val;
+
+ return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi32 = {
+ .reg_write = regmap_fsi32_reg_write,
+ .reg_read = regmap_fsi32_reg_read,
+};
+
+static int regmap_fsi32le_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ __be32 v;
+ int ret;
+
+ ret = fsi_slave_read(context, reg, &v, sizeof(v));
+ if (ret)
+ return ret;
+
+ *val = be32_to_cpu(v);
+ return 0;
+}
+
+static int regmap_fsi32le_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ __be32 v = cpu_to_be32(val);
+
+ return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi32le = {
+ .reg_write = regmap_fsi32le_reg_write,
+ .reg_read = regmap_fsi32le_reg_read,
+};
+
+static int regmap_fsi16_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ u16 v;
+ int ret;
+
+ ret = fsi_slave_read(context, reg, &v, sizeof(v));
+ if (ret)
+ return ret;
+
+ *val = v;
+ return 0;
+}
+
+static int regmap_fsi16_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ u16 v;
+
+ if (val > 0xffff)
+ return -EINVAL;
+
+ v = val;
+ return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi16 = {
+ .reg_write = regmap_fsi16_reg_write,
+ .reg_read = regmap_fsi16_reg_read,
+};
+
+static int regmap_fsi16le_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ __be16 v;
+ int ret;
+
+ ret = fsi_slave_read(context, reg, &v, sizeof(v));
+ if (ret)
+ return ret;
+
+ *val = be16_to_cpu(v);
+ return 0;
+}
+
+static int regmap_fsi16le_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ __be16 v;
+
+ if (val > 0xffff)
+ return -EINVAL;
+
+ v = cpu_to_be16(val);
+ return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi16le = {
+ .reg_write = regmap_fsi16le_reg_write,
+ .reg_read = regmap_fsi16le_reg_read,
+};
+
+static int regmap_fsi8_reg_read(void *context, unsigned int reg, unsigned int *val)
+{
+ u8 v;
+ int ret;
+
+ ret = fsi_slave_read(context, reg, &v, sizeof(v));
+ if (ret)
+ return ret;
+
+ *val = v;
+ return 0;
+}
+
+static int regmap_fsi8_reg_write(void *context, unsigned int reg, unsigned int val)
+{
+ u8 v;
+
+ if (val > 0xff)
+ return -EINVAL;
+
+ v = val;
+ return fsi_slave_write(context, reg, &v, sizeof(v));
+}
+
+static const struct regmap_bus regmap_fsi8 = {
+ .reg_write = regmap_fsi8_reg_write,
+ .reg_read = regmap_fsi8_reg_read,
+};
+
+static const struct regmap_bus *regmap_get_fsi_bus(struct fsi_device *fsi_dev,
+ const struct regmap_config *config)
+{
+ const struct regmap_bus *bus = NULL;
+
+ if (config->reg_bits == 8 || config->reg_bits == 16 || config->reg_bits == 32) {
+ switch (config->val_bits) {
+ case 8:
+ bus = &regmap_fsi8;
+ break;
+ case 16:
+ switch (regmap_get_val_endian(&fsi_dev->dev, NULL, config)) {
+ case REGMAP_ENDIAN_LITTLE:
+#ifdef __LITTLE_ENDIAN
+ case REGMAP_ENDIAN_NATIVE:
+#endif
+ bus = &regmap_fsi16le;
+ break;
+ case REGMAP_ENDIAN_DEFAULT:
+ case REGMAP_ENDIAN_BIG:
+#ifdef __BIG_ENDIAN
+ case REGMAP_ENDIAN_NATIVE:
+#endif
+ bus = &regmap_fsi16;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 32:
+ switch (regmap_get_val_endian(&fsi_dev->dev, NULL, config)) {
+ case REGMAP_ENDIAN_LITTLE:
+#ifdef __LITTLE_ENDIAN
+ case REGMAP_ENDIAN_NATIVE:
+#endif
+ bus = &regmap_fsi32le;
+ break;
+ case REGMAP_ENDIAN_DEFAULT:
+ case REGMAP_ENDIAN_BIG:
+#ifdef __BIG_ENDIAN
+ case REGMAP_ENDIAN_NATIVE:
+#endif
+ bus = &regmap_fsi32;
+ break;
+ default:
+ break;
+ }
+ break;
+ }
+ }
+
+ return bus ?: ERR_PTR(-EOPNOTSUPP);
+}
+
+struct regmap *__regmap_init_fsi(struct fsi_device *fsi_dev, const struct regmap_config *config,
+ struct lock_class_key *lock_key, const char *lock_name)
+{
+ const struct regmap_bus *bus = regmap_get_fsi_bus(fsi_dev, config);
+
+ if (IS_ERR(bus))
+ return ERR_CAST(bus);
+
+ return __regmap_init(&fsi_dev->dev, bus, fsi_dev->slave, config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__regmap_init_fsi);
+
+struct regmap *__devm_regmap_init_fsi(struct fsi_device *fsi_dev,
+ const struct regmap_config *config,
+ struct lock_class_key *lock_key, const char *lock_name)
+{
+ const struct regmap_bus *bus = regmap_get_fsi_bus(fsi_dev, config);
+
+ if (IS_ERR(bus))
+ return ERR_CAST(bus);
+
+ return __devm_regmap_init(&fsi_dev->dev, bus, fsi_dev->slave, config, lock_key, lock_name);
+}
+EXPORT_SYMBOL_GPL(__devm_regmap_init_fsi);
+
+MODULE_LICENSE("GPL");