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| author | Andi Shyti <andi.shyti@linux.intel.com> | 2026-08-22 14:19:12 +0200 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2026-08-22 14:19:34 +0200 |
| commit | d576a9561a1c80ae593539fb0ce0743d66825ac2 (patch) | |
| tree | 68f6de7e06b350afa42edeea2f7f33f086014597 /arch/powerpc/sysdev/ipic.h | |
| download | linux-stable-d576a9561a1c80ae593539fb0ce0743d66825ac2.tar.gz linux-stable-d576a9561a1c80ae593539fb0ce0743d66825ac2.zip | |
Merge tag 'rust-i2c-for-7.3' into i2c/i2cgrafted
i2c: rust: mark I2cAdapter methods as inline
A single cleanup for the Rust I2C abstractions, targeting 7.3.
`I2cAdapter::get`, `inc_ref`, and `dec_ref` are trivial wrappers around
`i2c_get_adapter`/`i2c_put_adapter` and were showing up as their own
symbols in the build. Mark them `#[inline]` so they get folded into
their callers instead.
Signed-off-by: Igor Korotin <igor.korotin@linux.dev>
* tag 'rust-i2c-for-7.3':
i2c: rust: mark I2cAdapter methods as inline
Diffstat (limited to 'arch/powerpc/sysdev/ipic.h')
| -rw-r--r-- | arch/powerpc/sysdev/ipic.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h new file mode 100644 index 000000000..45ab61406 --- /dev/null +++ b/arch/powerpc/sysdev/ipic.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * IPIC private definitions and structure. + * + * Maintainer: Kumar Gala <galak@kernel.crashing.org> + * + * Copyright 2005 Freescale Semiconductor, Inc + */ +#ifndef __IPIC_H__ +#define __IPIC_H__ + +#include <asm/ipic.h> + +#define NR_IPIC_INTS 128 + +/* External IRQS */ +#define IPIC_IRQ_EXT0 48 +#define IPIC_IRQ_EXT1 17 +#define IPIC_IRQ_EXT7 23 + +/* Default Priority Registers */ +#define IPIC_PRIORITY_DEFAULT 0x05309770 + +/* System Global Interrupt Configuration Register */ +#define SICFR_IPSA 0x00010000 +#define SICFR_IPSB 0x00020000 +#define SICFR_IPSC 0x00040000 +#define SICFR_IPSD 0x00080000 +#define SICFR_MPSA 0x00200000 +#define SICFR_MPSB 0x00400000 + +/* System External Interrupt Mask Register */ +#define SEMSR_SIRQ0 0x00008000 + +/* System Error Control Register */ +#define SERCR_MCPR 0x00000001 + +struct ipic { + volatile u32 __iomem *regs; + + /* The remapper for this IPIC */ + struct irq_domain *irqhost; +}; + +struct ipic_info { + u8 ack; /* pending register offset from base if the irq + supports ack operation */ + u8 mask; /* mask register offset from base */ + u8 prio; /* priority register offset from base */ + u8 force; /* force register offset from base */ + u8 bit; /* register bit position (as per doc) + bit mask = 1 << (31 - bit) */ + u8 prio_mask; /* priority mask value */ +}; + +#endif /* __IPIC_H__ */ |
