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authorLinus Torvalds <torvalds@linux-foundation.org>2026-08-24 08:46:03 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2026-08-24 08:46:03 -0700
commitcf9610f9116d55c5a66ef9f1faecacabd93a9322 (patch)
tree757a3d280760c654767631cab5ad8af2d86d1848 /arch/mips/power
downloadlinux-stable-cf9610f9116d55c5a66ef9f1faecacabd93a9322.tar.gz
linux-stable-cf9610f9116d55c5a66ef9f1faecacabd93a9322.zip
Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlgrafted
Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...
Diffstat (limited to 'arch/mips/power')
-rw-r--r--arch/mips/power/Makefile2
-rw-r--r--arch/mips/power/cpu.c43
-rw-r--r--arch/mips/power/hibernate.c12
-rw-r--r--arch/mips/power/hibernate_asm.S60
4 files changed, 117 insertions, 0 deletions
diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile
new file mode 100644
index 000000000..14b7d9ee6
--- /dev/null
+++ b/arch/mips/power/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o hibernate_asm.o
diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
new file mode 100644
index 000000000..d8ef7778e
--- /dev/null
+++ b/arch/mips/power/cpu.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Suspend support specific for mips.
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Hu Hongbing <huhb@lemote.com>
+ * Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+#include <linux/suspend.h>
+#include <asm/sections.h>
+#include <asm/fpu.h>
+#include <asm/dsp.h>
+
+static u32 saved_status;
+struct pt_regs saved_regs;
+
+void save_processor_state(void)
+{
+ saved_status = read_c0_status();
+
+ if (is_fpu_owner())
+ save_fp(current);
+
+ save_dsp(current);
+}
+
+void restore_processor_state(void)
+{
+ write_c0_status(saved_status);
+
+ if (is_fpu_owner())
+ restore_fp(current);
+
+ restore_dsp(current);
+}
+
+int pfn_is_nosave(unsigned long pfn)
+{
+ unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin));
+ unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end));
+
+ return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
+}
diff --git a/arch/mips/power/hibernate.c b/arch/mips/power/hibernate.c
new file mode 100644
index 000000000..192879e76
--- /dev/null
+++ b/arch/mips/power/hibernate.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/suspend.h>
+#include <asm/tlbflush.h>
+
+extern int restore_image(void);
+
+int swsusp_arch_resume(void)
+{
+ /* Avoid TLB mismatch during and after kernel resume */
+ local_flush_tlb_all();
+ return restore_image();
+}
diff --git a/arch/mips/power/hibernate_asm.S b/arch/mips/power/hibernate_asm.S
new file mode 100644
index 000000000..e62538734
--- /dev/null
+++ b/arch/mips/power/hibernate_asm.S
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Hibernation support specific for mips - temporary page tables
+ *
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Hu Hongbing <huhb@lemote.com>
+ * Wu Zhangjin <wuzhangjin@gmail.com>
+ */
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/asm.h>
+
+.text
+LEAF(swsusp_arch_suspend)
+ PTR_LA t0, saved_regs
+ PTR_S ra, PT_R31(t0)
+ PTR_S sp, PT_R29(t0)
+ PTR_S fp, PT_R30(t0)
+ PTR_S gp, PT_R28(t0)
+ PTR_S s0, PT_R16(t0)
+ PTR_S s1, PT_R17(t0)
+ PTR_S s2, PT_R18(t0)
+ PTR_S s3, PT_R19(t0)
+ PTR_S s4, PT_R20(t0)
+ PTR_S s5, PT_R21(t0)
+ PTR_S s6, PT_R22(t0)
+ PTR_S s7, PT_R23(t0)
+ j swsusp_save
+END(swsusp_arch_suspend)
+
+LEAF(restore_image)
+ PTR_L t0, restore_pblist
+0:
+ PTR_L t1, PBE_ADDRESS(t0) /* source */
+ PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
+ PTR_ADDU t3, t1, _PAGE_SIZE
+1:
+ REG_L t8, (t1)
+ REG_S t8, (t2)
+ PTR_ADDIU t1, t1, SZREG
+ PTR_ADDIU t2, t2, SZREG
+ bne t1, t3, 1b
+ PTR_L t0, PBE_NEXT(t0)
+ bnez t0, 0b
+ PTR_LA t0, saved_regs
+ PTR_L ra, PT_R31(t0)
+ PTR_L sp, PT_R29(t0)
+ PTR_L fp, PT_R30(t0)
+ PTR_L gp, PT_R28(t0)
+ PTR_L s0, PT_R16(t0)
+ PTR_L s1, PT_R17(t0)
+ PTR_L s2, PT_R18(t0)
+ PTR_L s3, PT_R19(t0)
+ PTR_L s4, PT_R20(t0)
+ PTR_L s5, PT_R21(t0)
+ PTR_L s6, PT_R22(t0)
+ PTR_L s7, PT_R23(t0)
+ PTR_LI v0, 0x0
+ jr ra
+END(restore_image)