perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rspgrafted

DMR introduces Offmodule Response events in place of the legacy
Offcore Response events, but it still exposes the inherited
offcore_rsp PMU attribute for programming the corresponding MSR data.

Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface
matches the underlying event name and avoids user & tooling confusion.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260917015234.981153-12-dapeng1.mi@linux.intel.com

1 files changed, 41 insertions, 0 deletions

diff --git a/arch/mips/cobalt/time.c b/arch/mips/cobalt/time.c
new file mode 100644
index 000000000..1b6fa6649
--- /dev/null
+++ b/arch/mips/cobalt/time.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  Cobalt time initialization.
+ *
+ *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ */
+#include <linux/i8253.h>
+#include <linux/init.h>
+
+#include <asm/gt64120.h>
+#include <asm/time.h>
+
+#define GT641XX_BASE_CLOCK	50000000	/* 50MHz */
+
+void __init plat_time_init(void)
+{
+	u32 start, end;
+	int i = HZ / 10;
+
+	setup_pit_timer();
+
+	gt641xx_set_base_clock(GT641XX_BASE_CLOCK);
+
+	/*
+	 * MIPS counter frequency is measured during a 100msec interval
+	 * using GT64111 timer0.
+	 */
+	while (!gt641xx_timer0_state())
+		;
+
+	start = read_c0_count();
+
+	while (i--)
+		while (!gt641xx_timer0_state())
+			;
+
+	end = read_c0_count();
+
+	mips_hpt_frequency = (end - start) * 10;
+	printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency);
+}