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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-08-24 08:46:03 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-08-24 08:46:03 -0700 |
| commit | cf9610f9116d55c5a66ef9f1faecacabd93a9322 (patch) | |
| tree | 757a3d280760c654767631cab5ad8af2d86d1848 /arch/arm64/tools/cpucaps | |
| download | linux-stable-cf9610f9116d55c5a66ef9f1faecacabd93a9322.tar.gz linux-stable-cf9610f9116d55c5a66ef9f1faecacabd93a9322.zip | |
Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlgrafted
Pull pin control updates from Linus Walleij:
"Core changes:
- Use the non-blocking mux_state_try_select() in the generic MUX pin
control back-end
- Free pin maps on pinctrl_generic_to_map() failure in the core
helpers
New hardware pin control:
- Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC
(this is for the low power audio, LPASS = Low Power Audio SubSystem
portions)
- Upboard support on top of the Intel pin controller
- Apple T6030 and T6031 support (just compatible strings)
- Samsung Exynos 8855 SoC
- Mediatek MT6858 SoC
- Rockchip RK3308B and RV1106 SoCs
- Airoha EN7523 and AN7563 SoCs
Improvements:
- Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable
- Qualcomm improvements on top of the Qualcomm PDC (power domain
controller) irqchip improvements from tglx:s tree
- Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups
- The NPCM8xx driver has been put into shape fixing many pin and
group definitions
- Some non-urgent Tegra 264 pin assignments are fixed up
- Some non-urgent fixups to Airoha AN7581 and AN7583 registers and
pin assignments, missing features etc"
* tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits)
dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema
pinctrl: meson: sync some modify from A4
pinctrl: meson: a4: Add input enable pin configuration
pinctrl: realtek: rtd1625: remove unused group name spdif_sel
pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13
dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema
Revert "Merge branch 'ib-rsk7204' into devel"
pinctrl: rockchip: Add RV1106 pinctrl support
dt-bindings: pinctrl: rockchip: Add RV1106 compatible
pinctrl: rockchip: Decode drive strength in the get function
pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable
pinctrl: airoha: add support of an7563 SoC
dt-bindings: pinctrl: airoha: add support of an7563 pin controller
pinctrl: airoha: try to find chip scu node by phandle first
pinctrl: airoha: add support of en7523 SoC
dt-bindings: pinctrl: airoha: add support of en7523 pin controller
pinctrl: airoha: an7583: add support for olt pinmux
pinctrl: airoha: an7583: add support for pon_alt pinmux
pinctrl: airoha: an7583: add support for npu_uart pinmux
dt-bindings: pinctrl: airoha: an7583: add missed features
...
Diffstat (limited to 'arch/arm64/tools/cpucaps')
| -rw-r--r-- | arch/arm64/tools/cpucaps | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps new file mode 100644 index 000000000..0ee42b0cc --- /dev/null +++ b/arch/arm64/tools/cpucaps @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Internal CPU capabilities constants + +ALWAYS_BOOT +ALWAYS_SYSTEM +BTI +# Unreliable: use system_supports_32bit_el0() instead. +HAS_32BIT_EL0_DO_NOT_USE +HAS_32BIT_EL1 +HAS_ADDRESS_AUTH +HAS_ADDRESS_AUTH_ARCH_QARMA3 +HAS_ADDRESS_AUTH_ARCH_QARMA5 +HAS_ADDRESS_AUTH_IMP_DEF +HAS_AMU_EXTN +HAS_ARMv8_4_TTL +HAS_BBML3 +HAS_CACHE_DIC +HAS_CACHE_IDC +HAS_CNP +HAS_CRC32 +HAS_DCPODP +HAS_DCPOP +HAS_DIT +HAS_E0PD +HAS_ECV +HAS_ECV_CNTPOFF +HAS_EPAN +HAS_EVT +HAS_FPMR +HAS_FGT +HAS_FGT2 +HAS_FPSIMD +HAS_GCS +HAS_GENERIC_AUTH +HAS_GENERIC_AUTH_ARCH_QARMA3 +HAS_GENERIC_AUTH_ARCH_QARMA5 +HAS_GENERIC_AUTH_IMP_DEF +HAS_GICV3_CPUIF +HAS_GICV5_CPUIF +HAS_GICV5_LEGACY +HAS_GIC_PRIO_MASKING +HAS_GIC_PRIO_RELAXED_SYNC +HAS_ICH_HCR_EL2_TDIR +HAS_HCR_NV1 +HAS_HCX +HAS_LDAPR +HAS_LPA2 +HAS_LSE_ATOMICS +HAS_LS64 +HAS_LS64_V +HAS_LSUI +HAS_MOPS +HAS_NESTED_VIRT +HAS_PAN +HAS_PMUV3 +HAS_S1PIE +HAS_S1POE +HAS_SCTLR2 +HAS_RAS_EXTN +HAS_RASV1P1_EXTN +HAS_RNG +HAS_SB +HAS_STAGE2_FWB +HAS_TCR2 +HAS_TIDCP1 +HAS_TLB_RANGE +HAS_VA52 +HAS_VIRT_HOST_EXTN +HAS_WFXT +HAS_XNX +HAFT +HW_DBM +KVM_HVHE +KVM_PROTECTED_MODE +MISMATCHED_CACHE_TYPE +MPAM +MPAM_HCR +MTE +MTE_ASYMM +MTE_FAR +MTE_STORE_ONLY +SME +SME_FA64 +SME2 +SPECTRE_V2 +SPECTRE_V3A +SPECTRE_V4 +SPECTRE_BHB +SSBS +SVE +UNMAP_KERNEL_AT_EL0 +WORKAROUND_834220 +WORKAROUND_843419 +WORKAROUND_845719 +WORKAROUND_858921 +WORKAROUND_1418040 +WORKAROUND_1463225 +WORKAROUND_1508412 +WORKAROUND_1542419 +WORKAROUND_1742098 +WORKAROUND_1902691 +WORKAROUND_2038923 +WORKAROUND_2064142 +WORKAROUND_2077057 +WORKAROUND_2457168 +WORKAROUND_2645198 +WORKAROUND_2658417 +WORKAROUND_4193714 +WORKAROUND_4311569 +WORKAROUND_AMPERE_AC03_CPU_38 +WORKAROUND_AMPERE_AC04_CPU_23 +WORKAROUND_TRBE_OVERWRITE_FILL_MODE +WORKAROUND_TSB_FLUSH_FAILURE +WORKAROUND_TRBE_WRITE_OUT_OF_RANGE +WORKAROUND_CAVIUM_23154 +WORKAROUND_CAVIUM_27456 +WORKAROUND_CAVIUM_30115 +WORKAROUND_CAVIUM_TX2_219_PRFM +WORKAROUND_CAVIUM_TX2_219_TVM +WORKAROUND_CLEAN_CACHE +WORKAROUND_DEVICE_LOAD_ACQUIRE +WORKAROUND_DISABLE_CNP +WORKAROUND_NVIDIA_OLYMPUS_1027 +WORKAROUND_PMUV3_IMPDEF_TRAPS +WORKAROUND_QCOM_FALKOR_E1003 +WORKAROUND_QCOM_ORYON_CNTVOFF +WORKAROUND_REPEAT_TLBI_SYNC +WORKAROUND_SPECULATIVE_AT +WORKAROUND_SPECULATIVE_SSBS +WORKAROUND_SPECULATIVE_UNPRIV_LOAD |
