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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2026-09-11 09:40:14 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-09-13 16:05:23 +0530 |
| commit | de7f29a1fe1dc2864d8a47f8c39d508442cae167 (patch) | |
| tree | bf3286f48dfa67821868a864fc8ed1f2397344fd | |
| parent | 48e97c59a49c9e90270f5e3d221db253b76de5da (diff) | |
| download | linux-stable-de7f29a1fe1dc2864d8a47f8c39d508442cae167.tar.gz linux-stable-de7f29a1fe1dc2864d8a47f8c39d508442cae167.zip | |
phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow
When trying to calculate a PLL rate for target display resolutions
above 2560x1440, 24bpp, 30Hz, the pixel clock value will be more
than 32-bits long but the division to finally calculate the digital
clock divider is being done with div_u64(), which expects a 32bit
unsigned divisor.
Fix the overflow by using div64_u64() instead.
Fixes: 9d9ff3d2a4a5 ("phy: mediatek: hdmi: mt8195: fix wrong pll calculus")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20260911074015.9994-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index 1426a2db9..e6ee8e080 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -290,7 +290,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, posdiv2 = 1; /* Digital clk divider, max /32 */ - digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); + digital_div = div64_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL; |