/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (C) 2025 Mobileye Vision Technologies Ltd.
 */

#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H
#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ7H_CLK_H

/* ACC0 and ACC1 OLBs PLL and dividers */
#define EQ7HC_ACC_PLL_VMP	0
#define EQ7HC_ACC_PLL_MPC	1
#define EQ7HC_ACC_PLL_PMA	2
#define EQ7HC_ACC_PLL_NOC	3
#define EQ7HC_ACC_DIV_PMA	4
#define EQ7HC_ACC_DIV_NCORE	5
#define EQ7HC_ACC_DIV_CFG	6

/* DDR0 and DDR1 OLBs PLL and dividers */
#define EQ7HC_DDR_PLL		0
#define EQ7HC_DDR_DIV_APB	1
#define EQ7HC_DDR_DIV_PLLREF	2
#define EQ7HC_DDR_DIV_DFI	3

/* east OLB PLL and dividers */
#define EQ7HC_EAST_PLL_106P6		0
#define EQ7HC_EAST_DIV_REF_106P6	1
#define EQ7HC_EAST_PLL_NOC		2
#define EQ7HC_EAST_PLL_ISP		3
#define EQ7HC_EAST_PLL_VEU		4
#define EQ7HC_EAST_DIV_REF_DDR_PHY	5
#define EQ7HC_EAST_DIV_CORE		6
#define EQ7HC_EAST_DIV_CORE_MBIST	7
#define EQ7HC_EAST_DIV_ISRAM_MBIST	8
#define EQ7HC_EAST_DIV_CFG		9
#define EQ7HC_EAST_DIV_VEU_CORE		10
#define EQ7HC_EAST_DIV_VEU_MBIST	11
#define EQ7HC_EAST_DIV_VEU_OCP		12
#define EQ7HC_EAST_DIV_LBITS		13
#define EQ7HC_EAST_DIV_ISP0_CORE	14

/* MIPS0, MIPS1 and MIPS2 OLBs PLL and dividers */
#define EQ7HC_MIPS_PLL_CPU	0
#define EQ7HC_MIPS_DIV_CM	1

/* periph east OLB PLL and dividers */
#define EQ7HC_PERIPH_EAST_PLL_PER	0
#define EQ7HC_PERIPH_EAST_DIV_PER	1

/* periph west OLB PLL and dividers */
#define EQ7HC_PERIPH_WEST_PLL_PER	0
#define EQ7HC_PERIPH_WEST_PLL_I2S	1
#define EQ7HC_PERIPH_WEST_DIV_PER	2
#define EQ7HC_PERIPH_WEST_DIV_I2S	3

/* south OLB PLL and dividers */
#define EQ7HC_SOUTH_PLL_100P0		0
#define EQ7HC_SOUTH_DIV_REF_100P0	1
#define EQ7HC_SOUTH_PLL_XSPI		2
#define EQ7HC_SOUTH_PLL_VDIO		3
#define EQ7HC_SOUTH_PLL_PER		4
#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS	5
#define EQ7HC_SOUTH_DIV_PMA_CMN_REF	6
#define EQ7HC_SOUTH_DIV_REF_UFS		7
#define EQ7HC_SOUTH_DIV_XSPI_SYS	8
#define EQ7HC_SOUTH_DIV_XSPI_MBIST	9
#define EQ7HC_SOUTH_DIV_NOC_S		10
#define EQ7HC_SOUTH_DIV_PCIE_SYS	11
#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBIST	12
#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY	13
#define EQ7HC_SOUTH_DIV_UFS_CORE	14
#define EQ7HC_SOUTH_DIV_UFS_SMS		15
#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS	16
#define EQ7HC_SOUTH_DIV_ETH_SYS		17
#define EQ7HC_SOUTH_DIV_ETH_MBIST	18
#define EQ7HC_SOUTH_DIV_CFG_S		19
#define EQ7HC_SOUTH_DIV_TSU		20
#define EQ7HC_SOUTH_DIV_VDIO		21
#define EQ7HC_SOUTH_DIV_VDIO_CORE	22
#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIST	23
#define EQ7HC_SOUTH_DIV_VDO_CORE_MBIST	24
#define EQ7HC_SOUTH_DIV_VDO_P		25
#define EQ7HC_SOUTH_DIV_VDIO_CFG	26
#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC	27

/* west OLB PLL and dividers */
#define EQ7HC_WEST_PLL_106P6		0
#define EQ7HC_WEST_DIV_REF_106P6	1
#define EQ7HC_WEST_PLL_NOC		2
#define EQ7HC_WEST_PLL_GPU		3
#define EQ7HC_WEST_PLL_SSI		4
#define EQ7HC_WEST_DIV_GPU		5
#define EQ7HC_WEST_DIV_GPU_MBIST	6
#define EQ7HC_WEST_DIV_LBITS		7
#define EQ7HC_WEST_DIV_MIPS_TIMER	8
#define EQ7HC_WEST_DIV_SSI_CORE		9
#define EQ7HC_WEST_DIV_SSI_CORE_MBIST	10
#define EQ7HC_WEST_DIV_SSI_ROM		11
#define EQ7HC_WEST_DIV_SSI_ROM_MBIST	12
#define EQ7HC_WEST_DIV_REF_DDR_PHY	13
#define EQ7HC_WEST_DIV_CORE		14
#define EQ7HC_WEST_DIV_CORE_MBIST	15
#define EQ7HC_WEST_DIV_CFG		16
#define EQ7HC_WEST_DIV_CAU		17
#define EQ7HC_WEST_DIV_CAU_MBIST	18

/* XNN0 and XNN1 OLBs PLL and dividers */
#define EQ7HC_XNN_PLL_XNN0	0
#define EQ7HC_XNN_PLL_XNN1	1
#define EQ7HC_XNN_PLL_XNN2	2
#define EQ7HC_XNN_PLL_CLSTR	3
#define EQ7HC_XNN_DIV_XNN0	4
#define EQ7HC_XNN_DIV_XNN1	5
#define EQ7HC_XNN_DIV_XNN2	6
#define EQ7HC_XNN_DIV_CLSTR	7
#define EQ7HC_XNN_DIV_I2	8
#define EQ7HC_XNN_DIV_I2_SMS	9
#define EQ7HC_XNN_DIV_CFG	10

#endif