// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
 */

/dts-v1/;
#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include <dt-bindings/clock/sophgo,sg2042-pll.h>
#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
#include <dt-bindings/reset/sophgo,sg2042-reset.h>

#include "sg2042-cpus.dtsi"

/ {
	compatible = "sophgo,sg2042";
	#address-cells = <2>;
	#size-cells = <2>;
	dma-noncoherent;

	distance-map {
		compatible = "numa-distance-map-v1";
		distance-matrix = <0 0 10>,
				  <0 1 15>,
				  <0 2 25>,
				  <0 3 30>,
				  <1 0 15>,
				  <1 1 10>,
				  <1 2 30>,
				  <1 3 25>,
				  <2 0 25>,
				  <2 1 30>,
				  <2 2 10>,
				  <2 3 15>,
				  <3 0 30>,
				  <3 1 25>,
				  <3 2 15>,
				  <3 3 10>;
	};

	aliases {
		serial0 = &uart0;
	};

	cgi_main: oscillator0 {
		compatible = "fixed-clock";
		clock-output-names = "cgi_main";
		#clock-cells = <0>;
	};

	cgi_dpll0: oscillator1 {
		compatible = "fixed-clock";
		clock-output-names = "cgi_dpll0";
		#clock-cells = <0>;
	};

	cgi_dpll1: oscillator2 {
		compatible = "fixed-clock";
		clock-output-names = "cgi_dpll1";
		#clock-cells = <0>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&intc>;
		ranges;

		spifmc0: spi@7000180000 {
			compatible = "sophgo,sg2042-spifmc-nor";
			reg = <0x70 0x00180000 0x0 0x1000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_AHB_SF>;
			interrupt-parent = <&intc>;
			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rstgen RST_SF0>;
			status = "disabled";
		};

		spifmc1: spi@7002180000 {
			compatible = "sophgo,sg2042-spifmc-nor";
			reg = <0x70 0x02180000 0x0 0x1000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_AHB_SF>;
			interrupt-parent = <&intc>;
			interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rstgen RST_SF1>;
			status = "disabled";
		};

		i2c0: i2c@7030005000 {
			compatible = "snps,designware-i2c";
			reg = <0x70 0x30005000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_I2C>;
			clock-names = "ref";
			clock-frequency = <100000>;
			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rstgen RST_I2C0>;
			status = "disabled";
		};

		i2c1: i2c@7030006000 {
			compatible = "snps,designware-i2c";
			reg = <0x70 0x30006000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_I2C>;
			clock-names = "ref";
			clock-frequency = <100000>;
			interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rstgen RST_I2C1>;
			status = "disabled";
		};

		i2c2: i2c@7030007000 {
			compatible = "snps,designware-i2c";
			reg = <0x70 0x30007000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_I2C>;
			clock-names = "ref";
			clock-frequency = <100000>;
			interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rstgen RST_I2C2>;
			status = "disabled";
		};

		i2c3: i2c@7030008000 {
			compatible = "snps,designware-i2c";
			reg = <0x70 0x30008000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_I2C>;
			clock-names = "ref";
			clock-frequency = <100000>;
			interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&rstgen RST_I2C3>;
			status = "disabled";
		};

		gpio0: gpio@7030009000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x70 0x30009000 0x0 0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_GPIO>,
				 <&clkgen GATE_CLK_GPIO_DB>;
			clock-names = "bus", "db";

			port0a: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&intc>;
				interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@703000a000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x70 0x3000a000 0x0 0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_GPIO>,
				 <&clkgen GATE_CLK_GPIO_DB>;
			clock-names = "bus", "db";

			port1a: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&intc>;
				interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio2: gpio@703000b000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x70 0x3000b000 0x0 0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clkgen GATE_CLK_APB_GPIO>,
				 <&clkgen GATE_CLK_GPIO_DB>;
			clock-names = "bus", "db";

			port2a: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&intc>;
				interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pwm: pwm@703000c000 {
			compatible = "sophgo,sg2042-pwm";
			reg = <0x70 0x3000c000 0x0 0x20>;
			#pwm-cells = <3>;
			clocks = <&clkgen GATE_CLK_APB_PWM>;
			clock-names = "apb";
			resets = <&rstgen RST_PWM>;
		};

		pllclk: clock-controller@70300100c0 {
			compatible = "sophgo,sg2042-pll";
			reg = <0x70 0x300100c0 0x0 0x40>;
			clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
			clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
			#clock-cells = <1>;
		};

		msi: msi-controller@7030010304 {
			compatible = "sophgo,sg2042-msi";
			reg = <0x70 0x30010304 0x0 0x4>,
			      <0x70 0x30010300 0x0 0x4>;
			reg-names = "clr", "doorbell";
			msi-controller;
			#msi-cells = <0>;
			msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
		};

		rpgate: clock-controller@7030010368 {
			compatible = "sophgo,sg2042-rpgate";
			reg = <0x70 0x30010368 0x0 0x98>;
			clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
			clock-names = "rpgate";
			#clock-cells = <1>;
		};

		pinctrl: pinctrl@7030011000 {
			compatible = "sophgo,sg2042-pinctrl";
			reg = <0x70 0x30011000 0x0 0x1000>;
		};

		clkgen: clock-controller@7030012000 {
			compatible = "sophgo,sg2042-clkgen";
			reg = <0x70 0x30012000 0x0 0x1000>;
			clocks = <&pllclk MPLL_CLK>,
				 <&pllclk FPLL_CLK>,
				 <&pllclk DPLL0_CLK>,
				 <&pllclk DPLL1_CLK>;
			clock-names = "mpll",
				      "fpll",
				      "dpll0",
				      "dpll1";
			#clock-cells = <1>;
		};

		rstgen: reset-controller@7030013000 {
			compatible = "sophgo,sg2042-reset";
			reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
			#reset-cells = <1>;
		};

		uart0: serial@7040000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <500000000>;
			clocks = <&clkgen GATE_CLK_UART_500M>,
				 <&clkgen GATE_CLK_APB_UART>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rstgen RST_UART0>;
			status = "disabled";
		};

		spi0: spi@7040004000 {
			compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
			reg = <0x70 0x40004000 0x00 0x1000>;
			clocks = <&clkgen GATE_CLK_APB_SPI>;
			interrupt-parent = <&intc>;
			interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			num-cs = <2>;
			resets = <&rstgen RST_SPI0>;
			status = "disabled";
		};

		spi1: spi@7040005000 {
			compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
			reg = <0x70 0x40005000 0x00 0x1000>;
			clocks = <&clkgen GATE_CLK_APB_SPI>;
			interrupt-parent = <&intc>;
			interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			num-cs = <2>;
			resets = <&rstgen RST_SPI1>;
			status = "disabled";
		};

		gmac0: ethernet@7040026000 {
			compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
			reg = <0x70 0x40026000 0x0 0x4000>;
			clocks = <&clkgen GATE_CLK_AXI_ETH0>,
				 <&clkgen GATE_CLK_PTP_REF_I_ETH0>,
				 <&clkgen GATE_CLK_TX_ETH0>;
			clock-names = "stmmaceth", "ptp_ref", "tx";
			dma-noncoherent;
			interrupt-parent = <&intc>;
			interrupts = <132 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			resets = <&rstgen RST_ETH0>;
			reset-names = "stmmaceth";
			snps,multicast-filter-bins = <0>;
			snps,perfect-filter-entries = <1>;
			snps,aal;
			snps,tso;
			snps,txpbl = <32>;
			snps,rxpbl = <32>;
			snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
			snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
			snps,axi-config = <&gmac0_stmmac_axi_setup>;
			status = "disabled";

			mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
			};

			gmac0_mtl_rx_setup: rx-queues-config {
				snps,rx-queues-to-use = <8>;
				queue0 {};
				queue1 {};
				queue2 {};
				queue3 {};
				queue4 {};
				queue5 {};
				queue6 {};
				queue7 {};
			};

			gmac0_mtl_tx_setup: tx-queues-config {
				snps,tx-queues-to-use = <8>;
				queue0 {};
				queue1 {};
				queue2 {};
				queue3 {};
				queue4 {};
				queue5 {};
				queue6 {};
				queue7 {};
			};

			gmac0_stmmac_axi_setup: stmmac-axi-config {
				snps,blen = <16 8 4 0 0 0 0>;
				snps,wr_osr_lmt = <1>;
				snps,rd_osr_lmt = <2>;
			};
		};

		emmc: mmc@704002a000 {
			compatible = "sophgo,sg2042-dwcmshc";
			reg = <0x70 0x4002a000 0x0 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkgen GATE_CLK_EMMC_100M>,
				 <&clkgen GATE_CLK_AXI_EMMC>,
				 <&clkgen GATE_CLK_100K_EMMC>;
			clock-names = "core",
				      "bus",
				      "timer";
			status = "disabled";
		};

		sd: mmc@704002b000 {
			compatible = "sophgo,sg2042-dwcmshc";
			reg = <0x70 0x4002b000 0x0 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkgen GATE_CLK_SD_100M>,
				 <&clkgen GATE_CLK_AXI_SD>,
				 <&clkgen GATE_CLK_100K_SD>;
			clock-names = "core",
				      "bus",
				      "timer";
			status = "disabled";
		};

		pcie_rc0: pcie@7060000000 {
			compatible = "sophgo,sg2042-pcie-host";
			device_type = "pci";
			reg = <0x70 0x60000000  0x0 0x00800000>,
			      <0x40 0x00000000  0x0 0x00001000>;
			reg-names = "reg", "cfg";
			linux,pci-domain = <0>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0  0x00000000  0x40 0xc0000000  0x0 0x00400000>,
				 <0x42000000 0x0  0xd0000000  0x40 0xd0000000  0x0 0x10000000>,
				 <0x02000000 0x0  0xe0000000  0x40 0xe0000000  0x0 0x20000000>,
				 <0x43000000 0x42 0x00000000  0x42 0x00000000  0x2 0x00000000>,
				 <0x03000000 0x41 0x00000000  0x41 0x00000000  0x1 0x00000000>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x1f1c>;
			device-id = <0x2042>;
			cdns,no-bar-match-nbits = <48>;
			dma-coherent;
			msi-parent = <&msi>;
			status = "disabled";
		};

		pcie_rc1: pcie@7060800000 {
			compatible = "sophgo,sg2042-pcie-host";
			device_type = "pci";
			reg = <0x70 0x60800000  0x0 0x00800000>,
			      <0x44 0x00000000  0x0 0x00001000>;
			reg-names = "reg", "cfg";
			linux,pci-domain = <1>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0  0x00000000  0x44 0xc0400000  0x0 0x00400000>,
				 <0x42000000 0x0  0xd0000000  0x44 0xd0000000  0x0 0x10000000>,
				 <0x02000000 0x0  0xe0000000  0x44 0xe0000000  0x0 0x20000000>,
				 <0x43000000 0x46 0x00000000  0x46 0x00000000  0x2 0x00000000>,
				 <0x03000000 0x45 0x00000000  0x45 0x00000000  0x1 0x00000000>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x1f1c>;
			device-id = <0x2042>;
			cdns,no-bar-match-nbits = <48>;
			dma-coherent;
			msi-parent = <&msi>;
			status = "disabled";
		};

		pcie_rc2: pcie@7062000000 {
			compatible = "sophgo,sg2042-pcie-host";
			device_type = "pci";
			reg = <0x70 0x62000000  0x0 0x00800000>,
			      <0x48 0x00000000  0x0 0x00001000>;
			reg-names = "reg", "cfg";
			linux,pci-domain = <2>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0  0x00000000  0x48 0xc0800000  0x0 0x00400000>,
				 <0x42000000 0x0  0xd0000000  0x48 0xd0000000  0x0 0x10000000>,
				 <0x02000000 0x0  0xe0000000  0x48 0xe0000000  0x0 0x20000000>,
				 <0x03000000 0x49 0x00000000  0x49 0x00000000  0x1 0x00000000>,
				 <0x43000000 0x4a 0x00000000  0x4a 0x00000000  0x2 0x00000000>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x1f1c>;
			device-id = <0x2042>;
			cdns,no-bar-match-nbits = <48>;
			dma-coherent;
			msi-parent = <&msi>;
			status = "disabled";
		};

		pcie_rc3: pcie@7062800000 {
			compatible = "sophgo,sg2042-pcie-host";
			device_type = "pci";
			reg = <0x70 0x62800000  0x0 0x00800000>,
			      <0x4c 0x00000000  0x0 0x00001000>;
			reg-names = "reg", "cfg";
			linux,pci-domain = <3>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0  0x00000000  0x4c 0xc0c00000  0x0 0x00400000>,
				 <0x42000000 0x0  0xf8000000  0x4c 0xf8000000  0x0 0x04000000>,
				 <0x02000000 0x0  0xfc000000  0x4c 0xfc000000  0x0 0x04000000>,
				 <0x43000000 0x4e 0x00000000  0x4e 0x00000000  0x2 0x00000000>,
				 <0x03000000 0x4d 0x00000000  0x4d 0x00000000  0x1 0x00000000>;
			bus-range = <0x0 0xff>;
			vendor-id = <0x1f1c>;
			device-id = <0x2042>;
			cdns,no-bar-match-nbits = <48>;
			dma-coherent;
			msi-parent = <&msi>;
			status = "disabled";
		};
	};
};