// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 Microchip Technology Inc */

/dts-v1/;

#include "mpfs-icicle-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	aliases {
		ethernet0 = &mac1;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led-1 {
			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_RED>;
			label = "led1";
		};

		led-2 {
			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_RED>;
			label = "led2";
		};

		led-3 {
			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_AMBER>;
			label = "led3";
		};

		led-4 {
			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_AMBER>;
			label = "led4";
		};
	};

	ddrc_cache_lo: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

	ddrc_cache_hi: memory@1040000000 {
		device_type = "memory";
		reg = <0x10 0x40000000 0x0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hss_payload: region@bfc00000 {
			reg = <0x0 0xbfc00000 0x0 0x400000>;
			no-map;
		};
	};
};

&core_pwm0 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";

	power-monitor@10 {
		compatible = "microchip,pac1934";
		reg = <0x10>;

		#address-cells = <1>;
		#size-cells = <0>;

		channel@1 {
			reg = <0x1>;
			shunt-resistor-micro-ohms = <10000>;
			label = "VDDREG";
		};

		channel@2 {
			reg = <0x2>;
			shunt-resistor-micro-ohms = <10000>;
			label = "VDDA25";
		};

		channel@3 {
			reg = <0x3>;
			shunt-resistor-micro-ohms = <10000>;
			label = "VDD25";
		};

		channel@4 {
			reg = <0x4>;
			shunt-resistor-micro-ohms = <10000>;
			label = "VDDA_REG";
		};
	};
};

&i2c2 {
	status = "okay";
};

&ihc {
	status = "okay";
};

&irqmux {
	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
			<12 &plic 25>, <13 &plic 26>,

			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,

			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
			<94 &plic 53>, <95 &plic 53>;
};

&mac0 {
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	status = "okay";
};

&mac1 {
	phy-mode = "sgmii";
	phy-handle = <&phy1>;
	status = "okay";

	phy1: ethernet-phy@9 {
		reg = <9>;
	};

	phy0: ethernet-phy@8 {
		reg = <8>;
	};
};

&mbox {
	status = "okay";
};

&mmc {
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};

&pcie {
	status = "okay";
};

&qspi {
	status = "okay";
};

&refclk {
	clock-frequency = <125000000>;
};

&refclk_ccc {
	clock-frequency = <50000000>;
};

&rtc {
	status = "okay";
};

&spi0 {
	status = "okay";
};

&spi1 {
	status = "okay";
};

&syscontroller_qspi {
	/*
	 * The flash *is* there, but Icicle kits that have engineering sample
	 * silicon (write?) access to this flash to non-functional. The system
	 * controller itself can actually access it, but the MSS cannot write
	 * an image there. Instantiating a coreQSPI in the fabric & connecting
	 * it to the flash instead should work though. Pre-production or later
	 * silicon does not have this issue.
	 */
	status = "disabled";

	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <1>;
		reg = <0>;
	};
};

&usb {
	status = "okay";
	dr_mode = "host";
};