// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ9574 RDP454 board device tree source
 *
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

/dts-v1/;

#include "ipq9574-rdp-common.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
	compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
};

&qpic_nand {
	status = "okay";
};

&pcie0 {
	pinctrl-0 = <&pcie0_default>;
	pinctrl-names = "default";

	status = "okay";
};

&pcie0_phy {
	status = "okay";
};

&pcie0_port0 {
	reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
	wake-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
};

&pcie2 {
	pinctrl-0 = <&pcie2_default>;
	pinctrl-names = "default";

	status = "okay";
};

&pcie2_phy {
	status = "okay";
};

&pcie2_port0 {
	reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
	wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};

&tlmm {
	pcie0_default: pcie0-default-state {
		clkreq-n-pins {
			pins = "gpio22";
			function = "pcie0_clk";
			drive-strength = <6>;
			bias-pull-up;
		};

		perst-n-pins {
			pins = "gpio23";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-up;
		};

		wake-n-pins {
			pins = "gpio24";
			function = "pcie0_wake";
			drive-strength = <6>;
			bias-pull-up;
		};
	};

	pcie2_default: pcie2-default-state {
		clkreq-n-pins {
			pins = "gpio28";
			function = "pcie2_clk";
			drive-strength = <6>;
			bias-pull-up;
		};

		perst-n-pins {
			pins = "gpio29";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-down;
		};

		wake-n-pins {
			pins = "gpio30";
			function = "pcie2_wake";
			drive-strength = <6>;
			bias-pull-up;
		};
	};
};