// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2025 NXP
 */

#include "imx94.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			cpu_pd_wait: cpu-pd-wait {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010033>;
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
				wakeup-latency-us = <1500>;
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x0>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l0>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l1>;
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x200>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l2>;
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x300>;
			enable-method = "psci";
			#cooling-cells = <2>;
			cpu-idle-states = <&cpu_pd_wait>;
			power-domains = <&scmi_perf IMX94_PERF_A55>;
			power-domain-names = "perf";
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <128>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_cache_l3>;
		};

		l2_cache_l0: l2-cache-l0 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l1: l2-cache-l1 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l2: l2-cache-l2 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l2_cache_l3: l2-cache-l3 {
			compatible = "cache";
			cache-size = <65536>;
			cache-line-size = <64>;
			cache-sets = <256>;
			cache-level = <2>;
			cache-unified;
			next-level-cache = <&l3_cache>;
		};

		l3_cache: l3-cache {
			compatible = "cache";
			cache-size = <1048576>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <3>;
			cache-unified;
		};
	};

	thermal_zones: thermal-zones {
		a55-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&scmi_sensor 1>;

			trips {
				cpu_alert0: trip0 {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <125000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		ana-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&scmi_sensor 0>;

			trips {
				ana_alert: trip0 {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "passive";
				};

				ana_crit0: trip1 {
					temperature = <125000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&ana_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc {
		pcie1: pcie@4c380000 {
			compatible = "fsl,imx943-pcie", "fsl,imx95-pcie";
			reg = <0 0x4c380000 0 0x10000>,
			      <8 0x80100000 0 0xfe00000>,
			      <0 0x4c3e0000 0 0x10000>,
			      <0 0x4c3c0000 0 0x4000>;
			reg-names = "dbi", "config", "atu", "app";
			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
				 <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>,
				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			linux,pci-domain = <3>;
			msi-map = <0x0 &its 0x98 0x1>,
				  <0x100 &its 0x99 0x7>;
			msi-map-mask = <0x1ff>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			num-viewport = <8>;
			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi", "dma";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gic 0 0 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gic 0 0 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gic 0 0 GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scmi_clk IMX94_CLK_HSIO>,
				 <&scmi_clk IMX94_CLK_HSIOPLL>,
				 <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
				 <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
				 <&hsio_blk_ctl 0>;
			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
			assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
					  <&scmi_clk IMX94_CLK_HSIOPLL>,
					  <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
			assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
			assigned-clock-parents = <0>, <0>,
						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
			power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
			fsl,max-link-speed = <3>;
			status = "disabled";

			pcie1_port0: pcie@0 {
				compatible = "pciclass,0604";
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				bus-range = <0x01 0xff>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
			};
		};

		pcie1_ep: pcie-ep@4c380000 {
			compatible = "fsl,imx943-pcie-ep", "fsl,imx95-pcie-ep";
			reg = <0 0x4c380000 0 0x10000>,
			      <0 0x4c3e0000 0 0x1000>,
			      <0 0x4c3a0000 0 0x1000>,
			      <0 0x4c3c0000 0 0x4000>,
			      <0 0x4c3f0000 0 0x10000>,
			      <0xa 0 1 0>;
			reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
			num-lanes = <1>;
			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dma";
			clocks = <&scmi_clk IMX94_CLK_HSIO>,
				 <&scmi_clk IMX94_CLK_HSIOPLL>,
				 <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
				 <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
			assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
					  <&scmi_clk IMX94_CLK_HSIOPLL>,
					  <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
			assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
			assigned-clock-parents = <0>, <0>,
						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
			msi-map = <0x0 &its 0x98 0x1>;
			power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
			status = "disabled";
		};
	};
};