// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2024-2025 NXP */ /dts-v1/; #include "imx943.dtsi" #include #include #define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */ #define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */ #define BRD_SM_CTRL_PCIE1_WAKE 0x8002 /*!< PCAL6416A-5 */ #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6416A-6 */ #define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6416A-7 */ / { compatible = "fsl,imx943-evk", "fsl,imx94"; model = "NXP i.MX943 EVK board"; aliases { ethernet0 = &enetc3; ethernet1 = &enetc1; ethernet2 = &enetc2; i2c2 = &lpi2c3; i2c3 = &lpi2c4; i2c5 = &lpi2c6; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; serial0 = &lpuart1; serial5 = &lpuart6; }; bt_sco_codec: bt-sco-codec { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; }; flexcan2_phy: can-phy0 { compatible = "nxp,tjr1443"; #phy-cells = <0>; enable-gpios = <&pcal6416_i2c6_u50 3 GPIO_ACTIVE_HIGH>; max-bitrate = <8000000>; standby-gpios = <&pcal6416_i2c6_u50 4 GPIO_ACTIVE_LOW>; }; flexcan4_phy: can-phy1 { compatible = "nxp,tjr1443"; #phy-cells = <0>; enable-gpios = <&pcal6416_i2c3_u171 0 GPIO_ACTIVE_HIGH>; max-bitrate = <8000000>; standby-gpios = <&pcal6416_i2c3_u171 1 GPIO_ACTIVE_LOW>; }; chosen { stdout-path = &lpuart1; }; pcie_ref_clk: clock-pcie-ref { compatible = "gpio-gate-clock"; clocks = <&xtal25m>; #clock-cells = <0>; enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>; }; xtal25m: clock-xtal25m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; clock-output-names = "xtal_25MHz"; }; dmic: dmic { compatible = "dmic-codec"; #sound-dai-cells = <0>; }; reg_m2_pwr: regulator-m2-pwr { compatible = "regulator-fixed"; regulator-name = "M.2-power"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&pcal6416_i2c3_u46 2 GPIO_ACTIVE_HIGH>; enable-active-high; /* * M.2 device only can be enabled(W_DISABLE1#) after all Power * Rails reach their minimum operating voltage (PCI Express M.2 * Specification r5.1 3.1.4 Power-up Timing). * Set a delay equal to the max value of Tsettle here. */ startup-delay-us = <5000>; }; reg_slot_pwr: regulator-slot-pwr { compatible = "regulator-fixed"; regulator-name = "PCIe slot-power"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&pcal6416_i2c3_u46 0 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_m2_wlan: regulator-wlan { compatible = "regulator-fixed"; regulator-name = "WLAN_EN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <®_m2_pwr>; gpio = <&pcal6416_i2c3_u46 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; pinctrl-names = "default"; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "VDD_SD2_3V3"; gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_audio_pwr: regulator-wm8962-pwr { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "audio-pwr"; gpio = <&pcal6416_i2c3_u171 12 GPIO_ACTIVE_HIGH>; enable-active-high; }; remoteproc-cm70 { compatible = "fsl,imx94-cm70"; mbox-names = "tx", "rx", "rxdb"; mboxes = <&mu11 0 1 &mu11 1 1 &mu11 3 1>; memory-region = <&cm70_vdev0buffer>, <&cm70_vdev0vring0>, <&cm70_vdev0vring1>, <&cm70_vdev1vring0>, <&cm70_vdev1vring1>, <&cm70_rsc_table>; }; remoteproc-cm71 { compatible = "fsl,imx94-cm71"; mbox-names = "tx", "rx", "rxdb"; mboxes = <&mu13 0 1 &mu13 1 1 &mu13 3 1>; memory-region = <&cm71_vdev0buffer>, <&cm71_vdev0vring0>, <&cm71_vdev0vring1>, <&cm71_vdev1vring0>, <&cm71_vdev1vring1>, <&cm71_rsc_table>; }; remoteproc-cm33s { compatible = "fsl,imx94-cm33s"; mbox-names = "tx", "rx", "rxdb"; mboxes = <&mu15 0 1 &mu15 1 1 &mu15 3 1>; memory-region = <&cm33s_vdev0buffer>, <&cm33s_vdev0vring0>, <&cm33s_vdev0vring1>, <&cm33s_vdev1vring0>, <&cm33s_vdev1vring1>, <&cm33s_rsc_table>; }; reserved-memory { ranges; #address-cells = <2>; #size-cells = <2>; linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0 0x80000000 0 0x7f000000>; reusable; size = <0 0x10000000>; linux,cma-default; }; cm33s_vdev0vring0: vdev0vring0@20800000 { reg = <0 0x20800000 0 0x8000>; no-map; }; cm33s_vdev0vring1: vdev0vring1@20808000 { reg = <0 0x20808000 0 0x8000>; no-map; }; cm33s_vdev1vring0: vdev1vring0@20810000 { reg = <0 0x20810000 0 0x8000>; no-map; }; cm33s_vdev1vring1: vdev1vring1@20818000 { reg = <0 0x20818000 0 0x8000>; no-map; }; cm33s_rsc_table: rsc-table@208a0000 { reg = <0 0x208a0000 0 0x1000>; no-map; }; cm33s_vdev0buffer: vdev0buffer@20820000 { compatible = "shared-dma-pool"; reg = <0 0x20820000 0 0x80000>; no-map; }; cm70_vdev0vring0: vdev0vring0@82000000 { reg = <0 0x82000000 0 0x8000>; no-map; }; cm70_vdev0vring1: vdev0vring1@82008000 { reg = <0 0x82008000 0 0x8000>; no-map; }; cm70_vdev1vring0: vdev1vring0@82010000 { reg = <0 0x82010000 0 0x8000>; no-map; }; cm70_vdev1vring1: vdev1vring1@82018000 { reg = <0 0x82018000 0 0x8000>; no-map; }; cm70_rsc_table: rsc-table@82220000 { reg = <0 0x82220000 0 0x1000>; no-map; }; cm70_vdev0buffer: vdev0buffer@82020000 { compatible = "shared-dma-pool"; reg = <0 0x82020000 0 0x100000>; no-map; }; cm71_vdev0vring0: vdev0vring0@84000000 { reg = <0 0x84000000 0 0x8000>; no-map; }; cm71_vdev0vring1: vdev0vring1@84008000 { reg = <0 0x84008000 0 0x8000>; no-map; }; cm71_vdev1vring0: vdev1vring0@84010000 { reg = <0 0x84010000 0 0x8000>; no-map; }; cm71_vdev1vring1: vdev1vring1@84018000 { reg = <0 0x84018000 0 0x8000>; no-map; }; cm71_rsc_table: rsc-table@84220000 { reg = <0 0x84220000 0 0x1000>; no-map; }; cm71_vdev0buffer: vdev0buffer@84020000 { compatible = "shared-dma-pool"; reg = <0 0x84020000 0 0x100000>; no-map; }; }; sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,bitclock-inversion; simple-audio-card,bitclock-master = <&btcpu>; simple-audio-card,format = "dsp_a"; simple-audio-card,frame-master = <&btcpu>; simple-audio-card,name = "bt-sco-audio"; simple-audio-card,codec { sound-dai = <&bt_sco_codec 1>; }; btcpu: simple-audio-card,cpu { dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; sound-dai = <&sai3>; }; }; sound-micfil { compatible = "fsl,imx-audio-card"; model = "micfil-audio"; pri-dai-link { format = "i2s"; link-name = "micfil hifi"; codec { sound-dai = <&dmic>; }; cpu { sound-dai = <&micfil>; }; }; }; sound-wm8962 { compatible = "fsl,imx-audio-wm8962"; audio-codec = <&wm8962>; audio-cpu = <&sai1>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", "IN3R", "AMIC", "IN1R", "AMIC"; hp-det-gpio = <&pcal6416_i2c3_u48 14 GPIO_ACTIVE_HIGH>; model = "wm8962-audio"; }; usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6416_i2c3_u46 4 GPIO_ACTIVE_LOW>; }; memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; device_type = "memory"; }; }; &enetc1 { clocks = <&scmi_clk IMX94_CLK_MAC4>; clock-names = "ref"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth3>; phy-handle = <ðphy3>; phy-mode = "rgmii-id"; status = "okay"; }; &enetc2 { clocks = <&scmi_clk IMX94_CLK_MAC5>; clock-names = "ref"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth4>; phy-handle = <ðphy4>; phy-mode = "rgmii-id"; status = "okay"; }; &enetc3 { status = "okay"; }; &flexcan2 { phys = <&flexcan2_phy>; pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; status = "okay"; }; &flexcan4 { phys = <&flexcan4_phy>; pinctrl-0 = <&pinctrl_flexcan4>; pinctrl-names = "default"; status = "okay"; }; &lpi2c3 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c3>; pinctrl-names = "default"; status = "okay"; pca9670_i2c3: gpio@23 { compatible = "nxp,pca9670"; reg = <0x23>; #gpio-cells = <2>; gpio-controller; }; ptn5110: tcpc@50 { compatible = "nxp,ptn5110", "tcpci"; reg = <0x50>; interrupt-parent = <&gpio3>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; typec_con: connector { compatible = "usb-c-connector"; label = "USB-C"; power-role = "dual"; data-role = "dual"; try-power-role = "sink"; source-pdos = ; sink-pdos = ; op-sink-microwatt = <0>; self-powered; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; typec_con_hs: endpoint { remote-endpoint = <&usb3_data_hs>; }; }; port@1 { reg = <1>; typec_con_ss: endpoint { remote-endpoint = <&usb3_data_ss>; }; }; }; }; }; pca9548_i2c3: i2c-mux@77 { compatible = "nxp,pca9548"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; }; i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; }; i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; wm8962: codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&scmi_clk IMX94_CLK_SAI1>; AVDD-supply = <®_audio_pwr>; CPVDD-supply = <®_audio_pwr>; DBVDD-supply = <®_audio_pwr>; DCVDD-supply = <®_audio_pwr>; gpio-cfg = < 0x0000 /* 0:Default */ 0x0000 /* 1:Default */ 0x0000 /* 2:FN_DMICCLK */ 0x0000 /* 3:Default */ 0x0000 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; MICVDD-supply = <®_audio_pwr>; PLLVDD-supply = <®_audio_pwr>; SPKVDD1-supply = <®_audio_pwr>; SPKVDD2-supply = <®_audio_pwr>; }; fan_controller: pwm@2f { compatible = "microchip,emc2301", "microchip,emc2305"; reg = <0x2f>; #pwm-cells = <3>; #address-cells = <1>; #size-cells = <0>; fan0: fan@0 { reg = <0x0>; pwms = <&fan_controller 26000 1 PWM_POLARITY_INVERTED>; #cooling-cells = <2>; }; }; ptn5150: tcpc@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; interrupt-parent = <&pcal6408_i2c3_u172>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; status = "disabled"; }; }; i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; pcal6416_i2c3_u46: gpio@20 { compatible = "nxp,pcal6416"; reg = <0x20>; #gpio-cells = <2>; gpio-controller; sd-card-on-hog { gpios = <13 GPIO_ACTIVE_HIGH>; gpio-hog; output-high; }; }; pcal6416_i2c3_u171: gpio@21 { compatible = "nxp,pcal6416"; reg = <0x21>; #gpio-cells = <2>; gpio-controller; audio-pwren-hog { gpios = <12 GPIO_ACTIVE_HIGH>; gpio-hog; output-high; }; mqs-mic-sel-hog { gpios = <11 GPIO_ACTIVE_HIGH>; gpio-hog; output-low; }; }; }; i2c@6 { reg = <6>; #address-cells = <1>; #size-cells = <0>; pcal6416_i2c3_u48: gpio@20 { compatible = "nxp,pcal6416"; reg = <0x20>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio3>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; pinctrl-0 = <&pinctrl_ioexpander_int>; pinctrl-names = "default"; }; }; i2c@7 { reg = <7>; #address-cells = <1>; #size-cells = <0>; pcal6408_i2c3_u172: gpio@20 { compatible = "nxp,pcal6408"; reg = <0x20>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio3>; /* shared int pin with u48 */ interrupts = <13 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; }; }; &lpi2c4 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c4>; pinctrl-names = "default"; status = "okay"; }; &lpi2c6 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c6>; pinctrl-names = "default"; status = "okay"; pca9544_i2c6: i2c-mux@77 { compatible = "nxp,pca9544"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; }; i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; pcal6416_i2c6_u50: gpio@21 { compatible = "nxp,pcal6416"; reg = <0x21>; #gpio-cells = <2>; gpio-controller; }; }; i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; pcal6408_i2c6_u170: gpio@20 { compatible = "nxp,pcal6408"; reg = <0x20>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio4>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; pinctrl-0 = <&pinctrl_ioexpander_int2>; pinctrl-names = "default"; }; }; i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; pcal6416_i2c6_u44: gpio@20 { compatible = "nxp,pcal6416"; reg = <0x20>; #gpio-cells = <2>; gpio-controller; /* pdm selection */ can-pdm-sel-hog { gpios = <12 GPIO_ACTIVE_HIGH>; gpio-hog; output-low; }; sai3-sel-hog { gpios = <11 GPIO_ACTIVE_HIGH>; gpio-hog; output-high; }; /* eMMC IOMUX selection */ sd1-sel-hog { gpios = <0 GPIO_ACTIVE_HIGH>; gpio-hog; output-high; }; /* SD card IOMUX selection */ sd2-sel-hog { gpios = <1 GPIO_ACTIVE_HIGH>; gpio-hog; output-high; }; }; }; }; }; &lpuart1 { pinctrl-0 = <&pinctrl_uart1>; pinctrl-names = "default"; status = "okay"; }; &lpuart6 { /* BT */ pinctrl-0 = <&pinctrl_uart6>; pinctrl-names = "default"; status = "okay"; bluetooth { compatible = "nxp,88w8987-bt"; }; }; &micfil { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL1>, <&scmi_clk IMX94_CLK_AUDIOPLL2>, <&scmi_clk IMX94_CLK_PDM>; assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX94_CLK_AUDIOPLL1>; assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <49152000>; pinctrl-0 = <&pinctrl_pdm>; pinctrl-names = "default"; status = "okay"; }; &mu11 { status = "okay"; }; &mu13 { status = "okay"; }; &mu15 { status = "okay"; }; &netc_blk_ctrl { assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>, <&scmi_clk IMX94_CLK_MAC5>; assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>, <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>; assigned-clock-rates = <250000000>, <250000000>; status = "okay"; }; &netc_emdio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emdio>; status = "okay"; ethphy3: ethernet-phy@6 { reg = <0x6>; realtek,clkout-disable; }; ethphy4: ethernet-phy@7 { reg = <0x7>; realtek,clkout-disable; }; }; &netc_timer0 { status = "okay"; }; &netc_timer1 { status = "okay"; }; &sai1 { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL1>, <&scmi_clk IMX94_CLK_AUDIOPLL2>, <&scmi_clk IMX94_CLK_SAI1>; assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX94_CLK_AUDIOPLL1>; assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; pinctrl-0 = <&pinctrl_sai1>; pinctrl-names = "default"; fsl,sai-mclk-direction-output; status = "okay"; }; &sai3 { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL1>, <&scmi_clk IMX94_CLK_AUDIOPLL2>, <&scmi_clk IMX94_CLK_SAI3>; assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX94_CLK_AUDIOPLL1>; assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; pinctrl-0 = <&pinctrl_sai3>; pinctrl-names = "default"; fsl,sai-mclk-direction-output; status = "okay"; }; &scmi_iomuxc { pinctrl_emdio: emdiogrp { fsl,pins = < IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e >; }; pinctrl_eth3: eth3grp { fsl,pins = < IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x50e IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x50e IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x50e IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x50e IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x51e IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x59e IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x51e IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x59e IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x51e IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x51e IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x51e IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x51e >; }; pinctrl_eth4: eth4grp { fsl,pins = < IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x50e IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x50e IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x50e IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x50e IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x51e IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x59e IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x51e IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x59e IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x51e IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x51e IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x51e IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < IMX94_PAD_GPIO_IO34__CAN2_TX 0x39e IMX94_PAD_GPIO_IO35__CAN2_RX 0x39e >; }; pinctrl_flexcan4: flexcan4grp { fsl,pins = < IMX94_PAD_GPIO_IO36__CAN4_TX 0x39e IMX94_PAD_GPIO_IO37__CAN4_RX 0x39e >; }; pinctrl_ioexpander_int2: ioexpanderint2grp { fsl,pins = < IMX94_PAD_CCM_CLKO4__GPIO4_IO3 0x31e >; }; pinctrl_ioexpander_int: ioexpanderintgrp { fsl,pins = < IMX94_PAD_GPIO_IO45__GPIO3_IO13 0x31e >; }; pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < IMX94_PAD_GPIO_IO16__LPI2C3_SDA 0x40000b9e IMX94_PAD_GPIO_IO17__LPI2C3_SCL 0x40000b9e >; }; pinctrl_lpi2c4: lpi2c4grp { fsl,pins = < IMX94_PAD_GPIO_IO18__LPI2C4_SDA 0x40000b9e IMX94_PAD_GPIO_IO19__LPI2C4_SCL 0x40000b9e >; }; pinctrl_lpi2c6: lpi2c6grp { fsl,pins = < IMX94_PAD_GPIO_IO29__LPI2C6_SDA 0x40000b9e IMX94_PAD_GPIO_IO28__LPI2C6_SCL 0x40000b9e >; }; pinctrl_pcie0: pcie0grp { fsl,pins = < IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x4000031e >; }; pinctrl_pcie1: pcie1grp { fsl,pins = < IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B 0x4000031e >; }; pinctrl_pdm: pdmgrp { fsl,pins = < IMX94_PAD_PDM_CLK__PDM_CLK 0x31e IMX94_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e IMX94_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e >; }; pinctrl_sai1: sai1grp { fsl,pins = < IMX94_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e IMX94_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e IMX94_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e IMX94_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e IMX94_PAD_I2C2_SDA__SAI1_MCLK 0x31e >; }; pinctrl_sai3: sai3grp { fsl,pins = < IMX94_PAD_GPIO_IO42__SAI3_TX_BCLK 0x31e IMX94_PAD_GPIO_IO56__SAI3_TX_SYNC 0x31e IMX94_PAD_GPIO_IO46__SAI3_RX_DATA0 0x31e IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0 0x31e >; }; pinctrl_typec: typecgrp { fsl,pins = < IMX94_PAD_GPIO_IO44__GPIO3_IO12 0x30e >; }; pinctrl_uart1: uart1grp { fsl,pins = < IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e >; }; pinctrl_uart6: uart6grp { fsl,pins = < IMX94_PAD_GPIO_IO04__LPUART6_TX 0x31e IMX94_PAD_GPIO_IO05__LPUART6_RX 0x31e IMX94_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e IMX94_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < IMX94_PAD_SD1_CLK__USDHC1_CLK 0x15fe IMX94_PAD_SD1_CMD__USDHC1_CMD 0x13fe IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < IMX94_PAD_SD2_CLK__USDHC2_CLK 0x15fe IMX94_PAD_SD2_CMD__USDHC2_CMD 0x13fe IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x31e >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp { fsl,pins = < IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < IMX94_PAD_GPIO_IO48__USDHC3_CLK 0x158e /* Need to config the SION for CMD pad, refer to ERR053138 */ IMX94_PAD_GPIO_IO49__USDHC3_CMD 0x4000138e IMX94_PAD_GPIO_IO50__USDHC3_DATA0 0x138e IMX94_PAD_GPIO_IO51__USDHC3_DATA1 0x138e IMX94_PAD_GPIO_IO52__USDHC3_DATA2 0x138e IMX94_PAD_GPIO_IO53__USDHC3_DATA3 0x138e >; }; pinctrl_xspi1: xspi1grp { fsl,pins = < IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe >; }; }; &scmi_misc { nxp,ctrl-ids = ; }; &thermal_zones { a55-thermal { trips { atrip2: trip2 { temperature = <55000>; hysteresis = <2000>; type = "active"; }; atrip3: trip3 { temperature = <65000>; hysteresis = <2000>; type = "active"; }; atrip4: trip4 { temperature = <75000>; hysteresis = <2000>; type = "active"; }; }; cooling-maps { map1 { trip = <&atrip2>; cooling-device = <&fan0 4 6>; }; map2 { trip = <&atrip3>; cooling-device = <&fan0 6 8>; }; map3 { trip = <&atrip4>; cooling-device = <&fan0 8 10>; }; }; }; pf09-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&scmi_sensor 2>; trips { pf09_alert: trip0 { temperature = <140000>; hysteresis = <2000>; type = "passive"; }; pf09_crit: trip1 { temperature = <155000>; hysteresis = <2000>; type = "critical"; }; }; }; pf53soc-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&scmi_sensor 3>; trips { pf5302_alert: trip0 { temperature = <140000>; hysteresis = <2000>; type = "passive"; }; pf5302_crit: trip1 { temperature = <155000>; hysteresis = <2000>; type = "critical"; }; }; }; }; &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; clocks = <&scmi_clk IMX94_CLK_HSIO>, <&scmi_clk IMX94_CLK_HSIOPLL>, <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, <&hsio_blk_ctl 0>, <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; supports-clkreq; status = "okay"; }; &pcie0_port0 { reset-gpios = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; vpcie3v3aux-supply = <®_m2_wlan>; }; &pcie0_ep { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; vpcie-supply = <®_m2_pwr>; status = "disabled"; }; &pcie1 { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; clocks = <&scmi_clk IMX94_CLK_HSIO>, <&scmi_clk IMX94_CLK_HSIOPLL>, <&scmi_clk IMX94_CLK_HSIOPLL_VCO>, <&scmi_clk IMX94_CLK_HSIOPCIEAUX>, <&hsio_blk_ctl 0>, <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; status = "okay"; }; &pcie1_port0 { reset-gpios = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; vpcie3v3aux-supply = <®_slot_pwr>; }; &pcie1_ep { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; vpcie-supply = <®_slot_pwr>; status = "disabled"; }; &usb2 { dr_mode = "otg"; disable-over-current; adp-disable; hnp-disable; srp-disable; samsung,picophy-dc-vol-level-adjust = <10>; status = "okay"; }; &usb3 { dr_mode = "otg"; adp-disable; hnp-disable; srp-disable; usb-role-switch; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; status = "okay"; port { usb3_data_hs: endpoint { remote-endpoint = <&typec_con_hs>; }; }; }; &usb3_phy { orientation-switch; fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; fsl,phy-pcs-tx-swing-full-percent = <100>; fsl,phy-tx-preemp-amp-tune-microamp = <600>; fsl,phy-tx-vboost-level-microvolt = <1156>; fsl,phy-tx-vref-tune-percent = <100>; status = "okay"; port { usb3_data_ss: endpoint { remote-endpoint = <&typec_con_ss>; }; }; }; &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; bus-width = <8>; non-removable; no-sdio; no-sd; status = "okay"; }; &usdhc2 { pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; bus-width = <4>; no-mmc; no-sdio; cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; status = "okay"; }; &usdhc3 { /* * Only enable SDIO2.0 mode as the corresponding GPIO pads are 3.3V, the * max frequency is 50MHz. */ pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3>; pinctrl-names = "default", "sleep"; bus-width = <4>; vmmc-supply = <®_m2_wlan>; mmc-pwrseq = <&usdhc3_pwrseq>; keep-power-in-suspend; non-removable; wakeup-source; status = "disabled"; }; &wdog3 { fsl,ext-reset-output; status = "okay"; }; &xspi1 { pinctrl-0 = <&pinctrl_xspi1>; pinctrl-1 = <&pinctrl_xspi1>; pinctrl-names = "default", "sleep"; status = "okay"; mt35xu512aba: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; reset-gpios = <&pcal6416_i2c6_u50 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; spi-max-frequency = <200000000>; spi-rx-bus-width = <8>; spi-tx-bus-width = <8>; }; };