// SPDX-License-Identifier: GPL-2.0 /* * Samsung Exynos8855 SoC device tree source * * Copyright (C) 2023 Samsung Electronics Co., Ltd. * * Samsung Exynos8855 SoC device nodes are listed in this file. * Exynos8855 based board files can include this file and provide * values for board specific bindings. */ #include / { compatible = "samsung,exynos8855"; #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&gic>; aliases { pinctrl0 = &pinctrl_alive; pinctrl1 = &pinctrl_cmgp; pinctrl2 = &pinctrl_hsi_ufs; pinctrl3 = &pinctrl_peric; pinctrl4 = &pinctrl_pericmmc; pinctrl5 = &pinctrl_usi; }; oscclk: clock-oscclk { compatible = "fixed-clock"; clock-output-names = "oscclk"; #clock-cells = <0>; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; }; cluster1 { core0 { cpu = <&cpu4>; }; core1 { cpu = <&cpu5>; }; core2 { cpu = <&cpu6>; }; }; cluster2 { core0 { cpu = <&cpu7>; }; }; }; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a520"; reg = <0x0>; enable-method = "psci"; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a520"; reg = <0x100>; enable-method = "psci"; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a520"; reg = <0x200>; enable-method = "psci"; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a520"; reg = <0x300>; enable-method = "psci"; }; cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0x400>; enable-method = "psci"; }; cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0x500>; enable-method = "psci"; }; cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0x600>; enable-method = "psci"; }; cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0x700>; enable-method = "psci"; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x20000000>; gic: interrupt-controller@10200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; reg = <0x10200000 0x10000>, <0x10240000 0x140000>; interrupts = ; }; pinctrl_alive: pinctrl@11850000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x11850000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos8855-wakeup-eint", "samsung,exynos7-wakeup-eint"; }; }; pinctrl_cmgp: pinctrl@12030000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x12030000 0x1000>; interrupts = ; }; pinctrl_usi: pinctrl@15030000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x15030000 0x1000>; interrupts = ; }; pinctrl_peric: pinctrl@15440000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x15440000 0x1000>; interrupts = ; }; pinctrl_pericmmc: pinctrl@154f0000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x154f0000 0x1000>; interrupts = ; }; pinctrl_hsi_ufs: pinctrl@17040000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x17040000 0x1000>; interrupts = ; }; }; timer { compatible = "arm,armv8-timer"; /* Hypervisor Virtual Timer interrupt is not wired to GIC */ interrupts = , , , ; }; }; #include "exynos8855-pinctrl.dtsi"