// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/amlogic,t7-pwrc.h>
#include "amlogic-t7-reset.h"
#include <dt-bindings/clock/amlogic,t7-scmi.h>
#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu100>;
				};
				core1 {
					cpu = <&cpu101>;
				};
				core2 {
					cpu = <&cpu102>;
				};
				core3 {
					cpu = <&cpu103>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu100: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
		};

		cpu101: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
		};

		cpu102: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
		};

		cpu103: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			enable-method = "psci";
			d-cache-line-size = <32>;
			d-cache-size = <0x8000>;
			d-cache-sets = <32>;
			i-cache-line-size = <32>;
			i-cache-size = <0x8000>;
			i-cache-sets = <32>;
			next-level-cache = <&l2_cache_l>;
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x0>;
			enable-method = "psci";
			d-cache-line-size = <64>;
			d-cache-size = <0x10000>;
			d-cache-sets = <64>;
			i-cache-line-size = <64>;
			i-cache-size = <0x10000>;
			i-cache-sets = <64>;
			next-level-cache = <&l2_cache_b>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x1>;
			enable-method = "psci";
			d-cache-line-size = <64>;
			d-cache-size = <0x10000>;
			d-cache-sets = <64>;
			i-cache-line-size = <64>;
			i-cache-size = <0x10000>;
			i-cache-sets = <64>;
			next-level-cache = <&l2_cache_b>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x2>;
			enable-method = "psci";
			d-cache-line-size = <64>;
			d-cache-size = <0x10000>;
			d-cache-sets = <64>;
			i-cache-line-size = <64>;
			i-cache-size = <0x10000>;
			i-cache-sets = <64>;
			next-level-cache = <&l2_cache_b>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x3>;
			enable-method = "psci";
			d-cache-line-size = <64>;
			d-cache-size = <0x10000>;
			d-cache-sets = <64>;
			i-cache-line-size = <64>;
			i-cache-size = <0x10000>;
			i-cache-sets = <64>;
			next-level-cache = <&l2_cache_b>;
		};

		l2_cache_l: l2-cache-cluster0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x40000>;  /* L2. 256 KB */
			cache-line-size = <64>;
			cache-sets = <512>;
		};

		l2_cache_b: l2-cache-cluster1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x100000>; /* L2. 1 Mb */
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	sm: secure-monitor {
		compatible = "amlogic,meson-gxbb-sm";

		pwrc: power-controller {
			compatible = "amlogic,t7-pwrc";
			#power-domain-cells = <1>;
		};
	};

	sram@f7042000 {
		compatible = "mmio-sram";
		reg = <0x0 0xf7042000 0x0 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0xf7042000 0x100>;

		scmi_shmem: sram@0 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x100>;
		};
	};

	firmware {
		scmi: scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0x820000c1>;
			shmem = <&scmi_shmem>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@fff01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xfff01000 0 0x1000>,
			      <0x0 0xfff02000 0 0x2000>,
			      <0x0 0xfff04000 0 0x2000>,
			      <0x0 0xfff06000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb4: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x480000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;

			clkc_periphs: clock-controller@0 {
				compatible = "amlogic,t7-peripherals-clkc";
				reg = <0x0 0x0 0x0 0x1c8>;
				#clock-cells = <1>;
				clocks = <&xtal>,
					 <&scmi_clk CLKID_SYS_CLK>,
					 <&scmi_clk CLKID_FIXED_PLL>,
					 <&scmi_clk CLKID_FCLK_DIV2>,
					 <&scmi_clk CLKID_FCLK_DIV2P5>,
					 <&scmi_clk CLKID_FCLK_DIV3>,
					 <&scmi_clk CLKID_FCLK_DIV4>,
					 <&scmi_clk CLKID_FCLK_DIV5>,
					 <&scmi_clk CLKID_FCLK_DIV7>,
					 <&hifi CLKID_HIFI_PLL>,
					 <&gp0 CLKID_GP0_PLL>,
					 <&gp1 CLKID_GP1_PLL>,
					 <&mpll CLKID_MPLL1>,
					 <&mpll CLKID_MPLL2>,
					 <&mpll CLKID_MPLL3>;
				clock-names = "xtal",
					      "sys",
					      "fix",
					      "fdiv2",
					      "fdiv2p5",
					      "fdiv3",
					      "fdiv4",
					      "fdiv5",
					      "fdiv7",
					      "hifi",
					      "gp0",
					      "gp1",
					      "mpll1",
					      "mpll2",
					      "mpll3";
			};

			reset: reset-controller@2000 {
				compatible = "amlogic,t7-reset";
				reg = <0x0 0x2000 0x0 0x98>;
				#reset-cells = <1>;
			};

			watchdog@2100 {
				compatible = "amlogic,t7-wdt";
				reg = <0x0 0x2100 0x0 0x10>;
				clocks = <&xtal>;
			};

			periphs_pinctrl: pinctrl@4000 {
				compatible = "amlogic,t7-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@4000 {
					reg = <0x0 0x4000 0x0 0x0064>,
					      <0x0 0x40c0 0x0 0x0220>;
					reg-names = "mux", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 0 157>;
				};

				emmc_ctrl_pins: emmc-ctrl {
					mux-0 {
						groups = "emmc_cmd";
						function = "emmc";
						bias-pull-up;
					};

					mux-1 {
						groups = "emmc_clk";
						function = "emmc";
						bias-disable;
					};
				};

				emmc_data_4b_pins: emmc-data-4b {
					mux {
						groups = "emmc_nand_d0",
							 "emmc_nand_d1",
							 "emmc_nand_d2",
							 "emmc_nand_d3";
						function = "emmc";
						bias-pull-up;
					};
				};

				emmc_data_8b_pins: emmc-data-8b {
					mux {
						groups = "emmc_nand_d0",
							 "emmc_nand_d1",
							 "emmc_nand_d2",
							 "emmc_nand_d3",
							 "emmc_nand_d4",
							 "emmc_nand_d5",
							 "emmc_nand_d6",
							 "emmc_nand_d7";
						function = "emmc";
						bias-pull-up;
					};
				};

				emmc_ds_pins: emmc-ds {
					mux {
						groups = "emmc_nand_ds";
						function = "emmc";
						bias-pull-down;
					};
				};

				emmc_clk_gate_pins: emmc-clk-gate {
					mux {
						groups = "GPIOB_8";
						function = "gpio_periphs";
						bias-pull-down;
					};
				};

				i2c0_ao_d_pins: i2c0-ao-d {
					mux {
						groups = "i2c0_ao_sck_d",
							 "i2c0_ao_sda_d";
						function = "i2c0_ao";
						bias-disable;
						drive-strength-microamp = <3000>;
					};
				};

				pwm_a_pins: pwm-a {
					mux {
						groups = "pwm_a";
						function = "pwm_a";
						bias-disable;
					};
				};

				pwm_ao_a_pins: pwm-ao-a {
					mux {
						groups = "pwm_ao_a";
						function = "pwm_ao_a";
						bias-disable;
					};
				};

				pwm_ao_b_pins: pwm-ao-b {
					mux {
						groups = "pwm_ao_b";
						function = "pwm_ao_b";
						bias-disable;
					};
				};

				pwm_ao_c_d_pins: pwm-ao-c-d {
					mux {
						groups = "pwm_ao_c_d";
						function = "pwm_ao_c";
						bias-disable;
					};
				};

				pwm_ao_c_e_pins: pwm-ao-c-e {
					mux {
						groups = "pwm_ao_c_e";
						function = "pwm_ao_c";
						bias-disable;
					};
				};

				pwm_ao_c_hiz_pins: pwm-ao-c-hiz {
					mux {
						groups = "pwm_ao_c_hiz";
						function = "pwm_ao_c_hiz";
						bias-disable;
					};
				};

				pwm_ao_d_pins: pwm-ao-d {
					mux {
						groups = "pwm_ao_d";
						function = "pwm_ao_d";
						bias-disable;
					};
				};

				pwm_ao_e_pins: pwm-ao-e {
					mux {
						groups = "pwm_ao_e";
						function = "pwm_ao_e";
						bias-disable;
					};
				};

				pwm_ao_f_pins: pwm-ao-f {
					mux {
						groups = "pwm_ao_f";
						function = "pwm_ao_f";
						bias-disable;
					};
				};

				pwm_ao_g_d11_pins: pwm-ao-g-d11 {
					mux {
						groups = "pwm_ao_g_d11";
						function = "pwm_ao_g";
						bias-disable;
					};
				};

				pwm_ao_g_d7_pins: pwm-ao-g-d7 {
					mux {
						groups = "pwm_ao_g_d7";
						function = "pwm_ao_g";
						bias-disable;
					};
				};

				pwm_ao_g_e_pins: pwm-ao-g-e {
					mux {
						groups = "pwm_ao_g_e";
						function = "pwm_ao_g";
						bias-disable;
					};
				};

				pwm_ao_g_hiz_pins: pwm-ao-g-hiz {
					mux {
						groups = "pwm_ao_g_hiz";
						function = "pwm_ao_g_hiz";
						bias-disable;
					};
				};

				pwm_ao_h_d5_pins: pwm-ao-h-d5 {
					mux {
						groups = "pwm_ao_h_d5";
						function = "pwm_ao_h";
						bias-disable;
					};
				};

				pwm_ao_h_d10_pins: pwm-ao-h-d10 {
					mux {
						groups = "pwm_ao_h_d10";
						function = "pwm_ao_h";
						bias-disable;
					};
				};

				pwm_b_pins: pwm-b {
					mux {
						groups = "pwm_b";
						function = "pwm_b";
						bias-disable;
					};
				};

				pwm_c_pins: pwm-c {
					mux {
						groups = "pwm_c";
						function = "pwm_c";
						bias-disable;
					};
				};

				pwm_d_pins: pwm-d {
					mux {
						groups = "pwm_d";
						function = "pwm_d";
						bias-disable;
					};
				};

				pwm_e_pins: pwm-e {
					mux {
						groups = "pwm_e";
						function = "pwm_e";
						bias-disable;
					};
				};

				pwm_f_pins: pwm-f {
					mux {
						groups = "pwm_f";
						function = "pwm_f";
						bias-disable;
					};
				};

				pwm_vs_y_pins: pwm-vs-y {
					mux {
						groups = "pwm_vs_y";
						function = "pwm_vs";
						bias-disable;
					};
				};

				pwm_vs_h_pins: pwm-vs-h {
					mux {
						groups = "pwm_vs_h";
						function = "pwm_vs";
						bias-disable;
					};
				};

				sdcard_pins: sdcard {
					mux {
						groups = "sdcard_d0",
							 "sdcard_d1",
							 "sdcard_d2",
							 "sdcard_d3",
							 "sdcard_clk",
							 "sdcard_cmd";
						function = "sdcard";
						bias-pull-up;
					};
				};

				sdcard_clk_gate_pins: sdcard-clk-gate {
					mux {
						groups = "GPIOC_4";
						function = "gpio_periphs";
						bias-pull-down;
					};
				};

				sdio_pins: sdio {
					mux {
						groups = "sdio_d0",
							 "sdio_d1",
							 "sdio_d2",
							 "sdio_d3",
							 "sdio_clk",
							 "sdio_cmd";
						function = "sdio";
						bias-pull-up;
					};
				};

				sdio_clk_gate_pins: sdio-clk-gate {
					mux {
						groups = "GPIOX_4";
						function = "gpio_periphs";
						bias-pull-up;
					};
				};
			};

			gpio_intc: interrupt-controller@4080 {
				compatible = "amlogic,t7-gpio-intc",
					     "amlogic,meson-gpio-intc";
				reg = <0x0 0x4080 0x0 0x20>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts =
					<10 11 12 13 14 15 16 17 18 19 20 21>;
			};

			uart_a: serial@78000 {
				compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
				reg = <0x0 0x78000 0x0 0x18>;
				interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			gp0: clock-controller@8080 {
				compatible = "amlogic,t7-gp0-pll";
				reg = <0x0 0x8080 0x0 0x20>;
				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
				clock-names = "in0";
				#clock-cells = <1>;
			};

			gp1: clock-controller@80c0 {
				compatible = "amlogic,t7-gp1-pll";
				reg = <0x0 0x80c0 0x0 0x14>;
				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
				clock-names = "in0";
				#clock-cells = <1>;
			};

			hifi: clock-controller@8100 {
				compatible = "amlogic,t7-hifi-pll";
				reg = <0x0 0x8100 0x0 0x20>;
				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
				clock-names = "in0";
				#clock-cells = <1>;
			};

			pcie: clock-controller@8140 {
				compatible = "amlogic,t7-pcie-pll";
				reg = <0x0 0x8140 0x0 0x1c>;
				clocks = <&scmi_clk CLKID_PCIE_OSC>;
				clock-names = "in0";
				#clock-cells = <1>;
			};

			mpll: clock-controller@8180 {
				compatible = "amlogic,t7-mpll";
				reg = <0x0 0x8180 0x0 0x28>;
				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
				clock-names = "in0";
				#clock-cells = <1>;
			};

			hdmi: clock-controller@81c0 {
				compatible = "amlogic,t7-hdmi-pll";
				reg = <0x0 0x81c0 0x0 0x20>;
				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
				clock-names = "in0";
				#clock-cells = <1>;
			};

			mclk: clock-controller@8300 {
				compatible = "amlogic,t7-mclk-pll";
				reg = <0x0 0x8300 0x0 0x18>;
				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
					 <&xtal>,
					 <&scmi_clk CLKID_FCLK_50M>;
				clock-names = "in0", "in1", "in2";
				#clock-cells = <1>;
			};

			sec_ao: ao-secure@10220 {
				compatible = "amlogic,t7-ao-secure",
					     "amlogic,meson-gx-ao-secure",
					     "syscon";
				reg = <0x0 0x10220 0x0 0x140>;
				amlogic,has-chip-id;
			};

			pwm_ao_ef: pwm@30000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x30000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_AO_E>,
					 <&clkc_periphs CLKID_PWM_AO_F>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_ao_gh: pwm@32000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x32000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_AO_G>,
					 <&clkc_periphs CLKID_PWM_AO_H>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			clock-measurer@48000 {
				compatible = "amlogic,t7-clk-measure";
				reg = <0x0 0x48000 0x0 0x1c>;
			};

			pwm_ab: pwm@58000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x58000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_A>,
					 <&clkc_periphs CLKID_PWM_B>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_cd: pwm@5a000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x5a000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_C>,
					 <&clkc_periphs CLKID_PWM_D>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_ef: pwm@5c000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x5c000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_E>,
					 <&clkc_periphs CLKID_PWM_F>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_ao_ab: pwm@5e000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x5e000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_AO_A>,
					 <&clkc_periphs CLKID_PWM_AO_B>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_ao_cd: pwm@60000 {
				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
				reg = <0x0 0x60000 0x0 0x24>;
				clocks = <&clkc_periphs CLKID_PWM_AO_C>,
					 <&clkc_periphs CLKID_PWM_AO_D>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			sd_emmc_a: mmc@88000 {
				compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
				reg = <0x0 0x88000 0x0 0x800>;
				interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
					 <&clkc_periphs CLKID_SD_EMMC_A>,
					 <&scmi_clk CLKID_FCLK_DIV2>;
				clock-names = "core", "clkin0", "clkin1";
				resets = <&reset RESET_SD_EMMC_A>;
				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>;
				assigned-clock-parents = <&xtal>;
				status = "disabled";
			};

			sd_emmc_b: mmc@8a000 {
				compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
				reg = <0x0 0x8a000 0x0 0x800>;
				interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
					 <&clkc_periphs CLKID_SD_EMMC_B>,
					 <&scmi_clk CLKID_FCLK_DIV2>;
				clock-names = "core", "clkin0", "clkin1";
				resets = <&reset RESET_SD_EMMC_B>;
				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>;
				assigned-clock-parents = <&xtal>;
				status = "disabled";
			};

			sd_emmc_c: mmc@8c000 {
				compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
				reg = <0x0 0x8c000 0x0 0x800>;
				interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
					 <&clkc_periphs CLKID_SD_EMMC_C>,
					 <&scmi_clk CLKID_FCLK_DIV2>;
				clock-names = "core", "clkin0", "clkin1";
				resets = <&reset RESET_SD_EMMC_C>;
				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>;
				assigned-clock-parents = <&xtal>;
				status = "disabled";
			};
		};

	};
};