# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: EcoNet EN751221 Interrupt Controller

maintainers:
  - Caleb James DeLisle <cjd@cjdns.fr>

description:
  The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
  designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
  be routed to either VPE but not both, so to support per-CPU interrupts, a
  secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
  lack of a better term we call these "shadow interrupts". The assignment of
  shadow interrupts is defined by the SoC integrator when wiring the interrupt
  lines, so they are configurable in the device tree.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    const: econet,en751221-intc

  reg:
    maxItems: 1

  "#interrupt-cells":
    const: 1

  interrupt-controller: true

  interrupts:
    maxItems: 1
    description: Interrupt line connecting this controller to its parent.

  econet,shadow-interrupts:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description:
      An array of interrupt number pairs where each pair represents a shadow
      interrupt relationship. The first number in each pair is the primary IRQ,
      and the second is its shadow IRQ used for VPE#1 control. For example,
      <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but
      when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit.
    minItems: 1
    maxItems: 20
    items:
      items:
        - description: primary per-CPU IRQ
        - description: shadow IRQ number

  econet,cpu-interrupt-map:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description:
      When running in VEIC mode, the hardware re-routes interrupts from the
      CPU interrupt controller core to the "external" interrupt controller
      (this device). It then prioritizes them and sends them back to the CPU
      along with its own interrupts. The CPU hardware handles interrupts using
      a special dispatch table (the normal interrupt handler is not invoked).
      In this interrupt controller, the CPU interrupts are renumbered as they
      are merged with this controller's own hardware interrupts.

      This is the inverse of an interrupt-map, mapping which interrupts from
      this controller must be routed back to the CPU interrupt domain for
      correct handling there.
    items:
      items:
        - description: The interrupt number as received in this controller
        - description: The interrupt number to be dispatched on the CPU intc

required:
  - compatible
  - reg
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    interrupt-controller@1fb40000 {
        compatible = "econet,en751221-intc";
        reg = <0x1fb40000 0x100>;

        interrupt-controller;
        #interrupt-cells = <1>;

        interrupt-parent = <&cpuintc>;
        interrupts = <2>;

        econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
        econet,cpu-interrupt-map = <7 0>, <8 1>;
    };
...