# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100 maintainers: - Rajendra Nayak - Abel Vesa description: | RPMh interconnect providers support system bandwidth requirements through RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is able to communicate with the BCM through the Resource State Coordinator (RSC) associated with each execution environment. Provider nodes must point to at least one RPMh device child node pertaining to their RSC and each provider can map to multiple RPMh resources. See also: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h properties: compatible: enum: - qcom,x1e80100-aggre1-noc - qcom,x1e80100-aggre2-noc - qcom,x1e80100-clk-virt - qcom,x1e80100-cnoc-cfg - qcom,x1e80100-cnoc-main - qcom,x1e80100-gem-noc - qcom,x1e80100-lpass-ag-noc - qcom,x1e80100-lpass-lpiaon-noc - qcom,x1e80100-lpass-lpicx-noc - qcom,x1e80100-mc-virt - qcom,x1e80100-mmss-noc - qcom,x1e80100-nsp-noc - qcom,x1e80100-pcie-center-anoc - qcom,x1e80100-pcie-north-anoc - qcom,x1e80100-pcie-south-anoc - qcom,x1e80100-system-noc - qcom,x1e80100-usb-center-anoc - qcom,x1e80100-usb-north-anoc - qcom,x1e80100-usb-south-anoc reg: maxItems: 1 clocks: minItems: 1 maxItems: 6 required: - compatible allOf: - $ref: qcom,rpmh-common.yaml# - if: properties: compatible: contains: enum: - qcom,x1e80100-clk-virt - qcom,x1e80100-mc-virt then: properties: reg: false else: required: - reg - if: properties: compatible: contains: enum: - qcom,x1e80100-aggre1-noc then: properties: clocks: items: - description: aggre UFS PHY AXI clock - if: properties: compatible: contains: enum: - qcom,x1e80100-usb-north-anoc then: properties: clocks: items: - description: aggre USB2 PRIM AXI clock - description: aggre USB3 MP AXI clock - if: properties: compatible: contains: enum: - qcom,x1e80100-usb-south-anoc then: properties: clocks: items: - description: aggre USB3 PRIM AXI clock - description: aggre USB3 SEC AXI clock - description: aggre USB3 TERT AXI clock - description: aggre USB4_0 AXI clock - description: aggre USB4_1 AXI clock - description: aggre USB4_2 AXI clock - if: properties: compatible: contains: enum: - qcom,x1e80100-aggre2-noc - qcom,x1e80100-clk-virt - qcom,x1e80100-cnoc-cfg - qcom,x1e80100-cnoc-main - qcom,x1e80100-gem-noc - qcom,x1e80100-lpass-ag-noc - qcom,x1e80100-lpass-lpiaon-noc - qcom,x1e80100-lpass-lpicx-noc - qcom,x1e80100-mc-virt - qcom,x1e80100-mmss-noc - qcom,x1e80100-nsp-noc - qcom,x1e80100-pcie-center-anoc - qcom,x1e80100-pcie-north-anoc - qcom,x1e80100-pcie-south-anoc - qcom,x1e80100-system-noc - qcom,x1e80100-usb-center-anoc then: properties: clocks: false unevaluatedProperties: false examples: - | clk_virt: interconnect-0 { compatible = "qcom,x1e80100-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,x1e80100-aggre1-noc"; reg = <0x016e0000 0x14400>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc_aggre_ufs_phy_axi_clk>; };