From 6668ed271eaefaa63e686bdfbedaeb7b8e492722 Mon Sep 17 00:00:00 2001 From: Kumar Kartikeya Dwivedi Date: Fri, 4 Sep 2026 10:43:19 +0200 Subject: selftests/bpf: Reject graph kptr use after RCU unlock Add a sleepable verifier test that loads a graph-node local kptr in an explicit RCU read-side critical section, then passes its node to bpf_rbtree_remove() after the section ends. Before the verifier fix, the stale NON_OWN_REF flag makes the node look like a live borrowed reference and the program is accepted. After the fix, the pointer is demoted without NON_OWN_REF and the graph kfunc argument is rejected. Also exercise a graph kptr loaded while a spin lock provides implicit RCU protection. The pointer must be invalidated when the lock is released, which guards the required ordering between non-owning-reference invalidation and RCU demotion. Update the existing fault-protected load test state description. The post-unlock pointer no longer carries NON_OWN_REF, but remains readable because the load is rewritten to use BPF_PROBE_MEM. Signed-off-by: Kumar Kartikeya Dwivedi Link: https://lore.kernel.org/r/20260904084325.52250-7-memxor@gmail.com Signed-off-by: Alexei Starovoitov --- sound/soc/starfive/Kconfig | 20 ++ sound/soc/starfive/Makefile | 4 + sound/soc/starfive/jh7110_pwmdac.c | 525 ++++++++++++++++++++++++++++++ sound/soc/starfive/jh7110_tdm.c | 651 +++++++++++++++++++++++++++++++++++++ 4 files changed, 1200 insertions(+) create mode 100644 sound/soc/starfive/Kconfig create mode 100644 sound/soc/starfive/Makefile create mode 100644 sound/soc/starfive/jh7110_pwmdac.c create mode 100644 sound/soc/starfive/jh7110_tdm.c (limited to 'sound/soc/starfive') diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig new file mode 100644 index 000000000..1e11aa745 --- /dev/null +++ b/sound/soc/starfive/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "StarFive" + depends on COMPILE_TEST || ARCH_STARFIVE + depends on HAVE_CLK + +config SND_SOC_JH7110_PWMDAC + tristate "JH7110 PWM-DAC device driver" + select SND_SOC_GENERIC_DMAENGINE_PCM + select SND_SOC_SPDIF + help + Say Y or M if you want to add support for StarFive JH7110 + PWM-DAC driver. + +config SND_SOC_JH7110_TDM + tristate "JH7110 TDM device driver" + select SND_SOC_GENERIC_DMAENGINE_PCM + help + Say Y or M if you want to add support for StarFive TDM driver. + +endmenu diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile new file mode 100644 index 000000000..cfe03c83d --- /dev/null +++ b/sound/soc/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# StarFive Platform Support +obj-$(CONFIG_SND_SOC_JH7110_PWMDAC) += jh7110_pwmdac.o +obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o diff --git a/sound/soc/starfive/jh7110_pwmdac.c b/sound/soc/starfive/jh7110_pwmdac.c new file mode 100644 index 000000000..5953c3a4e --- /dev/null +++ b/sound/soc/starfive/jh7110_pwmdac.c @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver + * + * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. + * + * Authors: Jenny Zhang + * Curry Zhang + * Xingyu Wu + * Hal Feng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define JH7110_PWMDAC_WDATA 0x00 +#define JH7110_PWMDAC_CTRL 0x04 + #define JH7110_PWMDAC_ENABLE BIT(0) + #define JH7110_PWMDAC_SHIFT BIT(1) + #define JH7110_PWMDAC_DUTY_CYCLE_SHIFT 2 + #define JH7110_PWMDAC_DUTY_CYCLE_MASK GENMASK(3, 2) + #define JH7110_PWMDAC_CNT_N_SHIFT 4 + #define JH7110_PWMDAC_CNT_N_MASK GENMASK(12, 4) + #define JH7110_PWMDAC_DATA_CHANGE BIT(13) + #define JH7110_PWMDAC_DATA_MODE BIT(14) + #define JH7110_PWMDAC_DATA_SHIFT_SHIFT 15 + #define JH7110_PWMDAC_DATA_SHIFT_MASK GENMASK(17, 15) + +enum JH7110_PWMDAC_SHIFT_VAL { + PWMDAC_SHIFT_8 = 0, + PWMDAC_SHIFT_10, +}; + +enum JH7110_PWMDAC_DUTY_CYCLE_VAL { + PWMDAC_CYCLE_LEFT = 0, + PWMDAC_CYCLE_RIGHT, + PWMDAC_CYCLE_CENTER, +}; + +enum JH7110_PWMDAC_CNT_N_VAL { + PWMDAC_SAMPLE_CNT_1 = 1, + PWMDAC_SAMPLE_CNT_2, + PWMDAC_SAMPLE_CNT_3, + PWMDAC_SAMPLE_CNT_512 = 512, /* max */ +}; + +enum JH7110_PWMDAC_DATA_CHANGE_VAL { + NO_CHANGE = 0, + CHANGE, +}; + +enum JH7110_PWMDAC_DATA_MODE_VAL { + UNSIGNED_DATA = 0, + INVERTER_DATA_MSB, +}; + +enum JH7110_PWMDAC_DATA_SHIFT_VAL { + PWMDAC_DATA_LEFT_SHIFT_BIT_0 = 0, + PWMDAC_DATA_LEFT_SHIFT_BIT_1, + PWMDAC_DATA_LEFT_SHIFT_BIT_2, + PWMDAC_DATA_LEFT_SHIFT_BIT_3, + PWMDAC_DATA_LEFT_SHIFT_BIT_4, + PWMDAC_DATA_LEFT_SHIFT_BIT_5, + PWMDAC_DATA_LEFT_SHIFT_BIT_6, + PWMDAC_DATA_LEFT_SHIFT_BIT_7, +}; + +struct jh7110_pwmdac_cfg { + enum JH7110_PWMDAC_SHIFT_VAL shift; + enum JH7110_PWMDAC_DUTY_CYCLE_VAL duty_cycle; + u16 cnt_n; + enum JH7110_PWMDAC_DATA_CHANGE_VAL data_change; + enum JH7110_PWMDAC_DATA_MODE_VAL data_mode; + enum JH7110_PWMDAC_DATA_SHIFT_VAL data_shift; +}; + +struct jh7110_pwmdac_dev { + void __iomem *base; + resource_size_t mapbase; + struct jh7110_pwmdac_cfg cfg; + + struct clk_bulk_data clks[2]; + struct reset_control *rst_apb; + struct device *dev; + struct snd_dmaengine_dai_dma_data play_dma_data; + u32 saved_ctrl; +}; + +static inline void jh7110_pwmdac_write_reg(void __iomem *io_base, int reg, u32 val) +{ + writel(val, io_base + reg); +} + +static inline u32 jh7110_pwmdac_read_reg(void __iomem *io_base, int reg) +{ + return readl(io_base + reg); +} + +static void jh7110_pwmdac_set_enable(struct jh7110_pwmdac_dev *dev, bool enable) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + if (enable) + value |= JH7110_PWMDAC_ENABLE; + else + value &= ~JH7110_PWMDAC_ENABLE; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set_shift(struct jh7110_pwmdac_dev *dev) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + if (dev->cfg.shift == PWMDAC_SHIFT_8) + value &= ~JH7110_PWMDAC_SHIFT; + else if (dev->cfg.shift == PWMDAC_SHIFT_10) + value |= JH7110_PWMDAC_SHIFT; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set_duty_cycle(struct jh7110_pwmdac_dev *dev) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + value &= ~JH7110_PWMDAC_DUTY_CYCLE_MASK; + value |= (dev->cfg.duty_cycle & 0x3) << JH7110_PWMDAC_DUTY_CYCLE_SHIFT; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set_cnt_n(struct jh7110_pwmdac_dev *dev) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + value &= ~JH7110_PWMDAC_CNT_N_MASK; + value |= ((dev->cfg.cnt_n - 1) & 0x1ff) << JH7110_PWMDAC_CNT_N_SHIFT; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set_data_change(struct jh7110_pwmdac_dev *dev) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + if (dev->cfg.data_change == NO_CHANGE) + value &= ~JH7110_PWMDAC_DATA_CHANGE; + else if (dev->cfg.data_change == CHANGE) + value |= JH7110_PWMDAC_DATA_CHANGE; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set_data_mode(struct jh7110_pwmdac_dev *dev) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + if (dev->cfg.data_mode == UNSIGNED_DATA) + value &= ~JH7110_PWMDAC_DATA_MODE; + else if (dev->cfg.data_mode == INVERTER_DATA_MSB) + value |= JH7110_PWMDAC_DATA_MODE; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set_data_shift(struct jh7110_pwmdac_dev *dev) +{ + u32 value; + + value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); + value &= ~JH7110_PWMDAC_DATA_SHIFT_MASK; + value |= (dev->cfg.data_shift & 0x7) << JH7110_PWMDAC_DATA_SHIFT_SHIFT; + + jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); +} + +static void jh7110_pwmdac_set(struct jh7110_pwmdac_dev *dev) +{ + jh7110_pwmdac_set_shift(dev); + jh7110_pwmdac_set_duty_cycle(dev); + jh7110_pwmdac_set_cnt_n(dev); + jh7110_pwmdac_set_enable(dev, true); + + jh7110_pwmdac_set_data_change(dev); + jh7110_pwmdac_set_data_mode(dev); + jh7110_pwmdac_set_data_shift(dev); +} + +static void jh7110_pwmdac_stop(struct jh7110_pwmdac_dev *dev) +{ + jh7110_pwmdac_set_enable(dev, false); +} + +static int jh7110_pwmdac_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_dai_link *dai_link = rtd->dai_link; + + dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC; + + return 0; +} + +static int jh7110_pwmdac_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev); + unsigned long core_clk_rate; + int ret; + + switch (params_rate(params)) { + case 8000: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_3; + core_clk_rate = 6144000; + break; + case 11025: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_2; + core_clk_rate = 5644800; + break; + case 16000: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_3; + core_clk_rate = 12288000; + break; + case 22050: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_1; + core_clk_rate = 5644800; + break; + case 32000: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_1; + core_clk_rate = 8192000; + break; + case 44100: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_1; + core_clk_rate = 11289600; + break; + case 48000: + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_1; + core_clk_rate = 12288000; + break; + default: + dev_err(dai->dev, "%d rate not supported\n", + params_rate(params)); + return -EINVAL; + } + + switch (params_channels(params)) { + case 1: + dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + break; + case 2: + dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + break; + default: + dev_err(dai->dev, "%d channels not supported\n", + params_channels(params)); + return -EINVAL; + } + + /* + * The clock rate always rounds down when using clk_set_rate() + * so increase the rate a bit + */ + core_clk_rate += 64; + jh7110_pwmdac_set(dev); + + ret = clk_set_rate(dev->clks[1].clk, core_clk_rate); + if (ret) + return dev_err_probe(dai->dev, ret, + "failed to set rate %lu for core clock\n", + core_clk_rate); + + return 0; +} + +static int jh7110_pwmdac_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + struct jh7110_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai); + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + jh7110_pwmdac_set(dev); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + jh7110_pwmdac_stop(dev); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int jh7110_pwmdac_crg_enable(struct jh7110_pwmdac_dev *dev, bool enable) +{ + int ret; + + if (enable) { + ret = clk_bulk_prepare_enable(ARRAY_SIZE(dev->clks), dev->clks); + if (ret) + return dev_err_probe(dev->dev, ret, + "failed to enable pwmdac clocks\n"); + + ret = reset_control_deassert(dev->rst_apb); + if (ret) { + dev_err(dev->dev, "failed to deassert pwmdac apb reset\n"); + goto err_rst_apb; + } + } else { + clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks); + } + + return 0; + +err_rst_apb: + clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks); + + return ret; +} + +static int jh7110_pwmdac_dai_probe(struct snd_soc_dai *dai) +{ + struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev); + + snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL); + snd_soc_dai_set_drvdata(dai, dev); + + return 0; +} + +static const struct snd_soc_dai_ops jh7110_pwmdac_dai_ops = { + .probe = jh7110_pwmdac_dai_probe, + .startup = jh7110_pwmdac_startup, + .hw_params = jh7110_pwmdac_hw_params, + .trigger = jh7110_pwmdac_trigger, +}; + +static const struct snd_soc_component_driver jh7110_pwmdac_component = { + .name = "jh7110-pwmdac", +}; + +static struct snd_soc_dai_driver jh7110_pwmdac_dai = { + .name = "jh7110-pwmdac", + .id = 0, + .playback = { + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &jh7110_pwmdac_dai_ops, +}; + +static int jh7110_pwmdac_runtime_suspend(struct device *dev) +{ + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); + + return jh7110_pwmdac_crg_enable(pwmdac, false); +} + +static int jh7110_pwmdac_runtime_resume(struct device *dev) +{ + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); + + return jh7110_pwmdac_crg_enable(pwmdac, true); +} + +static int jh7110_pwmdac_system_suspend(struct device *dev) +{ + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); + + /* save the CTRL register value */ + pwmdac->saved_ctrl = jh7110_pwmdac_read_reg(pwmdac->base, + JH7110_PWMDAC_CTRL); + return pm_runtime_force_suspend(dev); +} + +static int jh7110_pwmdac_system_resume(struct device *dev) +{ + struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret) + return ret; + + /* restore the CTRL register value */ + jh7110_pwmdac_write_reg(pwmdac->base, JH7110_PWMDAC_CTRL, + pwmdac->saved_ctrl); + return 0; +} + +static const struct dev_pm_ops jh7110_pwmdac_pm_ops = { + RUNTIME_PM_OPS(jh7110_pwmdac_runtime_suspend, + jh7110_pwmdac_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(jh7110_pwmdac_system_suspend, + jh7110_pwmdac_system_resume) +}; + +static void jh7110_pwmdac_init_params(struct jh7110_pwmdac_dev *dev) +{ + dev->cfg.shift = PWMDAC_SHIFT_8; + dev->cfg.duty_cycle = PWMDAC_CYCLE_CENTER; + dev->cfg.cnt_n = PWMDAC_SAMPLE_CNT_1; + dev->cfg.data_change = NO_CHANGE; + dev->cfg.data_mode = INVERTER_DATA_MSB; + dev->cfg.data_shift = PWMDAC_DATA_LEFT_SHIFT_BIT_0; + + dev->play_dma_data.addr = dev->mapbase + JH7110_PWMDAC_WDATA; + dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dev->play_dma_data.fifo_size = 1; + dev->play_dma_data.maxburst = 16; +} + +static int jh7110_pwmdac_probe(struct platform_device *pdev) +{ + struct jh7110_pwmdac_dev *dev; + struct resource *res; + int ret; + + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(dev->base)) + return PTR_ERR(dev->base); + + dev->mapbase = res->start; + + dev->clks[0].id = "apb"; + dev->clks[1].id = "core"; + + ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(dev->clks), dev->clks); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get pwmdac clocks\n"); + + dev->rst_apb = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(dev->rst_apb)) + return dev_err_probe(&pdev->dev, PTR_ERR(dev->rst_apb), + "failed to get pwmdac apb reset\n"); + + jh7110_pwmdac_init_params(dev); + + dev->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, dev); + ret = devm_snd_soc_register_component(&pdev->dev, + &jh7110_pwmdac_component, + &jh7110_pwmdac_dai, 1); + if (ret) + return ret; + + ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); + if (ret) + return ret; + + pm_runtime_enable(dev->dev); + if (!pm_runtime_enabled(&pdev->dev)) { + ret = jh7110_pwmdac_runtime_resume(&pdev->dev); + if (ret) { + pm_runtime_disable(&pdev->dev); + return ret; + } + } + + return 0; +} + +static void jh7110_pwmdac_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id jh7110_pwmdac_of_match[] = { + { .compatible = "starfive,jh7110-pwmdac" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_pwmdac_of_match); + +static struct platform_driver jh7110_pwmdac_driver = { + .driver = { + .name = "jh7110-pwmdac", + .of_match_table = jh7110_pwmdac_of_match, + .pm = pm_ptr(&jh7110_pwmdac_pm_ops), + }, + .probe = jh7110_pwmdac_probe, + .remove = jh7110_pwmdac_remove, +}; +module_platform_driver(jh7110_pwmdac_driver); + +MODULE_AUTHOR("Jenny Zhang"); +MODULE_AUTHOR("Curry Zhang"); +MODULE_AUTHOR("Xingyu Wu "); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("StarFive JH7110 PWM-DAC driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/starfive/jh7110_tdm.c b/sound/soc/starfive/jh7110_tdm.c new file mode 100644 index 000000000..f7522bfbe --- /dev/null +++ b/sound/soc/starfive/jh7110_tdm.c @@ -0,0 +1,651 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * jh7110_tdm.c -- StarFive JH7110 TDM driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * + * Author: Walker Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TDM_PCMGBCR 0x00 + #define PCMGBCR_ENABLE BIT(0) + #define CLKPOL_BIT 5 + #define ELM_BIT 3 + #define SYNCM_BIT 2 + #define MS_BIT 1 +#define TDM_PCMTXCR 0x04 + #define PCMTXCR_TXEN BIT(0) + #define IFL_BIT 11 + #define WL_BIT 8 + #define SSCALE_BIT 4 + #define SL_BIT 2 + #define LRJ_BIT 1 +#define TDM_PCMRXCR 0x08 + #define PCMRXCR_RXEN BIT(0) +#define TDM_PCMDIV 0x0c + +#define JH7110_TDM_FIFO 0x170c0000 +#define JH7110_TDM_FIFO_DEPTH 32 + +enum TDM_MASTER_SLAVE_MODE { + TDM_AS_MASTER = 0, + TDM_AS_SLAVE, +}; + +enum TDM_CLKPOL { + /* tx raising and rx falling */ + TDM_TX_RASING_RX_FALLING = 0, + /* tx falling and rx raising */ + TDM_TX_FALLING_RX_RASING, +}; + +enum TDM_ELM { + /* only work while SYNCM=0 */ + TDM_ELM_LATE = 0, + TDM_ELM_EARLY, +}; + +enum TDM_SYNCM { + /* short frame sync */ + TDM_SYNCM_SHORT = 0, + /* long frame sync */ + TDM_SYNCM_LONG, +}; + +enum TDM_IFL { + /* FIFO to send or received : half-1/2, Quarter-1/4 */ + TDM_FIFO_HALF = 0, + TDM_FIFO_QUARTER, +}; + +enum TDM_WL { + /* send or received word length */ + TDM_8BIT_WORD_LEN = 0, + TDM_16BIT_WORD_LEN, + TDM_20BIT_WORD_LEN, + TDM_24BIT_WORD_LEN, + TDM_32BIT_WORD_LEN, +}; + +enum TDM_SL { + /* send or received slot length */ + TDM_8BIT_SLOT_LEN = 0, + TDM_16BIT_SLOT_LEN, + TDM_32BIT_SLOT_LEN, +}; + +enum TDM_LRJ { + /* left-justify or right-justify */ + TDM_RIGHT_JUSTIFY = 0, + TDM_LEFT_JUSTIFT, +}; + +struct tdm_chan_cfg { + enum TDM_IFL ifl; + enum TDM_WL wl; + unsigned char sscale; + enum TDM_SL sl; + enum TDM_LRJ lrj; + unsigned char enable; +}; + +struct jh7110_tdm_dev { + void __iomem *tdm_base; + struct device *dev; + struct clk_bulk_data clks[6]; + struct reset_control *resets; + + enum TDM_CLKPOL clkpolity; + enum TDM_ELM elm; + enum TDM_SYNCM syncm; + enum TDM_MASTER_SLAVE_MODE ms_mode; + + struct tdm_chan_cfg tx; + struct tdm_chan_cfg rx; + + u16 syncdiv; + u32 samplerate; + u32 pcmclk; + + /* data related to DMA transfers b/w tdm and DMAC */ + struct snd_dmaengine_dai_dma_data play_dma_data; + struct snd_dmaengine_dai_dma_data capture_dma_data; + u32 saved_pcmgbcr; + u32 saved_pcmtxcr; + u32 saved_pcmrxcr; + u32 saved_pcmdiv; +}; + +static inline u32 jh7110_tdm_readl(struct jh7110_tdm_dev *tdm, u16 reg) +{ + return readl_relaxed(tdm->tdm_base + reg); +} + +static inline void jh7110_tdm_writel(struct jh7110_tdm_dev *tdm, u16 reg, u32 val) +{ + writel_relaxed(val, tdm->tdm_base + reg); +} + +static void jh7110_tdm_save_context(struct jh7110_tdm_dev *tdm, + struct snd_pcm_substream *substream) +{ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + tdm->saved_pcmtxcr = jh7110_tdm_readl(tdm, TDM_PCMTXCR); + else + tdm->saved_pcmrxcr = jh7110_tdm_readl(tdm, TDM_PCMRXCR); +} + +static void jh7110_tdm_start(struct jh7110_tdm_dev *tdm, + struct snd_pcm_substream *substream) +{ + u32 data; + + data = jh7110_tdm_readl(tdm, TDM_PCMGBCR); + jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | PCMGBCR_ENABLE); + + /* restore context */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr | PCMTXCR_TXEN); + else + jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr | PCMRXCR_RXEN); +} + +static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm, + struct snd_pcm_substream *substream) +{ + unsigned int val; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + val = jh7110_tdm_readl(tdm, TDM_PCMTXCR); + val &= ~PCMTXCR_TXEN; + jh7110_tdm_writel(tdm, TDM_PCMTXCR, val); + } else { + val = jh7110_tdm_readl(tdm, TDM_PCMRXCR); + val &= ~PCMRXCR_RXEN; + jh7110_tdm_writel(tdm, TDM_PCMRXCR, val); + } +} + +static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm) +{ + u32 sl, sscale, syncdiv; + + sl = max(tdm->rx.sl, tdm->tx.sl); + sscale = max(tdm->rx.sscale, tdm->tx.sscale); + syncdiv = tdm->pcmclk / tdm->samplerate - 1; + + if ((syncdiv + 1) < (sl * sscale)) { + dev_err(tdm->dev, "Failed to set syncdiv!\n"); + return -EINVAL; + } + + if (tdm->syncm == TDM_SYNCM_LONG && + (tdm->rx.sscale <= 1 || tdm->tx.sscale <= 1) && + ((syncdiv + 1) <= sl)) { + dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[tx.sl, rx.sl]\n"); + return -EINVAL; + } + + jh7110_tdm_writel(tdm, TDM_PCMDIV, syncdiv); + return 0; +} + +static int jh7110_tdm_config(struct jh7110_tdm_dev *tdm, + struct snd_pcm_substream *substream) +{ + u32 datarx, datatx; + int ret; + + ret = jh7110_tdm_syncdiv(tdm); + if (ret) + return ret; + + datarx = (tdm->rx.ifl << IFL_BIT) | + (tdm->rx.wl << WL_BIT) | + (tdm->rx.sscale << SSCALE_BIT) | + (tdm->rx.sl << SL_BIT) | + (tdm->rx.lrj << LRJ_BIT); + + datatx = (tdm->tx.ifl << IFL_BIT) | + (tdm->tx.wl << WL_BIT) | + (tdm->tx.sscale << SSCALE_BIT) | + (tdm->tx.sl << SL_BIT) | + (tdm->tx.lrj << LRJ_BIT); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + jh7110_tdm_writel(tdm, TDM_PCMTXCR, datatx); + else + jh7110_tdm_writel(tdm, TDM_PCMRXCR, datarx); + + return 0; +} + +static void jh7110_tdm_clk_disable(struct jh7110_tdm_dev *tdm) +{ + clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks); +} + +static int jh7110_tdm_clk_enable(struct jh7110_tdm_dev *tdm) +{ + int ret; + + ret = clk_bulk_prepare_enable(ARRAY_SIZE(tdm->clks), tdm->clks); + if (ret) { + dev_err(tdm->dev, "Failed to enable tdm clocks\n"); + return ret; + } + + ret = reset_control_deassert(tdm->resets); + if (ret) { + dev_err(tdm->dev, "Failed to deassert tdm resets\n"); + goto dis_tdm_clk; + } + + /* select tdm_ext clock as the clock source for tdm */ + ret = clk_set_parent(tdm->clks[5].clk, tdm->clks[4].clk); + if (ret) { + dev_err(tdm->dev, "Can't set extern clock source for clk_tdm\n"); + goto dis_tdm_clk; + } + + return 0; + +dis_tdm_clk: + clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks); + + return ret; +} + +static int jh7110_tdm_runtime_suspend(struct device *dev) +{ + struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); + + jh7110_tdm_clk_disable(tdm); + return 0; +} + +static int jh7110_tdm_runtime_resume(struct device *dev) +{ + struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); + + return jh7110_tdm_clk_enable(tdm); +} + +static int jh7110_tdm_system_suspend(struct device *dev) +{ + struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); + + /* save context */ + tdm->saved_pcmgbcr = jh7110_tdm_readl(tdm, TDM_PCMGBCR); + tdm->saved_pcmdiv = jh7110_tdm_readl(tdm, TDM_PCMDIV); + + return pm_runtime_force_suspend(dev); +} + +static int jh7110_tdm_system_resume(struct device *dev) +{ + struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); + + /* restore context */ + jh7110_tdm_writel(tdm, TDM_PCMGBCR, tdm->saved_pcmgbcr); + jh7110_tdm_writel(tdm, TDM_PCMDIV, tdm->saved_pcmdiv); + + return pm_runtime_force_resume(dev); +} + +static const struct snd_soc_component_driver jh7110_tdm_component = { + .name = "jh7110-tdm", +}; + +static int jh7110_tdm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); + struct snd_soc_dai_link *dai_link = rtd->dai_link; + + dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC; + + return 0; +} + +static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); + int chan_wl, chan_sl, chan_nr; + unsigned int data_width; + unsigned int dma_bus_width; + struct snd_dmaengine_dai_dma_data *dma_data = NULL; + int ret; + + data_width = params_width(params); + + tdm->samplerate = params_rate(params); + tdm->pcmclk = params_channels(params) * tdm->samplerate * data_width; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + chan_wl = TDM_16BIT_WORD_LEN; + chan_sl = TDM_16BIT_SLOT_LEN; + dma_bus_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + break; + + case SNDRV_PCM_FORMAT_S32_LE: + chan_wl = TDM_32BIT_WORD_LEN; + chan_sl = TDM_32BIT_SLOT_LEN; + dma_bus_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + break; + + default: + dev_err(tdm->dev, "tdm: unsupported PCM fmt"); + return -EINVAL; + } + + chan_nr = params_channels(params); + switch (chan_nr) { + case 1: + case 2: + case 4: + case 6: + case 8: + break; + default: + dev_err(tdm->dev, "channel not supported\n"); + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + tdm->tx.wl = chan_wl; + tdm->tx.sl = chan_sl; + tdm->tx.sscale = chan_nr; + tdm->play_dma_data.addr_width = dma_bus_width; + dma_data = &tdm->play_dma_data; + } else { + tdm->rx.wl = chan_wl; + tdm->rx.sl = chan_sl; + tdm->rx.sscale = chan_nr; + tdm->capture_dma_data.addr_width = dma_bus_width; + dma_data = &tdm->capture_dma_data; + } + + snd_soc_dai_set_dma_data(dai, substream, dma_data); + + ret = jh7110_tdm_config(tdm, substream); + if (ret) + return ret; + + jh7110_tdm_save_context(tdm, substream); + return 0; +} + +static int jh7110_tdm_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + jh7110_tdm_start(tdm, substream); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + jh7110_tdm_stop(tdm, substream); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int jh7110_tdm_set_dai_fmt(struct snd_soc_dai *cpu_dai, + unsigned int fmt) +{ + struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int gbcr; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { + case SND_SOC_DAIFMT_BP_FP: + /* cpu is master */ + tdm->ms_mode = TDM_AS_MASTER; + break; + case SND_SOC_DAIFMT_BC_FC: + /* codec is master */ + tdm->ms_mode = TDM_AS_SLAVE; + break; + case SND_SOC_DAIFMT_BC_FP: + case SND_SOC_DAIFMT_BP_FC: + return -EINVAL; + default: + dev_dbg(tdm->dev, "dwc : Invalid clock provider format\n"); + return -EINVAL; + } + + gbcr = (tdm->clkpolity << CLKPOL_BIT) | + (tdm->elm << ELM_BIT) | + (tdm->syncm << SYNCM_BIT) | + (tdm->ms_mode << MS_BIT); + jh7110_tdm_writel(tdm, TDM_PCMGBCR, gbcr); + + return 0; +} + +static int jh7110_tdm_dai_probe(struct snd_soc_dai *dai) +{ + struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); + + snd_soc_dai_init_dma_data(dai, &tdm->play_dma_data, &tdm->capture_dma_data); + snd_soc_dai_set_drvdata(dai, tdm); + return 0; +} + +static const struct snd_soc_dai_ops jh7110_tdm_dai_ops = { + .probe = jh7110_tdm_dai_probe, + .startup = jh7110_tdm_startup, + .hw_params = jh7110_tdm_hw_params, + .trigger = jh7110_tdm_trigger, + .set_fmt = jh7110_tdm_set_dai_fmt, +}; + +#define JH7110_TDM_RATES SNDRV_PCM_RATE_8000_48000 + +#define JH7110_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver jh7110_tdm_dai = { + .name = "sf_tdm", + .id = 0, + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 8, + .rates = JH7110_TDM_RATES, + .formats = JH7110_TDM_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 8, + .rates = JH7110_TDM_RATES, + .formats = JH7110_TDM_FORMATS, + }, + .ops = &jh7110_tdm_dai_ops, + .symmetric_rate = 1, +}; + +static const struct snd_pcm_hardware jh7110_pcm_hardware = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER), + .buffer_bytes_max = 192512, + .period_bytes_min = 4096, + .period_bytes_max = 32768, + .periods_min = 1, + .periods_max = 48, + .fifo_size = 16, +}; + +static const struct snd_dmaengine_pcm_config jh7110_dmaengine_pcm_config = { + .pcm_hardware = &jh7110_pcm_hardware, + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, + .prealloc_buffer_size = 192512, +}; + +static void jh7110_tdm_init_params(struct jh7110_tdm_dev *tdm) +{ + tdm->clkpolity = TDM_TX_RASING_RX_FALLING; + tdm->elm = TDM_ELM_LATE; + tdm->syncm = TDM_SYNCM_SHORT; + + tdm->rx.ifl = TDM_FIFO_HALF; + tdm->tx.ifl = TDM_FIFO_HALF; + tdm->rx.wl = TDM_16BIT_WORD_LEN; + tdm->tx.wl = TDM_16BIT_WORD_LEN; + tdm->rx.sscale = 2; + tdm->tx.sscale = 2; + tdm->rx.lrj = TDM_LEFT_JUSTIFT; + tdm->tx.lrj = TDM_LEFT_JUSTIFT; + + tdm->play_dma_data.addr = JH7110_TDM_FIFO; + tdm->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + tdm->play_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2; + tdm->play_dma_data.maxburst = 16; + + tdm->capture_dma_data.addr = JH7110_TDM_FIFO; + tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + tdm->capture_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2; + tdm->capture_dma_data.maxburst = 8; +} + +static int jh7110_tdm_clk_reset_get(struct platform_device *pdev, + struct jh7110_tdm_dev *tdm) +{ + int ret; + + tdm->clks[0].id = "mclk_inner"; + tdm->clks[1].id = "tdm_ahb"; + tdm->clks[2].id = "tdm_apb"; + tdm->clks[3].id = "tdm_internal"; + tdm->clks[4].id = "tdm_ext"; + tdm->clks[5].id = "tdm"; + + ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(tdm->clks), tdm->clks); + if (ret) + return ret; + + tdm->resets = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(tdm->resets)) { + dev_err(&pdev->dev, "Failed to get tdm resets\n"); + return PTR_ERR(tdm->resets); + } + + return 0; +} + +static int jh7110_tdm_probe(struct platform_device *pdev) +{ + struct jh7110_tdm_dev *tdm; + int ret; + + tdm = devm_kzalloc(&pdev->dev, sizeof(*tdm), GFP_KERNEL); + if (!tdm) + return -ENOMEM; + + tdm->tdm_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tdm->tdm_base)) + return PTR_ERR(tdm->tdm_base); + + tdm->dev = &pdev->dev; + + ret = jh7110_tdm_clk_reset_get(pdev, tdm); + if (ret) + return ret; + + jh7110_tdm_init_params(tdm); + + dev_set_drvdata(&pdev->dev, tdm); + ret = devm_snd_soc_register_component(&pdev->dev, &jh7110_tdm_component, + &jh7110_tdm_dai, 1); + if (ret) + return ret; + + ret = devm_snd_dmaengine_pcm_register(&pdev->dev, + &jh7110_dmaengine_pcm_config, + SND_DMAENGINE_PCM_FLAG_COMPAT); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + if (!pm_runtime_enabled(&pdev->dev)) { + ret = jh7110_tdm_runtime_resume(&pdev->dev); + if (ret) { + pm_runtime_disable(&pdev->dev); + return ret; + } + } + + return 0; +} + +static void jh7110_tdm_dev_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id jh7110_tdm_of_match[] = { + { .compatible = "starfive,jh7110-tdm", }, + {} +}; + +MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match); + +static const struct dev_pm_ops jh7110_tdm_pm_ops = { + RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend, + jh7110_tdm_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(jh7110_tdm_system_suspend, + jh7110_tdm_system_resume) +}; + +static struct platform_driver jh7110_tdm_driver = { + .driver = { + .name = "jh7110-tdm", + .of_match_table = jh7110_tdm_of_match, + .pm = pm_ptr(&jh7110_tdm_pm_ops), + }, + .probe = jh7110_tdm_probe, + .remove = jh7110_tdm_dev_remove, +}; +module_platform_driver(jh7110_tdm_driver); + +MODULE_DESCRIPTION("StarFive JH7110 TDM ASoC Driver"); +MODULE_AUTHOR("Walker Chen "); +MODULE_LICENSE("GPL"); -- cgit v1.3.1