From 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 2 Sep 2026 15:31:14 -0700 Subject: treewide: refresh kmalloc_obj() conversions This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook --- lib/atomic64.c | 207 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 207 insertions(+) create mode 100644 lib/atomic64.c (limited to 'lib/atomic64.c') diff --git a/lib/atomic64.c b/lib/atomic64.c new file mode 100644 index 000000000..1a72bba36 --- /dev/null +++ b/lib/atomic64.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Generic implementation of 64-bit atomics using spinlocks, + * useful on processors that don't have 64-bit atomic instructions. + * + * Copyright © 2009 Paul Mackerras, IBM Corp. + */ +#include +#include +#include +#include +#include +#include + +/* + * We use a hashed array of spinlocks to provide exclusive access + * to each atomic64_t variable. Since this is expected to used on + * systems with small numbers of CPUs (<= 4 or so), we use a + * relatively small array of 16 spinlocks to avoid wasting too much + * memory on the spinlock array. + */ +#define NR_LOCKS 16 + +/* + * Ensure each lock is in a separate cacheline. + */ +static union { + arch_spinlock_t lock; + char pad[L1_CACHE_BYTES]; +} atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp = { + [0 ... (NR_LOCKS - 1)] = { + .lock = __ARCH_SPIN_LOCK_UNLOCKED, + }, +}; + +static inline arch_spinlock_t *lock_addr(const atomic64_t *v) +{ + unsigned long addr = (unsigned long) v; + + addr >>= L1_CACHE_SHIFT; + addr ^= (addr >> 8) ^ (addr >> 16); + return &atomic64_lock[addr & (NR_LOCKS - 1)].lock; +} + +s64 generic_atomic64_read(const atomic64_t *v) +{ + unsigned long flags; + arch_spinlock_t *lock = lock_addr(v); + s64 val; + + local_irq_save(flags); + arch_spin_lock(lock); + val = v->counter; + arch_spin_unlock(lock); + local_irq_restore(flags); + return val; +} +EXPORT_SYMBOL(generic_atomic64_read); + +void generic_atomic64_set(atomic64_t *v, s64 i) +{ + unsigned long flags; + arch_spinlock_t *lock = lock_addr(v); + + local_irq_save(flags); + arch_spin_lock(lock); + v->counter = i; + arch_spin_unlock(lock); + local_irq_restore(flags); +} +EXPORT_SYMBOL(generic_atomic64_set); + +#define ATOMIC64_OP(op, c_op) \ +void generic_atomic64_##op(s64 a, atomic64_t *v) \ +{ \ + unsigned long flags; \ + arch_spinlock_t *lock = lock_addr(v); \ + \ + local_irq_save(flags); \ + arch_spin_lock(lock); \ + v->counter c_op a; \ + arch_spin_unlock(lock); \ + local_irq_restore(flags); \ +} \ +EXPORT_SYMBOL(generic_atomic64_##op); + +#define ATOMIC64_OP_RETURN(op, c_op) \ +s64 generic_atomic64_##op##_return(s64 a, atomic64_t *v) \ +{ \ + unsigned long flags; \ + arch_spinlock_t *lock = lock_addr(v); \ + s64 val; \ + \ + local_irq_save(flags); \ + arch_spin_lock(lock); \ + val = (v->counter c_op a); \ + arch_spin_unlock(lock); \ + local_irq_restore(flags); \ + return val; \ +} \ +EXPORT_SYMBOL(generic_atomic64_##op##_return); + +#define ATOMIC64_FETCH_OP(op, c_op) \ +s64 generic_atomic64_fetch_##op(s64 a, atomic64_t *v) \ +{ \ + unsigned long flags; \ + arch_spinlock_t *lock = lock_addr(v); \ + s64 val; \ + \ + local_irq_save(flags); \ + arch_spin_lock(lock); \ + val = v->counter; \ + v->counter c_op a; \ + arch_spin_unlock(lock); \ + local_irq_restore(flags); \ + return val; \ +} \ +EXPORT_SYMBOL(generic_atomic64_fetch_##op); + +#define ATOMIC64_OPS(op, c_op) \ + ATOMIC64_OP(op, c_op) \ + ATOMIC64_OP_RETURN(op, c_op) \ + ATOMIC64_FETCH_OP(op, c_op) + +ATOMIC64_OPS(add, +=) +ATOMIC64_OPS(sub, -=) + +#undef ATOMIC64_OPS +#define ATOMIC64_OPS(op, c_op) \ + ATOMIC64_OP(op, c_op) \ + ATOMIC64_FETCH_OP(op, c_op) + +ATOMIC64_OPS(and, &=) +ATOMIC64_OPS(or, |=) +ATOMIC64_OPS(xor, ^=) + +#undef ATOMIC64_OPS +#undef ATOMIC64_FETCH_OP +#undef ATOMIC64_OP + +s64 generic_atomic64_dec_if_positive(atomic64_t *v) +{ + unsigned long flags; + arch_spinlock_t *lock = lock_addr(v); + s64 val; + + local_irq_save(flags); + arch_spin_lock(lock); + val = v->counter - 1; + if (val >= 0) + v->counter = val; + arch_spin_unlock(lock); + local_irq_restore(flags); + return val; +} +EXPORT_SYMBOL(generic_atomic64_dec_if_positive); + +s64 generic_atomic64_cmpxchg(atomic64_t *v, s64 o, s64 n) +{ + unsigned long flags; + arch_spinlock_t *lock = lock_addr(v); + s64 val; + + local_irq_save(flags); + arch_spin_lock(lock); + val = v->counter; + if (val == o) + v->counter = n; + arch_spin_unlock(lock); + local_irq_restore(flags); + return val; +} +EXPORT_SYMBOL(generic_atomic64_cmpxchg); + +s64 generic_atomic64_xchg(atomic64_t *v, s64 new) +{ + unsigned long flags; + arch_spinlock_t *lock = lock_addr(v); + s64 val; + + local_irq_save(flags); + arch_spin_lock(lock); + val = v->counter; + v->counter = new; + arch_spin_unlock(lock); + local_irq_restore(flags); + return val; +} +EXPORT_SYMBOL(generic_atomic64_xchg); + +s64 generic_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u) +{ + unsigned long flags; + arch_spinlock_t *lock = lock_addr(v); + s64 val; + + local_irq_save(flags); + arch_spin_lock(lock); + val = v->counter; + if (val != u) + v->counter += a; + arch_spin_unlock(lock); + local_irq_restore(flags); + + return val; +} +EXPORT_SYMBOL(generic_atomic64_fetch_add_unless); -- cgit v1.3.1