From 2bc6b218717b9d08f466f88209251d54bc09b207 Mon Sep 17 00:00:00 2001 From: Fuad Tabba Date: Tue, 22 Sep 2026 19:14:30 +0100 Subject: arm64/boot: Disable trapping of PMZR_EL0 writes to EL2 __init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2. PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a write from EL0 reaches the trap and takes the host down without a panic message. Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9 bits. Fixes: 858c7bfcb35e1 ("arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9") Cc: stable@vger.kernel.org Signed-off-by: Fuad Tabba Reviewed-by: Anshuman Khandual Reviewed-by: Oliver Upton Signed-off-by: Will Deacon --- include/video/maxinefb.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 include/video/maxinefb.h (limited to 'include/video/maxinefb.h') diff --git a/include/video/maxinefb.h b/include/video/maxinefb.h new file mode 100644 index 000000000..2b66b32f3 --- /dev/null +++ b/include/video/maxinefb.h @@ -0,0 +1,38 @@ +/* + * linux/drivers/video/maxinefb.h + * + * DECstation 5000/xx onboard framebuffer support, Copyright (C) 1999 by + * Michael Engel and Karsten Merker + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + */ + +#include + +/* + * IMS332 video controller register base address + */ +#define MAXINEFB_IMS332_ADDRESS CKSEG1ADDR(0x1c140000) + +/* + * Begin of DECstation 5000/xx onboard framebuffer memory, default resolution + * is 1024x768x8 + */ +#define DS5000_xx_ONBOARD_FBMEM_START CKSEG1ADDR(0x0a000000) + +/* + * The IMS 332 video controller used in the DECstation 5000/xx series + * uses 32 bits wide registers; the following defines declare the + * register numbers, to get the real offset, these have to be multiplied + * by four. + */ + +#define IMS332_REG_CURSOR_RAM 0x200 /* hardware cursor bitmap */ + +/* + * The color palette entries have the form 0x00BBGGRR + */ +#define IMS332_REG_COLOR_PALETTE 0x100 /* color palette, 256 entries */ +#define IMS332_REG_CURSOR_COLOR_PALETTE 0x0a1 /* cursor color palette, */ + /* 3 entries */ -- cgit v1.3.1