From cf9610f9116d55c5a66ef9f1faecacabd93a9322 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Mon, 24 Aug 2026 08:46:03 -0700 Subject: Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ... --- include/trace/events/percpu.h | 137 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 include/trace/events/percpu.h (limited to 'include/trace/events/percpu.h') diff --git a/include/trace/events/percpu.h b/include/trace/events/percpu.h new file mode 100644 index 000000000..5b8211ca8 --- /dev/null +++ b/include/trace/events/percpu.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM percpu + +#if !defined(_TRACE_PERCPU_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_PERCPU_H + +#include +#include + +TRACE_EVENT(percpu_alloc_percpu, + + TP_PROTO(unsigned long call_site, + bool reserved, bool is_atomic, size_t size, + size_t align, void *base_addr, int off, + void __percpu *ptr, size_t bytes_alloc, gfp_t gfp_flags), + + TP_ARGS(call_site, reserved, is_atomic, size, align, base_addr, off, + ptr, bytes_alloc, gfp_flags), + + TP_STRUCT__entry( + __field( unsigned long, call_site ) + __field( bool, reserved ) + __field( bool, is_atomic ) + __field( size_t, size ) + __field( size_t, align ) + __field( void *, base_addr ) + __field( int, off ) + __field( void __percpu *, ptr ) + __field( size_t, bytes_alloc ) + __field( unsigned long, gfp_flags ) + ), + TP_fast_assign( + __entry->call_site = call_site; + __entry->reserved = reserved; + __entry->is_atomic = is_atomic; + __entry->size = size; + __entry->align = align; + __entry->base_addr = base_addr; + __entry->off = off; + __entry->ptr = ptr; + __entry->bytes_alloc = bytes_alloc; + __entry->gfp_flags = (__force unsigned long)gfp_flags; + ), + + TP_printk("call_site=%pS reserved=%d is_atomic=%d size=%zu align=%zu base_addr=%p off=%d ptr=%p bytes_alloc=%zu gfp_flags=%s", + (void *)__entry->call_site, + __entry->reserved, __entry->is_atomic, + __entry->size, __entry->align, + __entry->base_addr, __entry->off, __entry->ptr, + __entry->bytes_alloc, show_gfp_flags(__entry->gfp_flags)) +); + +TRACE_EVENT(percpu_free_percpu, + + TP_PROTO(void *base_addr, int off, void __percpu *ptr), + + TP_ARGS(base_addr, off, ptr), + + TP_STRUCT__entry( + __field( void *, base_addr ) + __field( int, off ) + __field( void __percpu *, ptr ) + ), + + TP_fast_assign( + __entry->base_addr = base_addr; + __entry->off = off; + __entry->ptr = ptr; + ), + + TP_printk("base_addr=%p off=%d ptr=%p", + __entry->base_addr, __entry->off, __entry->ptr) +); + +TRACE_EVENT(percpu_alloc_percpu_fail, + + TP_PROTO(bool reserved, bool is_atomic, size_t size, size_t align), + + TP_ARGS(reserved, is_atomic, size, align), + + TP_STRUCT__entry( + __field( bool, reserved ) + __field( bool, is_atomic ) + __field( size_t, size ) + __field( size_t, align ) + ), + + TP_fast_assign( + __entry->reserved = reserved; + __entry->is_atomic = is_atomic; + __entry->size = size; + __entry->align = align; + ), + + TP_printk("reserved=%d is_atomic=%d size=%zu align=%zu", + __entry->reserved, __entry->is_atomic, + __entry->size, __entry->align) +); + +TRACE_EVENT(percpu_create_chunk, + + TP_PROTO(void *base_addr), + + TP_ARGS(base_addr), + + TP_STRUCT__entry( + __field( void *, base_addr ) + ), + + TP_fast_assign( + __entry->base_addr = base_addr; + ), + + TP_printk("base_addr=%p", __entry->base_addr) +); + +TRACE_EVENT(percpu_destroy_chunk, + + TP_PROTO(void *base_addr), + + TP_ARGS(base_addr), + + TP_STRUCT__entry( + __field( void *, base_addr ) + ), + + TP_fast_assign( + __entry->base_addr = base_addr; + ), + + TP_printk("base_addr=%p", __entry->base_addr) +); + +#endif /* _TRACE_PERCPU_H */ + +#include -- cgit v1.3.1