From 119e9db233ad0f4cbd4cfb9f9385a7bca378b37d Mon Sep 17 00:00:00 2001 From: Zeng Chi Date: Mon, 21 Sep 2026 18:24:42 +0800 Subject: KVM: Don't pre-reserve xarray entries when storing empty/NULL attributes Skip the xarray reservation loop when clearing all memory attributes, as storing NULL only erases the entry and never needs to allocate, so no reservation (and no cleanup of a failed one) is required in that case. Suggested-by: Sean Christopherson Cc: David Ballesteros Signed-off-by: Zeng Chi Link: https://patch.msgid.link/20260921102442.1232375-1-zeng_chi911@163.com [sean: split to separate patch] Signed-off-by: Sean Christopherson --- include/sound/ac97/codec.h | 116 ++ include/sound/ac97/compat.h | 17 + include/sound/ac97/controller.h | 82 + include/sound/ac97/regs.h | 246 +++ include/sound/ac97_codec.h | 421 +++++ include/sound/aci.h | 92 ++ include/sound/acp63_chip_offset_byte.h | 495 ++++++ include/sound/acp7x_chip_offset_byte.h | 2519 +++++++++++++++++++++++++++++ include/sound/ad1816a.h | 169 ++ include/sound/ad1843.h | 46 + include/sound/ak4113.h | 320 ++++ include/sound/ak4114.h | 202 +++ include/sound/ak4117.h | 179 ++ include/sound/ak4531_codec.h | 73 + include/sound/ak4xxx-adda.h | 85 + include/sound/alc5623.h | 16 + include/sound/asequencer.h | 72 + include/sound/asound.h | 25 + include/sound/asoundef.h | 323 ++++ include/sound/aw88399.h | 621 +++++++ include/sound/compress_driver.h | 295 ++++ include/sound/control.h | 322 ++++ include/sound/core.h | 476 ++++++ include/sound/cs-amp-lib.h | 93 ++ include/sound/cs35l33.h | 45 + include/sound/cs35l34.h | 32 + include/sound/cs35l35.h | 107 ++ include/sound/cs35l36.h | 43 + include/sound/cs35l41.h | 928 +++++++++++ include/sound/cs35l56.h | 459 ++++++ include/sound/cs4231-regs.h | 172 ++ include/sound/cs4271.h | 30 + include/sound/cs42l42.h | 815 ++++++++++ include/sound/cs42l43.h | 17 + include/sound/cs48l32.h | 47 + include/sound/cs48l32_registers.h | 530 ++++++ include/sound/cs8403.h | 242 +++ include/sound/cs8427.h | 187 +++ include/sound/da7213.h | 46 + include/sound/da7218.h | 105 ++ include/sound/da7219-aad.h | 101 ++ include/sound/da7219.h | 51 + include/sound/da9055.h | 29 + include/sound/designware_i2s.h | 67 + include/sound/dmaengine_pcm.h | 180 +++ include/sound/emu10k1.h | 1921 ++++++++++++++++++++++ include/sound/emu10k1_synth.h | 26 + include/sound/emu8000.h | 105 ++ include/sound/emu8000_reg.h | 193 +++ include/sound/emux_legacy.h | 132 ++ include/sound/emux_synth.h | 229 +++ include/sound/es1688.h | 108 ++ include/sound/graph_card.h | 35 + include/sound/gus.h | 605 +++++++ include/sound/hda-mlink.h | 231 +++ include/sound/hda-sdw-bpt.h | 77 + include/sound/hda_chmap.h | 79 + include/sound/hda_codec.h | 584 +++++++ include/sound/hda_component.h | 67 + include/sound/hda_hwdep.h | 31 + include/sound/hda_i915.h | 27 + include/sound/hda_register.h | 368 +++++ include/sound/hda_regmap.h | 235 +++ include/sound/hda_verbs.h | 568 +++++++ include/sound/hdaudio.h | 766 +++++++++ include/sound/hdaudio_ext.h | 149 ++ include/sound/hdmi-codec.h | 140 ++ include/sound/hwdep.h | 67 + include/sound/i2c.h | 88 + include/sound/info.h | 232 +++ include/sound/initval.h | 90 ++ include/sound/intel-dsp-config.h | 42 + include/sound/intel-nhlt.h | 199 +++ include/sound/jack.h | 116 ++ include/sound/madera-pdata.h | 59 + include/sound/max9768.h | 20 + include/sound/max98088.h | 45 + include/sound/max98090.h | 24 + include/sound/max98095.h | 61 + include/sound/memalloc.h | 120 ++ include/sound/minors.h | 97 ++ include/sound/mixer_oss.h | 66 + include/sound/mpu401.h | 123 ++ include/sound/omap-hdmi-audio.h | 39 + include/sound/opl3.h | 375 +++++ include/sound/opl4.h | 19 + include/sound/pcm-indirect.h | 180 +++ include/sound/pcm.h | 1591 ++++++++++++++++++ include/sound/pcm_drm_eld.h | 98 ++ include/sound/pcm_iec958.h | 20 + include/sound/pcm_oss.h | 75 + include/sound/pcm_params.h | 370 +++++ include/sound/pt2258.h | 23 + include/sound/pxa2xx-lib.h | 11 + include/sound/q6usboffload.h | 20 + include/sound/rawmidi.h | 219 +++ include/sound/rt1015.h | 15 + include/sound/rt1318.h | 16 + include/sound/rt286.h | 16 + include/sound/rt298.h | 17 + include/sound/rt5514.h | 19 + include/sound/rt5659.h | 47 + include/sound/rt5660.h | 28 + include/sound/rt5663.h | 22 + include/sound/rt5665.h | 42 + include/sound/rt5668.h | 34 + include/sound/rt5682.h | 46 + include/sound/rt5682s.h | 54 + include/sound/sb.h | 363 +++++ include/sound/sb16_csp.h | 76 + include/sound/sdca.h | 91 ++ include/sound/sdca_asoc.h | 115 ++ include/sound/sdca_fdl.h | 111 ++ include/sound/sdca_function.h | 1485 +++++++++++++++++ include/sound/sdca_hid.h | 41 + include/sound/sdca_interrupts.h | 109 ++ include/sound/sdca_jack.h | 38 + include/sound/sdca_regmap.h | 33 + include/sound/sdca_ump.h | 50 + include/sound/sdw.h | 49 + include/sound/seq_device.h | 86 + include/sound/seq_kernel.h | 102 ++ include/sound/seq_midi_emul.h | 184 +++ include/sound/seq_midi_event.h | 39 + include/sound/seq_oss.h | 83 + include/sound/seq_oss_legacy.h | 18 + include/sound/seq_virmidi.h | 68 + include/sound/sh_dac_audio.h | 18 + include/sound/sh_fsi.h | 32 + include/sound/simple_card.h | 26 + include/sound/simple_card_utils.h | 321 ++++ include/sound/snd_wavefront.h | 143 ++ include/sound/soc-acpi-intel-match.h | 58 + include/sound/soc-acpi-intel-ssp-common.h | 85 + include/sound/soc-acpi.h | 260 +++ include/sound/soc-card.h | 127 ++ include/sound/soc-component.h | 454 ++++++ include/sound/soc-dai.h | 608 +++++++ include/sound/soc-dapm.h | 757 +++++++++ include/sound/soc-dpcm.h | 157 ++ include/sound/soc-jack.h | 130 ++ include/sound/soc-link.h | 32 + include/sound/soc-topology.h | 198 +++ include/sound/soc-usb.h | 138 ++ include/sound/soc.h | 1553 ++++++++++++++++++ include/sound/soc_sdw_utils.h | 297 ++++ include/sound/sof.h | 182 +++ include/sound/sof/channel_map.h | 61 + include/sound/sof/control.h | 158 ++ include/sound/sof/dai-amd.h | 37 + include/sound/sof/dai-imx.h | 61 + include/sound/sof/dai-intel.h | 205 +++ include/sound/sof/dai-mediatek.h | 23 + include/sound/sof/dai.h | 135 ++ include/sound/sof/debug.h | 43 + include/sound/sof/ext_manifest.h | 124 ++ include/sound/sof/ext_manifest4.h | 119 ++ include/sound/sof/header.h | 205 +++ include/sound/sof/info.h | 144 ++ include/sound/sof/ipc4/header.h | 791 +++++++++ include/sound/sof/pm.h | 56 + include/sound/sof/stream.h | 151 ++ include/sound/sof/topology.h | 310 ++++ include/sound/sof/trace.h | 107 ++ include/sound/sof/xtensa.h | 49 + include/sound/soundfont.h | 136 ++ include/sound/spear_dma.h | 20 + include/sound/spear_spdif.h | 16 + include/sound/sta32x.h | 39 + include/sound/sta350.h | 53 + include/sound/tas2552-plat.h | 17 + include/sound/tas2563-tlv.h | 279 ++++ include/sound/tas2770-tlv.h | 23 + include/sound/tas2781-comlib-i2c.h | 37 + include/sound/tas2781-dsp.h | 234 +++ include/sound/tas2781-tlv.h | 21 + include/sound/tas2781.h | 278 ++++ include/sound/tas2x20-tlv.h | 259 +++ include/sound/tas5086.h | 8 + include/sound/tas5825-tlv.h | 24 + include/sound/tea6330t.h | 17 + include/sound/timer.h | 140 ++ include/sound/tlv.h | 45 + include/sound/ump.h | 282 ++++ include/sound/ump_convert.h | 47 + include/sound/ump_msg.h | 765 +++++++++ include/sound/util_mem.h | 51 + include/sound/vx_core.h | 535 ++++++ include/sound/wavefront.h | 631 ++++++++ include/sound/wm0010.h | 17 + include/sound/wm2000.h | 20 + include/sound/wm2200.h | 56 + include/sound/wm5100.h | 52 + include/sound/wm8903.h | 263 +++ include/sound/wm8904.h | 161 ++ include/sound/wm8955.h | 21 + include/sound/wm8960.h | 38 + include/sound/wm8962.h | 58 + include/sound/wm8993.h | 45 + include/sound/wm8996.h | 49 + include/sound/wm9081.h | 25 + include/sound/wm9090.h | 25 + include/sound/wss.h | 220 +++ 203 files changed, 39562 insertions(+) create mode 100644 include/sound/ac97/codec.h create mode 100644 include/sound/ac97/compat.h create mode 100644 include/sound/ac97/controller.h create mode 100644 include/sound/ac97/regs.h create mode 100644 include/sound/ac97_codec.h create mode 100644 include/sound/aci.h create mode 100644 include/sound/acp63_chip_offset_byte.h create mode 100644 include/sound/acp7x_chip_offset_byte.h create mode 100644 include/sound/ad1816a.h create mode 100644 include/sound/ad1843.h create mode 100644 include/sound/ak4113.h create mode 100644 include/sound/ak4114.h create mode 100644 include/sound/ak4117.h create mode 100644 include/sound/ak4531_codec.h create mode 100644 include/sound/ak4xxx-adda.h create mode 100644 include/sound/alc5623.h create mode 100644 include/sound/asequencer.h create mode 100644 include/sound/asound.h create mode 100644 include/sound/asoundef.h create mode 100644 include/sound/aw88399.h create mode 100644 include/sound/compress_driver.h create mode 100644 include/sound/control.h create mode 100644 include/sound/core.h create mode 100644 include/sound/cs-amp-lib.h create mode 100644 include/sound/cs35l33.h create mode 100644 include/sound/cs35l34.h create mode 100644 include/sound/cs35l35.h create mode 100644 include/sound/cs35l36.h create mode 100644 include/sound/cs35l41.h create mode 100644 include/sound/cs35l56.h create mode 100644 include/sound/cs4231-regs.h create mode 100644 include/sound/cs4271.h create mode 100644 include/sound/cs42l42.h create mode 100644 include/sound/cs42l43.h create mode 100644 include/sound/cs48l32.h create mode 100644 include/sound/cs48l32_registers.h create mode 100644 include/sound/cs8403.h create mode 100644 include/sound/cs8427.h create mode 100644 include/sound/da7213.h create mode 100644 include/sound/da7218.h create mode 100644 include/sound/da7219-aad.h create mode 100644 include/sound/da7219.h create mode 100644 include/sound/da9055.h create mode 100644 include/sound/designware_i2s.h create mode 100644 include/sound/dmaengine_pcm.h create mode 100644 include/sound/emu10k1.h create mode 100644 include/sound/emu10k1_synth.h create mode 100644 include/sound/emu8000.h create mode 100644 include/sound/emu8000_reg.h create mode 100644 include/sound/emux_legacy.h create mode 100644 include/sound/emux_synth.h create mode 100644 include/sound/es1688.h create mode 100644 include/sound/graph_card.h create mode 100644 include/sound/gus.h create mode 100644 include/sound/hda-mlink.h create mode 100644 include/sound/hda-sdw-bpt.h create mode 100644 include/sound/hda_chmap.h create mode 100644 include/sound/hda_codec.h create mode 100644 include/sound/hda_component.h create mode 100644 include/sound/hda_hwdep.h create mode 100644 include/sound/hda_i915.h create mode 100644 include/sound/hda_register.h create mode 100644 include/sound/hda_regmap.h create mode 100644 include/sound/hda_verbs.h create mode 100644 include/sound/hdaudio.h create mode 100644 include/sound/hdaudio_ext.h create mode 100644 include/sound/hdmi-codec.h create mode 100644 include/sound/hwdep.h create mode 100644 include/sound/i2c.h create mode 100644 include/sound/info.h create mode 100644 include/sound/initval.h create mode 100644 include/sound/intel-dsp-config.h create mode 100644 include/sound/intel-nhlt.h create mode 100644 include/sound/jack.h create mode 100644 include/sound/madera-pdata.h create mode 100644 include/sound/max9768.h create mode 100644 include/sound/max98088.h create mode 100644 include/sound/max98090.h create mode 100644 include/sound/max98095.h create mode 100644 include/sound/memalloc.h create mode 100644 include/sound/minors.h create mode 100644 include/sound/mixer_oss.h create mode 100644 include/sound/mpu401.h create mode 100644 include/sound/omap-hdmi-audio.h create mode 100644 include/sound/opl3.h create mode 100644 include/sound/opl4.h create mode 100644 include/sound/pcm-indirect.h create mode 100644 include/sound/pcm.h create mode 100644 include/sound/pcm_drm_eld.h create mode 100644 include/sound/pcm_iec958.h create mode 100644 include/sound/pcm_oss.h create mode 100644 include/sound/pcm_params.h create mode 100644 include/sound/pt2258.h create mode 100644 include/sound/pxa2xx-lib.h create mode 100644 include/sound/q6usboffload.h create mode 100644 include/sound/rawmidi.h create mode 100644 include/sound/rt1015.h create mode 100644 include/sound/rt1318.h create mode 100644 include/sound/rt286.h create mode 100644 include/sound/rt298.h create mode 100644 include/sound/rt5514.h create mode 100644 include/sound/rt5659.h create mode 100644 include/sound/rt5660.h create mode 100644 include/sound/rt5663.h create mode 100644 include/sound/rt5665.h create mode 100644 include/sound/rt5668.h create mode 100644 include/sound/rt5682.h create mode 100644 include/sound/rt5682s.h create mode 100644 include/sound/sb.h create mode 100644 include/sound/sb16_csp.h create mode 100644 include/sound/sdca.h create mode 100644 include/sound/sdca_asoc.h create mode 100644 include/sound/sdca_fdl.h create mode 100644 include/sound/sdca_function.h create mode 100644 include/sound/sdca_hid.h create mode 100644 include/sound/sdca_interrupts.h create mode 100644 include/sound/sdca_jack.h create mode 100644 include/sound/sdca_regmap.h create mode 100644 include/sound/sdca_ump.h create mode 100644 include/sound/sdw.h create mode 100644 include/sound/seq_device.h create mode 100644 include/sound/seq_kernel.h create mode 100644 include/sound/seq_midi_emul.h create mode 100644 include/sound/seq_midi_event.h create mode 100644 include/sound/seq_oss.h create mode 100644 include/sound/seq_oss_legacy.h create mode 100644 include/sound/seq_virmidi.h create mode 100644 include/sound/sh_dac_audio.h create mode 100644 include/sound/sh_fsi.h create mode 100644 include/sound/simple_card.h create mode 100644 include/sound/simple_card_utils.h create mode 100644 include/sound/snd_wavefront.h create mode 100644 include/sound/soc-acpi-intel-match.h create mode 100644 include/sound/soc-acpi-intel-ssp-common.h create mode 100644 include/sound/soc-acpi.h create mode 100644 include/sound/soc-card.h create mode 100644 include/sound/soc-component.h create mode 100644 include/sound/soc-dai.h create mode 100644 include/sound/soc-dapm.h create mode 100644 include/sound/soc-dpcm.h create mode 100644 include/sound/soc-jack.h create mode 100644 include/sound/soc-link.h create mode 100644 include/sound/soc-topology.h create mode 100644 include/sound/soc-usb.h create mode 100644 include/sound/soc.h create mode 100644 include/sound/soc_sdw_utils.h create mode 100644 include/sound/sof.h create mode 100644 include/sound/sof/channel_map.h create mode 100644 include/sound/sof/control.h create mode 100644 include/sound/sof/dai-amd.h create mode 100644 include/sound/sof/dai-imx.h create mode 100644 include/sound/sof/dai-intel.h create mode 100644 include/sound/sof/dai-mediatek.h create mode 100644 include/sound/sof/dai.h create mode 100644 include/sound/sof/debug.h create mode 100644 include/sound/sof/ext_manifest.h create mode 100644 include/sound/sof/ext_manifest4.h create mode 100644 include/sound/sof/header.h create mode 100644 include/sound/sof/info.h create mode 100644 include/sound/sof/ipc4/header.h create mode 100644 include/sound/sof/pm.h create mode 100644 include/sound/sof/stream.h create mode 100644 include/sound/sof/topology.h create mode 100644 include/sound/sof/trace.h create mode 100644 include/sound/sof/xtensa.h create mode 100644 include/sound/soundfont.h create mode 100644 include/sound/spear_dma.h create mode 100644 include/sound/spear_spdif.h create mode 100644 include/sound/sta32x.h create mode 100644 include/sound/sta350.h create mode 100644 include/sound/tas2552-plat.h create mode 100644 include/sound/tas2563-tlv.h create mode 100644 include/sound/tas2770-tlv.h create mode 100644 include/sound/tas2781-comlib-i2c.h create mode 100644 include/sound/tas2781-dsp.h create mode 100644 include/sound/tas2781-tlv.h create mode 100644 include/sound/tas2781.h create mode 100644 include/sound/tas2x20-tlv.h create mode 100644 include/sound/tas5086.h create mode 100644 include/sound/tas5825-tlv.h create mode 100644 include/sound/tea6330t.h create mode 100644 include/sound/timer.h create mode 100644 include/sound/tlv.h create mode 100644 include/sound/ump.h create mode 100644 include/sound/ump_convert.h create mode 100644 include/sound/ump_msg.h create mode 100644 include/sound/util_mem.h create mode 100644 include/sound/vx_core.h create mode 100644 include/sound/wavefront.h create mode 100644 include/sound/wm0010.h create mode 100644 include/sound/wm2000.h create mode 100644 include/sound/wm2200.h create mode 100644 include/sound/wm5100.h create mode 100644 include/sound/wm8903.h create mode 100644 include/sound/wm8904.h create mode 100644 include/sound/wm8955.h create mode 100644 include/sound/wm8960.h create mode 100644 include/sound/wm8962.h create mode 100644 include/sound/wm8993.h create mode 100644 include/sound/wm8996.h create mode 100644 include/sound/wm9081.h create mode 100644 include/sound/wm9090.h create mode 100644 include/sound/wss.h (limited to 'include/sound') diff --git a/include/sound/ac97/codec.h b/include/sound/ac97/codec.h new file mode 100644 index 000000000..69aa7ee15 --- /dev/null +++ b/include/sound/ac97/codec.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016 Robert Jarzmik + */ + +#ifndef __SOUND_AC97_CODEC2_H +#define __SOUND_AC97_CODEC2_H + +#include + +#define AC97_ID(vendor_id1, vendor_id2) \ + ((((vendor_id1) & 0xffff) << 16) | ((vendor_id2) & 0xffff)) +#define AC97_DRIVER_ID(vendor_id1, vendor_id2, mask_id1, mask_id2, _data) \ + { .id = (((vendor_id1) & 0xffff) << 16) | ((vendor_id2) & 0xffff), \ + .mask = (((mask_id1) & 0xffff) << 16) | ((mask_id2) & 0xffff), \ + .data = (_data) } + +struct ac97_controller; +struct clk; + +/** + * struct ac97_id - matches a codec device and driver on an ac97 bus + * @id: The significant bits if the codec vendor ID1 and ID2 + * @mask: Bitmask specifying which bits of the id field are significant when + * matching. A driver binds to a device when : + * ((vendorID1 << 8 | vendorID2) & (mask_id1 << 8 | mask_id2)) == id. + * @data: Private data used by the driver. + */ +struct ac97_id { + unsigned int id; + unsigned int mask; + void *data; +}; + +/** + * struct ac97_codec_device - a ac97 codec + * @dev: the core device + * @vendor_id: the vendor_id of the codec, as sensed on the AC-link + * @num: the codec number, 0 is primary, 1 is first slave, etc ... + * @clk: the clock BIT_CLK provided by the codec + * @ac97_ctrl: ac97 digital controller on the same AC-link + * + * This is the device instantiated for each codec living on a AC-link. There are + * normally 0 to 4 codec devices per AC-link, and all of them are controlled by + * an AC97 digital controller. + */ +struct ac97_codec_device { + struct device dev; + unsigned int vendor_id; + unsigned int num; + struct clk *clk; + struct ac97_controller *ac97_ctrl; +}; + +/** + * struct ac97_codec_driver - a ac97 codec driver + * @driver: the device driver structure + * @probe: the function called when a ac97_codec_device is matched + * @remove: the function called when the device is unbound/removed + * @shutdown: shutdown function (might be NULL) + * @id_table: ac97 vendor_id match table, { } member terminated + */ +struct ac97_codec_driver { + struct device_driver driver; + int (*probe)(struct ac97_codec_device *); + void (*remove)(struct ac97_codec_device *dev); + void (*shutdown)(struct ac97_codec_device *); + const struct ac97_id *id_table; +}; + +static inline struct ac97_codec_device *to_ac97_device(struct device *d) +{ + return container_of(d, struct ac97_codec_device, dev); +} + +#define to_ac97_driver(__drv) container_of_const(__drv, struct ac97_codec_driver, driver) + +#if IS_ENABLED(CONFIG_AC97_BUS_NEW) +int snd_ac97_codec_driver_register(struct ac97_codec_driver *drv); +void snd_ac97_codec_driver_unregister(struct ac97_codec_driver *drv); +#else +static inline int +snd_ac97_codec_driver_register(struct ac97_codec_driver *drv) +{ + return 0; +} +static inline void +snd_ac97_codec_driver_unregister(struct ac97_codec_driver *drv) +{ +} +#endif + + +static inline struct device * +ac97_codec_dev2dev(struct ac97_codec_device *adev) +{ + return &adev->dev; +} + +static inline void *ac97_get_drvdata(struct ac97_codec_device *adev) +{ + return dev_get_drvdata(ac97_codec_dev2dev(adev)); +} + +static inline void ac97_set_drvdata(struct ac97_codec_device *adev, + void *data) +{ + dev_set_drvdata(ac97_codec_dev2dev(adev), data); +} + +static inline void *snd_ac97_codec_get_platdata(const struct ac97_codec_device *adev) +{ + return NULL; +} + +#endif diff --git a/include/sound/ac97/compat.h b/include/sound/ac97/compat.h new file mode 100644 index 000000000..57e19afa3 --- /dev/null +++ b/include/sound/ac97/compat.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016 Robert Jarzmik + * + * This file is for backward compatibility with snd_ac97 structure and its + * multiple usages, such as the snd_ac97_bus and snd_ac97_build_ops. + */ + +#ifndef AC97_COMPAT_H +#define AC97_COMPAT_H + +#include + +struct snd_ac97 *snd_ac97_compat_alloc(struct ac97_codec_device *adev); +void snd_ac97_compat_release(struct snd_ac97 *ac97); + +#endif diff --git a/include/sound/ac97/controller.h b/include/sound/ac97/controller.h new file mode 100644 index 000000000..d5895ea39 --- /dev/null +++ b/include/sound/ac97/controller.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016 Robert Jarzmik + */ + +#ifndef AC97_CONTROLLER_H +#define AC97_CONTROLLER_H + +#include +#include + +#define AC97_BUS_MAX_CODECS 4 +#define AC97_SLOTS_AVAILABLE_ALL 0xf + +struct ac97_controller_ops; + +/** + * struct ac97_controller - The AC97 controller of the AC-Link + * @ops: the AC97 operations. + * @controllers: linked list of all existing controllers. + * @adap: the shell device ac97-%d, ie. ac97 adapter + * @nr: the number of the shell device + * @slots_available: the mask of accessible/scanable codecs. + * @parent: the device providing the AC97 controller. + * @codecs: the 4 possible AC97 codecs (NULL if none found). + * @codecs_pdata: platform_data for each codec (NULL if no pdata). + * + * This structure is internal to AC97 bus, and should not be used by the + * controllers themselves, excepting for using @dev. + */ +struct ac97_controller { + const struct ac97_controller_ops *ops; + struct list_head controllers; + struct device adap; + int nr; + unsigned short slots_available; + struct device *parent; + struct ac97_codec_device *codecs[AC97_BUS_MAX_CODECS]; + void *codecs_pdata[AC97_BUS_MAX_CODECS]; +}; + +/** + * struct ac97_controller_ops - The AC97 operations + * @reset: Cold reset of the AC97 AC-Link. + * @warm_reset: Warm reset of the AC97 AC-Link. + * @read: Read of a single AC97 register. + * Returns the register value or a negative error code. + * @write: Write of a single AC97 register. + * + * These are the basic operation an AC97 controller must provide for an AC97 + * access functions. Amongst these, all but the last 2 are mandatory. + * The slot number is also known as the AC97 codec number, between 0 and 3. + */ +struct ac97_controller_ops { + void (*reset)(struct ac97_controller *adrv); + void (*warm_reset)(struct ac97_controller *adrv); + int (*write)(struct ac97_controller *adrv, int slot, + unsigned short reg, unsigned short val); + int (*read)(struct ac97_controller *adrv, int slot, unsigned short reg); +}; + +#if IS_ENABLED(CONFIG_AC97_BUS_NEW) +struct ac97_controller *snd_ac97_controller_register( + const struct ac97_controller_ops *ops, struct device *dev, + unsigned short slots_available); +void snd_ac97_controller_unregister(struct ac97_controller *ac97_ctrl); +#else +static inline struct ac97_controller * +snd_ac97_controller_register(const struct ac97_controller_ops *ops, + struct device *dev, + unsigned short slots_available) +{ + return ERR_PTR(-ENODEV); +} + +static inline void +snd_ac97_controller_unregister(struct ac97_controller *ac97_ctrl) +{ +} +#endif + +#endif diff --git a/include/sound/ac97/regs.h b/include/sound/ac97/regs.h new file mode 100644 index 000000000..843f73f37 --- /dev/null +++ b/include/sound/ac97/regs.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) by Jaroslav Kysela + * Universal interface for Audio Codec '97 + * + * For more details look to AC '97 component specification revision 2.1 + * by Intel Corporation (http://developer.intel.com). + */ +/* + * AC'97 codec registers + */ + +#define AC97_RESET 0x00 /* Reset */ +#define AC97_MASTER 0x02 /* Master Volume */ +#define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */ +#define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */ +#define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */ +#define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */ +#define AC97_PHONE 0x0c /* Phone Volume (optional) */ +#define AC97_MIC 0x0e /* MIC Volume */ +#define AC97_LINE 0x10 /* Line In Volume */ +#define AC97_CD 0x12 /* CD Volume */ +#define AC97_VIDEO 0x14 /* Video Volume (optional) */ +#define AC97_AUX 0x16 /* AUX Volume (optional) */ +#define AC97_PCM 0x18 /* PCM Volume */ +#define AC97_REC_SEL 0x1a /* Record Select */ +#define AC97_REC_GAIN 0x1c /* Record Gain */ +#define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */ +#define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */ +#define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */ +#define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */ +#define AC97_POWERDOWN 0x26 /* Powerdown control / status */ +/* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */ +#define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */ +#define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */ +#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */ +#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */ +#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */ +#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */ +#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */ +#define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */ +#define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */ +#define AC97_SPDIF 0x3a /* S/PDIF control */ +/* range 0x3c-0x58 - MODEM */ +#define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */ +#define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */ +#define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */ +#define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */ +#define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */ +#define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */ +#define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */ +#define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */ +#define AC97_GPIO_CFG 0x4c /* GPIO Configuration */ +#define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */ +#define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */ +#define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */ +#define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */ +#define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */ +/* range 0x5a-0x7b - Vendor Specific */ +#define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */ +#define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */ +/* range 0x60-0x6f (page 1) - extended codec registers */ +#define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */ +#define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */ +#define AC97_PCI_SID 0x64 /* PCI Subsystem ID */ +#define AC97_FUNC_SELECT 0x66 /* Function Select */ +#define AC97_FUNC_INFO 0x68 /* Function Information */ +#define AC97_SENSE_INFO 0x6a /* Sense Details */ + +/* volume controls */ +#define AC97_MUTE_MASK_MONO 0x8000 +#define AC97_MUTE_MASK_STEREO 0x8080 + +/* slot allocation */ +#define AC97_SLOT_TAG 0 +#define AC97_SLOT_CMD_ADDR 1 +#define AC97_SLOT_CMD_DATA 2 +#define AC97_SLOT_PCM_LEFT 3 +#define AC97_SLOT_PCM_RIGHT 4 +#define AC97_SLOT_MODEM_LINE1 5 +#define AC97_SLOT_PCM_CENTER 6 +#define AC97_SLOT_MIC 6 /* input */ +#define AC97_SLOT_SPDIF_LEFT1 6 +#define AC97_SLOT_PCM_SLEFT 7 /* surround left */ +#define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */ +#define AC97_SLOT_SPDIF_LEFT 7 +#define AC97_SLOT_PCM_SRIGHT 8 /* surround right */ +#define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */ +#define AC97_SLOT_SPDIF_RIGHT 8 +#define AC97_SLOT_LFE 9 +#define AC97_SLOT_SPDIF_RIGHT1 9 +#define AC97_SLOT_MODEM_LINE2 10 +#define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */ +#define AC97_SLOT_SPDIF_LEFT2 10 +#define AC97_SLOT_HANDSET 11 /* output */ +#define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */ +#define AC97_SLOT_SPDIF_RIGHT2 11 +#define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */ +#define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */ + +/* basic capabilities (reset register) */ +#define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */ +#define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */ +#define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */ +#define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */ +#define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */ +#define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */ +#define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */ +#define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */ +#define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */ +#define AC97_BC_DAC_MASK 0x00c0 +#define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */ +#define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */ +#define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */ +#define AC97_BC_ADC_MASK 0x0300 +#define AC97_BC_3D_TECH_ID_MASK 0x7c00 /* Per-vendor ID of 3D enhancement */ + +/* general purpose */ +#define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */ +#define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */ +#define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */ + +/* powerdown bits */ +#define AC97_PD_ADC_STATUS 0x0001 /* ADC status (RO) */ +#define AC97_PD_DAC_STATUS 0x0002 /* DAC status (RO) */ +#define AC97_PD_MIXER_STATUS 0x0004 /* Analog mixer status (RO) */ +#define AC97_PD_VREF_STATUS 0x0008 /* Vref status (RO) */ +#define AC97_PD_PR0 0x0100 /* Power down PCM ADCs and input MUX */ +#define AC97_PD_PR1 0x0200 /* Power down PCM front DAC */ +#define AC97_PD_PR2 0x0400 /* Power down Mixer (Vref still on) */ +#define AC97_PD_PR3 0x0800 /* Power down Mixer (Vref off) */ +#define AC97_PD_PR4 0x1000 /* Power down AC-Link */ +#define AC97_PD_PR5 0x2000 /* Disable internal clock usage */ +#define AC97_PD_PR6 0x4000 /* Headphone amplifier */ +#define AC97_PD_EAPD 0x8000 /* External Amplifer Power Down (EAPD) */ + +/* extended audio ID bit defines */ +#define AC97_EI_VRA 0x0001 /* Variable bit rate supported */ +#define AC97_EI_DRA 0x0002 /* Double rate supported */ +#define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */ +#define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */ +#define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */ +#define AC97_EI_DACS_SLOT_SHIFT 4 +#define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */ +#define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */ +#define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */ +#define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */ +#define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */ +#define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */ +#define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */ +#define AC97_EI_REV_SHIFT 10 +#define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */ +#define AC97_EI_ADDR_SHIFT 14 + +/* extended audio status and control bit defines */ +#define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */ +#define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */ +#define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */ +#define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */ +#define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */ +#define AC97_EA_SPSA_SLOT_SHIFT 4 +#define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */ +#define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */ +#define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */ +#define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */ +#define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */ +#define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */ +#define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */ +#define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */ +#define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */ +#define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */ +#define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */ +#define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */ +#define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */ + +/* S/PDIF control bit defines */ +#define AC97_SC_PRO 0x0001 /* Professional status */ +#define AC97_SC_NAUDIO 0x0002 /* Non audio stream */ +#define AC97_SC_COPY 0x0004 /* Copyright status */ +#define AC97_SC_PRE 0x0008 /* Preemphasis status */ +#define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */ +#define AC97_SC_CC_SHIFT 4 +#define AC97_SC_L 0x0800 /* Generation Level status */ +#define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */ +#define AC97_SC_SPSR_SHIFT 12 +#define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */ +#define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */ +#define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */ +#define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */ +#define AC97_SC_V 0x8000 /* Validity status */ + +/* Interrupt and Paging bit defines (AC'97 2.3) */ +#define AC97_PAGE_MASK 0x000f /* Page Selector */ +#define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */ +#define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */ +#define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */ +#define AC97_INT_SENSE 0x1000 /* Sense Cycle */ +#define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */ +#define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */ +#define AC97_INT_STATUS 0x8000 /* Interrupt Status */ + +/* extended modem ID bit defines */ +#define AC97_MEI_LINE1 0x0001 /* Line1 present */ +#define AC97_MEI_LINE2 0x0002 /* Line2 present */ +#define AC97_MEI_HANDSET 0x0004 /* Handset present */ +#define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */ +#define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */ +#define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */ +#define AC97_MEI_ADDR_SHIFT 14 + +/* extended modem status and control bit defines */ +#define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */ +#define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */ +#define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */ +#define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */ +#define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */ +#define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */ +#define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */ +#define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */ +#define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */ +#define AC97_MEA_PRB 0x0200 /* reserved */ +#define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */ +#define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */ +#define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */ +#define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */ +#define AC97_MEA_PRG 0x4000 /* HADC power down (high) */ +#define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */ + +/* modem gpio status defines */ +#define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */ +#define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */ +#define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */ +#define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */ +#define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */ +#define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */ +#define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */ +#define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */ +#define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */ +#define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */ +#define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */ +#define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */ +#define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */ +#define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */ +#define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */ +#define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */ + diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h new file mode 100644 index 000000000..4bd3be3a3 --- /dev/null +++ b/include/sound/ac97_codec.h @@ -0,0 +1,421 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) by Jaroslav Kysela + * Universal interface for Audio Codec '97 + * + * For more details look to AC '97 component specification revision 2.1 + * by Intel Corporation (http://developer.intel.com). + */ + +#ifndef __SOUND_AC97_CODEC_H +#define __SOUND_AC97_CODEC_H + +#include +#include +#include +#include +#include +#include +#include + +/* maximum number of devices on the AC97 bus */ +#define AC97_BUS_MAX_DEVICES 4 + +/* specific - SigmaTel */ +#define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */ +#define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */ +#define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */ +#define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */ +#define AC97_SIGMATEL_DAC2INVERT 0x6e +#define AC97_SIGMATEL_BIAS1 0x70 +#define AC97_SIGMATEL_BIAS2 0x72 +#define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */ +#define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */ +#define AC97_SIGMATEL_CIC1 0x76 +#define AC97_SIGMATEL_CIC2 0x78 + +/* specific - Analog Devices */ +#define AC97_AD_TEST 0x5a /* test register */ +#define AC97_AD_TEST2 0x5c /* undocumented test register 2 */ +#define AC97_AD_HPFD_SHIFT 12 /* High Pass Filter Disable */ +#define AC97_AD_CODEC_CFG 0x70 /* codec configuration */ +#define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */ +#define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */ +#define AC97_AD_MISC 0x76 /* Misc Control Bits */ +#define AC97_AD_VREFD_SHIFT 2 /* V_REFOUT Disable (AD1888) */ + +/* specific - Cirrus Logic */ +#define AC97_CSR_ACMODE 0x5e /* AC Mode Register */ +#define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */ +#define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */ +#define AC97_CSR_SERIAL 0x6a /* Serial Port Control */ +#define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */ +#define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */ +#define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */ + +/* specific - Conexant */ +#define AC97_CXR_AUDIO_MISC 0x5c +#define AC97_CXR_SPDIFEN (1<<3) +#define AC97_CXR_COPYRGT (1<<2) +#define AC97_CXR_SPDIF_MASK (3<<0) +#define AC97_CXR_SPDIF_PCM 0x0 +#define AC97_CXR_SPDIF_AC3 0x2 + +/* specific - ALC */ +#define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60 +/* S/PDIF input status 1 bit defines */ +#define AC97_ALC650_PRO 0x0001 /* Professional status */ +#define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */ +#define AC97_ALC650_COPY 0x0004 /* Copyright status */ +#define AC97_ALC650_PRE 0x0038 /* Preemphasis status */ +#define AC97_ALC650_PRE_SHIFT 3 +#define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */ +#define AC97_ALC650_MODE_SHIFT 6 +#define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */ +#define AC97_ALC650_CC_SHIFT 8 +#define AC97_ALC650_L 0x8000 /* Generation Level status */ + +#define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62 +/* S/PDIF input status 2 bit defines */ +#define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */ +#define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */ +#define AC97_ALC650_CHANNEL_SHIFT 4 +#define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */ +#define AC97_ALC650_SPSR_SHIFT 8 +#define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */ +#define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */ +#define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */ +#define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */ +#define AC97_ALC650_CLOCK_SHIFT 12 +#define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */ +#define AC97_ALC650_V 0x8000 /* Validity status */ + +#define AC97_ALC650_SURR_DAC_VOL 0x64 +#define AC97_ALC650_LFE_DAC_VOL 0x66 +#define AC97_ALC650_UNKNOWN1 0x68 +#define AC97_ALC650_MULTICH 0x6a +#define AC97_ALC650_UNKNOWN2 0x6c +#define AC97_ALC650_REVISION 0x6e +#define AC97_ALC650_UNKNOWN3 0x70 +#define AC97_ALC650_UNKNOWN4 0x72 +#define AC97_ALC650_MISC 0x74 +#define AC97_ALC650_GPIO_SETUP 0x76 +#define AC97_ALC650_GPIO_STATUS 0x78 +#define AC97_ALC650_CLOCK 0x7a + +/* specific - Yamaha YMF7x3 */ +#define AC97_YMF7X3_DIT_CTRL 0x66 /* DIT Control (YMF743) / 2 (YMF753) */ +#define AC97_YMF7X3_3D_MODE_SEL 0x68 /* 3D Mode Select */ + +/* specific - C-Media */ +#define AC97_CM9738_VENDOR_CTRL 0x5a +#define AC97_CM9739_MULTI_CHAN 0x64 +#define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */ +#define AC97_CM9739_SPDIF_CTRL 0x6c + +/* specific - wolfson */ +#define AC97_WM97XX_FMIXER_VOL 0x72 +#define AC97_WM9704_RMIXER_VOL 0x74 +#define AC97_WM9704_TEST 0x5a +#define AC97_WM9704_RPCM_VOL 0x70 +#define AC97_WM9711_OUT3VOL 0x16 + + +/* ac97->scaps */ +#define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */ +#define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */ +#define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */ +#define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */ +#define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */ +#define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */ +#define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */ +#define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */ +#define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */ +#define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */ +#define AC97_SCAP_EAPD_LED (1<<10) /* EAPD as mute LED */ +#define AC97_SCAP_POWER_SAVE (1<<11) /* capable for aggressive power-saving */ + +/* ac97->flags */ +#define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */ +#define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */ +#define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */ +#define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */ +#define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */ +#define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */ +#define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */ +#define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */ +#define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */ +#define AC97_MODEM_PATCH (1<<9) /* modem patch */ +#define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */ +#define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */ +#define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */ +#define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */ +#define AC97_HAS_NO_CD (1<<14) /* no CD volume */ +#define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */ +#define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */ +#define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */ +#define AC97_HAS_NO_AUX (1<<18) /* no standard AC97 AUX volume and mute */ +#define AC97_HAS_8CH (1<<19) /* supports 8-channel output */ + +/* rates indexes */ +#define AC97_RATES_FRONT_DAC 0 +#define AC97_RATES_SURR_DAC 1 +#define AC97_RATES_LFE_DAC 2 +#define AC97_RATES_ADC 3 +#define AC97_RATES_MIC_ADC 4 +#define AC97_RATES_SPDIF 5 + +#define AC97_NUM_GPIOS 16 +/* + * + */ + +struct snd_ac97; +struct snd_ac97_gpio_priv; +struct snd_pcm_chmap; + +struct snd_ac97_build_ops { + int (*build_3d) (struct snd_ac97 *ac97); + int (*build_specific) (struct snd_ac97 *ac97); + int (*build_spdif) (struct snd_ac97 *ac97); + int (*build_post_spdif) (struct snd_ac97 *ac97); +#ifdef CONFIG_PM + void (*suspend) (struct snd_ac97 *ac97); + void (*resume) (struct snd_ac97 *ac97); +#endif + void (*update_jacks) (struct snd_ac97 *ac97); /* for jack-sharing */ +}; + +struct snd_ac97_bus_ops { + void (*reset) (struct snd_ac97 *ac97); + void (*warm_reset)(struct snd_ac97 *ac97); + void (*write) (struct snd_ac97 *ac97, unsigned short reg, unsigned short val); + unsigned short (*read) (struct snd_ac97 *ac97, unsigned short reg); + void (*wait) (struct snd_ac97 *ac97); + void (*init) (struct snd_ac97 *ac97); +}; + +struct snd_ac97_bus { + /* -- lowlevel (hardware) driver specific -- */ + const struct snd_ac97_bus_ops *ops; + void *private_data; + void (*private_free) (struct snd_ac97_bus *bus); + /* --- */ + struct snd_card *card; + unsigned short num; /* bus number */ + unsigned short no_vra: 1, /* bridge doesn't support VRA */ + dra: 1, /* bridge supports double rate */ + isdin: 1;/* independent SDIN */ + unsigned int clock; /* AC'97 base clock (usually 48000Hz) */ + spinlock_t bus_lock; /* used mainly for slot allocation */ + unsigned short used_slots[2][4]; /* actually used PCM slots */ + unsigned short pcms_count; /* count of PCMs */ + struct ac97_pcm *pcms; + struct snd_ac97 *codec[4]; + struct snd_info_entry *proc; +}; + +/* static resolution table */ +struct snd_ac97_res_table { + unsigned short reg; /* register */ + unsigned short bits; /* resolution bitmask */ +}; + +struct snd_ac97_template { + void *private_data; + void (*private_free) (struct snd_ac97 *ac97); + struct pci_dev *pci; /* assigned PCI device - used for quirks */ + unsigned short num; /* number of codec: 0 = primary, 1 = secondary */ + unsigned short addr; /* physical address of codec [0-3] */ + unsigned int scaps; /* driver capabilities */ + const struct snd_ac97_res_table *res_table; /* static resolution */ +}; + +struct snd_ac97 { + /* -- lowlevel (hardware) driver specific -- */ + const struct snd_ac97_build_ops *build_ops; + void *private_data; + void (*private_free) (struct snd_ac97 *ac97); + /* --- */ + struct snd_ac97_bus *bus; + struct pci_dev *pci; /* assigned PCI device - used for quirks */ + struct snd_info_entry *proc; + struct snd_info_entry *proc_regs; + unsigned short subsystem_vendor; + unsigned short subsystem_device; + struct mutex reg_mutex; + struct mutex page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */ + unsigned short num; /* number of codec: 0 = primary, 1 = secondary */ + unsigned short addr; /* physical address of codec [0-3] */ + unsigned int id; /* identification of codec */ + unsigned short caps; /* capabilities (register 0) */ + unsigned short ext_id; /* extended feature identification (register 28) */ + unsigned short ext_mid; /* extended modem ID (register 3C) */ + const struct snd_ac97_res_table *res_table; /* static resolution */ + unsigned int scaps; /* driver capabilities */ + unsigned int flags; /* specific code */ + unsigned int rates[6]; /* see AC97_RATES_* defines */ + unsigned int spdif_status; + unsigned short regs[0x80]; /* register cache */ + DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */ + union { /* vendor specific code */ + struct { + unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69 + unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69 + unsigned short id[3]; // codec IDs (lower 16-bit word) + unsigned short pcmreg[3]; // PCM registers + unsigned short codec_cfg[3]; // CODEC_CFG bits + unsigned char swap_mic_linein; // AD1986/AD1986A only + unsigned char lo_as_master; /* LO as master */ + } ad18xx; + unsigned int dev_flags; /* device specific */ + } spec; + /* jack-sharing info */ + unsigned char indep_surround; + unsigned char channel_mode; + +#ifdef CONFIG_SND_AC97_POWER_SAVE + unsigned int power_up; /* power states */ + struct delayed_work power_work; +#endif + struct device dev; + struct snd_ac97_gpio_priv *gpio_priv; + + struct snd_pcm_chmap *chmaps[2]; /* channel-maps (optional) */ +}; + +#define to_ac97_t(d) container_of(d, struct snd_ac97, dev) + +/* conditions */ +static inline int ac97_is_audio(struct snd_ac97 * ac97) +{ + return (ac97->scaps & AC97_SCAP_AUDIO); +} +static inline int ac97_is_modem(struct snd_ac97 * ac97) +{ + return (ac97->scaps & AC97_SCAP_MODEM); +} +static inline int ac97_is_rev22(struct snd_ac97 * ac97) +{ + return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22; +} +static inline int ac97_can_amap(struct snd_ac97 * ac97) +{ + return (ac97->ext_id & AC97_EI_AMAP) != 0; +} +static inline int ac97_can_spdif(struct snd_ac97 * ac97) +{ + return (ac97->ext_id & AC97_EI_SPDIF) != 0; +} + +/* functions */ +/* create new AC97 bus */ +int snd_ac97_bus(struct snd_card *card, int num, + const struct snd_ac97_bus_ops *ops, + void *private_data, struct snd_ac97_bus **rbus); +/* create mixer controls */ +int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template, + struct snd_ac97 **rac97); +const char *snd_ac97_get_short_name(struct snd_ac97 *ac97); + +void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); +unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg); +void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); +int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); +int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value); +#ifdef CONFIG_SND_AC97_POWER_SAVE +int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup); +#else +static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, + int powerup) +{ + return 0; +} +#endif +#ifdef CONFIG_PM +void snd_ac97_suspend(struct snd_ac97 *ac97); +void snd_ac97_resume(struct snd_ac97 *ac97); +#else +static inline void snd_ac97_suspend(struct snd_ac97 *ac97) {} +static inline void snd_ac97_resume(struct snd_ac97 *ac97) {} +#endif +int snd_ac97_reset(struct snd_ac97 *ac97, bool try_warm, unsigned int id, + unsigned int id_mask); + +/* quirk types */ +enum { + AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */ + AC97_TUNE_NONE = 0, /* nothing extra to do */ + AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */ + AC97_TUNE_SWAP_HP, /* swap headphone and master controls */ + AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */ + AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */ + AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */ + AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */ + AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */ + AC97_TUNE_HP_MUTE_LED, /* EAPD bit works as mute LED, use headphone control as master */ +}; + +struct ac97_quirk { + unsigned short subvendor; /* PCI subsystem vendor id */ + unsigned short subdevice; /* PCI subsystem device id */ + unsigned short mask; /* device id bit mask, 0 = accept all */ + unsigned int codec_id; /* codec id (if any), 0 = accept all */ + const char *name; /* name shown as info */ + int type; /* quirk type above */ +}; + +int snd_ac97_tune_hardware(struct snd_ac97 *ac97, + const struct ac97_quirk *quirk, + const char *override); +int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate); + +/* + * PCM allocation + */ + +enum ac97_pcm_cfg { + AC97_PCM_CFG_FRONT = 2, + AC97_PCM_CFG_REAR = 10, /* alias surround */ + AC97_PCM_CFG_LFE = 11, /* center + lfe */ + AC97_PCM_CFG_40 = 4, /* front + rear */ + AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */ + AC97_PCM_CFG_SPDIF = 20 +}; + +struct ac97_pcm { + struct snd_ac97_bus *bus; + unsigned int stream: 1, /* stream type: 1 = capture */ + exclusive: 1, /* exclusive mode, don't override with other pcms */ + copy_flag: 1, /* lowlevel driver must fill all entries */ + spdif: 1; /* spdif pcm */ + unsigned short aslots; /* active slots */ + unsigned short cur_dbl; /* current double-rate state */ + unsigned int rates; /* available rates */ + struct { + unsigned short slots; /* driver input: requested AC97 slot numbers */ + unsigned short rslots[4]; /* allocated slots per codecs */ + unsigned char rate_table[4]; + struct snd_ac97 *codec[4]; /* allocated codecs */ + } r[2]; /* 0 = standard rates, 1 = double rates */ + unsigned long private_value; /* used by the hardware driver */ +}; + +int snd_ac97_pcm_assign(struct snd_ac97_bus *ac97, + unsigned short pcms_count, + const struct ac97_pcm *pcms); +int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate, + enum ac97_pcm_cfg cfg, unsigned short slots); +int snd_ac97_pcm_close(struct ac97_pcm *pcm); +int snd_ac97_pcm_double_rate_rules(struct snd_pcm_runtime *runtime); + +/* ad hoc AC97 device driver access */ +extern const struct bus_type ac97_bus_type; + +/* AC97 platform_data adding function */ +static inline void snd_ac97_dev_add_pdata(struct snd_ac97 *ac97, void *data) +{ + ac97->dev.platform_data = data; +} + +#endif /* __SOUND_AC97_CODEC_H */ diff --git a/include/sound/aci.h b/include/sound/aci.h new file mode 100644 index 000000000..36a761c98 --- /dev/null +++ b/include/sound/aci.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ACI_H_ +#define _ACI_H_ + +#define ACI_REG_COMMAND 0 /* write register offset */ +#define ACI_REG_STATUS 1 /* read register offset */ +#define ACI_REG_BUSY 2 /* busy register offset */ +#define ACI_REG_RDS 2 /* PCM20: RDS register offset */ +#define ACI_MINTIME 500 /* ACI time out limit */ + +#define ACI_SET_MUTE 0x0d +#define ACI_SET_POWERAMP 0x0f +#define ACI_SET_TUNERMUTE 0xa3 +#define ACI_SET_TUNERMONO 0xa4 +#define ACI_SET_IDE 0xd0 +#define ACI_SET_WSS 0xd1 +#define ACI_SET_SOLOMODE 0xd2 +#define ACI_SET_PREAMP 0x03 +#define ACI_GET_PREAMP 0x21 +#define ACI_WRITE_TUNE 0xa7 +#define ACI_READ_TUNERSTEREO 0xa8 +#define ACI_READ_TUNERSTATION 0xa9 +#define ACI_READ_VERSION 0xf1 +#define ACI_READ_IDCODE 0xf2 +#define ACI_INIT 0xff +#define ACI_STATUS 0xf0 +#define ACI_S_GENERAL 0x00 +#define ACI_ERROR_OP 0xdf + +/* ACI Mixer */ + +/* These are the values for the right channel GET registers. + Add an offset of 0x01 for the left channel register. + (left=right+0x01) */ + +#define ACI_GET_MASTER 0x03 +#define ACI_GET_MIC 0x05 +#define ACI_GET_LINE 0x07 +#define ACI_GET_CD 0x09 +#define ACI_GET_SYNTH 0x0b +#define ACI_GET_PCM 0x0d +#define ACI_GET_LINE1 0x10 /* Radio on PCM20 */ +#define ACI_GET_LINE2 0x12 + +#define ACI_GET_EQ1 0x22 /* from Bass ... */ +#define ACI_GET_EQ2 0x24 +#define ACI_GET_EQ3 0x26 +#define ACI_GET_EQ4 0x28 +#define ACI_GET_EQ5 0x2a +#define ACI_GET_EQ6 0x2c +#define ACI_GET_EQ7 0x2e /* ... to Treble */ + +/* And these are the values for the right channel SET registers. + For left channel access you have to add an offset of 0x08. + MASTER is an exception, which needs an offset of 0x01 */ + +#define ACI_SET_MASTER 0x00 +#define ACI_SET_MIC 0x30 +#define ACI_SET_LINE 0x31 +#define ACI_SET_CD 0x34 +#define ACI_SET_SYNTH 0x33 +#define ACI_SET_PCM 0x32 +#define ACI_SET_LINE1 0x35 /* Radio on PCM20 */ +#define ACI_SET_LINE2 0x36 + +#define ACI_SET_EQ1 0x40 /* from Bass ... */ +#define ACI_SET_EQ2 0x41 +#define ACI_SET_EQ3 0x42 +#define ACI_SET_EQ4 0x43 +#define ACI_SET_EQ5 0x44 +#define ACI_SET_EQ6 0x45 +#define ACI_SET_EQ7 0x46 /* ... to Treble */ + +struct snd_miro_aci { + struct snd_card *card; + unsigned long aci_port; + int aci_vendor; + int aci_product; + int aci_version; + int aci_amp; + int aci_preamp; + int aci_solomode; + + struct mutex aci_mutex; +}; + +int snd_aci_cmd(struct snd_miro_aci *aci, int write1, int write2, int write3); + +struct snd_miro_aci *snd_aci_get_aci(void); + +#endif /* _ACI_H_ */ + diff --git a/include/sound/acp63_chip_offset_byte.h b/include/sound/acp63_chip_offset_byte.h new file mode 100644 index 000000000..d746c1cb0 --- /dev/null +++ b/include/sound/acp63_chip_offset_byte.h @@ -0,0 +1,495 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ACP 6.3 Register Documentation + * + * Copyright 2022 Advanced Micro Devices, Inc. + */ + +#ifndef _acp_ip_OFFSET_HEADER +#define _acp_ip_OFFSET_HEADER + +/* Registers from ACP_DMA block */ +#define ACP_DMA_CNTL_0 0x0000000 +#define ACP_DMA_CNTL_1 0x0000004 +#define ACP_DMA_CNTL_2 0x0000008 +#define ACP_DMA_CNTL_3 0x000000C +#define ACP_DMA_CNTL_4 0x0000010 +#define ACP_DMA_CNTL_5 0x0000014 +#define ACP_DMA_CNTL_6 0x0000018 +#define ACP_DMA_CNTL_7 0x000001C +#define ACP_DMA_DSCR_STRT_IDX_0 0x0000020 +#define ACP_DMA_DSCR_STRT_IDX_1 0x0000024 +#define ACP_DMA_DSCR_STRT_IDX_2 0x0000028 +#define ACP_DMA_DSCR_STRT_IDX_3 0x000002C +#define ACP_DMA_DSCR_STRT_IDX_4 0x0000030 +#define ACP_DMA_DSCR_STRT_IDX_5 0x0000034 +#define ACP_DMA_DSCR_STRT_IDX_6 0x0000038 +#define ACP_DMA_DSCR_STRT_IDX_7 0x000003C +#define ACP_DMA_DSCR_CNT_0 0x0000040 +#define ACP_DMA_DSCR_CNT_1 0x0000044 +#define ACP_DMA_DSCR_CNT_2 0x0000048 +#define ACP_DMA_DSCR_CNT_3 0x000004C +#define ACP_DMA_DSCR_CNT_4 0x0000050 +#define ACP_DMA_DSCR_CNT_5 0x0000054 +#define ACP_DMA_DSCR_CNT_6 0x0000058 +#define ACP_DMA_DSCR_CNT_7 0x000005C +#define ACP_DMA_PRIO_0 0x0000060 +#define ACP_DMA_PRIO_1 0x0000064 +#define ACP_DMA_PRIO_2 0x0000068 +#define ACP_DMA_PRIO_3 0x000006C +#define ACP_DMA_PRIO_4 0x0000070 +#define ACP_DMA_PRIO_5 0x0000074 +#define ACP_DMA_PRIO_6 0x0000078 +#define ACP_DMA_PRIO_7 0x000007C +#define ACP_DMA_CUR_DSCR_0 0x0000080 +#define ACP_DMA_CUR_DSCR_1 0x0000084 +#define ACP_DMA_CUR_DSCR_2 0x0000088 +#define ACP_DMA_CUR_DSCR_3 0x000008C +#define ACP_DMA_CUR_DSCR_4 0x0000090 +#define ACP_DMA_CUR_DSCR_5 0x0000094 +#define ACP_DMA_CUR_DSCR_6 0x0000098 +#define ACP_DMA_CUR_DSCR_7 0x000009C +#define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0 +#define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4 +#define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8 +#define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC +#define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0 +#define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4 +#define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8 +#define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC +#define ACP_DMA_ERR_STS_0 0x00000C0 +#define ACP_DMA_ERR_STS_1 0x00000C4 +#define ACP_DMA_ERR_STS_2 0x00000C8 +#define ACP_DMA_ERR_STS_3 0x00000CC +#define ACP_DMA_ERR_STS_4 0x00000D0 +#define ACP_DMA_ERR_STS_5 0x00000D4 +#define ACP_DMA_ERR_STS_6 0x00000D8 +#define ACP_DMA_ERR_STS_7 0x00000DC +#define ACP_DMA_DESC_BASE_ADDR 0x00000E0 +#define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4 +#define ACP_DMA_CH_STS 0x00000E8 +#define ACP_DMA_CH_GROUP 0x00000EC +#define ACP_DMA_CH_RST_STS 0x00000F0 + +/* Registers from ACP_AXI2AXIATU block */ +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C +#define ACPAXI2AXI_ATU_CTRL 0x0000C40 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80 + +/* Registers from ACP_CLKRST block */ +#define ACP_SOFT_RESET 0x0001000 +#define ACP_CONTROL 0x0001004 +#define ACP_STATUS 0x0001008 +#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010 +#define ACP_ZSC_DSP_CTRL 0x0001014 +#define ACP_ZSC_STS 0x0001018 +#define ACP_PGFSM_CONTROL 0x0001024 +#define ACP_PGFSM_STATUS 0x0001028 +#define ACP_CLKMUX_SEL 0x000102C + +/* Registers from ACP_AON block */ +#define ACP_PME_EN 0x0001400 +#define ACP_DEVICE_STATE 0x0001404 +#define AZ_DEVICE_STATE 0x0001408 +#define ACP_PIN_CONFIG 0x0001440 +#define ACP_PAD_PULLUP_CTRL 0x0001444 +#define ACP_PAD_PULLDOWN_CTRL 0x0001448 +#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C +#define ACP_PAD_SCHMEN_CTRL 0x0001450 +#define ACP_SW0_PAD_KEEPER_EN 0x0001454 +#define ACP_SW0_WAKE_EN 0x0001458 +#define ACP_I2S_WAKE_EN 0x000145C +#define ACP_SW1_WAKE_EN 0x0001460 + +#define ACP_SW0_I2S_ERROR_REASON 0x00018B4 +#define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL 0x00018B8 +#define ACP_SW0_AUDIO0_TX_DMA_POS 0x00018BC +#define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL 0x00018C0 +#define ACP_SW0_AUDIO1_TX_DMA_POS 0x00018C4 +#define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL 0x00018C8 +#define ACP_SW0_AUDIO2_TX_DMA_POS 0x00018CC +#define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL 0x00018D0 +#define ACP_SW0_AUDIO0_DMA_POS 0x00018D4 +#define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL 0x00018D8 +#define ACP_SW0_AUDIO1_RX_DMA_POS 0x00018DC +#define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL 0x00018E0 +#define ACP_SW0_AUDIO2_RX_DMA_POS 0x00018E4 +#define ACP_ERROR_INTR_MASK1 0X0001974 +#define ACP_ERROR_INTR_MASK2 0X0001978 +#define ACP_ERROR_INTR_MASK3 0X000197C + +/* Registers from ACP_P1_MISC block */ +#define ACP_EXTERNAL_INTR_ENB 0x0001A00 +#define ACP_EXTERNAL_INTR_CNTL 0x0001A04 +#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08 +#define ACP_EXTERNAL_INTR_STAT 0x0001A0C +#define ACP_EXTERNAL_INTR_STAT1 0x0001A10 +#define ACP_ERROR_STATUS 0x0001A4C +#define ACP_SW1_I2S_ERROR_REASON 0x0001A50 +#define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL 0x0001A6C +#define ACP_SW1_AUDIO0_TX_DMA_POS 0x0001A70 +#define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL 0x0001A74 +#define ACP_SW1_AUDIO0_RX_DMA_POS 0x0001A78 +#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C +#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80 +#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84 +#define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL 0x0001A88 +#define ACP_SW1_AUDIO1_TX_DMA_POS 0x0001A8C +#define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL 0x0001A90 +#define ACP_SW1_AUDIO2_TX_DMA_POS 0x0001A94 +#define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL 0x0001A98 +#define ACP_SW1_AUDIO1_RX_DMA_POS 0x0001A9C +#define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL 0x0001AA0 +#define ACP_SW1_AUDIO2_RX_DMA_POS 0x0001AA4 +#define ACP_ERROR_INTR_MASK4 0X0001AEC +#define ACP_ERROR_INTR_MASK5 0X0001AF0 + +/* Registers from ACP_AUDIO_BUFFERS block */ +#define ACP_AUDIO0_RX_RINGBUFADDR 0x0002000 +#define ACP_AUDIO0_RX_RINGBUFSIZE 0x0002004 +#define ACP_AUDIO0_RX_LINKPOSITIONCNTR 0x0002008 +#define ACP_AUDIO0_RX_FIFOADDR 0x000200C +#define ACP_AUDIO0_RX_FIFOSIZE 0x0002010 +#define ACP_AUDIO0_RX_DMA_SIZE 0x0002014 +#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 +#define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x000201C +#define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0002020 +#define ACP_AUDIO0_TX_RINGBUFADDR 0x0002024 +#define ACP_AUDIO0_TX_RINGBUFSIZE 0x0002028 +#define ACP_AUDIO0_TX_LINKPOSITIONCNTR 0x000202C +#define ACP_AUDIO0_TX_FIFOADDR 0x0002030 +#define ACP_AUDIO0_TX_FIFOSIZE 0x0002034 +#define ACP_AUDIO0_TX_DMA_SIZE 0x0002038 +#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x000203C +#define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0002040 +#define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0002044 +#define ACP_AUDIO1_RX_RINGBUFADDR 0x0002048 +#define ACP_AUDIO1_RX_RINGBUFSIZE 0x000204C +#define ACP_AUDIO1_RX_LINKPOSITIONCNTR 0x0002050 +#define ACP_AUDIO1_RX_FIFOADDR 0x0002054 +#define ACP_AUDIO1_RX_FIFOSIZE 0x0002058 +#define ACP_AUDIO1_RX_DMA_SIZE 0x000205C +#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 +#define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0002064 +#define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0002068 +#define ACP_AUDIO1_TX_RINGBUFADDR 0x000206C +#define ACP_AUDIO1_TX_RINGBUFSIZE 0x0002070 +#define ACP_AUDIO1_TX_LINKPOSITIONCNTR 0x0002074 +#define ACP_AUDIO1_TX_FIFOADDR 0x0002078 +#define ACP_AUDIO1_TX_FIFOSIZE 0x000207C +#define ACP_AUDIO1_TX_DMA_SIZE 0x0002080 +#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 +#define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0002088 +#define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE 0x000208C +#define ACP_AUDIO2_RX_RINGBUFADDR 0x0002090 +#define ACP_AUDIO2_RX_RINGBUFSIZE 0x0002094 +#define ACP_AUDIO2_RX_LINKPOSITIONCNTR 0x0002098 +#define ACP_AUDIO2_RX_FIFOADDR 0x000209C +#define ACP_AUDIO2_RX_FIFOSIZE 0x00020A0 +#define ACP_AUDIO2_RX_DMA_SIZE 0x00020A4 +#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 +#define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x00020AC +#define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE 0x00020B0 +#define ACP_AUDIO2_TX_RINGBUFADDR 0x00020B4 +#define ACP_AUDIO2_TX_RINGBUFSIZE 0x00020B8 +#define ACP_AUDIO2_TX_LINKPOSITIONCNTR 0x00020BC +#define ACP_AUDIO2_TX_FIFOADDR 0x00020C0 +#define ACP_AUDIO2_TX_FIFOSIZE 0x00020C4 +#define ACP_AUDIO2_TX_DMA_SIZE 0x00020C8 +#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC +#define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 +#define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE 0x00020D4 + +/* Registers from ACP_I2S_TDM block */ +#define ACP_I2STDM_IER 0x0002400 +#define ACP_I2STDM_IRER 0x0002404 +#define ACP_I2STDM_RXFRMT 0x0002408 +#define ACP_I2STDM_ITER 0x000240C +#define ACP_I2STDM_TXFRMT 0x0002410 +#define ACP_I2STDM0_MSTRCLKGEN 0x0002414 +#define ACP_I2STDM1_MSTRCLKGEN 0x0002418 +#define ACP_I2STDM2_MSTRCLKGEN 0x000241C +#define ACP_I2STDM_REFCLKGEN 0x0002420 + +/* Registers from ACP_BT_TDM block */ +#define ACP_BTTDM_IER 0x0002800 +#define ACP_BTTDM_IRER 0x0002804 +#define ACP_BTTDM_RXFRMT 0x0002808 +#define ACP_BTTDM_ITER 0x000280C +#define ACP_BTTDM_TXFRMT 0x0002810 +#define ACP_HSTDM_IER 0x0002814 +#define ACP_HSTDM_IRER 0x0002818 +#define ACP_HSTDM_RXFRMT 0x000281C +#define ACP_HSTDM_ITER 0x0002820 +#define ACP_HSTDM_TXFRMT 0x0002824 + +/* Registers from ACP_WOV block */ +#define ACP_WOV_PDM_ENABLE 0x0002C04 +#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08 +#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C +#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10 +#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C +#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20 +#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24 +#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28 +#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C +#define ACP_WOV_PDM_VAD_CTRL 0x0002C30 +#define ACP_WOV_WAKE 0x0002C54 +#define ACP_WOV_BUFFER_STATUS 0x0002C58 +#define ACP_WOV_MISC_CTRL 0x0002C5C +#define ACP_WOV_CLK_CTRL 0x0002C60 +#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64 +#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68 +#define ACP_PDM_CLKDIV 0x0002C6C + +/* Registers from ACP_SW0_SWCLK block */ +#define ACP_SW0_EN 0x0003000 +#define ACP_SW0_EN_STATUS 0x0003004 +#define ACP_SW0_FRAMESIZE 0x0003008 +#define ACP_SW0_SSP_COUNTER 0x000300C +#define ACP_SW0_AUDIO0_TX_EN 0x0003010 +#define ACP_SW0_AUDIO0_TX_EN_STATUS 0x0003014 +#define ACP_SW0_AUDIO0_TX_FRAME_FORMAT 0x0003018 +#define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL 0x000301C +#define ACP_SW0_AUDIO0_TX_HCTRL_DP0 0x0003020 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP1 0x0003024 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP2 0x0003028 +#define ACP_SW0_AUDIO0_TX_HCTRL_DP3 0x000302C +#define ACP_SW0_AUDIO0_TX_OFFSET_DP0 0x0003030 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP1 0x0003034 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP2 0x0003038 +#define ACP_SW0_AUDIO0_TX_OFFSET_DP3 0x000303C +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003040 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003044 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2 0x0003048 +#define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3 0x000304C +#define ACP_SW0_AUDIO1_TX_EN 0x0003050 +#define ACP_SW0_AUDIO1_TX_EN_STATUS 0x0003054 +#define ACP_SW0_AUDIO1_TX_FRAME_FORMAT 0x0003058 +#define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL 0x000305C +#define ACP_SW0_AUDIO1_TX_HCTRL 0x0003060 +#define ACP_SW0_AUDIO1_TX_OFFSET 0x0003064 +#define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003068 +#define ACP_SW0_AUDIO2_TX_EN 0x000306C +#define ACP_SW0_AUDIO2_TX_EN_STATUS 0x0003070 +#define ACP_SW0_AUDIO2_TX_FRAME_FORMAT 0x0003074 +#define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL 0x0003078 +#define ACP_SW0_AUDIO2_TX_HCTRL 0x000307C +#define ACP_SW0_AUDIO2_TX_OFFSET 0x0003080 +#define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003084 +#define ACP_SW0_AUDIO0_RX_EN 0x0003088 +#define ACP_SW0_AUDIO0_RX_EN_STATUS 0x000308C +#define ACP_SW0_AUDIO0_RX_FRAME_FORMAT 0x0003090 +#define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL 0x0003094 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP0 0x0003098 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP1 0x000309C +#define ACP_SW0_AUDIO0_RX_HCTRL_DP2 0x0003100 +#define ACP_SW0_AUDIO0_RX_HCTRL_DP3 0x0003104 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP0 0x0003108 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP1 0x000310C +#define ACP_SW0_AUDIO0_RX_OFFSET_DP2 0x0003110 +#define ACP_SW0_AUDIO0_RX_OFFSET_DP3 0x0003114 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003118 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x000311C +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2 0x0003120 +#define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3 0x0003124 +#define ACP_SW0_AUDIO1_RX_EN 0x0003128 +#define ACP_SW0_AUDIO1_RX_EN_STATUS 0x000312C +#define ACP_SW0_AUDIO1_RX_FRAME_FORMAT 0x0003130 +#define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL 0x0003134 +#define ACP_SW0_AUDIO1_RX_HCTRL 0x0003138 +#define ACP_SW0_AUDIO1_RX_OFFSET 0x000313C +#define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003140 +#define ACP_SW0_AUDIO2_RX_EN 0x0003144 +#define ACP_SW0_AUDIO2_RX_EN_STATUS 0x0003148 +#define ACP_SW0_AUDIO2_RX_FRAME_FORMAT 0x000314C +#define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL 0x0003150 +#define ACP_SW0_AUDIO2_RX_HCTRL 0x0003154 +#define ACP_SW0_AUDIO2_RX_OFFSET 0x0003158 +#define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x000315C +#define ACP_SW0_BPT_PORT_EN 0x0003160 +#define ACP_SW0_BPT_PORT_EN_STATUS 0x0003164 +#define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0003168 +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL 0x000316C +#define ACP_SW0_BPT_PORT_HCTRL 0x0003170 +#define ACP_SW0_BPT_PORT_OFFSET 0x0003174 +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE 0x0003178 +#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x000317C +#define ACP_SW0_CLK_RESUME_CTRL 0x0003180 +#define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0003184 +#define ACP_SW0_BUS_RESET_CTRL 0x0003188 +#define ACP_SW0_PRBS_ERR_STATUS 0x000318C +#define ACP_SW0_IMM_CMD_UPPER_WORD 0x0003230 +#define ACP_SW0_IMM_CMD_LOWER_QWORD 0x0003234 +#define ACP_SW0_IMM_RESP_UPPER_WORD 0x0003238 +#define ACP_SW0_IMM_RESP_LOWER_QWORD 0x000323C +#define ACP_SW0_IMM_CMD_STS 0x0003240 +#define ACP_SW0_BRA_BASE_ADDRESS 0x0003244 +#define ACP_SW0_BRA_TRANSFER_SIZE 0x0003248 +#define ACP_SW0_BRA_DMA_BUSY 0x000324C +#define ACP_SW0_BRA_RESP 0x0003250 +#define ACP_SW0_BRA_RESP_FRAME_ADDR 0x0003254 +#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x0003258 +#define ACP_SW0_STATECHANGE_STATUS_0TO7 0x000325C +#define ACP_SW0_STATECHANGE_STATUS_8TO11 0x0003260 +#define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7 0x0003264 +#define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11 0x0003268 +#define ACP_SW0_CLK_FREQUENCY_CTRL 0x000326C +#define ACP_SW0_ERROR_INTR_MASK 0x0003270 +#define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x0003274 + +/* Registers from ACP_P1_AUDIO_BUFFERS block */ +#define ACP_P1_AUDIO0_RX_RINGBUFADDR 0x0003A00 +#define ACP_P1_AUDIO0_RX_RINGBUFSIZE 0x0003A04 +#define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR 0x0003A08 +#define ACP_P1_AUDIO0_RX_FIFOADDR 0x0003A0C +#define ACP_P1_AUDIO0_RX_FIFOSIZE 0x0003A10 +#define ACP_P1_AUDIO0_RX_DMA_SIZE 0x0003A14 +#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 +#define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C +#define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0003A20 +#define ACP_P1_AUDIO0_TX_RINGBUFADDR 0x0003A24 +#define ACP_P1_AUDIO0_TX_RINGBUFSIZE 0x0003A28 +#define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR 0x0003A2C +#define ACP_P1_AUDIO0_TX_FIFOADDR 0x0003A30 +#define ACP_P1_AUDIO0_TX_FIFOSIZE 0x0003A34 +#define ACP_P1_AUDIO0_TX_DMA_SIZE 0x0003A38 +#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C +#define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 +#define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0003A44 +#define ACP_P1_AUDIO1_RX_RINGBUFADDR 0x0003A48 +#define ACP_P1_AUDIO1_RX_RINGBUFSIZE 0x0003A4C +#define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR 0x0003A50 +#define ACP_P1_AUDIO1_RX_FIFOADDR 0x0003A54 +#define ACP_P1_AUDIO1_RX_FIFOSIZE 0x0003A58 +#define ACP_P1_AUDIO1_RX_DMA_SIZE 0x0003A5C +#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 +#define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 +#define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0003A68 +#define ACP_P1_AUDIO1_TX_RINGBUFADDR 0x0003A6C +#define ACP_P1_AUDIO1_TX_RINGBUFSIZE 0x0003A70 +#define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR 0x0003A74 +#define ACP_P1_AUDIO1_TX_FIFOADDR 0x0003A78 +#define ACP_P1_AUDIO1_TX_FIFOSIZE 0x0003A7C +#define ACP_P1_AUDIO1_TX_DMA_SIZE 0x0003A80 +#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 +#define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 +#define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE 0x0003A8C +#define ACP_P1_AUDIO2_RX_RINGBUFADDR 0x0003A90 +#define ACP_P1_AUDIO2_RX_RINGBUFSIZE 0x0003A94 +#define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR 0x0003A98 +#define ACP_P1_AUDIO2_RX_FIFOADDR 0x0003A9C +#define ACP_P1_AUDIO2_RX_FIFOSIZE 0x0003AA0 +#define ACP_P1_AUDIO2_RX_DMA_SIZE 0x0003AA4 +#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 +#define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC +#define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE 0x0003AB0 +#define ACP_P1_AUDIO2_TX_RINGBUFADDR 0x0003AB4 +#define ACP_P1_AUDIO2_TX_RINGBUFSIZE 0x0003AB8 +#define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR 0x0003ABC +#define ACP_P1_AUDIO2_TX_FIFOADDR 0x0003AC0 +#define ACP_P1_AUDIO2_TX_FIFOSIZE 0x0003AC4 +#define ACP_P1_AUDIO2_TX_DMA_SIZE 0x0003AC8 +#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC +#define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 +#define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE 0x0003AD4 + +/* Registers from ACP_SW1_SWCLK block */ +#define ACP_SW1_EN 0x0003C00 +#define ACP_SW1_EN_STATUS 0x0003C04 +#define ACP_SW1_FRAMESIZE 0x0003C08 +#define ACP_SW1_SSP_COUNTER 0x0003C0C +#define ACP_SW1_AUDIO1_TX_EN 0x0003C50 +#define ACP_SW1_AUDIO1_TX_EN_STATUS 0x0003C54 +#define ACP_SW1_AUDIO1_TX_FRAME_FORMAT 0x0003C58 +#define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL 0x0003C5C +#define ACP_SW1_AUDIO1_TX_HCTRL 0x0003C60 +#define ACP_SW1_AUDIO1_TX_OFFSET 0x0003C64 +#define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003C68 +#define ACP_SW1_AUDIO1_RX_EN 0x0003D28 +#define ACP_SW1_AUDIO1_RX_EN_STATUS 0x0003D2C +#define ACP_SW1_AUDIO1_RX_FRAME_FORMAT 0x0003D30 +#define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL 0x0003D34 +#define ACP_SW1_AUDIO1_RX_HCTRL 0x0003D38 +#define ACP_SW1_AUDIO1_RX_OFFSET 0x0003D3C +#define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003D40 +#define ACP_SW1_BPT_PORT_EN 0x0003D60 +#define ACP_SW1_BPT_PORT_EN_STATUS 0x0003D64 +#define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0003D68 +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL 0x0003D6C +#define ACP_SW1_BPT_PORT_HCTRL 0x0003D70 +#define ACP_SW1_BPT_PORT_OFFSET 0x0003D74 +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE 0x0003D78 +#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C +#define ACP_SW1_CLK_RESUME_CTRL 0x0003D80 +#define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0003D84 +#define ACP_SW1_BUS_RESET_CTRL 0x0003D88 +#define ACP_SW1_PRBS_ERR_STATUS 0x0003D8C + +/* Registers from ACP_SW1_ACLK block */ +#define ACP_SW1_CORB_BASE_ADDRESS 0x0003E00 +#define ACP_SW1_CORB_WRITE_POINTER 0x0003E04 +#define ACP_SW1_CORB_READ_POINTER 0x0003E08 +#define ACP_SW1_CORB_CONTROL 0x0003E0C +#define ACP_SW1_CORB_SIZE 0x0003E14 +#define ACP_SW1_RIRB_BASE_ADDRESS 0x0003E18 +#define ACP_SW1_RIRB_WRITE_POINTER 0x0003E1C +#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20 +#define ACP_SW1_RIRB_CONTROL 0x0003E24 +#define ACP_SW1_RIRB_SIZE 0x0003E28 +#define ACP_SW1_RIRB_FIFO_MIN_THDL 0x0003E2C +#define ACP_SW1_IMM_CMD_UPPER_WORD 0x0003E30 +#define ACP_SW1_IMM_CMD_LOWER_QWORD 0x0003E34 +#define ACP_SW1_IMM_RESP_UPPER_WORD 0x0003E38 +#define ACP_SW1_IMM_RESP_LOWER_QWORD 0x0003E3C +#define ACP_SW1_IMM_CMD_STS 0x0003E40 +#define ACP_SW1_BRA_BASE_ADDRESS 0x0003E44 +#define ACP_SW1_BRA_TRANSFER_SIZE 0x0003E48 +#define ACP_SW1_BRA_DMA_BUSY 0x0003E4C +#define ACP_SW1_BRA_RESP 0x0003E50 +#define ACP_SW1_BRA_RESP_FRAME_ADDR 0x0003E54 +#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x0003E58 +#define ACP_SW1_STATECHANGE_STATUS_0TO7 0x0003E5C +#define ACP_SW1_STATECHANGE_STATUS_8TO11 0x0003E60 +#define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7 0x0003E64 +#define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11 0x0003E68 +#define ACP_SW1_CLK_FREQUENCY_CTRL 0x0003E6C +#define ACP_SW1_ERROR_INTR_MASK 0x0003E70 +#define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x0003E74 + +/* Registers from ACP_SCRATCH block */ +#define ACP_SCRATCH_REG_0 0x0010000 + +#endif diff --git a/include/sound/acp7x_chip_offset_byte.h b/include/sound/acp7x_chip_offset_byte.h new file mode 100644 index 000000000..772c3d38c --- /dev/null +++ b/include/sound/acp7x_chip_offset_byte.h @@ -0,0 +1,2519 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ACP 7.x Register Documentation + * + * Copyright 2026 Advanced Micro Devices, Inc. + */ + +#ifndef _acp_ip_7x_chip_OFFSET_BYTE_H +#define _acp_ip_7x_chip_OFFSET_BYTE_H + +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x000C00 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x000C04 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x000C08 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x000C0C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x000C10 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x000C14 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x000C18 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x000C1C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x000C20 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x000C24 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x000C28 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x000C2C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x000C30 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x000C34 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x000C38 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x000C3C +#define ACPAXI2AXI_ATU_CTRL 0x000C40 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x000C44 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x000C48 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x000C4C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x000C50 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x000C54 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x000C58 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x000C5C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x000C60 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x000C64 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x000C68 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x000C6C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x000C70 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x000C74 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x000C78 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x000C7C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x000C80 + +#define ACP_SOFT_RESET 0x001000 +#define ACP_CONTROL 0x001004 +#define ACP_STATUS 0x001008 +#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x001010 +#define ACP_ZSC_DSP_CTRL 0x001014 +#define ACP_ZSC_STS 0x001018 +#define ACP_PGFSM_CONTROL 0x001024 +#define ACP_PGFSM_STATUS 0x001028 +#define ACP_CLKMUX_SEL 0x00102C +#define ACP_SW_48MHz_CLK_SEL 0x001030 +#define ACP_AUDIO_CLK_SEL 0x001038 +#define ACP_PDM_CORE_CLK_SEL 0x00103C + +#define ACP_PME_EN 0x001400 +#define ACP_DEVICE_STATE 0x001404 +#define SW_DEVICE_STATE 0x001430 +#define ACP_PIN_CONFIG 0x001440 +#define ACP_PAD_PULLUP_CTRL 0x001444 +#define ACP_PAD_PULLDOWN_CTRL 0x001448 +#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x00144C +#define ACP_PAD_SCHMEN_CTRL 0x001450 +#define ACP_SW_PAD_KEEPER_EN 0x001454 +#define ACP_SW_WAKE_EN 0x001458 +#define ACP_I2S_WAKE_EN 0x00145C +#define ACP_ACLK_AUDIOCLK_CTRL 0x001464 +#define ACP_PAD_DISABLE_OE_CTRL 0x001468 +#define ACP_SW0_PME_STS 0x001474 +#define ACP_SW1_PME_STS 0x001478 +#define ACP_SW2_PME_STS 0x00147C +#define ACP_SW3_PME_STS 0x001480 +#define ACP_I2S_PME_STS 0x001484 +#define ACP_TDM_LOOPBACK_EN 0x001488 + +#define ACP_FUTURE_REG_ACLK_0 0x0018E0 +#define ACP_FUTURE_REG_ACLK_1 0x0018E4 +#define ACP_FUTURE_REG_ACLK_2 0x0018E8 +#define ACP_FUTURE_REG_ACLK_3 0x0018EC +#define ACP_FUTURE_REG_ACLK_4 0x0018F0 +#define ACP_AXI2DAGB_SEM_0 0x0018F4 + +#define ACP_EXTERNAL_INTR_ENB 0x001A00 +#define ACP_EXTERNAL_INTR_CNTL 0x001A04 +#define ACP_EXTERNAL_INTR_CNTL1 0x001A08 +#define ACP_EXTERNAL_SW0_INTR_CNTL 0x001A0C +#define ACP_EXTERNAL_SW1_INTR_CNTL 0x001A10 +#define ACP_EXTERNAL_SW2_INTR_CNTL 0x001A14 +#define ACP_EXTERNAL_SW3_INTR_CNTL 0x001A18 +#define ACP_EXTERNAL_INTR_STAT 0x001A1C +#define ACP_EXTERNAL_INTR_STAT1 0x001A20 +#define ACP_EXTERNAL_SW0_INTR_STAT 0x001A24 +#define ACP_EXTERNAL_SW1_INTR_STAT 0x001A28 +#define ACP_EXTERNAL_SW2_INTR_STAT 0x001A2C +#define ACP_EXTERNAL_SW3_INTR_STAT 0x001A30 +#define ACP_ERROR_STATUS 0x001A88 +#define ACP_ERROR_INTR_CTRL1 0x001AA4 +#define ACP_P1_FUTURE_REG_ACLK_0 0x001AB4 +#define ACP_P1_FUTURE_REG_ACLK_1 0x001AB8 + +#define ACP_I2S_TDM0_RX_RINGBUFADDR 0x002000 +#define ACP_I2S_TDM0_RX_RINGBUFSIZE 0x002004 +#define ACP_I2S_TDM0_RX_LINKPOSITIONCNTR 0x002008 +#define ACP_I2S_TDM0_RX_FIFOADDR 0x00200C +#define ACP_I2S_TDM0_RX_FIFOSIZE 0x002010 +#define ACP_I2S_TDM0_RX_DMA_SIZE 0x002014 +#define ACP_I2S_TDM0_RX_LINEARPOSITIONCNTR_HIGH 0x002018 +#define ACP_I2S_TDM0_RX_LINEARPOSITIONCNTR_LOW 0x00201C +#define ACP_I2S_TDM0_RX_INTR_WATERMARK_SIZE 0x002020 +#define ACP_I2S_TDM0_TX_RINGBUFADDR 0x002024 +#define ACP_I2S_TDM0_TX_RINGBUFSIZE 0x002028 +#define ACP_I2S_TDM0_TX_LINKPOSITIONCNTR 0x00202C +#define ACP_I2S_TDM0_TX_FIFOADDR 0x002030 +#define ACP_I2S_TDM0_TX_FIFOSIZE 0x002034 +#define ACP_I2S_TDM0_TX_DMA_SIZE 0x002038 +#define ACP_I2S_TDM0_TX_LINEARPOSITIONCNTR_HIGH 0x00203C +#define ACP_I2S_TDM0_TX_LINEARPOSITIONCNTR_LOW 0x002040 +#define ACP_I2S_TDM0_TX_INTR_WATERMARK_SIZE 0x002044 +#define ACP_I2S_TDM0_POS_TRACK_TX_CTRL 0x002048 +#define ACP_I2S_TDM0_TX_DMA_POS 0x00204C +#define ACP_I2S_TDM0_POS_TRACK_I2S_RX_CTRL 0x002050 +#define ACP_I2S_TDM0_RX_DMA_POS 0x002054 +#define ACP_I2S_TDM0_ERROR_STATUS 0x002058 +#define ACP_I2S_TDM0_ERROR_MASK 0x00205C +#define ACP_I2S_TDM0_IER 0x002100 +#define ACP_I2S_TDM0_IRER 0x002104 +#define ACP_I2S_TDM0_RXFRMT 0x002108 +#define ACP_I2S_TDM0_ITER 0x00210C +#define ACP_I2S_TDM0_TXFRMT 0x002110 +#define ACP_I2S_TDM0_MSTRCLKGEN 0x002114 +#define ACP_I2S_TDM0_OUTPUT_SPLIT_EN 0x002118 +#define ACP_I2S_TDM0_WALLCLK_MISC 0x00211C +#define ACP_I2S_TDM0_WALL_CLK_COUNTER 0x002120 +#define ACP_I2S_TDM_REFCLKGEN 0x002124 +#define ACP_TDM_SYNCEN 0x002128 +#define ACP_TDM_LRCLK_START 0x00212C +#define ACP_I2S_TDM0_WALLCLK_INTR_CNTL 0x002130 + +#define ACP_I2S_TDM1_RX_RINGBUFADDR 0x002200 +#define ACP_I2S_TDM1_RX_RINGBUFSIZE 0x002204 +#define ACP_I2S_TDM1_RX_LINKPOSITIONCNTR 0x002208 +#define ACP_I2S_TDM1_RX_FIFOADDR 0x00220C +#define ACP_I2S_TDM1_RX_FIFOSIZE 0x002210 +#define ACP_I2S_TDM1_RX_DMA_SIZE 0x002214 +#define ACP_I2S_TDM1_RX_LINEARPOSITIONCNTR_HIGH 0x002218 +#define ACP_I2S_TDM1_RX_LINEARPOSITIONCNTR_LOW 0x00221C +#define ACP_I2S_TDM1_RX_INTR_WATERMARK_SIZE 0x002220 +#define ACP_I2S_TDM1_TX_RINGBUFADDR 0x002224 +#define ACP_I2S_TDM1_TX_RINGBUFSIZE 0x002228 +#define ACP_I2S_TDM1_TX_LINKPOSITIONCNTR 0x00222C +#define ACP_I2S_TDM1_TX_FIFOADDR 0x002230 +#define ACP_I2S_TDM1_TX_FIFOSIZE 0x002234 +#define ACP_I2S_TDM1_TX_DMA_SIZE 0x002238 +#define ACP_I2S_TDM1_TX_LINEARPOSITIONCNTR_HIGH 0x00223C +#define ACP_I2S_TDM1_TX_LINEARPOSITIONCNTR_LOW 0x002240 +#define ACP_I2S_TDM1_TX_INTR_WATERMARK_SIZE 0x002244 +#define ACP_I2S_TDM1_POS_TRACK_TX_CTRL 0x002248 +#define ACP_I2S_TDM1_TX_DMA_POS 0x00224C +#define ACP_I2S_TDM1_POS_TRACK_I2S_RX_CTRL 0x002250 +#define ACP_I2S_TDM1_RX_DMA_POS 0x002254 +#define ACP_I2S_TDM1_ERROR_STATUS 0x002258 +#define ACP_I2S_TDM1_ERROR_MASK 0x00225C +#define ACP_I2S_TDM1_IER 0x002300 +#define ACP_I2S_TDM1_IRER 0x002304 +#define ACP_I2S_TDM1_RXFRMT 0x002308 +#define ACP_I2S_TDM1_ITER 0x00230C +#define ACP_I2S_TDM1_TXFRMT 0x002310 +#define ACP_I2S_TDM1_MSTRCLKGEN 0x002314 +#define ACP_I2S_TDM1_OUTPUT_SPLIT_EN 0x002318 +#define ACP_I2S_TDM1_WALLCLK_MISC 0x00231C +#define ACP_I2S_TDM1_WALL_CLK_COUNTER 0x002320 +#define ACP_I2S_TDM1_WALLCLK_INTR_CNTL 0x002330 + +#define ACP_I2S_TDM2_RX_RINGBUFADDR 0x002400 +#define ACP_I2S_TDM2_RX_RINGBUFSIZE 0x002404 +#define ACP_I2S_TDM2_RX_LINKPOSITIONCNTR 0x002408 +#define ACP_I2S_TDM2_RX_FIFOADDR 0x00240C +#define ACP_I2S_TDM2_RX_FIFOSIZE 0x002410 +#define ACP_I2S_TDM2_RX_DMA_SIZE 0x002414 +#define ACP_I2S_TDM2_RX_LINEARPOSITIONCNTR_HIGH 0x002418 +#define ACP_I2S_TDM2_RX_LINEARPOSITIONCNTR_LOW 0x00241C +#define ACP_I2S_TDM2_RX_INTR_WATERMARK_SIZE 0x002420 +#define ACP_I2S_TDM2_TX_RINGBUFADDR 0x002424 +#define ACP_I2S_TDM2_TX_RINGBUFSIZE 0x002428 +#define ACP_I2S_TDM2_TX_LINKPOSITIONCNTR 0x00242C +#define ACP_I2S_TDM2_TX_FIFOADDR 0x002430 +#define ACP_I2S_TDM2_TX_FIFOSIZE 0x002434 +#define ACP_I2S_TDM2_TX_DMA_SIZE 0x002438 +#define ACP_I2S_TDM2_TX_LINEARPOSITIONCNTR_HIGH 0x00243C +#define ACP_I2S_TDM2_TX_LINEARPOSITIONCNTR_LOW 0x002440 +#define ACP_I2S_TDM2_TX_INTR_WATERMARK_SIZE 0x002444 +#define ACP_I2S_TDM2_POS_TRACK_TX_CTRL 0x002448 +#define ACP_I2S_TDM2_TX_DMA_POS 0x00244C +#define ACP_I2S_TDM2_POS_TRACK_I2S_RX_CTRL 0x002450 +#define ACP_I2S_TDM2_RX_DMA_POS 0x002454 +#define ACP_I2S_TDM2_ERROR_STATUS 0x002458 +#define ACP_I2S_TDM2_ERROR_MASK 0x00245C +#define ACP_I2S_TDM2_IER 0x002500 +#define ACP_I2S_TDM2_IRER 0x002504 +#define ACP_I2S_TDM2_RXFRMT 0x002508 +#define ACP_I2S_TDM2_ITER 0x00250C +#define ACP_I2S_TDM2_TXFRMT 0x002510 +#define ACP_I2S_TDM2_MSTRCLKGEN 0x002514 +#define ACP_I2S_TDM2_OUTPUT_SPLIT_EN 0x002518 +#define ACP_I2S_TDM2_WALLCLK_MISC 0x00251C +#define ACP_I2S_TDM2_WALL_CLK_COUNTER 0x002520 +#define ACP_I2S_TDM2_WALLCLK_INTR_CNTL 0x002530 + +#define ACP_SW_CTRL_COUNT 0x004D00 +#define ACP_SW_GSYNC_EN 0x004D04 +#define ACP_SW_GSYNC_EN_PRE_SELECT 0x004D08 +#define ACP_SW_GSYNC_DP_EN 0x004D0C + +#define ACP_SW0_GLOBAL_CAPABILITIES 0x004E00 +#define ACP_SW0_RX_DMA0_RINGBUFADDR 0x004E04 +#define ACP_SW0_RX_DMA0_RINGBUFSIZE 0x004E08 +#define ACP_SW0_RX_DMA0_FIFOADDR 0x004E0C +#define ACP_SW0_RX_DMA0_FIFOSIZE 0x004E10 +#define ACP_SW0_RX_DMA0_BURST_SIZE 0x004E14 +#define ACP_SW0_RX_DMA0_LINKPOSITIONCNTR 0x004E18 +#define ACP_SW0_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x004E1C +#define ACP_SW0_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x004E20 +#define ACP_SW0_RX_DMA0_INTR_WATERMARK_SIZE 0x004E24 +#define ACP_SW0_RX_DMA1_RINGBUFADDR 0x004E28 +#define ACP_SW0_RX_DMA1_RINGBUFSIZE 0x004E2C +#define ACP_SW0_RX_DMA1_FIFOADDR 0x004E30 +#define ACP_SW0_RX_DMA1_FIFOSIZE 0x004E34 +#define ACP_SW0_RX_DMA1_BURST_SIZE 0x004E38 +#define ACP_SW0_RX_DMA1_LINKPOSITIONCNTR 0x004E3C +#define ACP_SW0_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x004E40 +#define ACP_SW0_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x004E44 +#define ACP_SW0_RX_DMA1_INTR_WATERMARK_SIZE 0x004E48 +#define ACP_SW0_RX_DMA2_RINGBUFADDR 0x004E4C +#define ACP_SW0_RX_DMA2_RINGBUFSIZE 0x004E50 +#define ACP_SW0_RX_DMA2_FIFOADDR 0x004E54 +#define ACP_SW0_RX_DMA2_FIFOSIZE 0x004E58 +#define ACP_SW0_RX_DMA2_BURST_SIZE 0x004E5C +#define ACP_SW0_RX_DMA2_LINKPOSITIONCNTR 0x004E60 +#define ACP_SW0_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x004E64 +#define ACP_SW0_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x004E68 +#define ACP_SW0_RX_DMA2_INTR_WATERMARK_SIZE 0x004E6C +#define ACP_SW0_RX_DMA3_RINGBUFADDR 0x004E70 +#define ACP_SW0_RX_DMA3_RINGBUFSIZE 0x004E74 +#define ACP_SW0_RX_DMA3_FIFOADDR 0x004E78 +#define ACP_SW0_RX_DMA3_FIFOSIZE 0x004E7C +#define ACP_SW0_RX_DMA3_BURST_SIZE 0x004E80 +#define ACP_SW0_RX_DMA3_LINKPOSITIONCNTR 0x004E84 +#define ACP_SW0_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x004E88 +#define ACP_SW0_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x004E8C +#define ACP_SW0_RX_DMA3_INTR_WATERMARK_SIZE 0x004E90 +#define ACP_SW0_RX_DMA4_RINGBUFADDR 0x004E94 +#define ACP_SW0_RX_DMA4_RINGBUFSIZE 0x004E98 +#define ACP_SW0_RX_DMA4_FIFOADDR 0x004E9C +#define ACP_SW0_RX_DMA4_FIFOSIZE 0x004EA0 +#define ACP_SW0_RX_DMA4_BURST_SIZE 0x004EA4 +#define ACP_SW0_RX_DMA4_LINKPOSITIONCNTR 0x004EA8 +#define ACP_SW0_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x004EAC +#define ACP_SW0_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x004EB0 +#define ACP_SW0_RX_DMA4_INTR_WATERMARK_SIZE 0x004EB4 +#define ACP_SW0_RX_DMA5_RINGBUFADDR 0x004EB8 +#define ACP_SW0_RX_DMA5_RINGBUFSIZE 0x004EBC +#define ACP_SW0_RX_DMA5_FIFOADDR 0x004EC0 +#define ACP_SW0_RX_DMA5_FIFOSIZE 0x004EC4 +#define ACP_SW0_RX_DMA5_BURST_SIZE 0x004EC8 +#define ACP_SW0_RX_DMA5_LINKPOSITIONCNTR 0x004ECC +#define ACP_SW0_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x004ED0 +#define ACP_SW0_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x004ED4 +#define ACP_SW0_RX_DMA5_INTR_WATERMARK_SIZE 0x004ED8 +#define ACP_SW0_RX_DMA6_RINGBUFADDR 0x004EDC +#define ACP_SW0_RX_DMA6_RINGBUFSIZE 0x004EE0 +#define ACP_SW0_RX_DMA6_FIFOADDR 0x004EE4 +#define ACP_SW0_RX_DMA6_FIFOSIZE 0x004EE8 +#define ACP_SW0_RX_DMA6_BURST_SIZE 0x004EEC +#define ACP_SW0_RX_DMA6_LINKPOSITIONCNTR 0x004EF0 +#define ACP_SW0_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x004EF4 +#define ACP_SW0_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x004EF8 +#define ACP_SW0_RX_DMA6_INTR_WATERMARK_SIZE 0x004EFC +#define ACP_SW0_RX_DMA7_RINGBUFADDR 0x004F00 +#define ACP_SW0_RX_DMA7_RINGBUFSIZE 0x004F04 +#define ACP_SW0_RX_DMA7_FIFOADDR 0x004F08 +#define ACP_SW0_RX_DMA7_FIFOSIZE 0x004F0C +#define ACP_SW0_RX_DMA7_BURST_SIZE 0x004F10 +#define ACP_SW0_RX_DMA7_LINKPOSITIONCNTR 0x004F14 +#define ACP_SW0_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x004F18 +#define ACP_SW0_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x004F1C +#define ACP_SW0_RX_DMA7_INTR_WATERMARK_SIZE 0x004F20 +#define ACP_SW0_TX_DMA0_RINGBUFADDR 0x004F24 +#define ACP_SW0_TX_DMA0_RINGBUFSIZE 0x004F28 +#define ACP_SW0_TX_DMA0_FIFOADDR 0x004F2C +#define ACP_SW0_TX_DMA0_FIFOSIZE 0x004F30 +#define ACP_SW0_TX_DMA0_BURST_SIZE 0x004F34 +#define ACP_SW0_TX_DMA0_LINKPOSITIONCNTR 0x004F38 +#define ACP_SW0_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x004F3C +#define ACP_SW0_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x004F40 +#define ACP_SW0_TX_DMA0_INTR_WATERMARK_SIZE 0x004F44 +#define ACP_SW0_TX_DMA1_RINGBUFADDR 0x004F48 +#define ACP_SW0_TX_DMA1_RINGBUFSIZE 0x004F4C +#define ACP_SW0_TX_DMA1_FIFOADDR 0x004F50 +#define ACP_SW0_TX_DMA1_FIFOSIZE 0x004F54 +#define ACP_SW0_TX_DMA1_BURST_SIZE 0x004F58 +#define ACP_SW0_TX_DMA1_LINKPOSITIONCNTR 0x004F5C +#define ACP_SW0_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x004F60 +#define ACP_SW0_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x004F64 +#define ACP_SW0_TX_DMA1_INTR_WATERMARK_SIZE 0x004F68 +#define ACP_SW0_TX_DMA2_RINGBUFADDR 0x004F6C +#define ACP_SW0_TX_DMA2_RINGBUFSIZE 0x004F70 +#define ACP_SW0_TX_DMA2_FIFOADDR 0x004F74 +#define ACP_SW0_TX_DMA2_FIFOSIZE 0x004F78 +#define ACP_SW0_TX_DMA2_BURST_SIZE 0x004F7C +#define ACP_SW0_TX_DMA2_LINKPOSITIONCNTR 0x004F80 +#define ACP_SW0_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x004F84 +#define ACP_SW0_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x004F88 +#define ACP_SW0_TX_DMA2_INTR_WATERMARK_SIZE 0x004F8C +#define ACP_SW0_TX_DMA3_RINGBUFADDR 0x004F90 +#define ACP_SW0_TX_DMA3_RINGBUFSIZE 0x004F94 +#define ACP_SW0_TX_DMA3_FIFOADDR 0x004F98 +#define ACP_SW0_TX_DMA3_FIFOSIZE 0x004F9C +#define ACP_SW0_TX_DMA3_BURST_SIZE 0x004FA0 +#define ACP_SW0_TX_DMA3_LINKPOSITIONCNTR 0x004FA4 +#define ACP_SW0_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x004FA8 +#define ACP_SW0_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x004FAC +#define ACP_SW0_TX_DMA3_INTR_WATERMARK_SIZE 0x004FB0 +#define ACP_SW0_TX_DMA4_RINGBUFADDR 0x004FB4 +#define ACP_SW0_TX_DMA4_RINGBUFSIZE 0x004FB8 +#define ACP_SW0_TX_DMA4_FIFOADDR 0x004FBC +#define ACP_SW0_TX_DMA4_FIFOSIZE 0x004FC0 +#define ACP_SW0_TX_DMA4_BURST_SIZE 0x004FC4 +#define ACP_SW0_TX_DMA4_LINKPOSITIONCNTR 0x004FC8 +#define ACP_SW0_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x004FCC +#define ACP_SW0_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x004FD0 +#define ACP_SW0_TX_DMA4_INTR_WATERMARK_SIZE 0x004FD4 +#define ACP_SW0_TX_DMA5_RINGBUFADDR 0x004FD8 +#define ACP_SW0_TX_DMA5_RINGBUFSIZE 0x004FDC +#define ACP_SW0_TX_DMA5_FIFOADDR 0x004FE0 +#define ACP_SW0_TX_DMA5_FIFOSIZE 0x004FE4 +#define ACP_SW0_TX_DMA5_BURST_SIZE 0x004FE8 +#define ACP_SW0_TX_DMA5_LINKPOSITIONCNTR 0x004FEC +#define ACP_SW0_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x004FF0 +#define ACP_SW0_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x004FF4 +#define ACP_SW0_TX_DMA5_INTR_WATERMARK_SIZE 0x004FF8 +#define ACP_SW0_TX_DMA6_RINGBUFADDR 0x004FFC +#define ACP_SW0_TX_DMA6_RINGBUFSIZE 0x005000 +#define ACP_SW0_TX_DMA6_FIFOADDR 0x005004 +#define ACP_SW0_TX_DMA6_FIFOSIZE 0x005008 +#define ACP_SW0_TX_DMA6_BURST_SIZE 0x00500C +#define ACP_SW0_TX_DMA6_LINKPOSITIONCNTR 0x005010 +#define ACP_SW0_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x005014 +#define ACP_SW0_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x005018 +#define ACP_SW0_TX_DMA6_INTR_WATERMARK_SIZE 0x00501C +#define ACP_SW0_TX_DMA7_RINGBUFADDR 0x005020 +#define ACP_SW0_TX_DMA7_RINGBUFSIZE 0x005024 +#define ACP_SW0_TX_DMA7_FIFOADDR 0x005028 +#define ACP_SW0_TX_DMA7_FIFOSIZE 0x00502C +#define ACP_SW0_TX_DMA7_BURST_SIZE 0x005030 +#define ACP_SW0_TX_DMA7_LINKPOSITIONCNTR 0x005034 +#define ACP_SW0_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x005038 +#define ACP_SW0_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00503C +#define ACP_SW0_TX_DMA7_INTR_WATERMARK_SIZE 0x005040 +#define ACP_SW0_RX_DMA0_POS_TRACK 0x005044 +#define ACP_SW0_RX_DMA0_POS 0x005048 +#define ACP_SW0_RX_DMA1_POS_TRACK 0x00504C +#define ACP_SW0_RX_DMA1_POS 0x005050 +#define ACP_SW0_RX_DMA2_POS_TRACK 0x005054 +#define ACP_SW0_RX_DMA2_POS 0x005058 +#define ACP_SW0_RX_DMA3_POS_TRACK 0x00505C +#define ACP_SW0_RX_DMA3_POS 0x005060 +#define ACP_SW0_RX_DMA4_POS_TRACK 0x005064 +#define ACP_SW0_RX_DMA4_POS 0x005068 +#define ACP_SW0_RX_DMA5_POS_TRACK 0x00506C +#define ACP_SW0_RX_DMA5_POS 0x005070 +#define ACP_SW0_RX_DMA6_POS_TRACK 0x005074 +#define ACP_SW0_RX_DMA6_POS 0x005078 +#define ACP_SW0_RX_DMA7_POS_TRACK 0x00507C +#define ACP_SW0_RX_DMA7_POS 0x005080 +#define ACP_SW0_TX_DMA0_POS_TRACK 0x005084 +#define ACP_SW0_TX_DMA0_POS 0x005088 +#define ACP_SW0_TX_DMA1_POS_TRACK 0x00508C +#define ACP_SW0_TX_DMA1_POS 0x005090 +#define ACP_SW0_TX_DMA2_POS_TRACK 0x005094 +#define ACP_SW0_TX_DMA2_POS 0x005098 +#define ACP_SW0_TX_DMA3_POS_TRACK 0x00509C +#define ACP_SW0_TX_DMA3_POS 0x0050A0 +#define ACP_SW0_TX_DMA4_POS_TRACK 0x0050A4 +#define ACP_SW0_TX_DMA4_POS 0x0050A8 +#define ACP_SW0_TX_DMA5_POS_TRACK 0x0050AC +#define ACP_SW0_TX_DMA5_POS 0x0050B0 +#define ACP_SW0_TX_DMA6_POS_TRACK 0x0050B4 +#define ACP_SW0_TX_DMA6_POS 0x0050B8 +#define ACP_SW0_TX_DMA7_POS_TRACK 0x0050BC +#define ACP_SW0_TX_DMA7_POS 0x0050C0 +#define ACP_SW0_FIFO_ERROR_REASON 0x0050C4 +#define ACP_SW0_FIFO_ERROR_INTR_MASK 0x0050C8 +#define ACP_SW0_ERROR_REASON1 0x0050CC +#define ACP_SW0_ERROR_INTR_MASK1 0x0050D0 +#define ACP_SW0_ERROR_REASON2 0x0050D4 +#define ACP_SW0_ERROR_INTR_MASK2 0x0050D8 + +#define ACP_SW0_CORB_BASE_ADDRESS 0x005100 +#define ACP_SW0_CORB_WRITE_POINTER 0x005104 +#define ACP_SW0_CORB_READ_POINTER 0x005108 +#define ACP_SW0_CORB_CONTROL 0x00510C +#define ACP_SW0_CORB_SIZE 0x005114 +#define ACP_SW0_RIRB_BASE_ADDRESS 0x005118 +#define ACP_SW0_RIRB_WRITE_POINTER 0x00511C +#define ACP_SW0_RIRB_RESPONSE_INTERRUPT_COUNT 0x005120 +#define ACP_SW0_RIRB_CONTROL 0x005124 +#define ACP_SW0_RIRB_SIZE 0x005128 +#define ACP_SW0_RIRB_FIFO_MIN_THDL 0x00512C +#define ACP_SW0_IMM_CMD_UPPER_WORD 0x005130 +#define ACP_SW0_IMM_CMD_LOWER_QWORD 0x005134 +#define ACP_SW0_IMM_RESP_UPPER_WORD 0x005138 +#define ACP_SW0_IMM_RESP_LOWER_QWORD 0x00513C +#define ACP_SW0_IMM_CMD_STS 0x005140 +#define ACP_SW0_BRA_BASE_ADDRESS 0x005144 +#define ACP_SW0_BRA_TRANSFER_SIZE 0x005148 +#define ACP_SW0_BRA_DMA_BUSY 0x00514C +#define ACP_SW0_BRA_RESP 0x005150 +#define ACP_SW0_BRA_RESP_FRAME_ADDR 0x005154 +#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x005158 +#define ACP_SW0_STATE_CHANGE_STATUS_0TO7 0x00515C +#define ACP_SW0_STATE_CHANGE_STATUS_8TO11 0x005160 +#define ACP_SW0_STATE_CHANGE_STATUS_MASK_0TO7 0x005164 +#define ACP_SW0_STATE_CHANGE_STATUS_MASK_8TO11 0x005168 +#define ACP_SW0_CLK_FREQUENCY_CTRL_BANK0 0x00516C +#define ACP_SW0_CLK_FREQUENCY_CTRL_BANK1 0x005170 +#define ACP_SW0_ERROR_INTR_MASK 0x005174 +#define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x005178 +#define ACP_SW0_DATA_TO_PDM_EN 0x00517C + +#define ACP_SW0_EN 0x005200 +#define ACP_SW0_EN_STATUS 0x005204 +#define ACP_SW0_FRAMESIZE_BANK0 0x005208 +#define ACP_SW0_FRAMESIZE_BANK1 0x00520C +#define ACP_SW0_SSP_COUNTER 0x005210 +#define ACP_SW0_TX_STREAM0_EN 0x005214 +#define ACP_SW0_TX_STREAM1_EN 0x005218 +#define ACP_SW0_TX_STREAM2_EN 0x00521C +#define ACP_SW0_TX_STREAM3_EN 0x005220 +#define ACP_SW0_TX_STREAM4_EN 0x005224 +#define ACP_SW0_TX_STREAM5_EN 0x005228 +#define ACP_SW0_TX_STREAM6_EN 0x00522C +#define ACP_SW0_TX_STREAM7_EN 0x005230 +#define ACP_SW0_TX_STREAM0_EN_STATUS 0x005234 +#define ACP_SW0_TX_STREAM1_EN_STATUS 0x005238 +#define ACP_SW0_TX_STREAM2_EN_STATUS 0x00523C +#define ACP_SW0_TX_STREAM3_EN_STATUS 0x005240 +#define ACP_SW0_TX_STREAM4_EN_STATUS 0x005244 +#define ACP_SW0_TX_STREAM5_EN_STATUS 0x005248 +#define ACP_SW0_TX_STREAM6_EN_STATUS 0x00524C +#define ACP_SW0_TX_STREAM7_EN_STATUS 0x005250 +#define ACP_SW0_TX_DP0_FRAME_FORMAT 0x005254 +#define ACP_SW0_TX_DP1_FRAME_FORMAT 0x005258 +#define ACP_SW0_TX_DP2_FRAME_FORMAT 0x00525C +#define ACP_SW0_TX_DP3_FRAME_FORMAT 0x005260 +#define ACP_SW0_TX_DP4_FRAME_FORMAT 0x005264 +#define ACP_SW0_TX_DP5_FRAME_FORMAT 0x005268 +#define ACP_SW0_TX_DP6_FRAME_FORMAT 0x00526C +#define ACP_SW0_TX_DP7_FRAME_FORMAT 0x005270 +#define ACP_SW0_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x005280 +#define ACP_SW0_TX_DP0_0_HCTRL_BANK0 0x005284 +#define ACP_SW0_TX_DP0_0_HCTRL_OFFSET_BANK0 0x005288 +#define ACP_SW0_TX_DP0_0_LANE_CTRL_BANK0 0x00528C +#define ACP_SW0_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x005290 +#define ACP_SW0_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005294 +#define ACP_SW0_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x005298 +#define ACP_SW0_TX_DP0_0_HCTRL_BANK1 0x00529C +#define ACP_SW0_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0052A0 +#define ACP_SW0_TX_DP0_0_LANE_CTRL_BANK1 0x0052A4 +#define ACP_SW0_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0052A8 +#define ACP_SW0_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0052AC +#define ACP_SW0_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0052B0 +#define ACP_SW0_TX_DP0_1_HCTRL_BANK0 0x0052B4 +#define ACP_SW0_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0052B8 +#define ACP_SW0_TX_DP0_1_LANE_CTRL_BANK0 0x0052BC +#define ACP_SW0_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0052C0 +#define ACP_SW0_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0052C4 +#define ACP_SW0_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0052C8 +#define ACP_SW0_TX_DP0_1_HCTRL_BANK1 0x0052CC +#define ACP_SW0_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0052D0 +#define ACP_SW0_TX_DP0_1_LANE_CTRL_BANK1 0x0052D4 +#define ACP_SW0_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0052D8 +#define ACP_SW0_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0052DC +#define ACP_SW0_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0052E0 +#define ACP_SW0_TX_DP0_2_HCTRL_BANK0 0x0052E4 +#define ACP_SW0_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0052E8 +#define ACP_SW0_TX_DP0_2_LANE_CTRL_BANK0 0x0052EC +#define ACP_SW0_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0052F0 +#define ACP_SW0_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0052F4 +#define ACP_SW0_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0052F8 +#define ACP_SW0_TX_DP0_2_HCTRL_BANK1 0x0052FC +#define ACP_SW0_TX_DP0_2_HCTRL_OFFSET_BANK1 0x005300 +#define ACP_SW0_TX_DP0_2_LANE_CTRL_BANK1 0x005304 +#define ACP_SW0_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x005308 +#define ACP_SW0_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00530C +#define ACP_SW0_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x005310 +#define ACP_SW0_TX_DP0_3_HCTRL_BANK0 0x005314 +#define ACP_SW0_TX_DP0_3_HCTRL_OFFSET_BANK0 0x005318 +#define ACP_SW0_TX_DP0_3_LANE_CTRL_BANK0 0x00531C +#define ACP_SW0_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x005320 +#define ACP_SW0_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005324 +#define ACP_SW0_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x005328 +#define ACP_SW0_TX_DP0_3_HCTRL_BANK1 0x00532C +#define ACP_SW0_TX_DP0_3_HCTRL_OFFSET_BANK1 0x005330 +#define ACP_SW0_TX_DP0_3_LANE_CTRL_BANK1 0x005334 +#define ACP_SW0_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x005338 +#define ACP_SW0_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00533C +#define ACP_SW0_TX_DP1_SAMPLEINTERVAL_BANK0 0x005370 +#define ACP_SW0_TX_DP1_HCTRL_BANK0 0x005374 +#define ACP_SW0_TX_DP1_HCTRL_OFFSET_BANK0 0x005378 +#define ACP_SW0_TX_DP1_LANE_CTRL_BANK0 0x00537C +#define ACP_SW0_TX_DP1_CHANNEL_ENABLE_BANK0 0x005380 +#define ACP_SW0_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005384 +#define ACP_SW0_TX_DP1_SAMPLEINTERVAL_BANK1 0x005388 +#define ACP_SW0_TX_DP1_HCTRL_BANK1 0x00538C +#define ACP_SW0_TX_DP1_HCTRL_OFFSET_BANK1 0x005390 +#define ACP_SW0_TX_DP1_LANE_CTRL_BANK1 0x005394 +#define ACP_SW0_TX_DP1_CHANNEL_ENABLE_BANK1 0x005398 +#define ACP_SW0_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00539C +#define ACP_SW0_TX_DP2_SAMPLEINTERVAL_BANK0 0x0053A0 +#define ACP_SW0_TX_DP2_HCTRL_BANK0 0x0053A4 +#define ACP_SW0_TX_DP2_HCTRL_OFFSET_BANK0 0x0053A8 +#define ACP_SW0_TX_DP2_LANE_CTRL_BANK0 0x0053AC +#define ACP_SW0_TX_DP2_CHANNEL_ENABLE_BANK0 0x0053B0 +#define ACP_SW0_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0053B4 +#define ACP_SW0_TX_DP2_SAMPLEINTERVAL_BANK1 0x0053B8 +#define ACP_SW0_TX_DP2_HCTRL_BANK1 0x0053BC +#define ACP_SW0_TX_DP2_HCTRL_OFFSET_BANK1 0x0053C0 +#define ACP_SW0_TX_DP2_LANE_CTRL_BANK1 0x0053C4 +#define ACP_SW0_TX_DP2_CHANNEL_ENABLE_BANK1 0x0053C8 +#define ACP_SW0_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0053CC +#define ACP_SW0_TX_DP3_SAMPLEINTERVAL_BANK0 0x0053D0 +#define ACP_SW0_TX_DP3_HCTRL_BANK0 0x0053D4 +#define ACP_SW0_TX_DP3_HCTRL_OFFSET_BANK0 0x0053D8 +#define ACP_SW0_TX_DP3_LANE_CTRL_BANK0 0x0053DC +#define ACP_SW0_TX_DP3_CHANNEL_ENABLE_BANK0 0x0053E0 +#define ACP_SW0_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0053E4 +#define ACP_SW0_TX_DP3_SAMPLEINTERVAL_BANK1 0x0053E8 +#define ACP_SW0_TX_DP3_HCTRL_BANK1 0x0053EC +#define ACP_SW0_TX_DP3_HCTRL_OFFSET_BANK1 0x0053F0 +#define ACP_SW0_TX_DP3_LANE_CTRL_BANK1 0x0053F4 +#define ACP_SW0_TX_DP3_CHANNEL_ENABLE_BANK1 0x0053F8 +#define ACP_SW0_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0053FC +#define ACP_SW0_TX_DP4_SAMPLEINTERVAL_BANK0 0x005400 +#define ACP_SW0_TX_DP4_HCTRL_BANK0 0x005404 +#define ACP_SW0_TX_DP4_HCTRL_OFFSET_BANK0 0x005408 +#define ACP_SW0_TX_DP4_LANE_CTRL_BANK0 0x00540C +#define ACP_SW0_TX_DP4_CHANNEL_ENABLE_BANK0 0x005410 +#define ACP_SW0_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005414 +#define ACP_SW0_TX_DP4_SAMPLEINTERVAL_BANK1 0x005418 +#define ACP_SW0_TX_DP4_HCTRL_BANK1 0x00541C +#define ACP_SW0_TX_DP4_HCTRL_OFFSET_BANK1 0x005420 +#define ACP_SW0_TX_DP4_LANE_CTRL_BANK1 0x005424 +#define ACP_SW0_TX_DP4_CHANNEL_ENABLE_BANK1 0x005428 +#define ACP_SW0_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00542C +#define ACP_SW0_TX_DP5_SAMPLEINTERVAL_BANK0 0x005430 +#define ACP_SW0_TX_DP5_HCTRL_BANK0 0x005434 +#define ACP_SW0_TX_DP5_HCTRL_OFFSET_BANK0 0x005438 +#define ACP_SW0_TX_DP5_LANE_CTRL_BANK0 0x00543C +#define ACP_SW0_TX_DP5_CHANNEL_ENABLE_BANK0 0x005440 +#define ACP_SW0_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005444 +#define ACP_SW0_TX_DP5_SAMPLEINTERVAL_BANK1 0x005448 +#define ACP_SW0_TX_DP5_HCTRL_BANK1 0x00544C +#define ACP_SW0_TX_DP5_HCTRL_OFFSET_BANK1 0x005450 +#define ACP_SW0_TX_DP5_LANE_CTRL_BANK1 0x005454 +#define ACP_SW0_TX_DP5_CHANNEL_ENABLE_BANK1 0x005458 +#define ACP_SW0_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00545C +#define ACP_SW0_TX_DP6_SAMPLEINTERVAL_BANK0 0x005460 +#define ACP_SW0_TX_DP6_HCTRL_BANK0 0x005464 +#define ACP_SW0_TX_DP6_HCTRL_OFFSET_BANK0 0x005468 +#define ACP_SW0_TX_DP6_LANE_CTRL_BANK0 0x00546C +#define ACP_SW0_TX_DP6_CHANNEL_ENABLE_BANK0 0x005470 +#define ACP_SW0_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005474 +#define ACP_SW0_TX_DP6_SAMPLEINTERVAL_BANK1 0x005478 +#define ACP_SW0_TX_DP6_HCTRL_BANK1 0x00547C +#define ACP_SW0_TX_DP6_HCTRL_OFFSET_BANK1 0x005480 +#define ACP_SW0_TX_DP6_LANE_CTRL_BANK1 0x005484 +#define ACP_SW0_TX_DP6_CHANNEL_ENABLE_BANK1 0x005488 +#define ACP_SW0_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00548C +#define ACP_SW0_TX_DP7_SAMPLEINTERVAL_BANK0 0x005490 +#define ACP_SW0_TX_DP7_HCTRL_BANK0 0x005494 +#define ACP_SW0_TX_DP7_HCTRL_OFFSET_BANK0 0x005498 +#define ACP_SW0_TX_DP7_LANE_CTRL_BANK0 0x00549C +#define ACP_SW0_TX_DP7_CHANNEL_ENABLE_BANK0 0x0054A0 +#define ACP_SW0_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0054A4 +#define ACP_SW0_TX_DP7_SAMPLEINTERVAL_BANK1 0x0054A8 +#define ACP_SW0_TX_DP7_HCTRL_BANK1 0x0054AC +#define ACP_SW0_TX_DP7_HCTRL_OFFSET_BANK1 0x0054B0 +#define ACP_SW0_TX_DP7_LANE_CTRL_BANK1 0x0054B4 +#define ACP_SW0_TX_DP7_CHANNEL_ENABLE_BANK1 0x0054B8 +#define ACP_SW0_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0054BC +#define ACP_SW0_RX_STREAM0_EN 0x005514 +#define ACP_SW0_RX_STREAM1_EN 0x005518 +#define ACP_SW0_RX_STREAM2_EN 0x00551C +#define ACP_SW0_RX_STREAM3_EN 0x005520 +#define ACP_SW0_RX_STREAM4_EN 0x005524 +#define ACP_SW0_RX_STREAM5_EN 0x005528 +#define ACP_SW0_RX_STREAM6_EN 0x00552C +#define ACP_SW0_RX_STREAM7_EN 0x005530 +#define ACP_SW0_RX_STREAM0_EN_STATUS 0x005534 +#define ACP_SW0_RX_STREAM1_EN_STATUS 0x005538 +#define ACP_SW0_RX_STREAM2_EN_STATUS 0x00553C +#define ACP_SW0_RX_STREAM3_EN_STATUS 0x005540 +#define ACP_SW0_RX_STREAM4_EN_STATUS 0x005544 +#define ACP_SW0_RX_STREAM5_EN_STATUS 0x005548 +#define ACP_SW0_RX_STREAM6_EN_STATUS 0x00554C +#define ACP_SW0_RX_STREAM7_EN_STATUS 0x005550 +#define ACP_SW0_RX_DP0_FRAME_FORMAT 0x005554 +#define ACP_SW0_RX_DP1_FRAME_FORMAT 0x005558 +#define ACP_SW0_RX_DP2_FRAME_FORMAT 0x00555C +#define ACP_SW0_RX_DP3_FRAME_FORMAT 0x005560 +#define ACP_SW0_RX_DP4_FRAME_FORMAT 0x005564 +#define ACP_SW0_RX_DP5_FRAME_FORMAT 0x005568 +#define ACP_SW0_RX_DP6_FRAME_FORMAT 0x00556C +#define ACP_SW0_RX_DP7_FRAME_FORMAT 0x005570 +#define ACP_SW0_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x005580 +#define ACP_SW0_RX_DP0_0_HCTRL_BANK0 0x005584 +#define ACP_SW0_RX_DP0_0_HCTRL_OFFSET_BANK0 0x005588 +#define ACP_SW0_RX_DP0_0_LANE_CTRL_BANK0 0x00558C +#define ACP_SW0_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x005590 +#define ACP_SW0_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005594 +#define ACP_SW0_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x005598 +#define ACP_SW0_RX_DP0_0_HCTRL_BANK1 0x00559C +#define ACP_SW0_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0055A0 +#define ACP_SW0_RX_DP0_0_LANE_CTRL_BANK1 0x0055A4 +#define ACP_SW0_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0055A8 +#define ACP_SW0_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0055AC +#define ACP_SW0_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0055B0 +#define ACP_SW0_RX_DP0_1_HCTRL_BANK0 0x0055B4 +#define ACP_SW0_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0055B8 +#define ACP_SW0_RX_DP0_1_LANE_CTRL_BANK0 0x0055BC +#define ACP_SW0_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0055C0 +#define ACP_SW0_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0055C4 +#define ACP_SW0_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0055C8 +#define ACP_SW0_RX_DP0_1_HCTRL_BANK1 0x0055CC +#define ACP_SW0_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0055D0 +#define ACP_SW0_RX_DP0_1_LANE_CTRL_BANK1 0x0055D4 +#define ACP_SW0_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0055D8 +#define ACP_SW0_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0055DC +#define ACP_SW0_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0055E0 +#define ACP_SW0_RX_DP0_2_HCTRL_BANK0 0x0055E4 +#define ACP_SW0_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0055E8 +#define ACP_SW0_RX_DP0_2_LANE_CTRL_BANK0 0x0055EC +#define ACP_SW0_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0055F0 +#define ACP_SW0_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0055F4 +#define ACP_SW0_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0055F8 +#define ACP_SW0_RX_DP0_2_HCTRL_BANK1 0x0055FC +#define ACP_SW0_RX_DP0_2_HCTRL_OFFSET_BANK1 0x005600 +#define ACP_SW0_RX_DP0_2_LANE_CTRL_BANK1 0x005604 +#define ACP_SW0_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x005608 +#define ACP_SW0_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00560C +#define ACP_SW0_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x005610 +#define ACP_SW0_RX_DP0_3_HCTRL_BANK0 0x005614 +#define ACP_SW0_RX_DP0_3_HCTRL_OFFSET_BANK0 0x005618 +#define ACP_SW0_RX_DP0_3_LANE_CTRL_BANK0 0x00561C +#define ACP_SW0_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x005620 +#define ACP_SW0_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005624 +#define ACP_SW0_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x005628 +#define ACP_SW0_RX_DP0_3_HCTRL_BANK1 0x00562C +#define ACP_SW0_RX_DP0_3_HCTRL_OFFSET_BANK1 0x005630 +#define ACP_SW0_RX_DP0_3_LANE_CTRL_BANK1 0x005634 +#define ACP_SW0_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x005638 +#define ACP_SW0_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00563C +#define ACP_SW0_RX_DP1_SAMPLEINTERVAL_BANK0 0x005670 +#define ACP_SW0_RX_DP1_HCTRL_BANK0 0x005674 +#define ACP_SW0_RX_DP1_HCTRL_OFFSET_BANK0 0x005678 +#define ACP_SW0_RX_DP1_LANE_CTRL_BANK0 0x00567C +#define ACP_SW0_RX_DP1_CHANNEL_ENABLE_BANK0 0x005680 +#define ACP_SW0_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005684 +#define ACP_SW0_RX_DP1_SAMPLEINTERVAL_BANK1 0x005688 +#define ACP_SW0_RX_DP1_HCTRL_BANK1 0x00568C +#define ACP_SW0_RX_DP1_HCTRL_OFFSET_BANK1 0x005690 +#define ACP_SW0_RX_DP1_LANE_CTRL_BANK1 0x005694 +#define ACP_SW0_RX_DP1_CHANNEL_ENABLE_BANK1 0x005698 +#define ACP_SW0_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00569C +#define ACP_SW0_RX_DP2_SAMPLEINTERVAL_BANK0 0x0056A0 +#define ACP_SW0_RX_DP2_HCTRL_BANK0 0x0056A4 +#define ACP_SW0_RX_DP2_HCTRL_OFFSET_BANK0 0x0056A8 +#define ACP_SW0_RX_DP2_LANE_CTRL_BANK0 0x0056AC +#define ACP_SW0_RX_DP2_CHANNEL_ENABLE_BANK0 0x0056B0 +#define ACP_SW0_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0056B4 +#define ACP_SW0_RX_DP2_SAMPLEINTERVAL_BANK1 0x0056B8 +#define ACP_SW0_RX_DP2_HCTRL_BANK1 0x0056BC +#define ACP_SW0_RX_DP2_HCTRL_OFFSET_BANK1 0x0056C0 +#define ACP_SW0_RX_DP2_LANE_CTRL_BANK1 0x0056C4 +#define ACP_SW0_RX_DP2_CHANNEL_ENABLE_BANK1 0x0056C8 +#define ACP_SW0_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0056CC +#define ACP_SW0_RX_DP3_SAMPLEINTERVAL_BANK0 0x0056D0 +#define ACP_SW0_RX_DP3_HCTRL_BANK0 0x0056D4 +#define ACP_SW0_RX_DP3_HCTRL_OFFSET_BANK0 0x0056D8 +#define ACP_SW0_RX_DP3_LANE_CTRL_BANK0 0x0056DC +#define ACP_SW0_RX_DP3_CHANNEL_ENABLE_BANK0 0x0056E0 +#define ACP_SW0_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0056E4 +#define ACP_SW0_RX_DP3_SAMPLEINTERVAL_BANK1 0x0056E8 +#define ACP_SW0_RX_DP3_HCTRL_BANK1 0x0056EC +#define ACP_SW0_RX_DP3_HCTRL_OFFSET_BANK1 0x0056F0 +#define ACP_SW0_RX_DP3_LANE_CTRL_BANK1 0x0056F4 +#define ACP_SW0_RX_DP3_CHANNEL_ENABLE_BANK1 0x0056F8 +#define ACP_SW0_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0056FC +#define ACP_SW0_RX_DP4_SAMPLEINTERVAL_BANK0 0x005700 +#define ACP_SW0_RX_DP4_HCTRL_BANK0 0x005704 +#define ACP_SW0_RX_DP4_HCTRL_OFFSET_BANK0 0x005708 +#define ACP_SW0_RX_DP4_LANE_CTRL_BANK0 0x00570C +#define ACP_SW0_RX_DP4_CHANNEL_ENABLE_BANK0 0x005710 +#define ACP_SW0_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005714 +#define ACP_SW0_RX_DP4_SAMPLEINTERVAL_BANK1 0x005718 +#define ACP_SW0_RX_DP4_HCTRL_BANK1 0x00571C +#define ACP_SW0_RX_DP4_HCTRL_OFFSET_BANK1 0x005720 +#define ACP_SW0_RX_DP4_LANE_CTRL_BANK1 0x005724 +#define ACP_SW0_RX_DP4_CHANNEL_ENABLE_BANK1 0x005728 +#define ACP_SW0_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00572C +#define ACP_SW0_RX_DP5_SAMPLEINTERVAL_BANK0 0x005730 +#define ACP_SW0_RX_DP5_HCTRL_BANK0 0x005734 +#define ACP_SW0_RX_DP5_HCTRL_OFFSET_BANK0 0x005738 +#define ACP_SW0_RX_DP5_LANE_CTRL_BANK0 0x00573C +#define ACP_SW0_RX_DP5_CHANNEL_ENABLE_BANK0 0x005740 +#define ACP_SW0_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005744 +#define ACP_SW0_RX_DP5_SAMPLEINTERVAL_BANK1 0x005748 +#define ACP_SW0_RX_DP5_HCTRL_BANK1 0x00574C +#define ACP_SW0_RX_DP5_HCTRL_OFFSET_BANK1 0x005750 +#define ACP_SW0_RX_DP5_LANE_CTRL_BANK1 0x005754 +#define ACP_SW0_RX_DP5_CHANNEL_ENABLE_BANK1 0x005758 +#define ACP_SW0_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00575C +#define ACP_SW0_RX_DP6_SAMPLEINTERVAL_BANK0 0x005760 +#define ACP_SW0_RX_DP6_HCTRL_BANK0 0x005764 +#define ACP_SW0_RX_DP6_HCTRL_OFFSET_BANK0 0x005768 +#define ACP_SW0_RX_DP6_LANE_CTRL_BANK0 0x00576C +#define ACP_SW0_RX_DP6_CHANNEL_ENABLE_BANK0 0x005770 +#define ACP_SW0_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005774 +#define ACP_SW0_RX_DP6_SAMPLEINTERVAL_BANK1 0x005778 +#define ACP_SW0_RX_DP6_HCTRL_BANK1 0x00577C +#define ACP_SW0_RX_DP6_HCTRL_OFFSET_BANK1 0x005780 +#define ACP_SW0_RX_DP6_LANE_CTRL_BANK1 0x005784 +#define ACP_SW0_RX_DP6_CHANNEL_ENABLE_BANK1 0x005788 +#define ACP_SW0_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00578C +#define ACP_SW0_RX_DP7_SAMPLEINTERVAL_BANK0 0x005790 +#define ACP_SW0_RX_DP7_HCTRL_BANK0 0x005794 +#define ACP_SW0_RX_DP7_HCTRL_OFFSET_BANK0 0x005798 +#define ACP_SW0_RX_DP7_LANE_CTRL_BANK0 0x00579C +#define ACP_SW0_RX_DP7_CHANNEL_ENABLE_BANK0 0x0057A0 +#define ACP_SW0_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0057A4 +#define ACP_SW0_RX_DP7_SAMPLEINTERVAL_BANK1 0x0057A8 +#define ACP_SW0_RX_DP7_HCTRL_BANK1 0x0057AC +#define ACP_SW0_RX_DP7_HCTRL_OFFSET_BANK1 0x0057B0 +#define ACP_SW0_RX_DP7_LANE_CTRL_BANK1 0x0057B4 +#define ACP_SW0_RX_DP7_CHANNEL_ENABLE_BANK1 0x0057B8 +#define ACP_SW0_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0057BC +#define ACP_SW0_BPT_PORT_EN 0x0057C0 +#define ACP_SW0_BPT_PORT_EN_STATUS 0x0057C4 +#define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0057C8 +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0057CC +#define ACP_SW0_BPT_PORT_HCTRL_BANK0 0x0057D0 +#define ACP_SW0_BPT_PORT_OFFSET_BANK0 0x0057D4 +#define ACP_SW0_BPT_PORT_LANE_SELECT_BANK0 0x0057D8 +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0057DC +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0057E0 +#define ACP_SW0_BPT_PORT_HCTRL_BANK1 0x0057E4 +#define ACP_SW0_BPT_PORT_OFFSET_BANK1 0x0057E8 +#define ACP_SW0_BPT_PORT_LANE_SELECT_BANK1 0x0057EC +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0057F0 +#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x0057F4 +#define ACP_SW0_CLK_RESUME_CTRL 0x0057F8 +#define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0057FC +#define ACP_SW0_BUS_RESET_CTRL 0x005800 +#define ACP_SW0_PRBS_ERR_STATUS 0x005804 +#define ACP_SW0_WALLCLK_MISC 0x005808 +#define ACP_SW0_WALL_CLK_COUNTER 0x00580C +#define ACP_SW0_PING_STATUS_REGISTER_LOW 0x005810 +#define ACP_SW0_PING_STATUS_REGISTER_HIGH 0x005814 +#define ACP_SW0_PING_STATUS_CURRENT_BANK_SEL 0x005818 +#define ACP_SW0_TZD_CHANGE 0x00581C +#define ACP_SW0_WALLCLK_INTR_CNTL 0x005820 + +#define ACP_SW1_GLOBAL_CAPABILITIES 0x006E00 +#define ACP_SW1_RX_DMA0_RINGBUFADDR 0x006E04 +#define ACP_SW1_RX_DMA0_RINGBUFSIZE 0x006E08 +#define ACP_SW1_RX_DMA0_FIFOADDR 0x006E0C +#define ACP_SW1_RX_DMA0_FIFOSIZE 0x006E10 +#define ACP_SW1_RX_DMA0_BURST_SIZE 0x006E14 +#define ACP_SW1_RX_DMA0_LINKPOSITIONCNTR 0x006E18 +#define ACP_SW1_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x006E1C +#define ACP_SW1_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x006E20 +#define ACP_SW1_RX_DMA0_INTR_WATERMARK_SIZE 0x006E24 +#define ACP_SW1_RX_DMA1_RINGBUFADDR 0x006E28 +#define ACP_SW1_RX_DMA1_RINGBUFSIZE 0x006E2C +#define ACP_SW1_RX_DMA1_FIFOADDR 0x006E30 +#define ACP_SW1_RX_DMA1_FIFOSIZE 0x006E34 +#define ACP_SW1_RX_DMA1_BURST_SIZE 0x006E38 +#define ACP_SW1_RX_DMA1_LINKPOSITIONCNTR 0x006E3C +#define ACP_SW1_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x006E40 +#define ACP_SW1_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x006E44 +#define ACP_SW1_RX_DMA1_INTR_WATERMARK_SIZE 0x006E48 +#define ACP_SW1_RX_DMA2_RINGBUFADDR 0x006E4C +#define ACP_SW1_RX_DMA2_RINGBUFSIZE 0x006E50 +#define ACP_SW1_RX_DMA2_FIFOADDR 0x006E54 +#define ACP_SW1_RX_DMA2_FIFOSIZE 0x006E58 +#define ACP_SW1_RX_DMA2_BURST_SIZE 0x006E5C +#define ACP_SW1_RX_DMA2_LINKPOSITIONCNTR 0x006E60 +#define ACP_SW1_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x006E64 +#define ACP_SW1_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x006E68 +#define ACP_SW1_RX_DMA2_INTR_WATERMARK_SIZE 0x006E6C +#define ACP_SW1_RX_DMA3_RINGBUFADDR 0x006E70 +#define ACP_SW1_RX_DMA3_RINGBUFSIZE 0x006E74 +#define ACP_SW1_RX_DMA3_FIFOADDR 0x006E78 +#define ACP_SW1_RX_DMA3_FIFOSIZE 0x006E7C +#define ACP_SW1_RX_DMA3_BURST_SIZE 0x006E80 +#define ACP_SW1_RX_DMA3_LINKPOSITIONCNTR 0x006E84 +#define ACP_SW1_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x006E88 +#define ACP_SW1_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x006E8C +#define ACP_SW1_RX_DMA3_INTR_WATERMARK_SIZE 0x006E90 +#define ACP_SW1_RX_DMA4_RINGBUFADDR 0x006E94 +#define ACP_SW1_RX_DMA4_RINGBUFSIZE 0x006E98 +#define ACP_SW1_RX_DMA4_FIFOADDR 0x006E9C +#define ACP_SW1_RX_DMA4_FIFOSIZE 0x006EA0 +#define ACP_SW1_RX_DMA4_BURST_SIZE 0x006EA4 +#define ACP_SW1_RX_DMA4_LINKPOSITIONCNTR 0x006EA8 +#define ACP_SW1_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x006EAC +#define ACP_SW1_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x006EB0 +#define ACP_SW1_RX_DMA4_INTR_WATERMARK_SIZE 0x006EB4 +#define ACP_SW1_RX_DMA5_RINGBUFADDR 0x006EB8 +#define ACP_SW1_RX_DMA5_RINGBUFSIZE 0x006EBC +#define ACP_SW1_RX_DMA5_FIFOADDR 0x006EC0 +#define ACP_SW1_RX_DMA5_FIFOSIZE 0x006EC4 +#define ACP_SW1_RX_DMA5_BURST_SIZE 0x006EC8 +#define ACP_SW1_RX_DMA5_LINKPOSITIONCNTR 0x006ECC +#define ACP_SW1_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x006ED0 +#define ACP_SW1_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x006ED4 +#define ACP_SW1_RX_DMA5_INTR_WATERMARK_SIZE 0x006ED8 +#define ACP_SW1_RX_DMA6_RINGBUFADDR 0x006EDC +#define ACP_SW1_RX_DMA6_RINGBUFSIZE 0x006EE0 +#define ACP_SW1_RX_DMA6_FIFOADDR 0x006EE4 +#define ACP_SW1_RX_DMA6_FIFOSIZE 0x006EE8 +#define ACP_SW1_RX_DMA6_BURST_SIZE 0x006EEC +#define ACP_SW1_RX_DMA6_LINKPOSITIONCNTR 0x006EF0 +#define ACP_SW1_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x006EF4 +#define ACP_SW1_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x006EF8 +#define ACP_SW1_RX_DMA6_INTR_WATERMARK_SIZE 0x006EFC +#define ACP_SW1_RX_DMA7_RINGBUFADDR 0x006F00 +#define ACP_SW1_RX_DMA7_RINGBUFSIZE 0x006F04 +#define ACP_SW1_RX_DMA7_FIFOADDR 0x006F08 +#define ACP_SW1_RX_DMA7_FIFOSIZE 0x006F0C +#define ACP_SW1_RX_DMA7_BURST_SIZE 0x006F10 +#define ACP_SW1_RX_DMA7_LINKPOSITIONCNTR 0x006F14 +#define ACP_SW1_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x006F18 +#define ACP_SW1_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x006F1C +#define ACP_SW1_RX_DMA7_INTR_WATERMARK_SIZE 0x006F20 +#define ACP_SW1_TX_DMA0_RINGBUFADDR 0x006F24 +#define ACP_SW1_TX_DMA0_RINGBUFSIZE 0x006F28 +#define ACP_SW1_TX_DMA0_FIFOADDR 0x006F2C +#define ACP_SW1_TX_DMA0_FIFOSIZE 0x006F30 +#define ACP_SW1_TX_DMA0_BURST_SIZE 0x006F34 +#define ACP_SW1_TX_DMA0_LINKPOSITIONCNTR 0x006F38 +#define ACP_SW1_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x006F3C +#define ACP_SW1_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x006F40 +#define ACP_SW1_TX_DMA0_INTR_WATERMARK_SIZE 0x006F44 +#define ACP_SW1_TX_DMA1_RINGBUFADDR 0x006F48 +#define ACP_SW1_TX_DMA1_RINGBUFSIZE 0x006F4C +#define ACP_SW1_TX_DMA1_FIFOADDR 0x006F50 +#define ACP_SW1_TX_DMA1_FIFOSIZE 0x006F54 +#define ACP_SW1_TX_DMA1_BURST_SIZE 0x006F58 +#define ACP_SW1_TX_DMA1_LINKPOSITIONCNTR 0x006F5C +#define ACP_SW1_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x006F60 +#define ACP_SW1_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x006F64 +#define ACP_SW1_TX_DMA1_INTR_WATERMARK_SIZE 0x006F68 +#define ACP_SW1_TX_DMA2_RINGBUFADDR 0x006F6C +#define ACP_SW1_TX_DMA2_RINGBUFSIZE 0x006F70 +#define ACP_SW1_TX_DMA2_FIFOADDR 0x006F74 +#define ACP_SW1_TX_DMA2_FIFOSIZE 0x006F78 +#define ACP_SW1_TX_DMA2_BURST_SIZE 0x006F7C +#define ACP_SW1_TX_DMA2_LINKPOSITIONCNTR 0x006F80 +#define ACP_SW1_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x006F84 +#define ACP_SW1_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x006F88 +#define ACP_SW1_TX_DMA2_INTR_WATERMARK_SIZE 0x006F8C +#define ACP_SW1_TX_DMA3_RINGBUFADDR 0x006F90 +#define ACP_SW1_TX_DMA3_RINGBUFSIZE 0x006F94 +#define ACP_SW1_TX_DMA3_FIFOADDR 0x006F98 +#define ACP_SW1_TX_DMA3_FIFOSIZE 0x006F9C +#define ACP_SW1_TX_DMA3_BURST_SIZE 0x006FA0 +#define ACP_SW1_TX_DMA3_LINKPOSITIONCNTR 0x006FA4 +#define ACP_SW1_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x006FA8 +#define ACP_SW1_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x006FAC +#define ACP_SW1_TX_DMA3_INTR_WATERMARK_SIZE 0x006FB0 +#define ACP_SW1_TX_DMA4_RINGBUFADDR 0x006FB4 +#define ACP_SW1_TX_DMA4_RINGBUFSIZE 0x006FB8 +#define ACP_SW1_TX_DMA4_FIFOADDR 0x006FBC +#define ACP_SW1_TX_DMA4_FIFOSIZE 0x006FC0 +#define ACP_SW1_TX_DMA4_BURST_SIZE 0x006FC4 +#define ACP_SW1_TX_DMA4_LINKPOSITIONCNTR 0x006FC8 +#define ACP_SW1_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x006FCC +#define ACP_SW1_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x006FD0 +#define ACP_SW1_TX_DMA4_INTR_WATERMARK_SIZE 0x006FD4 +#define ACP_SW1_TX_DMA5_RINGBUFADDR 0x006FD8 +#define ACP_SW1_TX_DMA5_RINGBUFSIZE 0x006FDC +#define ACP_SW1_TX_DMA5_FIFOADDR 0x006FE0 +#define ACP_SW1_TX_DMA5_FIFOSIZE 0x006FE4 +#define ACP_SW1_TX_DMA5_BURST_SIZE 0x006FE8 +#define ACP_SW1_TX_DMA5_LINKPOSITIONCNTR 0x006FEC +#define ACP_SW1_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x006FF0 +#define ACP_SW1_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x006FF4 +#define ACP_SW1_TX_DMA5_INTR_WATERMARK_SIZE 0x006FF8 +#define ACP_SW1_TX_DMA6_RINGBUFADDR 0x006FFC +#define ACP_SW1_TX_DMA6_RINGBUFSIZE 0x007000 +#define ACP_SW1_TX_DMA6_FIFOADDR 0x007004 +#define ACP_SW1_TX_DMA6_FIFOSIZE 0x007008 +#define ACP_SW1_TX_DMA6_BURST_SIZE 0x00700C +#define ACP_SW1_TX_DMA6_LINKPOSITIONCNTR 0x007010 +#define ACP_SW1_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x007014 +#define ACP_SW1_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x007018 +#define ACP_SW1_TX_DMA6_INTR_WATERMARK_SIZE 0x00701C +#define ACP_SW1_TX_DMA7_RINGBUFADDR 0x007020 +#define ACP_SW1_TX_DMA7_RINGBUFSIZE 0x007024 +#define ACP_SW1_TX_DMA7_FIFOADDR 0x007028 +#define ACP_SW1_TX_DMA7_FIFOSIZE 0x00702C +#define ACP_SW1_TX_DMA7_BURST_SIZE 0x007030 +#define ACP_SW1_TX_DMA7_LINKPOSITIONCNTR 0x007034 +#define ACP_SW1_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x007038 +#define ACP_SW1_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00703C +#define ACP_SW1_TX_DMA7_INTR_WATERMARK_SIZE 0x007040 +#define ACP_SW1_RX_DMA0_POS_TRACK 0x007044 +#define ACP_SW1_RX_DMA0_POS 0x007048 +#define ACP_SW1_RX_DMA1_POS_TRACK 0x00704C +#define ACP_SW1_RX_DMA1_POS 0x007050 +#define ACP_SW1_RX_DMA2_POS_TRACK 0x007054 +#define ACP_SW1_RX_DMA2_POS 0x007058 +#define ACP_SW1_RX_DMA3_POS_TRACK 0x00705C +#define ACP_SW1_RX_DMA3_POS 0x007060 +#define ACP_SW1_RX_DMA4_POS_TRACK 0x007064 +#define ACP_SW1_RX_DMA4_POS 0x007068 +#define ACP_SW1_RX_DMA5_POS_TRACK 0x00706C +#define ACP_SW1_RX_DMA5_POS 0x007070 +#define ACP_SW1_RX_DMA6_POS_TRACK 0x007074 +#define ACP_SW1_RX_DMA6_POS 0x007078 +#define ACP_SW1_RX_DMA7_POS_TRACK 0x00707C +#define ACP_SW1_RX_DMA7_POS 0x007080 +#define ACP_SW1_TX_DMA0_POS_TRACK 0x007084 +#define ACP_SW1_TX_DMA0_POS 0x007088 +#define ACP_SW1_TX_DMA1_POS_TRACK 0x00708C +#define ACP_SW1_TX_DMA1_POS 0x007090 +#define ACP_SW1_TX_DMA2_POS_TRACK 0x007094 +#define ACP_SW1_TX_DMA2_POS 0x007098 +#define ACP_SW1_TX_DMA3_POS_TRACK 0x00709C +#define ACP_SW1_TX_DMA3_POS 0x0070A0 +#define ACP_SW1_TX_DMA4_POS_TRACK 0x0070A4 +#define ACP_SW1_TX_DMA4_POS 0x0070A8 +#define ACP_SW1_TX_DMA5_POS_TRACK 0x0070AC +#define ACP_SW1_TX_DMA5_POS 0x0070B0 +#define ACP_SW1_TX_DMA6_POS_TRACK 0x0070B4 +#define ACP_SW1_TX_DMA6_POS 0x0070B8 +#define ACP_SW1_TX_DMA7_POS_TRACK 0x0070BC +#define ACP_SW1_TX_DMA7_POS 0x0070C0 +#define ACP_SW1_FIFO_ERROR_REASON 0x0070C4 +#define ACP_SW1_FIFO_ERROR_INTR_MASK 0x0070C8 +#define ACP_SW1_ERROR_REASON1 0x0070CC +#define ACP_SW1_ERROR_INTR_MASK1 0x0070D0 +#define ACP_SW1_ERROR_REASON2 0x0070D4 +#define ACP_SW1_ERROR_INTR_MASK2 0x0070D8 + +#define ACP_SW1_CORB_BASE_ADDRESS 0x007100 +#define ACP_SW1_CORB_WRITE_POINTER 0x007104 +#define ACP_SW1_CORB_READ_POINTER 0x007108 +#define ACP_SW1_CORB_CONTROL 0x00710C +#define ACP_SW1_CORB_SIZE 0x007114 +#define ACP_SW1_RIRB_BASE_ADDRESS 0x007118 +#define ACP_SW1_RIRB_WRITE_POINTER 0x00711C +#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x007120 +#define ACP_SW1_RIRB_CONTROL 0x007124 +#define ACP_SW1_RIRB_SIZE 0x007128 +#define ACP_SW1_RIRB_FIFO_MIN_THDL 0x00712C +#define ACP_SW1_IMM_CMD_UPPER_WORD 0x007130 +#define ACP_SW1_IMM_CMD_LOWER_QWORD 0x007134 +#define ACP_SW1_IMM_RESP_UPPER_WORD 0x007138 +#define ACP_SW1_IMM_RESP_LOWER_QWORD 0x00713C +#define ACP_SW1_IMM_CMD_STS 0x007140 +#define ACP_SW1_BRA_BASE_ADDRESS 0x007144 +#define ACP_SW1_BRA_TRANSFER_SIZE 0x007148 +#define ACP_SW1_BRA_DMA_BUSY 0x00714C +#define ACP_SW1_BRA_RESP 0x007150 +#define ACP_SW1_BRA_RESP_FRAME_ADDR 0x007154 +#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x007158 +#define ACP_SW1_STATE_CHANGE_STATUS_0TO7 0x00715C +#define ACP_SW1_STATE_CHANGE_STATUS_8TO11 0x007160 +#define ACP_SW1_STATE_CHANGE_STATUS_MASK_0TO7 0x007164 +#define ACP_SW1_STATE_CHANGE_STATUS_MASK_8TO11 0x007168 +#define ACP_SW1_CLK_FREQUENCY_CTRL_BANK0 0x00716C +#define ACP_SW1_CLK_FREQUENCY_CTRL_BANK1 0x007170 +#define ACP_SW1_ERROR_INTR_MASK 0x007174 +#define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x007178 +#define ACP_SW1_DATA_TO_PDM_EN 0x00717C + +#define ACP_SW1_EN 0x007200 +#define ACP_SW1_EN_STATUS 0x007204 +#define ACP_SW1_FRAMESIZE_BANK0 0x007208 +#define ACP_SW1_FRAMESIZE_BANK1 0x00720C +#define ACP_SW1_SSP_COUNTER 0x007210 +#define ACP_SW1_TX_STREAM0_EN 0x007214 +#define ACP_SW1_TX_STREAM1_EN 0x007218 +#define ACP_SW1_TX_STREAM2_EN 0x00721C +#define ACP_SW1_TX_STREAM3_EN 0x007220 +#define ACP_SW1_TX_STREAM4_EN 0x007224 +#define ACP_SW1_TX_STREAM5_EN 0x007228 +#define ACP_SW1_TX_STREAM6_EN 0x00722C +#define ACP_SW1_TX_STREAM7_EN 0x007230 +#define ACP_SW1_TX_STREAM0_EN_STATUS 0x007234 +#define ACP_SW1_TX_STREAM1_EN_STATUS 0x007238 +#define ACP_SW1_TX_STREAM2_EN_STATUS 0x00723C +#define ACP_SW1_TX_STREAM3_EN_STATUS 0x007240 +#define ACP_SW1_TX_STREAM4_EN_STATUS 0x007244 +#define ACP_SW1_TX_STREAM5_EN_STATUS 0x007248 +#define ACP_SW1_TX_STREAM6_EN_STATUS 0x00724C +#define ACP_SW1_TX_STREAM7_EN_STATUS 0x007250 +#define ACP_SW1_TX_DP0_FRAME_FORMAT 0x007254 +#define ACP_SW1_TX_DP1_FRAME_FORMAT 0x007258 +#define ACP_SW1_TX_DP2_FRAME_FORMAT 0x00725C +#define ACP_SW1_TX_DP3_FRAME_FORMAT 0x007260 +#define ACP_SW1_TX_DP4_FRAME_FORMAT 0x007264 +#define ACP_SW1_TX_DP5_FRAME_FORMAT 0x007268 +#define ACP_SW1_TX_DP6_FRAME_FORMAT 0x00726C +#define ACP_SW1_TX_DP7_FRAME_FORMAT 0x007270 +#define ACP_SW1_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x007280 +#define ACP_SW1_TX_DP0_0_HCTRL_BANK0 0x007284 +#define ACP_SW1_TX_DP0_0_HCTRL_OFFSET_BANK0 0x007288 +#define ACP_SW1_TX_DP0_0_LANE_CTRL_BANK0 0x00728C +#define ACP_SW1_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x007290 +#define ACP_SW1_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007294 +#define ACP_SW1_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x007298 +#define ACP_SW1_TX_DP0_0_HCTRL_BANK1 0x00729C +#define ACP_SW1_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0072A0 +#define ACP_SW1_TX_DP0_0_LANE_CTRL_BANK1 0x0072A4 +#define ACP_SW1_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0072A8 +#define ACP_SW1_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0072AC +#define ACP_SW1_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0072B0 +#define ACP_SW1_TX_DP0_1_HCTRL_BANK0 0x0072B4 +#define ACP_SW1_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0072B8 +#define ACP_SW1_TX_DP0_1_LANE_CTRL_BANK0 0x0072BC +#define ACP_SW1_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0072C0 +#define ACP_SW1_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0072C4 +#define ACP_SW1_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0072C8 +#define ACP_SW1_TX_DP0_1_HCTRL_BANK1 0x0072CC +#define ACP_SW1_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0072D0 +#define ACP_SW1_TX_DP0_1_LANE_CTRL_BANK1 0x0072D4 +#define ACP_SW1_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0072D8 +#define ACP_SW1_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0072DC +#define ACP_SW1_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0072E0 +#define ACP_SW1_TX_DP0_2_HCTRL_BANK0 0x0072E4 +#define ACP_SW1_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0072E8 +#define ACP_SW1_TX_DP0_2_LANE_CTRL_BANK0 0x0072EC +#define ACP_SW1_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0072F0 +#define ACP_SW1_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0072F4 +#define ACP_SW1_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0072F8 +#define ACP_SW1_TX_DP0_2_HCTRL_BANK1 0x0072FC +#define ACP_SW1_TX_DP0_2_HCTRL_OFFSET_BANK1 0x007300 +#define ACP_SW1_TX_DP0_2_LANE_CTRL_BANK1 0x007304 +#define ACP_SW1_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x007308 +#define ACP_SW1_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00730C +#define ACP_SW1_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x007310 +#define ACP_SW1_TX_DP0_3_HCTRL_BANK0 0x007314 +#define ACP_SW1_TX_DP0_3_HCTRL_OFFSET_BANK0 0x007318 +#define ACP_SW1_TX_DP0_3_LANE_CTRL_BANK0 0x00731C +#define ACP_SW1_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x007320 +#define ACP_SW1_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007324 +#define ACP_SW1_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x007328 +#define ACP_SW1_TX_DP0_3_HCTRL_BANK1 0x00732C +#define ACP_SW1_TX_DP0_3_HCTRL_OFFSET_BANK1 0x007330 +#define ACP_SW1_TX_DP0_3_LANE_CTRL_BANK1 0x007334 +#define ACP_SW1_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x007338 +#define ACP_SW1_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00733C +#define ACP_SW1_TX_DP1_SAMPLEINTERVAL_BANK0 0x007370 +#define ACP_SW1_TX_DP1_HCTRL_BANK0 0x007374 +#define ACP_SW1_TX_DP1_HCTRL_OFFSET_BANK0 0x007378 +#define ACP_SW1_TX_DP1_LANE_CTRL_BANK0 0x00737C +#define ACP_SW1_TX_DP1_CHANNEL_ENABLE_BANK0 0x007380 +#define ACP_SW1_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007384 +#define ACP_SW1_TX_DP1_SAMPLEINTERVAL_BANK1 0x007388 +#define ACP_SW1_TX_DP1_HCTRL_BANK1 0x00738C +#define ACP_SW1_TX_DP1_HCTRL_OFFSET_BANK1 0x007390 +#define ACP_SW1_TX_DP1_LANE_CTRL_BANK1 0x007394 +#define ACP_SW1_TX_DP1_CHANNEL_ENABLE_BANK1 0x007398 +#define ACP_SW1_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00739C +#define ACP_SW1_TX_DP2_SAMPLEINTERVAL_BANK0 0x0073A0 +#define ACP_SW1_TX_DP2_HCTRL_BANK0 0x0073A4 +#define ACP_SW1_TX_DP2_HCTRL_OFFSET_BANK0 0x0073A8 +#define ACP_SW1_TX_DP2_LANE_CTRL_BANK0 0x0073AC +#define ACP_SW1_TX_DP2_CHANNEL_ENABLE_BANK0 0x0073B0 +#define ACP_SW1_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0073B4 +#define ACP_SW1_TX_DP2_SAMPLEINTERVAL_BANK1 0x0073B8 +#define ACP_SW1_TX_DP2_HCTRL_BANK1 0x0073BC +#define ACP_SW1_TX_DP2_HCTRL_OFFSET_BANK1 0x0073C0 +#define ACP_SW1_TX_DP2_LANE_CTRL_BANK1 0x0073C4 +#define ACP_SW1_TX_DP2_CHANNEL_ENABLE_BANK1 0x0073C8 +#define ACP_SW1_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0073CC +#define ACP_SW1_TX_DP3_SAMPLEINTERVAL_BANK0 0x0073D0 +#define ACP_SW1_TX_DP3_HCTRL_BANK0 0x0073D4 +#define ACP_SW1_TX_DP3_HCTRL_OFFSET_BANK0 0x0073D8 +#define ACP_SW1_TX_DP3_LANE_CTRL_BANK0 0x0073DC +#define ACP_SW1_TX_DP3_CHANNEL_ENABLE_BANK0 0x0073E0 +#define ACP_SW1_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0073E4 +#define ACP_SW1_TX_DP3_SAMPLEINTERVAL_BANK1 0x0073E8 +#define ACP_SW1_TX_DP3_HCTRL_BANK1 0x0073EC +#define ACP_SW1_TX_DP3_HCTRL_OFFSET_BANK1 0x0073F0 +#define ACP_SW1_TX_DP3_LANE_CTRL_BANK1 0x0073F4 +#define ACP_SW1_TX_DP3_CHANNEL_ENABLE_BANK1 0x0073F8 +#define ACP_SW1_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0073FC +#define ACP_SW1_TX_DP4_SAMPLEINTERVAL_BANK0 0x007400 +#define ACP_SW1_TX_DP4_HCTRL_BANK0 0x007404 +#define ACP_SW1_TX_DP4_HCTRL_OFFSET_BANK0 0x007408 +#define ACP_SW1_TX_DP4_LANE_CTRL_BANK0 0x00740C +#define ACP_SW1_TX_DP4_CHANNEL_ENABLE_BANK0 0x007410 +#define ACP_SW1_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007414 +#define ACP_SW1_TX_DP4_SAMPLEINTERVAL_BANK1 0x007418 +#define ACP_SW1_TX_DP4_HCTRL_BANK1 0x00741C +#define ACP_SW1_TX_DP4_HCTRL_OFFSET_BANK1 0x007420 +#define ACP_SW1_TX_DP4_LANE_CTRL_BANK1 0x007424 +#define ACP_SW1_TX_DP4_CHANNEL_ENABLE_BANK1 0x007428 +#define ACP_SW1_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00742C +#define ACP_SW1_TX_DP5_SAMPLEINTERVAL_BANK0 0x007430 +#define ACP_SW1_TX_DP5_HCTRL_BANK0 0x007434 +#define ACP_SW1_TX_DP5_HCTRL_OFFSET_BANK0 0x007438 +#define ACP_SW1_TX_DP5_LANE_CTRL_BANK0 0x00743C +#define ACP_SW1_TX_DP5_CHANNEL_ENABLE_BANK0 0x007440 +#define ACP_SW1_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007444 +#define ACP_SW1_TX_DP5_SAMPLEINTERVAL_BANK1 0x007448 +#define ACP_SW1_TX_DP5_HCTRL_BANK1 0x00744C +#define ACP_SW1_TX_DP5_HCTRL_OFFSET_BANK1 0x007450 +#define ACP_SW1_TX_DP5_LANE_CTRL_BANK1 0x007454 +#define ACP_SW1_TX_DP5_CHANNEL_ENABLE_BANK1 0x007458 +#define ACP_SW1_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00745C +#define ACP_SW1_TX_DP6_SAMPLEINTERVAL_BANK0 0x007460 +#define ACP_SW1_TX_DP6_HCTRL_BANK0 0x007464 +#define ACP_SW1_TX_DP6_HCTRL_OFFSET_BANK0 0x007468 +#define ACP_SW1_TX_DP6_LANE_CTRL_BANK0 0x00746C +#define ACP_SW1_TX_DP6_CHANNEL_ENABLE_BANK0 0x007470 +#define ACP_SW1_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007474 +#define ACP_SW1_TX_DP6_SAMPLEINTERVAL_BANK1 0x007478 +#define ACP_SW1_TX_DP6_HCTRL_BANK1 0x00747C +#define ACP_SW1_TX_DP6_HCTRL_OFFSET_BANK1 0x007480 +#define ACP_SW1_TX_DP6_LANE_CTRL_BANK1 0x007484 +#define ACP_SW1_TX_DP6_CHANNEL_ENABLE_BANK1 0x007488 +#define ACP_SW1_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00748C +#define ACP_SW1_TX_DP7_SAMPLEINTERVAL_BANK0 0x007490 +#define ACP_SW1_TX_DP7_HCTRL_BANK0 0x007494 +#define ACP_SW1_TX_DP7_HCTRL_OFFSET_BANK0 0x007498 +#define ACP_SW1_TX_DP7_LANE_CTRL_BANK0 0x00749C +#define ACP_SW1_TX_DP7_CHANNEL_ENABLE_BANK0 0x0074A0 +#define ACP_SW1_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0074A4 +#define ACP_SW1_TX_DP7_SAMPLEINTERVAL_BANK1 0x0074A8 +#define ACP_SW1_TX_DP7_HCTRL_BANK1 0x0074AC +#define ACP_SW1_TX_DP7_HCTRL_OFFSET_BANK1 0x0074B0 +#define ACP_SW1_TX_DP7_LANE_CTRL_BANK1 0x0074B4 +#define ACP_SW1_TX_DP7_CHANNEL_ENABLE_BANK1 0x0074B8 +#define ACP_SW1_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0074BC +#define ACP_SW1_RX_STREAM0_EN 0x007514 +#define ACP_SW1_RX_STREAM1_EN 0x007518 +#define ACP_SW1_RX_STREAM2_EN 0x00751C +#define ACP_SW1_RX_STREAM3_EN 0x007520 +#define ACP_SW1_RX_STREAM4_EN 0x007524 +#define ACP_SW1_RX_STREAM5_EN 0x007528 +#define ACP_SW1_RX_STREAM6_EN 0x00752C +#define ACP_SW1_RX_STREAM7_EN 0x007530 +#define ACP_SW1_RX_STREAM0_EN_STATUS 0x007534 +#define ACP_SW1_RX_STREAM1_EN_STATUS 0x007538 +#define ACP_SW1_RX_STREAM2_EN_STATUS 0x00753C +#define ACP_SW1_RX_STREAM3_EN_STATUS 0x007540 +#define ACP_SW1_RX_STREAM4_EN_STATUS 0x007544 +#define ACP_SW1_RX_STREAM5_EN_STATUS 0x007548 +#define ACP_SW1_RX_STREAM6_EN_STATUS 0x00754C +#define ACP_SW1_RX_STREAM7_EN_STATUS 0x007550 +#define ACP_SW1_RX_DP0_FRAME_FORMAT 0x007554 +#define ACP_SW1_RX_DP1_FRAME_FORMAT 0x007558 +#define ACP_SW1_RX_DP2_FRAME_FORMAT 0x00755C +#define ACP_SW1_RX_DP3_FRAME_FORMAT 0x007560 +#define ACP_SW1_RX_DP4_FRAME_FORMAT 0x007564 +#define ACP_SW1_RX_DP5_FRAME_FORMAT 0x007568 +#define ACP_SW1_RX_DP6_FRAME_FORMAT 0x00756C +#define ACP_SW1_RX_DP7_FRAME_FORMAT 0x007570 +#define ACP_SW1_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x007580 +#define ACP_SW1_RX_DP0_0_HCTRL_BANK0 0x007584 +#define ACP_SW1_RX_DP0_0_HCTRL_OFFSET_BANK0 0x007588 +#define ACP_SW1_RX_DP0_0_LANE_CTRL_BANK0 0x00758C +#define ACP_SW1_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x007590 +#define ACP_SW1_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007594 +#define ACP_SW1_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x007598 +#define ACP_SW1_RX_DP0_0_HCTRL_BANK1 0x00759C +#define ACP_SW1_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0075A0 +#define ACP_SW1_RX_DP0_0_LANE_CTRL_BANK1 0x0075A4 +#define ACP_SW1_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0075A8 +#define ACP_SW1_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0075AC +#define ACP_SW1_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0075B0 +#define ACP_SW1_RX_DP0_1_HCTRL_BANK0 0x0075B4 +#define ACP_SW1_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0075B8 +#define ACP_SW1_RX_DP0_1_LANE_CTRL_BANK0 0x0075BC +#define ACP_SW1_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0075C0 +#define ACP_SW1_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0075C4 +#define ACP_SW1_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0075C8 +#define ACP_SW1_RX_DP0_1_HCTRL_BANK1 0x0075CC +#define ACP_SW1_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0075D0 +#define ACP_SW1_RX_DP0_1_LANE_CTRL_BANK1 0x0075D4 +#define ACP_SW1_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0075D8 +#define ACP_SW1_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0075DC +#define ACP_SW1_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0075E0 +#define ACP_SW1_RX_DP0_2_HCTRL_BANK0 0x0075E4 +#define ACP_SW1_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0075E8 +#define ACP_SW1_RX_DP0_2_LANE_CTRL_BANK0 0x0075EC +#define ACP_SW1_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0075F0 +#define ACP_SW1_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0075F4 +#define ACP_SW1_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0075F8 +#define ACP_SW1_RX_DP0_2_HCTRL_BANK1 0x0075FC +#define ACP_SW1_RX_DP0_2_HCTRL_OFFSET_BANK1 0x007600 +#define ACP_SW1_RX_DP0_2_LANE_CTRL_BANK1 0x007604 +#define ACP_SW1_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x007608 +#define ACP_SW1_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00760C +#define ACP_SW1_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x007610 +#define ACP_SW1_RX_DP0_3_HCTRL_BANK0 0x007614 +#define ACP_SW1_RX_DP0_3_HCTRL_OFFSET_BANK0 0x007618 +#define ACP_SW1_RX_DP0_3_LANE_CTRL_BANK0 0x00761C +#define ACP_SW1_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x007620 +#define ACP_SW1_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007624 +#define ACP_SW1_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x007628 +#define ACP_SW1_RX_DP0_3_HCTRL_BANK1 0x00762C +#define ACP_SW1_RX_DP0_3_HCTRL_OFFSET_BANK1 0x007630 +#define ACP_SW1_RX_DP0_3_LANE_CTRL_BANK1 0x007634 +#define ACP_SW1_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x007638 +#define ACP_SW1_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00763C +#define ACP_SW1_RX_DP1_SAMPLEINTERVAL_BANK0 0x007670 +#define ACP_SW1_RX_DP1_HCTRL_BANK0 0x007674 +#define ACP_SW1_RX_DP1_HCTRL_OFFSET_BANK0 0x007678 +#define ACP_SW1_RX_DP1_LANE_CTRL_BANK0 0x00767C +#define ACP_SW1_RX_DP1_CHANNEL_ENABLE_BANK0 0x007680 +#define ACP_SW1_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007684 +#define ACP_SW1_RX_DP1_SAMPLEINTERVAL_BANK1 0x007688 +#define ACP_SW1_RX_DP1_HCTRL_BANK1 0x00768C +#define ACP_SW1_RX_DP1_HCTRL_OFFSET_BANK1 0x007690 +#define ACP_SW1_RX_DP1_LANE_CTRL_BANK1 0x007694 +#define ACP_SW1_RX_DP1_CHANNEL_ENABLE_BANK1 0x007698 +#define ACP_SW1_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00769C +#define ACP_SW1_RX_DP2_SAMPLEINTERVAL_BANK0 0x0076A0 +#define ACP_SW1_RX_DP2_HCTRL_BANK0 0x0076A4 +#define ACP_SW1_RX_DP2_HCTRL_OFFSET_BANK0 0x0076A8 +#define ACP_SW1_RX_DP2_LANE_CTRL_BANK0 0x0076AC +#define ACP_SW1_RX_DP2_CHANNEL_ENABLE_BANK0 0x0076B0 +#define ACP_SW1_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0076B4 +#define ACP_SW1_RX_DP2_SAMPLEINTERVAL_BANK1 0x0076B8 +#define ACP_SW1_RX_DP2_HCTRL_BANK1 0x0076BC +#define ACP_SW1_RX_DP2_HCTRL_OFFSET_BANK1 0x0076C0 +#define ACP_SW1_RX_DP2_LANE_CTRL_BANK1 0x0076C4 +#define ACP_SW1_RX_DP2_CHANNEL_ENABLE_BANK1 0x0076C8 +#define ACP_SW1_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0076CC +#define ACP_SW1_RX_DP3_SAMPLEINTERVAL_BANK0 0x0076D0 +#define ACP_SW1_RX_DP3_HCTRL_BANK0 0x0076D4 +#define ACP_SW1_RX_DP3_HCTRL_OFFSET_BANK0 0x0076D8 +#define ACP_SW1_RX_DP3_LANE_CTRL_BANK0 0x0076DC +#define ACP_SW1_RX_DP3_CHANNEL_ENABLE_BANK0 0x0076E0 +#define ACP_SW1_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0076E4 +#define ACP_SW1_RX_DP3_SAMPLEINTERVAL_BANK1 0x0076E8 +#define ACP_SW1_RX_DP3_HCTRL_BANK1 0x0076EC +#define ACP_SW1_RX_DP3_HCTRL_OFFSET_BANK1 0x0076F0 +#define ACP_SW1_RX_DP3_LANE_CTRL_BANK1 0x0076F4 +#define ACP_SW1_RX_DP3_CHANNEL_ENABLE_BANK1 0x0076F8 +#define ACP_SW1_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0076FC +#define ACP_SW1_RX_DP4_SAMPLEINTERVAL_BANK0 0x007700 +#define ACP_SW1_RX_DP4_HCTRL_BANK0 0x007704 +#define ACP_SW1_RX_DP4_HCTRL_OFFSET_BANK0 0x007708 +#define ACP_SW1_RX_DP4_LANE_CTRL_BANK0 0x00770C +#define ACP_SW1_RX_DP4_CHANNEL_ENABLE_BANK0 0x007710 +#define ACP_SW1_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007714 +#define ACP_SW1_RX_DP4_SAMPLEINTERVAL_BANK1 0x007718 +#define ACP_SW1_RX_DP4_HCTRL_BANK1 0x00771C +#define ACP_SW1_RX_DP4_HCTRL_OFFSET_BANK1 0x007720 +#define ACP_SW1_RX_DP4_LANE_CTRL_BANK1 0x007724 +#define ACP_SW1_RX_DP4_CHANNEL_ENABLE_BANK1 0x007728 +#define ACP_SW1_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00772C +#define ACP_SW1_RX_DP5_SAMPLEINTERVAL_BANK0 0x007730 +#define ACP_SW1_RX_DP5_HCTRL_BANK0 0x007734 +#define ACP_SW1_RX_DP5_HCTRL_OFFSET_BANK0 0x007738 +#define ACP_SW1_RX_DP5_LANE_CTRL_BANK0 0x00773C +#define ACP_SW1_RX_DP5_CHANNEL_ENABLE_BANK0 0x007740 +#define ACP_SW1_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007744 +#define ACP_SW1_RX_DP5_SAMPLEINTERVAL_BANK1 0x007748 +#define ACP_SW1_RX_DP5_HCTRL_BANK1 0x00774C +#define ACP_SW1_RX_DP5_HCTRL_OFFSET_BANK1 0x007750 +#define ACP_SW1_RX_DP5_LANE_CTRL_BANK1 0x007754 +#define ACP_SW1_RX_DP5_CHANNEL_ENABLE_BANK1 0x007758 +#define ACP_SW1_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00775C +#define ACP_SW1_RX_DP6_SAMPLEINTERVAL_BANK0 0x007760 +#define ACP_SW1_RX_DP6_HCTRL_BANK0 0x007764 +#define ACP_SW1_RX_DP6_HCTRL_OFFSET_BANK0 0x007768 +#define ACP_SW1_RX_DP6_LANE_CTRL_BANK0 0x00776C +#define ACP_SW1_RX_DP6_CHANNEL_ENABLE_BANK0 0x007770 +#define ACP_SW1_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007774 +#define ACP_SW1_RX_DP6_SAMPLEINTERVAL_BANK1 0x007778 +#define ACP_SW1_RX_DP6_HCTRL_BANK1 0x00777C +#define ACP_SW1_RX_DP6_HCTRL_OFFSET_BANK1 0x007780 +#define ACP_SW1_RX_DP6_LANE_CTRL_BANK1 0x007784 +#define ACP_SW1_RX_DP6_CHANNEL_ENABLE_BANK1 0x007788 +#define ACP_SW1_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00778C +#define ACP_SW1_RX_DP7_SAMPLEINTERVAL_BANK0 0x007790 +#define ACP_SW1_RX_DP7_HCTRL_BANK0 0x007794 +#define ACP_SW1_RX_DP7_HCTRL_OFFSET_BANK0 0x007798 +#define ACP_SW1_RX_DP7_LANE_CTRL_BANK0 0x00779C +#define ACP_SW1_RX_DP7_CHANNEL_ENABLE_BANK0 0x0077A0 +#define ACP_SW1_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0077A4 +#define ACP_SW1_RX_DP7_SAMPLEINTERVAL_BANK1 0x0077A8 +#define ACP_SW1_RX_DP7_HCTRL_BANK1 0x0077AC +#define ACP_SW1_RX_DP7_HCTRL_OFFSET_BANK1 0x0077B0 +#define ACP_SW1_RX_DP7_LANE_CTRL_BANK1 0x0077B4 +#define ACP_SW1_RX_DP7_CHANNEL_ENABLE_BANK1 0x0077B8 +#define ACP_SW1_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0077BC +#define ACP_SW1_BPT_PORT_EN 0x0077C0 +#define ACP_SW1_BPT_PORT_EN_STATUS 0x0077C4 +#define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0077C8 +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0077CC +#define ACP_SW1_BPT_PORT_HCTRL_BANK0 0x0077D0 +#define ACP_SW1_BPT_PORT_OFFSET_BANK0 0x0077D4 +#define ACP_SW1_BPT_PORT_LANE_SELECT_BANK0 0x0077D8 +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0077DC +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0077E0 +#define ACP_SW1_BPT_PORT_HCTRL_BANK1 0x0077E4 +#define ACP_SW1_BPT_PORT_OFFSET_BANK1 0x0077E8 +#define ACP_SW1_BPT_PORT_LANE_SELECT_BANK1 0x0077EC +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0077F0 +#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0077F4 +#define ACP_SW1_CLK_RESUME_CTRL 0x0077F8 +#define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0077FC +#define ACP_SW1_BUS_RESET_CTRL 0x007800 +#define ACP_SW1_PRBS_ERR_STATUS 0x007804 +#define ACP_SW1_WALLCLK_MISC 0x007808 +#define ACP_SW1_WALL_CLK_COUNTER 0x00780C +#define ACP_SW1_PING_STATUS_REGISTER_LOW 0x007810 +#define ACP_SW1_PING_STATUS_REGISTER_HIGH 0x007814 +#define ACP_SW1_PING_STATUS_CURRENT_BANK_SEL 0x007818 +#define ACP_SW1_TZD_CHANGE 0x00781C +#define ACP_SW1_WALLCLK_INTR_CNTL 0x007820 + +#define ACP_SW2_GLOBAL_CAPABILITIES 0x008E00 +#define ACP_SW2_RX_DMA0_RINGBUFADDR 0x008E04 +#define ACP_SW2_RX_DMA0_RINGBUFSIZE 0x008E08 +#define ACP_SW2_RX_DMA0_FIFOADDR 0x008E0C +#define ACP_SW2_RX_DMA0_FIFOSIZE 0x008E10 +#define ACP_SW2_RX_DMA0_BURST_SIZE 0x008E14 +#define ACP_SW2_RX_DMA0_LINKPOSITIONCNTR 0x008E18 +#define ACP_SW2_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x008E1C +#define ACP_SW2_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x008E20 +#define ACP_SW2_RX_DMA0_INTR_WATERMARK_SIZE 0x008E24 +#define ACP_SW2_RX_DMA1_RINGBUFADDR 0x008E28 +#define ACP_SW2_RX_DMA1_RINGBUFSIZE 0x008E2C +#define ACP_SW2_RX_DMA1_FIFOADDR 0x008E30 +#define ACP_SW2_RX_DMA1_FIFOSIZE 0x008E34 +#define ACP_SW2_RX_DMA1_BURST_SIZE 0x008E38 +#define ACP_SW2_RX_DMA1_LINKPOSITIONCNTR 0x008E3C +#define ACP_SW2_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x008E40 +#define ACP_SW2_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x008E44 +#define ACP_SW2_RX_DMA1_INTR_WATERMARK_SIZE 0x008E48 +#define ACP_SW2_RX_DMA2_RINGBUFADDR 0x008E4C +#define ACP_SW2_RX_DMA2_RINGBUFSIZE 0x008E50 +#define ACP_SW2_RX_DMA2_FIFOADDR 0x008E54 +#define ACP_SW2_RX_DMA2_FIFOSIZE 0x008E58 +#define ACP_SW2_RX_DMA2_BURST_SIZE 0x008E5C +#define ACP_SW2_RX_DMA2_LINKPOSITIONCNTR 0x008E60 +#define ACP_SW2_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x008E64 +#define ACP_SW2_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x008E68 +#define ACP_SW2_RX_DMA2_INTR_WATERMARK_SIZE 0x008E6C +#define ACP_SW2_RX_DMA3_RINGBUFADDR 0x008E70 +#define ACP_SW2_RX_DMA3_RINGBUFSIZE 0x008E74 +#define ACP_SW2_RX_DMA3_FIFOADDR 0x008E78 +#define ACP_SW2_RX_DMA3_FIFOSIZE 0x008E7C +#define ACP_SW2_RX_DMA3_BURST_SIZE 0x008E80 +#define ACP_SW2_RX_DMA3_LINKPOSITIONCNTR 0x008E84 +#define ACP_SW2_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x008E88 +#define ACP_SW2_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x008E8C +#define ACP_SW2_RX_DMA3_INTR_WATERMARK_SIZE 0x008E90 +#define ACP_SW2_RX_DMA4_RINGBUFADDR 0x008E94 +#define ACP_SW2_RX_DMA4_RINGBUFSIZE 0x008E98 +#define ACP_SW2_RX_DMA4_FIFOADDR 0x008E9C +#define ACP_SW2_RX_DMA4_FIFOSIZE 0x008EA0 +#define ACP_SW2_RX_DMA4_BURST_SIZE 0x008EA4 +#define ACP_SW2_RX_DMA4_LINKPOSITIONCNTR 0x008EA8 +#define ACP_SW2_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x008EAC +#define ACP_SW2_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x008EB0 +#define ACP_SW2_RX_DMA4_INTR_WATERMARK_SIZE 0x008EB4 +#define ACP_SW2_RX_DMA5_RINGBUFADDR 0x008EB8 +#define ACP_SW2_RX_DMA5_RINGBUFSIZE 0x008EBC +#define ACP_SW2_RX_DMA5_FIFOADDR 0x008EC0 +#define ACP_SW2_RX_DMA5_FIFOSIZE 0x008EC4 +#define ACP_SW2_RX_DMA5_BURST_SIZE 0x008EC8 +#define ACP_SW2_RX_DMA5_LINKPOSITIONCNTR 0x008ECC +#define ACP_SW2_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x008ED0 +#define ACP_SW2_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x008ED4 +#define ACP_SW2_RX_DMA5_INTR_WATERMARK_SIZE 0x008ED8 +#define ACP_SW2_RX_DMA6_RINGBUFADDR 0x008EDC +#define ACP_SW2_RX_DMA6_RINGBUFSIZE 0x008EE0 +#define ACP_SW2_RX_DMA6_FIFOADDR 0x008EE4 +#define ACP_SW2_RX_DMA6_FIFOSIZE 0x008EE8 +#define ACP_SW2_RX_DMA6_BURST_SIZE 0x008EEC +#define ACP_SW2_RX_DMA6_LINKPOSITIONCNTR 0x008EF0 +#define ACP_SW2_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x008EF4 +#define ACP_SW2_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x008EF8 +#define ACP_SW2_RX_DMA6_INTR_WATERMARK_SIZE 0x008EFC +#define ACP_SW2_RX_DMA7_RINGBUFADDR 0x008F00 +#define ACP_SW2_RX_DMA7_RINGBUFSIZE 0x008F04 +#define ACP_SW2_RX_DMA7_FIFOADDR 0x008F08 +#define ACP_SW2_RX_DMA7_FIFOSIZE 0x008F0C +#define ACP_SW2_RX_DMA7_BURST_SIZE 0x008F10 +#define ACP_SW2_RX_DMA7_LINKPOSITIONCNTR 0x008F14 +#define ACP_SW2_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x008F18 +#define ACP_SW2_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x008F1C +#define ACP_SW2_RX_DMA7_INTR_WATERMARK_SIZE 0x008F20 +#define ACP_SW2_TX_DMA0_RINGBUFADDR 0x008F24 +#define ACP_SW2_TX_DMA0_RINGBUFSIZE 0x008F28 +#define ACP_SW2_TX_DMA0_FIFOADDR 0x008F2C +#define ACP_SW2_TX_DMA0_FIFOSIZE 0x008F30 +#define ACP_SW2_TX_DMA0_BURST_SIZE 0x008F34 +#define ACP_SW2_TX_DMA0_LINKPOSITIONCNTR 0x008F38 +#define ACP_SW2_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x008F3C +#define ACP_SW2_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x008F40 +#define ACP_SW2_TX_DMA0_INTR_WATERMARK_SIZE 0x008F44 +#define ACP_SW2_TX_DMA1_RINGBUFADDR 0x008F48 +#define ACP_SW2_TX_DMA1_RINGBUFSIZE 0x008F4C +#define ACP_SW2_TX_DMA1_FIFOADDR 0x008F50 +#define ACP_SW2_TX_DMA1_FIFOSIZE 0x008F54 +#define ACP_SW2_TX_DMA1_BURST_SIZE 0x008F58 +#define ACP_SW2_TX_DMA1_LINKPOSITIONCNTR 0x008F5C +#define ACP_SW2_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x008F60 +#define ACP_SW2_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x008F64 +#define ACP_SW2_TX_DMA1_INTR_WATERMARK_SIZE 0x008F68 +#define ACP_SW2_TX_DMA2_RINGBUFADDR 0x008F6C +#define ACP_SW2_TX_DMA2_RINGBUFSIZE 0x008F70 +#define ACP_SW2_TX_DMA2_FIFOADDR 0x008F74 +#define ACP_SW2_TX_DMA2_FIFOSIZE 0x008F78 +#define ACP_SW2_TX_DMA2_BURST_SIZE 0x008F7C +#define ACP_SW2_TX_DMA2_LINKPOSITIONCNTR 0x008F80 +#define ACP_SW2_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x008F84 +#define ACP_SW2_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x008F88 +#define ACP_SW2_TX_DMA2_INTR_WATERMARK_SIZE 0x008F8C +#define ACP_SW2_TX_DMA3_RINGBUFADDR 0x008F90 +#define ACP_SW2_TX_DMA3_RINGBUFSIZE 0x008F94 +#define ACP_SW2_TX_DMA3_FIFOADDR 0x008F98 +#define ACP_SW2_TX_DMA3_FIFOSIZE 0x008F9C +#define ACP_SW2_TX_DMA3_BURST_SIZE 0x008FA0 +#define ACP_SW2_TX_DMA3_LINKPOSITIONCNTR 0x008FA4 +#define ACP_SW2_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x008FA8 +#define ACP_SW2_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x008FAC +#define ACP_SW2_TX_DMA3_INTR_WATERMARK_SIZE 0x008FB0 +#define ACP_SW2_TX_DMA4_RINGBUFADDR 0x008FB4 +#define ACP_SW2_TX_DMA4_RINGBUFSIZE 0x008FB8 +#define ACP_SW2_TX_DMA4_FIFOADDR 0x008FBC +#define ACP_SW2_TX_DMA4_FIFOSIZE 0x008FC0 +#define ACP_SW2_TX_DMA4_BURST_SIZE 0x008FC4 +#define ACP_SW2_TX_DMA4_LINKPOSITIONCNTR 0x008FC8 +#define ACP_SW2_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x008FCC +#define ACP_SW2_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x008FD0 +#define ACP_SW2_TX_DMA4_INTR_WATERMARK_SIZE 0x008FD4 +#define ACP_SW2_TX_DMA5_RINGBUFADDR 0x008FD8 +#define ACP_SW2_TX_DMA5_RINGBUFSIZE 0x008FDC +#define ACP_SW2_TX_DMA5_FIFOADDR 0x008FE0 +#define ACP_SW2_TX_DMA5_FIFOSIZE 0x008FE4 +#define ACP_SW2_TX_DMA5_BURST_SIZE 0x008FE8 +#define ACP_SW2_TX_DMA5_LINKPOSITIONCNTR 0x008FEC +#define ACP_SW2_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x008FF0 +#define ACP_SW2_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x008FF4 +#define ACP_SW2_TX_DMA5_INTR_WATERMARK_SIZE 0x008FF8 +#define ACP_SW2_TX_DMA6_RINGBUFADDR 0x008FFC +#define ACP_SW2_TX_DMA6_RINGBUFSIZE 0x009000 +#define ACP_SW2_TX_DMA6_FIFOADDR 0x009004 +#define ACP_SW2_TX_DMA6_FIFOSIZE 0x009008 +#define ACP_SW2_TX_DMA6_BURST_SIZE 0x00900C +#define ACP_SW2_TX_DMA6_LINKPOSITIONCNTR 0x009010 +#define ACP_SW2_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x009014 +#define ACP_SW2_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x009018 +#define ACP_SW2_TX_DMA6_INTR_WATERMARK_SIZE 0x00901C +#define ACP_SW2_TX_DMA7_RINGBUFADDR 0x009020 +#define ACP_SW2_TX_DMA7_RINGBUFSIZE 0x009024 +#define ACP_SW2_TX_DMA7_FIFOADDR 0x009028 +#define ACP_SW2_TX_DMA7_FIFOSIZE 0x00902C +#define ACP_SW2_TX_DMA7_BURST_SIZE 0x009030 +#define ACP_SW2_TX_DMA7_LINKPOSITIONCNTR 0x009034 +#define ACP_SW2_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x009038 +#define ACP_SW2_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00903C +#define ACP_SW2_TX_DMA7_INTR_WATERMARK_SIZE 0x009040 +#define ACP_SW2_RX_DMA0_POS_TRACK 0x009044 +#define ACP_SW2_RX_DMA0_POS 0x009048 +#define ACP_SW2_RX_DMA1_POS_TRACK 0x00904C +#define ACP_SW2_RX_DMA1_POS 0x009050 +#define ACP_SW2_RX_DMA2_POS_TRACK 0x009054 +#define ACP_SW2_RX_DMA2_POS 0x009058 +#define ACP_SW2_RX_DMA3_POS_TRACK 0x00905C +#define ACP_SW2_RX_DMA3_POS 0x009060 +#define ACP_SW2_RX_DMA4_POS_TRACK 0x009064 +#define ACP_SW2_RX_DMA4_POS 0x009068 +#define ACP_SW2_RX_DMA5_POS_TRACK 0x00906C +#define ACP_SW2_RX_DMA5_POS 0x009070 +#define ACP_SW2_RX_DMA6_POS_TRACK 0x009074 +#define ACP_SW2_RX_DMA6_POS 0x009078 +#define ACP_SW2_RX_DMA7_POS_TRACK 0x00907C +#define ACP_SW2_RX_DMA7_POS 0x009080 +#define ACP_SW2_TX_DMA0_POS_TRACK 0x009084 +#define ACP_SW2_TX_DMA0_POS 0x009088 +#define ACP_SW2_TX_DMA1_POS_TRACK 0x00908C +#define ACP_SW2_TX_DMA1_POS 0x009090 +#define ACP_SW2_TX_DMA2_POS_TRACK 0x009094 +#define ACP_SW2_TX_DMA2_POS 0x009098 +#define ACP_SW2_TX_DMA3_POS_TRACK 0x00909C +#define ACP_SW2_TX_DMA3_POS 0x0090A0 +#define ACP_SW2_TX_DMA4_POS_TRACK 0x0090A4 +#define ACP_SW2_TX_DMA4_POS 0x0090A8 +#define ACP_SW2_TX_DMA5_POS_TRACK 0x0090AC +#define ACP_SW2_TX_DMA5_POS 0x0090B0 +#define ACP_SW2_TX_DMA6_POS_TRACK 0x0090B4 +#define ACP_SW2_TX_DMA6_POS 0x0090B8 +#define ACP_SW2_TX_DMA7_POS_TRACK 0x0090BC +#define ACP_SW2_TX_DMA7_POS 0x0090C0 +#define ACP_SW2_FIFO_ERROR_REASON 0x0090C4 +#define ACP_SW2_FIFO_ERROR_INTR_MASK 0x0090C8 +#define ACP_SW2_ERROR_REASON1 0x0090CC +#define ACP_SW2_ERROR_INTR_MASK1 0x0090D0 +#define ACP_SW2_ERROR_REASON2 0x0090D4 +#define ACP_SW2_ERROR_INTR_MASK2 0x0090D8 + +#define ACP_SW2_CORB_BASE_ADDRESS 0x009100 +#define ACP_SW2_CORB_WRITE_POINTER 0x009104 +#define ACP_SW2_CORB_READ_POINTER 0x009108 +#define ACP_SW2_CORB_CONTROL 0x00910C +#define ACP_SW2_CORB_SIZE 0x009114 +#define ACP_SW2_RIRB_BASE_ADDRESS 0x009118 +#define ACP_SW2_RIRB_WRITE_POINTER 0x00911C +#define ACP_SW2_RIRB_RESPONSE_INTERRUPT_COUNT 0x009120 +#define ACP_SW2_RIRB_CONTROL 0x009124 +#define ACP_SW2_RIRB_SIZE 0x009128 +#define ACP_SW2_RIRB_FIFO_MIN_THDL 0x00912C +#define ACP_SW2_IMM_CMD_UPPER_WORD 0x009130 +#define ACP_SW2_IMM_CMD_LOWER_QWORD 0x009134 +#define ACP_SW2_IMM_RESP_UPPER_WORD 0x009138 +#define ACP_SW2_IMM_RESP_LOWER_QWORD 0x00913C +#define ACP_SW2_IMM_CMD_STS 0x009140 +#define ACP_SW2_BRA_BASE_ADDRESS 0x009144 +#define ACP_SW2_BRA_TRANSFER_SIZE 0x009148 +#define ACP_SW2_BRA_DMA_BUSY 0x00914C +#define ACP_SW2_BRA_RESP 0x009150 +#define ACP_SW2_BRA_RESP_FRAME_ADDR 0x009154 +#define ACP_SW2_BRA_CURRENT_TRANSFER_SIZE 0x009158 +#define ACP_SW2_STATE_CHANGE_STATUS_0TO7 0x00915C +#define ACP_SW2_STATE_CHANGE_STATUS_8TO11 0x009160 +#define ACP_SW2_STATE_CHANGE_STATUS_MASK_0TO7 0x009164 +#define ACP_SW2_STATE_CHANGE_STATUS_MASK_8TO11 0x009168 +#define ACP_SW2_CLK_FREQUENCY_CTRL_BANK0 0x00916C +#define ACP_SW2_CLK_FREQUENCY_CTRL_BANK1 0x009170 +#define ACP_SW2_ERROR_INTR_MASK 0x009174 +#define ACP_SW2_PHY_TEST_MODE_DATA_OFF 0x009178 +#define ACP_SW2_DATA_TO_PDM_EN 0x00917C + +#define ACP_SW2_EN 0x009200 +#define ACP_SW2_EN_STATUS 0x009204 +#define ACP_SW2_FRAMESIZE_BANK0 0x009208 +#define ACP_SW2_FRAMESIZE_BANK1 0x00920C +#define ACP_SW2_SSP_COUNTER 0x009210 +#define ACP_SW2_TX_STREAM0_EN 0x009214 +#define ACP_SW2_TX_STREAM1_EN 0x009218 +#define ACP_SW2_TX_STREAM2_EN 0x00921C +#define ACP_SW2_TX_STREAM3_EN 0x009220 +#define ACP_SW2_TX_STREAM4_EN 0x009224 +#define ACP_SW2_TX_STREAM5_EN 0x009228 +#define ACP_SW2_TX_STREAM6_EN 0x00922C +#define ACP_SW2_TX_STREAM7_EN 0x009230 +#define ACP_SW2_TX_STREAM0_EN_STATUS 0x009234 +#define ACP_SW2_TX_STREAM1_EN_STATUS 0x009238 +#define ACP_SW2_TX_STREAM2_EN_STATUS 0x00923C +#define ACP_SW2_TX_STREAM3_EN_STATUS 0x009240 +#define ACP_SW2_TX_STREAM4_EN_STATUS 0x009244 +#define ACP_SW2_TX_STREAM5_EN_STATUS 0x009248 +#define ACP_SW2_TX_STREAM6_EN_STATUS 0x00924C +#define ACP_SW2_TX_STREAM7_EN_STATUS 0x009250 +#define ACP_SW2_TX_DP0_FRAME_FORMAT 0x009254 +#define ACP_SW2_TX_DP1_FRAME_FORMAT 0x009258 +#define ACP_SW2_TX_DP2_FRAME_FORMAT 0x00925C +#define ACP_SW2_TX_DP3_FRAME_FORMAT 0x009260 +#define ACP_SW2_TX_DP4_FRAME_FORMAT 0x009264 +#define ACP_SW2_TX_DP5_FRAME_FORMAT 0x009268 +#define ACP_SW2_TX_DP6_FRAME_FORMAT 0x00926C +#define ACP_SW2_TX_DP7_FRAME_FORMAT 0x009270 +#define ACP_SW2_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x009280 +#define ACP_SW2_TX_DP0_0_HCTRL_BANK0 0x009284 +#define ACP_SW2_TX_DP0_0_HCTRL_OFFSET_BANK0 0x009288 +#define ACP_SW2_TX_DP0_0_LANE_CTRL_BANK0 0x00928C +#define ACP_SW2_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x009290 +#define ACP_SW2_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009294 +#define ACP_SW2_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x009298 +#define ACP_SW2_TX_DP0_0_HCTRL_BANK1 0x00929C +#define ACP_SW2_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0092A0 +#define ACP_SW2_TX_DP0_0_LANE_CTRL_BANK1 0x0092A4 +#define ACP_SW2_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0092A8 +#define ACP_SW2_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0092AC +#define ACP_SW2_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0092B0 +#define ACP_SW2_TX_DP0_1_HCTRL_BANK0 0x0092B4 +#define ACP_SW2_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0092B8 +#define ACP_SW2_TX_DP0_1_LANE_CTRL_BANK0 0x0092BC +#define ACP_SW2_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0092C0 +#define ACP_SW2_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0092C4 +#define ACP_SW2_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0092C8 +#define ACP_SW2_TX_DP0_1_HCTRL_BANK1 0x0092CC +#define ACP_SW2_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0092D0 +#define ACP_SW2_TX_DP0_1_LANE_CTRL_BANK1 0x0092D4 +#define ACP_SW2_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0092D8 +#define ACP_SW2_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0092DC +#define ACP_SW2_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0092E0 +#define ACP_SW2_TX_DP0_2_HCTRL_BANK0 0x0092E4 +#define ACP_SW2_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0092E8 +#define ACP_SW2_TX_DP0_2_LANE_CTRL_BANK0 0x0092EC +#define ACP_SW2_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0092F0 +#define ACP_SW2_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0092F4 +#define ACP_SW2_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0092F8 +#define ACP_SW2_TX_DP0_2_HCTRL_BANK1 0x0092FC +#define ACP_SW2_TX_DP0_2_HCTRL_OFFSET_BANK1 0x009300 +#define ACP_SW2_TX_DP0_2_LANE_CTRL_BANK1 0x009304 +#define ACP_SW2_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x009308 +#define ACP_SW2_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00930C +#define ACP_SW2_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x009310 +#define ACP_SW2_TX_DP0_3_HCTRL_BANK0 0x009314 +#define ACP_SW2_TX_DP0_3_HCTRL_OFFSET_BANK0 0x009318 +#define ACP_SW2_TX_DP0_3_LANE_CTRL_BANK0 0x00931C +#define ACP_SW2_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x009320 +#define ACP_SW2_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009324 +#define ACP_SW2_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x009328 +#define ACP_SW2_TX_DP0_3_HCTRL_BANK1 0x00932C +#define ACP_SW2_TX_DP0_3_HCTRL_OFFSET_BANK1 0x009330 +#define ACP_SW2_TX_DP0_3_LANE_CTRL_BANK1 0x009334 +#define ACP_SW2_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x009338 +#define ACP_SW2_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00933C +#define ACP_SW2_TX_DP1_SAMPLEINTERVAL_BANK0 0x009370 +#define ACP_SW2_TX_DP1_HCTRL_BANK0 0x009374 +#define ACP_SW2_TX_DP1_HCTRL_OFFSET_BANK0 0x009378 +#define ACP_SW2_TX_DP1_LANE_CTRL_BANK0 0x00937C +#define ACP_SW2_TX_DP1_CHANNEL_ENABLE_BANK0 0x009380 +#define ACP_SW2_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009384 +#define ACP_SW2_TX_DP1_SAMPLEINTERVAL_BANK1 0x009388 +#define ACP_SW2_TX_DP1_HCTRL_BANK1 0x00938C +#define ACP_SW2_TX_DP1_HCTRL_OFFSET_BANK1 0x009390 +#define ACP_SW2_TX_DP1_LANE_CTRL_BANK1 0x009394 +#define ACP_SW2_TX_DP1_CHANNEL_ENABLE_BANK1 0x009398 +#define ACP_SW2_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00939C +#define ACP_SW2_TX_DP2_SAMPLEINTERVAL_BANK0 0x0093A0 +#define ACP_SW2_TX_DP2_HCTRL_BANK0 0x0093A4 +#define ACP_SW2_TX_DP2_HCTRL_OFFSET_BANK0 0x0093A8 +#define ACP_SW2_TX_DP2_LANE_CTRL_BANK0 0x0093AC +#define ACP_SW2_TX_DP2_CHANNEL_ENABLE_BANK0 0x0093B0 +#define ACP_SW2_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0093B4 +#define ACP_SW2_TX_DP2_SAMPLEINTERVAL_BANK1 0x0093B8 +#define ACP_SW2_TX_DP2_HCTRL_BANK1 0x0093BC +#define ACP_SW2_TX_DP2_HCTRL_OFFSET_BANK1 0x0093C0 +#define ACP_SW2_TX_DP2_LANE_CTRL_BANK1 0x0093C4 +#define ACP_SW2_TX_DP2_CHANNEL_ENABLE_BANK1 0x0093C8 +#define ACP_SW2_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0093CC +#define ACP_SW2_TX_DP3_SAMPLEINTERVAL_BANK0 0x0093D0 +#define ACP_SW2_TX_DP3_HCTRL_BANK0 0x0093D4 +#define ACP_SW2_TX_DP3_HCTRL_OFFSET_BANK0 0x0093D8 +#define ACP_SW2_TX_DP3_LANE_CTRL_BANK0 0x0093DC +#define ACP_SW2_TX_DP3_CHANNEL_ENABLE_BANK0 0x0093E0 +#define ACP_SW2_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0093E4 +#define ACP_SW2_TX_DP3_SAMPLEINTERVAL_BANK1 0x0093E8 +#define ACP_SW2_TX_DP3_HCTRL_BANK1 0x0093EC +#define ACP_SW2_TX_DP3_HCTRL_OFFSET_BANK1 0x0093F0 +#define ACP_SW2_TX_DP3_LANE_CTRL_BANK1 0x0093F4 +#define ACP_SW2_TX_DP3_CHANNEL_ENABLE_BANK1 0x0093F8 +#define ACP_SW2_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0093FC +#define ACP_SW2_TX_DP4_SAMPLEINTERVAL_BANK0 0x009400 +#define ACP_SW2_TX_DP4_HCTRL_BANK0 0x009404 +#define ACP_SW2_TX_DP4_HCTRL_OFFSET_BANK0 0x009408 +#define ACP_SW2_TX_DP4_LANE_CTRL_BANK0 0x00940C +#define ACP_SW2_TX_DP4_CHANNEL_ENABLE_BANK0 0x009410 +#define ACP_SW2_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009414 +#define ACP_SW2_TX_DP4_SAMPLEINTERVAL_BANK1 0x009418 +#define ACP_SW2_TX_DP4_HCTRL_BANK1 0x00941C +#define ACP_SW2_TX_DP4_HCTRL_OFFSET_BANK1 0x009420 +#define ACP_SW2_TX_DP4_LANE_CTRL_BANK1 0x009424 +#define ACP_SW2_TX_DP4_CHANNEL_ENABLE_BANK1 0x009428 +#define ACP_SW2_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00942C +#define ACP_SW2_TX_DP5_SAMPLEINTERVAL_BANK0 0x009430 +#define ACP_SW2_TX_DP5_HCTRL_BANK0 0x009434 +#define ACP_SW2_TX_DP5_HCTRL_OFFSET_BANK0 0x009438 +#define ACP_SW2_TX_DP5_LANE_CTRL_BANK0 0x00943C +#define ACP_SW2_TX_DP5_CHANNEL_ENABLE_BANK0 0x009440 +#define ACP_SW2_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009444 +#define ACP_SW2_TX_DP5_SAMPLEINTERVAL_BANK1 0x009448 +#define ACP_SW2_TX_DP5_HCTRL_BANK1 0x00944C +#define ACP_SW2_TX_DP5_HCTRL_OFFSET_BANK1 0x009450 +#define ACP_SW2_TX_DP5_LANE_CTRL_BANK1 0x009454 +#define ACP_SW2_TX_DP5_CHANNEL_ENABLE_BANK1 0x009458 +#define ACP_SW2_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00945C +#define ACP_SW2_TX_DP6_SAMPLEINTERVAL_BANK0 0x009460 +#define ACP_SW2_TX_DP6_HCTRL_BANK0 0x009464 +#define ACP_SW2_TX_DP6_HCTRL_OFFSET_BANK0 0x009468 +#define ACP_SW2_TX_DP6_LANE_CTRL_BANK0 0x00946C +#define ACP_SW2_TX_DP6_CHANNEL_ENABLE_BANK0 0x009470 +#define ACP_SW2_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009474 +#define ACP_SW2_TX_DP6_SAMPLEINTERVAL_BANK1 0x009478 +#define ACP_SW2_TX_DP6_HCTRL_BANK1 0x00947C +#define ACP_SW2_TX_DP6_HCTRL_OFFSET_BANK1 0x009480 +#define ACP_SW2_TX_DP6_LANE_CTRL_BANK1 0x009484 +#define ACP_SW2_TX_DP6_CHANNEL_ENABLE_BANK1 0x009488 +#define ACP_SW2_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00948C +#define ACP_SW2_TX_DP7_SAMPLEINTERVAL_BANK0 0x009490 +#define ACP_SW2_TX_DP7_HCTRL_BANK0 0x009494 +#define ACP_SW2_TX_DP7_HCTRL_OFFSET_BANK0 0x009498 +#define ACP_SW2_TX_DP7_LANE_CTRL_BANK0 0x00949C +#define ACP_SW2_TX_DP7_CHANNEL_ENABLE_BANK0 0x0094A0 +#define ACP_SW2_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0094A4 +#define ACP_SW2_TX_DP7_SAMPLEINTERVAL_BANK1 0x0094A8 +#define ACP_SW2_TX_DP7_HCTRL_BANK1 0x0094AC +#define ACP_SW2_TX_DP7_HCTRL_OFFSET_BANK1 0x0094B0 +#define ACP_SW2_TX_DP7_LANE_CTRL_BANK1 0x0094B4 +#define ACP_SW2_TX_DP7_CHANNEL_ENABLE_BANK1 0x0094B8 +#define ACP_SW2_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0094BC +#define ACP_SW2_RX_STREAM0_EN 0x009514 +#define ACP_SW2_RX_STREAM1_EN 0x009518 +#define ACP_SW2_RX_STREAM2_EN 0x00951C +#define ACP_SW2_RX_STREAM3_EN 0x009520 +#define ACP_SW2_RX_STREAM4_EN 0x009524 +#define ACP_SW2_RX_STREAM5_EN 0x009528 +#define ACP_SW2_RX_STREAM6_EN 0x00952C +#define ACP_SW2_RX_STREAM7_EN 0x009530 +#define ACP_SW2_RX_STREAM0_EN_STATUS 0x009534 +#define ACP_SW2_RX_STREAM1_EN_STATUS 0x009538 +#define ACP_SW2_RX_STREAM2_EN_STATUS 0x00953C +#define ACP_SW2_RX_STREAM3_EN_STATUS 0x009540 +#define ACP_SW2_RX_STREAM4_EN_STATUS 0x009544 +#define ACP_SW2_RX_STREAM5_EN_STATUS 0x009548 +#define ACP_SW2_RX_STREAM6_EN_STATUS 0x00954C +#define ACP_SW2_RX_STREAM7_EN_STATUS 0x009550 +#define ACP_SW2_RX_DP0_FRAME_FORMAT 0x009554 +#define ACP_SW2_RX_DP1_FRAME_FORMAT 0x009558 +#define ACP_SW2_RX_DP2_FRAME_FORMAT 0x00955C +#define ACP_SW2_RX_DP3_FRAME_FORMAT 0x009560 +#define ACP_SW2_RX_DP4_FRAME_FORMAT 0x009564 +#define ACP_SW2_RX_DP5_FRAME_FORMAT 0x009568 +#define ACP_SW2_RX_DP6_FRAME_FORMAT 0x00956C +#define ACP_SW2_RX_DP7_FRAME_FORMAT 0x009570 +#define ACP_SW2_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x009580 +#define ACP_SW2_RX_DP0_0_HCTRL_BANK0 0x009584 +#define ACP_SW2_RX_DP0_0_HCTRL_OFFSET_BANK0 0x009588 +#define ACP_SW2_RX_DP0_0_LANE_CTRL_BANK0 0x00958C +#define ACP_SW2_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x009590 +#define ACP_SW2_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009594 +#define ACP_SW2_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x009598 +#define ACP_SW2_RX_DP0_0_HCTRL_BANK1 0x00959C +#define ACP_SW2_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0095A0 +#define ACP_SW2_RX_DP0_0_LANE_CTRL_BANK1 0x0095A4 +#define ACP_SW2_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0095A8 +#define ACP_SW2_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0095AC +#define ACP_SW2_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0095B0 +#define ACP_SW2_RX_DP0_1_HCTRL_BANK0 0x0095B4 +#define ACP_SW2_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0095B8 +#define ACP_SW2_RX_DP0_1_LANE_CTRL_BANK0 0x0095BC +#define ACP_SW2_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0095C0 +#define ACP_SW2_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0095C4 +#define ACP_SW2_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0095C8 +#define ACP_SW2_RX_DP0_1_HCTRL_BANK1 0x0095CC +#define ACP_SW2_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0095D0 +#define ACP_SW2_RX_DP0_1_LANE_CTRL_BANK1 0x0095D4 +#define ACP_SW2_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0095D8 +#define ACP_SW2_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0095DC +#define ACP_SW2_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0095E0 +#define ACP_SW2_RX_DP0_2_HCTRL_BANK0 0x0095E4 +#define ACP_SW2_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0095E8 +#define ACP_SW2_RX_DP0_2_LANE_CTRL_BANK0 0x0095EC +#define ACP_SW2_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0095F0 +#define ACP_SW2_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0095F4 +#define ACP_SW2_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0095F8 +#define ACP_SW2_RX_DP0_2_HCTRL_BANK1 0x0095FC +#define ACP_SW2_RX_DP0_2_HCTRL_OFFSET_BANK1 0x009600 +#define ACP_SW2_RX_DP0_2_LANE_CTRL_BANK1 0x009604 +#define ACP_SW2_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x009608 +#define ACP_SW2_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00960C +#define ACP_SW2_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x009610 +#define ACP_SW2_RX_DP0_3_HCTRL_BANK0 0x009614 +#define ACP_SW2_RX_DP0_3_HCTRL_OFFSET_BANK0 0x009618 +#define ACP_SW2_RX_DP0_3_LANE_CTRL_BANK0 0x00961C +#define ACP_SW2_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x009620 +#define ACP_SW2_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009624 +#define ACP_SW2_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x009628 +#define ACP_SW2_RX_DP0_3_HCTRL_BANK1 0x00962C +#define ACP_SW2_RX_DP0_3_HCTRL_OFFSET_BANK1 0x009630 +#define ACP_SW2_RX_DP0_3_LANE_CTRL_BANK1 0x009634 +#define ACP_SW2_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x009638 +#define ACP_SW2_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00963C +#define ACP_SW2_RX_DP1_SAMPLEINTERVAL_BANK0 0x009670 +#define ACP_SW2_RX_DP1_HCTRL_BANK0 0x009674 +#define ACP_SW2_RX_DP1_HCTRL_OFFSET_BANK0 0x009678 +#define ACP_SW2_RX_DP1_LANE_CTRL_BANK0 0x00967C +#define ACP_SW2_RX_DP1_CHANNEL_ENABLE_BANK0 0x009680 +#define ACP_SW2_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009684 +#define ACP_SW2_RX_DP1_SAMPLEINTERVAL_BANK1 0x009688 +#define ACP_SW2_RX_DP1_HCTRL_BANK1 0x00968C +#define ACP_SW2_RX_DP1_HCTRL_OFFSET_BANK1 0x009690 +#define ACP_SW2_RX_DP1_LANE_CTRL_BANK1 0x009694 +#define ACP_SW2_RX_DP1_CHANNEL_ENABLE_BANK1 0x009698 +#define ACP_SW2_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00969C +#define ACP_SW2_RX_DP2_SAMPLEINTERVAL_BANK0 0x0096A0 +#define ACP_SW2_RX_DP2_HCTRL_BANK0 0x0096A4 +#define ACP_SW2_RX_DP2_HCTRL_OFFSET_BANK0 0x0096A8 +#define ACP_SW2_RX_DP2_LANE_CTRL_BANK0 0x0096AC +#define ACP_SW2_RX_DP2_CHANNEL_ENABLE_BANK0 0x0096B0 +#define ACP_SW2_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0096B4 +#define ACP_SW2_RX_DP2_SAMPLEINTERVAL_BANK1 0x0096B8 +#define ACP_SW2_RX_DP2_HCTRL_BANK1 0x0096BC +#define ACP_SW2_RX_DP2_HCTRL_OFFSET_BANK1 0x0096C0 +#define ACP_SW2_RX_DP2_LANE_CTRL_BANK1 0x0096C4 +#define ACP_SW2_RX_DP2_CHANNEL_ENABLE_BANK1 0x0096C8 +#define ACP_SW2_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0096CC +#define ACP_SW2_RX_DP3_SAMPLEINTERVAL_BANK0 0x0096D0 +#define ACP_SW2_RX_DP3_HCTRL_BANK0 0x0096D4 +#define ACP_SW2_RX_DP3_HCTRL_OFFSET_BANK0 0x0096D8 +#define ACP_SW2_RX_DP3_LANE_CTRL_BANK0 0x0096DC +#define ACP_SW2_RX_DP3_CHANNEL_ENABLE_BANK0 0x0096E0 +#define ACP_SW2_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0096E4 +#define ACP_SW2_RX_DP3_SAMPLEINTERVAL_BANK1 0x0096E8 +#define ACP_SW2_RX_DP3_HCTRL_BANK1 0x0096EC +#define ACP_SW2_RX_DP3_HCTRL_OFFSET_BANK1 0x0096F0 +#define ACP_SW2_RX_DP3_LANE_CTRL_BANK1 0x0096F4 +#define ACP_SW2_RX_DP3_CHANNEL_ENABLE_BANK1 0x0096F8 +#define ACP_SW2_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0096FC +#define ACP_SW2_RX_DP4_SAMPLEINTERVAL_BANK0 0x009700 +#define ACP_SW2_RX_DP4_HCTRL_BANK0 0x009704 +#define ACP_SW2_RX_DP4_HCTRL_OFFSET_BANK0 0x009708 +#define ACP_SW2_RX_DP4_LANE_CTRL_BANK0 0x00970C +#define ACP_SW2_RX_DP4_CHANNEL_ENABLE_BANK0 0x009710 +#define ACP_SW2_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009714 +#define ACP_SW2_RX_DP4_SAMPLEINTERVAL_BANK1 0x009718 +#define ACP_SW2_RX_DP4_HCTRL_BANK1 0x00971C +#define ACP_SW2_RX_DP4_HCTRL_OFFSET_BANK1 0x009720 +#define ACP_SW2_RX_DP4_LANE_CTRL_BANK1 0x009724 +#define ACP_SW2_RX_DP4_CHANNEL_ENABLE_BANK1 0x009728 +#define ACP_SW2_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00972C +#define ACP_SW2_RX_DP5_SAMPLEINTERVAL_BANK0 0x009730 +#define ACP_SW2_RX_DP5_HCTRL_BANK0 0x009734 +#define ACP_SW2_RX_DP5_HCTRL_OFFSET_BANK0 0x009738 +#define ACP_SW2_RX_DP5_LANE_CTRL_BANK0 0x00973C +#define ACP_SW2_RX_DP5_CHANNEL_ENABLE_BANK0 0x009740 +#define ACP_SW2_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009744 +#define ACP_SW2_RX_DP5_SAMPLEINTERVAL_BANK1 0x009748 +#define ACP_SW2_RX_DP5_HCTRL_BANK1 0x00974C +#define ACP_SW2_RX_DP5_HCTRL_OFFSET_BANK1 0x009750 +#define ACP_SW2_RX_DP5_LANE_CTRL_BANK1 0x009754 +#define ACP_SW2_RX_DP5_CHANNEL_ENABLE_BANK1 0x009758 +#define ACP_SW2_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00975C +#define ACP_SW2_RX_DP6_SAMPLEINTERVAL_BANK0 0x009760 +#define ACP_SW2_RX_DP6_HCTRL_BANK0 0x009764 +#define ACP_SW2_RX_DP6_HCTRL_OFFSET_BANK0 0x009768 +#define ACP_SW2_RX_DP6_LANE_CTRL_BANK0 0x00976C +#define ACP_SW2_RX_DP6_CHANNEL_ENABLE_BANK0 0x009770 +#define ACP_SW2_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009774 +#define ACP_SW2_RX_DP6_SAMPLEINTERVAL_BANK1 0x009778 +#define ACP_SW2_RX_DP6_HCTRL_BANK1 0x00977C +#define ACP_SW2_RX_DP6_HCTRL_OFFSET_BANK1 0x009780 +#define ACP_SW2_RX_DP6_LANE_CTRL_BANK1 0x009784 +#define ACP_SW2_RX_DP6_CHANNEL_ENABLE_BANK1 0x009788 +#define ACP_SW2_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00978C +#define ACP_SW2_RX_DP7_SAMPLEINTERVAL_BANK0 0x009790 +#define ACP_SW2_RX_DP7_HCTRL_BANK0 0x009794 +#define ACP_SW2_RX_DP7_HCTRL_OFFSET_BANK0 0x009798 +#define ACP_SW2_RX_DP7_LANE_CTRL_BANK0 0x00979C +#define ACP_SW2_RX_DP7_CHANNEL_ENABLE_BANK0 0x0097A0 +#define ACP_SW2_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0097A4 +#define ACP_SW2_RX_DP7_SAMPLEINTERVAL_BANK1 0x0097A8 +#define ACP_SW2_RX_DP7_HCTRL_BANK1 0x0097AC +#define ACP_SW2_RX_DP7_HCTRL_OFFSET_BANK1 0x0097B0 +#define ACP_SW2_RX_DP7_LANE_CTRL_BANK1 0x0097B4 +#define ACP_SW2_RX_DP7_CHANNEL_ENABLE_BANK1 0x0097B8 +#define ACP_SW2_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0097BC +#define ACP_SW2_BPT_PORT_EN 0x0097C0 +#define ACP_SW2_BPT_PORT_EN_STATUS 0x0097C4 +#define ACP_SW2_BPT_PORT_FRAME_FORMAT 0x0097C8 +#define ACP_SW2_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0097CC +#define ACP_SW2_BPT_PORT_HCTRL_BANK0 0x0097D0 +#define ACP_SW2_BPT_PORT_OFFSET_BANK0 0x0097D4 +#define ACP_SW2_BPT_PORT_LANE_SELECT_BANK0 0x0097D8 +#define ACP_SW2_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0097DC +#define ACP_SW2_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0097E0 +#define ACP_SW2_BPT_PORT_HCTRL_BANK1 0x0097E4 +#define ACP_SW2_BPT_PORT_OFFSET_BANK1 0x0097E8 +#define ACP_SW2_BPT_PORT_LANE_SELECT_BANK1 0x0097EC +#define ACP_SW2_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0097F0 +#define ACP_SW2_BPT_PORT_FIRST_BYTE_ADDR 0x0097F4 +#define ACP_SW2_CLK_RESUME_CTRL 0x0097F8 +#define ACP_SW2_CLK_RESUME_DELAY_CNTR 0x0097FC +#define ACP_SW2_BUS_RESET_CTRL 0x009800 +#define ACP_SW2_PRBS_ERR_STATUS 0x009804 +#define ACP_SW2_WALLCLK_MISC 0x009808 +#define ACP_SW2_WALL_CLK_COUNTER 0x00980C +#define ACP_SW2_PING_STATUS_REGISTER_LOW 0x009810 +#define ACP_SW2_PING_STATUS_REGISTER_HIGH 0x009814 +#define ACP_SW2_PING_STATUS_CURRENT_BANK_SEL 0x009818 +#define ACP_SW2_TZD_CHANGE 0x00981C +#define ACP_SW2_WALLCLK_INTR_CNTL 0x009820 + +#define ACP_SW3_GLOBAL_CAPABILITIES 0x00AE00 +#define ACP_SW3_RX_DMA0_RINGBUFADDR 0x00AE04 +#define ACP_SW3_RX_DMA0_RINGBUFSIZE 0x00AE08 +#define ACP_SW3_RX_DMA0_FIFOADDR 0x00AE0C +#define ACP_SW3_RX_DMA0_FIFOSIZE 0x00AE10 +#define ACP_SW3_RX_DMA0_BURST_SIZE 0x00AE14 +#define ACP_SW3_RX_DMA0_LINKPOSITIONCNTR 0x00AE18 +#define ACP_SW3_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x00AE1C +#define ACP_SW3_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x00AE20 +#define ACP_SW3_RX_DMA0_INTR_WATERMARK_SIZE 0x00AE24 +#define ACP_SW3_RX_DMA1_RINGBUFADDR 0x00AE28 +#define ACP_SW3_RX_DMA1_RINGBUFSIZE 0x00AE2C +#define ACP_SW3_RX_DMA1_FIFOADDR 0x00AE30 +#define ACP_SW3_RX_DMA1_FIFOSIZE 0x00AE34 +#define ACP_SW3_RX_DMA1_BURST_SIZE 0x00AE38 +#define ACP_SW3_RX_DMA1_LINKPOSITIONCNTR 0x00AE3C +#define ACP_SW3_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x00AE40 +#define ACP_SW3_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x00AE44 +#define ACP_SW3_RX_DMA1_INTR_WATERMARK_SIZE 0x00AE48 +#define ACP_SW3_RX_DMA2_RINGBUFADDR 0x00AE4C +#define ACP_SW3_RX_DMA2_RINGBUFSIZE 0x00AE50 +#define ACP_SW3_RX_DMA2_FIFOADDR 0x00AE54 +#define ACP_SW3_RX_DMA2_FIFOSIZE 0x00AE58 +#define ACP_SW3_RX_DMA2_BURST_SIZE 0x00AE5C +#define ACP_SW3_RX_DMA2_LINKPOSITIONCNTR 0x00AE60 +#define ACP_SW3_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x00AE64 +#define ACP_SW3_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x00AE68 +#define ACP_SW3_RX_DMA2_INTR_WATERMARK_SIZE 0x00AE6C +#define ACP_SW3_RX_DMA3_RINGBUFADDR 0x00AE70 +#define ACP_SW3_RX_DMA3_RINGBUFSIZE 0x00AE74 +#define ACP_SW3_RX_DMA3_FIFOADDR 0x00AE78 +#define ACP_SW3_RX_DMA3_FIFOSIZE 0x00AE7C +#define ACP_SW3_RX_DMA3_BURST_SIZE 0x00AE80 +#define ACP_SW3_RX_DMA3_LINKPOSITIONCNTR 0x00AE84 +#define ACP_SW3_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x00AE88 +#define ACP_SW3_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x00AE8C +#define ACP_SW3_RX_DMA3_INTR_WATERMARK_SIZE 0x00AE90 +#define ACP_SW3_RX_DMA4_RINGBUFADDR 0x00AE94 +#define ACP_SW3_RX_DMA4_RINGBUFSIZE 0x00AE98 +#define ACP_SW3_RX_DMA4_FIFOADDR 0x00AE9C +#define ACP_SW3_RX_DMA4_FIFOSIZE 0x00AEA0 +#define ACP_SW3_RX_DMA4_BURST_SIZE 0x00AEA4 +#define ACP_SW3_RX_DMA4_LINKPOSITIONCNTR 0x00AEA8 +#define ACP_SW3_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x00AEAC +#define ACP_SW3_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x00AEB0 +#define ACP_SW3_RX_DMA4_INTR_WATERMARK_SIZE 0x00AEB4 +#define ACP_SW3_RX_DMA5_RINGBUFADDR 0x00AEB8 +#define ACP_SW3_RX_DMA5_RINGBUFSIZE 0x00AEBC +#define ACP_SW3_RX_DMA5_FIFOADDR 0x00AEC0 +#define ACP_SW3_RX_DMA5_FIFOSIZE 0x00AEC4 +#define ACP_SW3_RX_DMA5_BURST_SIZE 0x00AEC8 +#define ACP_SW3_RX_DMA5_LINKPOSITIONCNTR 0x00AECC +#define ACP_SW3_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x00AED0 +#define ACP_SW3_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x00AED4 +#define ACP_SW3_RX_DMA5_INTR_WATERMARK_SIZE 0x00AED8 +#define ACP_SW3_RX_DMA6_RINGBUFADDR 0x00AEDC +#define ACP_SW3_RX_DMA6_RINGBUFSIZE 0x00AEE0 +#define ACP_SW3_RX_DMA6_FIFOADDR 0x00AEE4 +#define ACP_SW3_RX_DMA6_FIFOSIZE 0x00AEE8 +#define ACP_SW3_RX_DMA6_BURST_SIZE 0x00AEEC +#define ACP_SW3_RX_DMA6_LINKPOSITIONCNTR 0x00AEF0 +#define ACP_SW3_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x00AEF4 +#define ACP_SW3_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x00AEF8 +#define ACP_SW3_RX_DMA6_INTR_WATERMARK_SIZE 0x00AEFC +#define ACP_SW3_RX_DMA7_RINGBUFADDR 0x00AF00 +#define ACP_SW3_RX_DMA7_RINGBUFSIZE 0x00AF04 +#define ACP_SW3_RX_DMA7_FIFOADDR 0x00AF08 +#define ACP_SW3_RX_DMA7_FIFOSIZE 0x00AF0C +#define ACP_SW3_RX_DMA7_BURST_SIZE 0x00AF10 +#define ACP_SW3_RX_DMA7_LINKPOSITIONCNTR 0x00AF14 +#define ACP_SW3_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x00AF18 +#define ACP_SW3_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x00AF1C +#define ACP_SW3_RX_DMA7_INTR_WATERMARK_SIZE 0x00AF20 +#define ACP_SW3_TX_DMA0_RINGBUFADDR 0x00AF24 +#define ACP_SW3_TX_DMA0_RINGBUFSIZE 0x00AF28 +#define ACP_SW3_TX_DMA0_FIFOADDR 0x00AF2C +#define ACP_SW3_TX_DMA0_FIFOSIZE 0x00AF30 +#define ACP_SW3_TX_DMA0_BURST_SIZE 0x00AF34 +#define ACP_SW3_TX_DMA0_LINKPOSITIONCNTR 0x00AF38 +#define ACP_SW3_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x00AF3C +#define ACP_SW3_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x00AF40 +#define ACP_SW3_TX_DMA0_INTR_WATERMARK_SIZE 0x00AF44 +#define ACP_SW3_TX_DMA1_RINGBUFADDR 0x00AF48 +#define ACP_SW3_TX_DMA1_RINGBUFSIZE 0x00AF4C +#define ACP_SW3_TX_DMA1_FIFOADDR 0x00AF50 +#define ACP_SW3_TX_DMA1_FIFOSIZE 0x00AF54 +#define ACP_SW3_TX_DMA1_BURST_SIZE 0x00AF58 +#define ACP_SW3_TX_DMA1_LINKPOSITIONCNTR 0x00AF5C +#define ACP_SW3_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x00AF60 +#define ACP_SW3_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x00AF64 +#define ACP_SW3_TX_DMA1_INTR_WATERMARK_SIZE 0x00AF68 +#define ACP_SW3_TX_DMA2_RINGBUFADDR 0x00AF6C +#define ACP_SW3_TX_DMA2_RINGBUFSIZE 0x00AF70 +#define ACP_SW3_TX_DMA2_FIFOADDR 0x00AF74 +#define ACP_SW3_TX_DMA2_FIFOSIZE 0x00AF78 +#define ACP_SW3_TX_DMA2_BURST_SIZE 0x00AF7C +#define ACP_SW3_TX_DMA2_LINKPOSITIONCNTR 0x00AF80 +#define ACP_SW3_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x00AF84 +#define ACP_SW3_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x00AF88 +#define ACP_SW3_TX_DMA2_INTR_WATERMARK_SIZE 0x00AF8C +#define ACP_SW3_TX_DMA3_RINGBUFADDR 0x00AF90 +#define ACP_SW3_TX_DMA3_RINGBUFSIZE 0x00AF94 +#define ACP_SW3_TX_DMA3_FIFOADDR 0x00AF98 +#define ACP_SW3_TX_DMA3_FIFOSIZE 0x00AF9C +#define ACP_SW3_TX_DMA3_BURST_SIZE 0x00AFA0 +#define ACP_SW3_TX_DMA3_LINKPOSITIONCNTR 0x00AFA4 +#define ACP_SW3_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x00AFA8 +#define ACP_SW3_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x00AFAC +#define ACP_SW3_TX_DMA3_INTR_WATERMARK_SIZE 0x00AFB0 +#define ACP_SW3_TX_DMA4_RINGBUFADDR 0x00AFB4 +#define ACP_SW3_TX_DMA4_RINGBUFSIZE 0x00AFB8 +#define ACP_SW3_TX_DMA4_FIFOADDR 0x00AFBC +#define ACP_SW3_TX_DMA4_FIFOSIZE 0x00AFC0 +#define ACP_SW3_TX_DMA4_BURST_SIZE 0x00AFC4 +#define ACP_SW3_TX_DMA4_LINKPOSITIONCNTR 0x00AFC8 +#define ACP_SW3_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x00AFCC +#define ACP_SW3_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x00AFD0 +#define ACP_SW3_TX_DMA4_INTR_WATERMARK_SIZE 0x00AFD4 +#define ACP_SW3_TX_DMA5_RINGBUFADDR 0x00AFD8 +#define ACP_SW3_TX_DMA5_RINGBUFSIZE 0x00AFDC +#define ACP_SW3_TX_DMA5_FIFOADDR 0x00AFE0 +#define ACP_SW3_TX_DMA5_FIFOSIZE 0x00AFE4 +#define ACP_SW3_TX_DMA5_BURST_SIZE 0x00AFE8 +#define ACP_SW3_TX_DMA5_LINKPOSITIONCNTR 0x00AFEC +#define ACP_SW3_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x00AFF0 +#define ACP_SW3_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x00AFF4 +#define ACP_SW3_TX_DMA5_INTR_WATERMARK_SIZE 0x00AFF8 +#define ACP_SW3_TX_DMA6_RINGBUFADDR 0x00AFFC +#define ACP_SW3_TX_DMA6_RINGBUFSIZE 0x00B000 +#define ACP_SW3_TX_DMA6_FIFOADDR 0x00B004 +#define ACP_SW3_TX_DMA6_FIFOSIZE 0x00B008 +#define ACP_SW3_TX_DMA6_BURST_SIZE 0x00B00C +#define ACP_SW3_TX_DMA6_LINKPOSITIONCNTR 0x00B010 +#define ACP_SW3_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x00B014 +#define ACP_SW3_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x00B018 +#define ACP_SW3_TX_DMA6_INTR_WATERMARK_SIZE 0x00B01C +#define ACP_SW3_TX_DMA7_RINGBUFADDR 0x00B020 +#define ACP_SW3_TX_DMA7_RINGBUFSIZE 0x00B024 +#define ACP_SW3_TX_DMA7_FIFOADDR 0x00B028 +#define ACP_SW3_TX_DMA7_FIFOSIZE 0x00B02C +#define ACP_SW3_TX_DMA7_BURST_SIZE 0x00B030 +#define ACP_SW3_TX_DMA7_LINKPOSITIONCNTR 0x00B034 +#define ACP_SW3_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x00B038 +#define ACP_SW3_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00B03C +#define ACP_SW3_TX_DMA7_INTR_WATERMARK_SIZE 0x00B040 +#define ACP_SW3_RX_DMA0_POS_TRACK 0x00B044 +#define ACP_SW3_RX_DMA0_POS 0x00B048 +#define ACP_SW3_RX_DMA1_POS_TRACK 0x00B04C +#define ACP_SW3_RX_DMA1_POS 0x00B050 +#define ACP_SW3_RX_DMA2_POS_TRACK 0x00B054 +#define ACP_SW3_RX_DMA2_POS 0x00B058 +#define ACP_SW3_RX_DMA3_POS_TRACK 0x00B05C +#define ACP_SW3_RX_DMA3_POS 0x00B060 +#define ACP_SW3_RX_DMA4_POS_TRACK 0x00B064 +#define ACP_SW3_RX_DMA4_POS 0x00B068 +#define ACP_SW3_RX_DMA5_POS_TRACK 0x00B06C +#define ACP_SW3_RX_DMA5_POS 0x00B070 +#define ACP_SW3_RX_DMA6_POS_TRACK 0x00B074 +#define ACP_SW3_RX_DMA6_POS 0x00B078 +#define ACP_SW3_RX_DMA7_POS_TRACK 0x00B07C +#define ACP_SW3_RX_DMA7_POS 0x00B080 +#define ACP_SW3_TX_DMA0_POS_TRACK 0x00B084 +#define ACP_SW3_TX_DMA0_POS 0x00B088 +#define ACP_SW3_TX_DMA1_POS_TRACK 0x00B08C +#define ACP_SW3_TX_DMA1_POS 0x00B090 +#define ACP_SW3_TX_DMA2_POS_TRACK 0x00B094 +#define ACP_SW3_TX_DMA2_POS 0x00B098 +#define ACP_SW3_TX_DMA3_POS_TRACK 0x00B09C +#define ACP_SW3_TX_DMA3_POS 0x00B0A0 +#define ACP_SW3_TX_DMA4_POS_TRACK 0x00B0A4 +#define ACP_SW3_TX_DMA4_POS 0x00B0A8 +#define ACP_SW3_TX_DMA5_POS_TRACK 0x00B0AC +#define ACP_SW3_TX_DMA5_POS 0x00B0B0 +#define ACP_SW3_TX_DMA6_POS_TRACK 0x00B0B4 +#define ACP_SW3_TX_DMA6_POS 0x00B0B8 +#define ACP_SW3_TX_DMA7_POS_TRACK 0x00B0BC +#define ACP_SW3_TX_DMA7_POS 0x00B0C0 +#define ACP_SW3_FIFO_ERROR_REASON 0x00B0C4 +#define ACP_SW3_FIFO_ERROR_INTR_MASK 0x00B0C8 +#define ACP_SW3_ERROR_REASON1 0x00B0CC +#define ACP_SW3_ERROR_INTR_MASK1 0x00B0D0 +#define ACP_SW3_ERROR_REASON2 0x00B0D4 +#define ACP_SW3_ERROR_INTR_MASK2 0x00B0D8 + +#define ACP_SW3_CORB_BASE_ADDRESS 0x00B100 +#define ACP_SW3_CORB_WRITE_POINTER 0x00B104 +#define ACP_SW3_CORB_READ_POINTER 0x00B108 +#define ACP_SW3_CORB_CONTROL 0x00B10C +#define ACP_SW3_CORB_SIZE 0x00B114 +#define ACP_SW3_RIRB_BASE_ADDRESS 0x00B118 +#define ACP_SW3_RIRB_WRITE_POINTER 0x00B11C +#define ACP_SW3_RIRB_RESPONSE_INTERRUPT_COUNT 0x00B120 +#define ACP_SW3_RIRB_CONTROL 0x00B124 +#define ACP_SW3_RIRB_SIZE 0x00B128 +#define ACP_SW3_RIRB_FIFO_MIN_THDL 0x00B12C +#define ACP_SW3_IMM_CMD_UPPER_WORD 0x00B130 +#define ACP_SW3_IMM_CMD_LOWER_QWORD 0x00B134 +#define ACP_SW3_IMM_RESP_UPPER_WORD 0x00B138 +#define ACP_SW3_IMM_RESP_LOWER_QWORD 0x00B13C +#define ACP_SW3_IMM_CMD_STS 0x00B140 +#define ACP_SW3_BRA_BASE_ADDRESS 0x00B144 +#define ACP_SW3_BRA_TRANSFER_SIZE 0x00B148 +#define ACP_SW3_BRA_DMA_BUSY 0x00B14C +#define ACP_SW3_BRA_RESP 0x00B150 +#define ACP_SW3_BRA_RESP_FRAME_ADDR 0x00B154 +#define ACP_SW3_BRA_CURRENT_TRANSFER_SIZE 0x00B158 +#define ACP_SW3_STATE_CHANGE_STATUS_0TO7 0x00B15C +#define ACP_SW3_STATE_CHANGE_STATUS_8TO11 0x00B160 +#define ACP_SW3_STATE_CHANGE_STATUS_MASK_0TO7 0x00B164 +#define ACP_SW3_STATE_CHANGE_STATUS_MASK_8TO11 0x00B168 +#define ACP_SW3_CLK_FREQUENCY_CTRL_BANK0 0x00B16C +#define ACP_SW3_CLK_FREQUENCY_CTRL_BANK1 0x00B170 +#define ACP_SW3_ERROR_INTR_MASK 0x00B174 +#define ACP_SW3_PHY_TEST_MODE_DATA_OFF 0x00B178 +#define ACP_SW3_DATA_TO_PDM_EN 0x00B17C + +#define ACP_SW3_EN 0x00B200 +#define ACP_SW3_EN_STATUS 0x00B204 +#define ACP_SW3_FRAMESIZE_BANK0 0x00B208 +#define ACP_SW3_FRAMESIZE_BANK1 0x00B20C +#define ACP_SW3_SSP_COUNTER 0x00B210 +#define ACP_SW3_TX_STREAM0_EN 0x00B214 +#define ACP_SW3_TX_STREAM1_EN 0x00B218 +#define ACP_SW3_TX_STREAM2_EN 0x00B21C +#define ACP_SW3_TX_STREAM3_EN 0x00B220 +#define ACP_SW3_TX_STREAM4_EN 0x00B224 +#define ACP_SW3_TX_STREAM5_EN 0x00B228 +#define ACP_SW3_TX_STREAM6_EN 0x00B22C +#define ACP_SW3_TX_STREAM7_EN 0x00B230 +#define ACP_SW3_TX_STREAM0_EN_STATUS 0x00B234 +#define ACP_SW3_TX_STREAM1_EN_STATUS 0x00B238 +#define ACP_SW3_TX_STREAM2_EN_STATUS 0x00B23C +#define ACP_SW3_TX_STREAM3_EN_STATUS 0x00B240 +#define ACP_SW3_TX_STREAM4_EN_STATUS 0x00B244 +#define ACP_SW3_TX_STREAM5_EN_STATUS 0x00B248 +#define ACP_SW3_TX_STREAM6_EN_STATUS 0x00B24C +#define ACP_SW3_TX_STREAM7_EN_STATUS 0x00B250 +#define ACP_SW3_TX_DP0_FRAME_FORMAT 0x00B254 +#define ACP_SW3_TX_DP1_FRAME_FORMAT 0x00B258 +#define ACP_SW3_TX_DP2_FRAME_FORMAT 0x00B25C +#define ACP_SW3_TX_DP3_FRAME_FORMAT 0x00B260 +#define ACP_SW3_TX_DP4_FRAME_FORMAT 0x00B264 +#define ACP_SW3_TX_DP5_FRAME_FORMAT 0x00B268 +#define ACP_SW3_TX_DP6_FRAME_FORMAT 0x00B26C +#define ACP_SW3_TX_DP7_FRAME_FORMAT 0x00B270 +#define ACP_SW3_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x00B280 +#define ACP_SW3_TX_DP0_0_HCTRL_BANK0 0x00B284 +#define ACP_SW3_TX_DP0_0_HCTRL_OFFSET_BANK0 0x00B288 +#define ACP_SW3_TX_DP0_0_LANE_CTRL_BANK0 0x00B28C +#define ACP_SW3_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x00B290 +#define ACP_SW3_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B294 +#define ACP_SW3_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x00B298 +#define ACP_SW3_TX_DP0_0_HCTRL_BANK1 0x00B29C +#define ACP_SW3_TX_DP0_0_HCTRL_OFFSET_BANK1 0x00B2A0 +#define ACP_SW3_TX_DP0_0_LANE_CTRL_BANK1 0x00B2A4 +#define ACP_SW3_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x00B2A8 +#define ACP_SW3_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B2AC +#define ACP_SW3_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x00B2B0 +#define ACP_SW3_TX_DP0_1_HCTRL_BANK0 0x00B2B4 +#define ACP_SW3_TX_DP0_1_HCTRL_OFFSET_BANK0 0x00B2B8 +#define ACP_SW3_TX_DP0_1_LANE_CTRL_BANK0 0x00B2BC +#define ACP_SW3_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x00B2C0 +#define ACP_SW3_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B2C4 +#define ACP_SW3_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x00B2C8 +#define ACP_SW3_TX_DP0_1_HCTRL_BANK1 0x00B2CC +#define ACP_SW3_TX_DP0_1_HCTRL_OFFSET_BANK1 0x00B2D0 +#define ACP_SW3_TX_DP0_1_LANE_CTRL_BANK1 0x00B2D4 +#define ACP_SW3_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x00B2D8 +#define ACP_SW3_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B2DC +#define ACP_SW3_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x00B2E0 +#define ACP_SW3_TX_DP0_2_HCTRL_BANK0 0x00B2E4 +#define ACP_SW3_TX_DP0_2_HCTRL_OFFSET_BANK0 0x00B2E8 +#define ACP_SW3_TX_DP0_2_LANE_CTRL_BANK0 0x00B2EC +#define ACP_SW3_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x00B2F0 +#define ACP_SW3_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B2F4 +#define ACP_SW3_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x00B2F8 +#define ACP_SW3_TX_DP0_2_HCTRL_BANK1 0x00B2FC +#define ACP_SW3_TX_DP0_2_HCTRL_OFFSET_BANK1 0x00B300 +#define ACP_SW3_TX_DP0_2_LANE_CTRL_BANK1 0x00B304 +#define ACP_SW3_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x00B308 +#define ACP_SW3_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B30C +#define ACP_SW3_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x00B310 +#define ACP_SW3_TX_DP0_3_HCTRL_BANK0 0x00B314 +#define ACP_SW3_TX_DP0_3_HCTRL_OFFSET_BANK0 0x00B318 +#define ACP_SW3_TX_DP0_3_LANE_CTRL_BANK0 0x00B31C +#define ACP_SW3_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x00B320 +#define ACP_SW3_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B324 +#define ACP_SW3_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x00B328 +#define ACP_SW3_TX_DP0_3_HCTRL_BANK1 0x00B32C +#define ACP_SW3_TX_DP0_3_HCTRL_OFFSET_BANK1 0x00B330 +#define ACP_SW3_TX_DP0_3_LANE_CTRL_BANK1 0x00B334 +#define ACP_SW3_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x00B338 +#define ACP_SW3_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B33C +#define ACP_SW3_TX_DP1_SAMPLEINTERVAL_BANK0 0x00B370 +#define ACP_SW3_TX_DP1_HCTRL_BANK0 0x00B374 +#define ACP_SW3_TX_DP1_HCTRL_OFFSET_BANK0 0x00B378 +#define ACP_SW3_TX_DP1_LANE_CTRL_BANK0 0x00B37C +#define ACP_SW3_TX_DP1_CHANNEL_ENABLE_BANK0 0x00B380 +#define ACP_SW3_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B384 +#define ACP_SW3_TX_DP1_SAMPLEINTERVAL_BANK1 0x00B388 +#define ACP_SW3_TX_DP1_HCTRL_BANK1 0x00B38C +#define ACP_SW3_TX_DP1_HCTRL_OFFSET_BANK1 0x00B390 +#define ACP_SW3_TX_DP1_LANE_CTRL_BANK1 0x00B394 +#define ACP_SW3_TX_DP1_CHANNEL_ENABLE_BANK1 0x00B398 +#define ACP_SW3_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B39C +#define ACP_SW3_TX_DP2_SAMPLEINTERVAL_BANK0 0x00B3A0 +#define ACP_SW3_TX_DP2_HCTRL_BANK0 0x00B3A4 +#define ACP_SW3_TX_DP2_HCTRL_OFFSET_BANK0 0x00B3A8 +#define ACP_SW3_TX_DP2_LANE_CTRL_BANK0 0x00B3AC +#define ACP_SW3_TX_DP2_CHANNEL_ENABLE_BANK0 0x00B3B0 +#define ACP_SW3_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B3B4 +#define ACP_SW3_TX_DP2_SAMPLEINTERVAL_BANK1 0x00B3B8 +#define ACP_SW3_TX_DP2_HCTRL_BANK1 0x00B3BC +#define ACP_SW3_TX_DP2_HCTRL_OFFSET_BANK1 0x00B3C0 +#define ACP_SW3_TX_DP2_LANE_CTRL_BANK1 0x00B3C4 +#define ACP_SW3_TX_DP2_CHANNEL_ENABLE_BANK1 0x00B3C8 +#define ACP_SW3_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B3CC +#define ACP_SW3_TX_DP3_SAMPLEINTERVAL_BANK0 0x00B3D0 +#define ACP_SW3_TX_DP3_HCTRL_BANK0 0x00B3D4 +#define ACP_SW3_TX_DP3_HCTRL_OFFSET_BANK0 0x00B3D8 +#define ACP_SW3_TX_DP3_LANE_CTRL_BANK0 0x00B3DC +#define ACP_SW3_TX_DP3_CHANNEL_ENABLE_BANK0 0x00B3E0 +#define ACP_SW3_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B3E4 +#define ACP_SW3_TX_DP3_SAMPLEINTERVAL_BANK1 0x00B3E8 +#define ACP_SW3_TX_DP3_HCTRL_BANK1 0x00B3EC +#define ACP_SW3_TX_DP3_HCTRL_OFFSET_BANK1 0x00B3F0 +#define ACP_SW3_TX_DP3_LANE_CTRL_BANK1 0x00B3F4 +#define ACP_SW3_TX_DP3_CHANNEL_ENABLE_BANK1 0x00B3F8 +#define ACP_SW3_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B3FC +#define ACP_SW3_TX_DP4_SAMPLEINTERVAL_BANK0 0x00B400 +#define ACP_SW3_TX_DP4_HCTRL_BANK0 0x00B404 +#define ACP_SW3_TX_DP4_HCTRL_OFFSET_BANK0 0x00B408 +#define ACP_SW3_TX_DP4_LANE_CTRL_BANK0 0x00B40C +#define ACP_SW3_TX_DP4_CHANNEL_ENABLE_BANK0 0x00B410 +#define ACP_SW3_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B414 +#define ACP_SW3_TX_DP4_SAMPLEINTERVAL_BANK1 0x00B418 +#define ACP_SW3_TX_DP4_HCTRL_BANK1 0x00B41C +#define ACP_SW3_TX_DP4_HCTRL_OFFSET_BANK1 0x00B420 +#define ACP_SW3_TX_DP4_LANE_CTRL_BANK1 0x00B424 +#define ACP_SW3_TX_DP4_CHANNEL_ENABLE_BANK1 0x00B428 +#define ACP_SW3_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B42C +#define ACP_SW3_TX_DP5_SAMPLEINTERVAL_BANK0 0x00B430 +#define ACP_SW3_TX_DP5_HCTRL_BANK0 0x00B434 +#define ACP_SW3_TX_DP5_HCTRL_OFFSET_BANK0 0x00B438 +#define ACP_SW3_TX_DP5_LANE_CTRL_BANK0 0x00B43C +#define ACP_SW3_TX_DP5_CHANNEL_ENABLE_BANK0 0x00B440 +#define ACP_SW3_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B444 +#define ACP_SW3_TX_DP5_SAMPLEINTERVAL_BANK1 0x00B448 +#define ACP_SW3_TX_DP5_HCTRL_BANK1 0x00B44C +#define ACP_SW3_TX_DP5_HCTRL_OFFSET_BANK1 0x00B450 +#define ACP_SW3_TX_DP5_LANE_CTRL_BANK1 0x00B454 +#define ACP_SW3_TX_DP5_CHANNEL_ENABLE_BANK1 0x00B458 +#define ACP_SW3_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B45C +#define ACP_SW3_TX_DP6_SAMPLEINTERVAL_BANK0 0x00B460 +#define ACP_SW3_TX_DP6_HCTRL_BANK0 0x00B464 +#define ACP_SW3_TX_DP6_HCTRL_OFFSET_BANK0 0x00B468 +#define ACP_SW3_TX_DP6_LANE_CTRL_BANK0 0x00B46C +#define ACP_SW3_TX_DP6_CHANNEL_ENABLE_BANK0 0x00B470 +#define ACP_SW3_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B474 +#define ACP_SW3_TX_DP6_SAMPLEINTERVAL_BANK1 0x00B478 +#define ACP_SW3_TX_DP6_HCTRL_BANK1 0x00B47C +#define ACP_SW3_TX_DP6_HCTRL_OFFSET_BANK1 0x00B480 +#define ACP_SW3_TX_DP6_LANE_CTRL_BANK1 0x00B484 +#define ACP_SW3_TX_DP6_CHANNEL_ENABLE_BANK1 0x00B488 +#define ACP_SW3_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B48C +#define ACP_SW3_TX_DP7_SAMPLEINTERVAL_BANK0 0x00B490 +#define ACP_SW3_TX_DP7_HCTRL_BANK0 0x00B494 +#define ACP_SW3_TX_DP7_HCTRL_OFFSET_BANK0 0x00B498 +#define ACP_SW3_TX_DP7_LANE_CTRL_BANK0 0x00B49C +#define ACP_SW3_TX_DP7_CHANNEL_ENABLE_BANK0 0x00B4A0 +#define ACP_SW3_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B4A4 +#define ACP_SW3_TX_DP7_SAMPLEINTERVAL_BANK1 0x00B4A8 +#define ACP_SW3_TX_DP7_HCTRL_BANK1 0x00B4AC +#define ACP_SW3_TX_DP7_HCTRL_OFFSET_BANK1 0x00B4B0 +#define ACP_SW3_TX_DP7_LANE_CTRL_BANK1 0x00B4B4 +#define ACP_SW3_TX_DP7_CHANNEL_ENABLE_BANK1 0x00B4B8 +#define ACP_SW3_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B4BC +#define ACP_SW3_RX_STREAM0_EN 0x00B514 +#define ACP_SW3_RX_STREAM1_EN 0x00B518 +#define ACP_SW3_RX_STREAM2_EN 0x00B51C +#define ACP_SW3_RX_STREAM3_EN 0x00B520 +#define ACP_SW3_RX_STREAM4_EN 0x00B524 +#define ACP_SW3_RX_STREAM5_EN 0x00B528 +#define ACP_SW3_RX_STREAM6_EN 0x00B52C +#define ACP_SW3_RX_STREAM7_EN 0x00B530 +#define ACP_SW3_RX_STREAM0_EN_STATUS 0x00B534 +#define ACP_SW3_RX_STREAM1_EN_STATUS 0x00B538 +#define ACP_SW3_RX_STREAM2_EN_STATUS 0x00B53C +#define ACP_SW3_RX_STREAM3_EN_STATUS 0x00B540 +#define ACP_SW3_RX_STREAM4_EN_STATUS 0x00B544 +#define ACP_SW3_RX_STREAM5_EN_STATUS 0x00B548 +#define ACP_SW3_RX_STREAM6_EN_STATUS 0x00B54C +#define ACP_SW3_RX_STREAM7_EN_STATUS 0x00B550 +#define ACP_SW3_RX_DP0_FRAME_FORMAT 0x00B554 +#define ACP_SW3_RX_DP1_FRAME_FORMAT 0x00B558 +#define ACP_SW3_RX_DP2_FRAME_FORMAT 0x00B55C +#define ACP_SW3_RX_DP3_FRAME_FORMAT 0x00B560 +#define ACP_SW3_RX_DP4_FRAME_FORMAT 0x00B564 +#define ACP_SW3_RX_DP5_FRAME_FORMAT 0x00B568 +#define ACP_SW3_RX_DP6_FRAME_FORMAT 0x00B56C +#define ACP_SW3_RX_DP7_FRAME_FORMAT 0x00B570 +#define ACP_SW3_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x00B580 +#define ACP_SW3_RX_DP0_0_HCTRL_BANK0 0x00B584 +#define ACP_SW3_RX_DP0_0_HCTRL_OFFSET_BANK0 0x00B588 +#define ACP_SW3_RX_DP0_0_LANE_CTRL_BANK0 0x00B58C +#define ACP_SW3_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x00B590 +#define ACP_SW3_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B594 +#define ACP_SW3_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x00B598 +#define ACP_SW3_RX_DP0_0_HCTRL_BANK1 0x00B59C +#define ACP_SW3_RX_DP0_0_HCTRL_OFFSET_BANK1 0x00B5A0 +#define ACP_SW3_RX_DP0_0_LANE_CTRL_BANK1 0x00B5A4 +#define ACP_SW3_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x00B5A8 +#define ACP_SW3_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B5AC +#define ACP_SW3_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x00B5B0 +#define ACP_SW3_RX_DP0_1_HCTRL_BANK0 0x00B5B4 +#define ACP_SW3_RX_DP0_1_HCTRL_OFFSET_BANK0 0x00B5B8 +#define ACP_SW3_RX_DP0_1_LANE_CTRL_BANK0 0x00B5BC +#define ACP_SW3_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x00B5C0 +#define ACP_SW3_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B5C4 +#define ACP_SW3_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x00B5C8 +#define ACP_SW3_RX_DP0_1_HCTRL_BANK1 0x00B5CC +#define ACP_SW3_RX_DP0_1_HCTRL_OFFSET_BANK1 0x00B5D0 +#define ACP_SW3_RX_DP0_1_LANE_CTRL_BANK1 0x00B5D4 +#define ACP_SW3_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x00B5D8 +#define ACP_SW3_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B5DC +#define ACP_SW3_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x00B5E0 +#define ACP_SW3_RX_DP0_2_HCTRL_BANK0 0x00B5E4 +#define ACP_SW3_RX_DP0_2_HCTRL_OFFSET_BANK0 0x00B5E8 +#define ACP_SW3_RX_DP0_2_LANE_CTRL_BANK0 0x00B5EC +#define ACP_SW3_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x00B5F0 +#define ACP_SW3_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B5F4 +#define ACP_SW3_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x00B5F8 +#define ACP_SW3_RX_DP0_2_HCTRL_BANK1 0x00B5FC +#define ACP_SW3_RX_DP0_2_HCTRL_OFFSET_BANK1 0x00B600 +#define ACP_SW3_RX_DP0_2_LANE_CTRL_BANK1 0x00B604 +#define ACP_SW3_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x00B608 +#define ACP_SW3_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B60C +#define ACP_SW3_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x00B610 +#define ACP_SW3_RX_DP0_3_HCTRL_BANK0 0x00B614 +#define ACP_SW3_RX_DP0_3_HCTRL_OFFSET_BANK0 0x00B618 +#define ACP_SW3_RX_DP0_3_LANE_CTRL_BANK0 0x00B61C +#define ACP_SW3_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x00B620 +#define ACP_SW3_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B624 +#define ACP_SW3_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x00B628 +#define ACP_SW3_RX_DP0_3_HCTRL_BANK1 0x00B62C +#define ACP_SW3_RX_DP0_3_HCTRL_OFFSET_BANK1 0x00B630 +#define ACP_SW3_RX_DP0_3_LANE_CTRL_BANK1 0x00B634 +#define ACP_SW3_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x00B638 +#define ACP_SW3_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B63C +#define ACP_SW3_RX_DP1_SAMPLEINTERVAL_BANK0 0x00B670 +#define ACP_SW3_RX_DP1_HCTRL_BANK0 0x00B674 +#define ACP_SW3_RX_DP1_HCTRL_OFFSET_BANK0 0x00B678 +#define ACP_SW3_RX_DP1_LANE_CTRL_BANK0 0x00B67C +#define ACP_SW3_RX_DP1_CHANNEL_ENABLE_BANK0 0x00B680 +#define ACP_SW3_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B684 +#define ACP_SW3_RX_DP1_SAMPLEINTERVAL_BANK1 0x00B688 +#define ACP_SW3_RX_DP1_HCTRL_BANK1 0x00B68C +#define ACP_SW3_RX_DP1_HCTRL_OFFSET_BANK1 0x00B690 +#define ACP_SW3_RX_DP1_LANE_CTRL_BANK1 0x00B694 +#define ACP_SW3_RX_DP1_CHANNEL_ENABLE_BANK1 0x00B698 +#define ACP_SW3_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B69C +#define ACP_SW3_RX_DP2_SAMPLEINTERVAL_BANK0 0x00B6A0 +#define ACP_SW3_RX_DP2_HCTRL_BANK0 0x00B6A4 +#define ACP_SW3_RX_DP2_HCTRL_OFFSET_BANK0 0x00B6A8 +#define ACP_SW3_RX_DP2_LANE_CTRL_BANK0 0x00B6AC +#define ACP_SW3_RX_DP2_CHANNEL_ENABLE_BANK0 0x00B6B0 +#define ACP_SW3_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B6B4 +#define ACP_SW3_RX_DP2_SAMPLEINTERVAL_BANK1 0x00B6B8 +#define ACP_SW3_RX_DP2_HCTRL_BANK1 0x00B6BC +#define ACP_SW3_RX_DP2_HCTRL_OFFSET_BANK1 0x00B6C0 +#define ACP_SW3_RX_DP2_LANE_CTRL_BANK1 0x00B6C4 +#define ACP_SW3_RX_DP2_CHANNEL_ENABLE_BANK1 0x00B6C8 +#define ACP_SW3_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B6CC +#define ACP_SW3_RX_DP3_SAMPLEINTERVAL_BANK0 0x00B6D0 +#define ACP_SW3_RX_DP3_HCTRL_BANK0 0x00B6D4 +#define ACP_SW3_RX_DP3_HCTRL_OFFSET_BANK0 0x00B6D8 +#define ACP_SW3_RX_DP3_LANE_CTRL_BANK0 0x00B6DC +#define ACP_SW3_RX_DP3_CHANNEL_ENABLE_BANK0 0x00B6E0 +#define ACP_SW3_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B6E4 +#define ACP_SW3_RX_DP3_SAMPLEINTERVAL_BANK1 0x00B6E8 +#define ACP_SW3_RX_DP3_HCTRL_BANK1 0x00B6EC +#define ACP_SW3_RX_DP3_HCTRL_OFFSET_BANK1 0x00B6F0 +#define ACP_SW3_RX_DP3_LANE_CTRL_BANK1 0x00B6F4 +#define ACP_SW3_RX_DP3_CHANNEL_ENABLE_BANK1 0x00B6F8 +#define ACP_SW3_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B6FC +#define ACP_SW3_RX_DP4_SAMPLEINTERVAL_BANK0 0x00B700 +#define ACP_SW3_RX_DP4_HCTRL_BANK0 0x00B704 +#define ACP_SW3_RX_DP4_HCTRL_OFFSET_BANK0 0x00B708 +#define ACP_SW3_RX_DP4_LANE_CTRL_BANK0 0x00B70C +#define ACP_SW3_RX_DP4_CHANNEL_ENABLE_BANK0 0x00B710 +#define ACP_SW3_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B714 +#define ACP_SW3_RX_DP4_SAMPLEINTERVAL_BANK1 0x00B718 +#define ACP_SW3_RX_DP4_HCTRL_BANK1 0x00B71C +#define ACP_SW3_RX_DP4_HCTRL_OFFSET_BANK1 0x00B720 +#define ACP_SW3_RX_DP4_LANE_CTRL_BANK1 0x00B724 +#define ACP_SW3_RX_DP4_CHANNEL_ENABLE_BANK1 0x00B728 +#define ACP_SW3_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B72C +#define ACP_SW3_RX_DP5_SAMPLEINTERVAL_BANK0 0x00B730 +#define ACP_SW3_RX_DP5_HCTRL_BANK0 0x00B734 +#define ACP_SW3_RX_DP5_HCTRL_OFFSET_BANK0 0x00B738 +#define ACP_SW3_RX_DP5_LANE_CTRL_BANK0 0x00B73C +#define ACP_SW3_RX_DP5_CHANNEL_ENABLE_BANK0 0x00B740 +#define ACP_SW3_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B744 +#define ACP_SW3_RX_DP5_SAMPLEINTERVAL_BANK1 0x00B748 +#define ACP_SW3_RX_DP5_HCTRL_BANK1 0x00B74C +#define ACP_SW3_RX_DP5_HCTRL_OFFSET_BANK1 0x00B750 +#define ACP_SW3_RX_DP5_LANE_CTRL_BANK1 0x00B754 +#define ACP_SW3_RX_DP5_CHANNEL_ENABLE_BANK1 0x00B758 +#define ACP_SW3_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B75C +#define ACP_SW3_RX_DP6_SAMPLEINTERVAL_BANK0 0x00B760 +#define ACP_SW3_RX_DP6_HCTRL_BANK0 0x00B764 +#define ACP_SW3_RX_DP6_HCTRL_OFFSET_BANK0 0x00B768 +#define ACP_SW3_RX_DP6_LANE_CTRL_BANK0 0x00B76C +#define ACP_SW3_RX_DP6_CHANNEL_ENABLE_BANK0 0x00B770 +#define ACP_SW3_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B774 +#define ACP_SW3_RX_DP6_SAMPLEINTERVAL_BANK1 0x00B778 +#define ACP_SW3_RX_DP6_HCTRL_BANK1 0x00B77C +#define ACP_SW3_RX_DP6_HCTRL_OFFSET_BANK1 0x00B780 +#define ACP_SW3_RX_DP6_LANE_CTRL_BANK1 0x00B784 +#define ACP_SW3_RX_DP6_CHANNEL_ENABLE_BANK1 0x00B788 +#define ACP_SW3_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B78C +#define ACP_SW3_RX_DP7_SAMPLEINTERVAL_BANK0 0x00B790 +#define ACP_SW3_RX_DP7_HCTRL_BANK0 0x00B794 +#define ACP_SW3_RX_DP7_HCTRL_OFFSET_BANK0 0x00B798 +#define ACP_SW3_RX_DP7_LANE_CTRL_BANK0 0x00B79C +#define ACP_SW3_RX_DP7_CHANNEL_ENABLE_BANK0 0x00B7A0 +#define ACP_SW3_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B7A4 +#define ACP_SW3_RX_DP7_SAMPLEINTERVAL_BANK1 0x00B7A8 +#define ACP_SW3_RX_DP7_HCTRL_BANK1 0x00B7AC +#define ACP_SW3_RX_DP7_HCTRL_OFFSET_BANK1 0x00B7B0 +#define ACP_SW3_RX_DP7_LANE_CTRL_BANK1 0x00B7B4 +#define ACP_SW3_RX_DP7_CHANNEL_ENABLE_BANK1 0x00B7B8 +#define ACP_SW3_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B7BC +#define ACP_SW3_BPT_PORT_EN 0x00B7C0 +#define ACP_SW3_BPT_PORT_EN_STATUS 0x00B7C4 +#define ACP_SW3_BPT_PORT_FRAME_FORMAT 0x00B7C8 +#define ACP_SW3_BPT_PORT_SAMPLEINTERVAL_BANK0 0x00B7CC +#define ACP_SW3_BPT_PORT_HCTRL_BANK0 0x00B7D0 +#define ACP_SW3_BPT_PORT_OFFSET_BANK0 0x00B7D4 +#define ACP_SW3_BPT_PORT_LANE_SELECT_BANK0 0x00B7D8 +#define ACP_SW3_BPT_PORT_CHANNEL_ENABLE_BANK0 0x00B7DC +#define ACP_SW3_BPT_PORT_SAMPLEINTERVAL_BANK1 0x00B7E0 +#define ACP_SW3_BPT_PORT_HCTRL_BANK1 0x00B7E4 +#define ACP_SW3_BPT_PORT_OFFSET_BANK1 0x00B7E8 +#define ACP_SW3_BPT_PORT_LANE_SELECT_BANK1 0x00B7EC +#define ACP_SW3_BPT_PORT_CHANNEL_ENABLE_BANK1 0x00B7F0 +#define ACP_SW3_BPT_PORT_FIRST_BYTE_ADDR 0x00B7F4 +#define ACP_SW3_CLK_RESUME_CTRL 0x00B7F8 +#define ACP_SW3_CLK_RESUME_DELAY_CNTR 0x00B7FC +#define ACP_SW3_BUS_RESET_CTRL 0x00B800 +#define ACP_SW3_PRBS_ERR_STATUS 0x00B804 +#define ACP_SW3_WALLCLK_MISC 0x00B808 +#define ACP_SW3_WALL_CLK_COUNTER 0x00B80C +#define ACP_SW3_PING_STATUS_REGISTER_LOW 0x00B810 +#define ACP_SW3_PING_STATUS_REGISTER_HIGH 0x00B814 +#define ACP_SW3_PING_STATUS_CURRENT_BANK_SEL 0x00B818 +#define ACP_SW3_TZD_CHANGE 0x00B81C +#define ACP_SW3_WALLCLK_INTR_CNTL 0x00B820 + +#define ACP_PDM_ENABLE 0x002C04 +#define ACP_PDM_DMA_ENABLE 0x002C08 +#define ACP_PDM_RX_RINGBUFADDR 0x002C0C +#define ACP_PDM_RX_RINGBUFSIZE 0x002C10 +#define ACP_PDM_RX_LINKPOSITIONCNTR 0x002C14 +#define ACP_PDM_RX_LINEARPOSITIONCNTR_HIGH 0x002C18 +#define ACP_PDM_RX_LINEARPOSITIONCNTR_LOW 0x002C1C +#define ACP_PDM_RX_INTR_WATERMARK_SIZE 0x002C20 +#define ACP_PDM_FIFO_FLUSH 0x002C24 +#define ACP_PDM_NO_OF_CHANNELS 0x002C28 +#define ACP_PDM_DECIMATION_FACTOR 0x002C2C +#define ACP_PDM_VAD_CTRL 0x002C30 +#define ACP_PDM_WAKE 0x002C54 +#define ACP_PDM_BUFFER_STATUS 0x002C58 +#define ACP_PDM_MISC_CTRL 0x002C5C +#define ACP_PDM_CLK_CTRL 0x002C60 +#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x002C64 +#define ACP_PDM_ERROR_STATUS_REGISTER 0x002C68 +#define ACP_PDM_CLKDIV 0x002C6C +#define ACP_PDM_WALLCLK_MISC 0x002C70 +#define ACP_PDM_WALL_CLK_COUNTER 0x002C74 +#define ACP_PDM_SW_ENABLE_REG 0x002CC4 +#define ACP_PDM_SW_CTRLREG 0x002CC8 +#define ACP_PDM_WALLCLK_INTR_CNTL 0x002CCC + +#define ACP_PDM_2_ENABLE 0x002D04 +#define ACP_PDM_2_DMA_ENABLE 0x002D08 +#define ACP_PDM_2_RX_RINGBUFADDR_96K 0x002D0C +#define ACP_PDM_2_RX_RINGBUFADDR_48K 0x002D10 +#define ACP_PDM_2_RX_RINGBUFADDR_16K 0x002D14 +#define ACP_PDM_2_RX_RINGBUFSIZE_96K 0x002D18 +#define ACP_PDM_2_RX_RINGBUFSIZE_48K 0x002D1C +#define ACP_PDM_2_RX_RINGBUFSIZE_16K 0x002D20 +#define ACP_PDM_2_RX_LINKPOSITIONCNTR_96K 0x002D24 +#define ACP_PDM_2_RX_LINKPOSITIONCNTR_48K 0x002D28 +#define ACP_PDM_2_RX_LINKPOSITIONCNTR_16K 0x002D2C +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_96K 0x002D30 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_96K 0x002D34 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_48K 0x002D38 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_48K 0x002D3C +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_16K 0x002D40 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_16K 0x002D44 +#define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_96K 0x002D48 +#define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_48K 0x002D4C +#define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_16K 0x002D50 +#define ACP_PDM_2_FIFO_FLUSH_96K 0x002D54 +#define ACP_PDM_2_FIFO_FLUSH_48K 0x002D58 +#define ACP_PDM_2_FIFO_FLUSH_16K 0x002D5C +#define ACP_PDM_2_NO_OF_CHANNELS 0x002D60 +#define ACP_PDM_2_DECIMATION_FACTOR 0x002D64 +#define ACP_PDM_2_VAD_CTRL 0x002D68 +#define ACP_PDM_2_WAKE 0x002D6C +#define ACP_PDM_2_BUFFER_STATUS_96K 0x002D70 +#define ACP_PDM_2_BUFFER_STATUS_48K 0x002D74 +#define ACP_PDM_2_BUFFER_STATUS_16K 0x002D78 +#define ACP_PDM_2_MISC_CTRL 0x002D7C +#define ACP_PDM_2_CLK_CTRL 0x002D80 +#define ACP_PDM_2_VAD_DYNAMIC_CLK_GATING_EN 0x002D84 +#define ACP_PDM_2_ERROR_STATUS_REGISTER 0x002D8C +#define ACP_PDM_2_CLKDIV 0x002D90 +#define ACP_PDM_2_WALLCLK_MISC 0x002D94 +#define ACP_PDM_2_WALL_CLK_COUNTER 0x002D98 +#define ACP_PDM_2_SW_ENABLE_REG 0x002D9C +#define ACP_PDM_2_SW_CTRLREG 0x002DA0 +#define ACP_PDM_2_WALLCLK_INTR_CNTL 0x002DA4 + +#define ACP_SCRATCH_REG_0 0x0010000 +#endif diff --git a/include/sound/ad1816a.h b/include/sound/ad1816a.h new file mode 100644 index 000000000..283477e86 --- /dev/null +++ b/include/sound/ad1816a.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AD1816A_H +#define __SOUND_AD1816A_H + +/* + ad1816a.h - definitions for ADI SoundPort AD1816A chip. + Copyright (C) 1999-2000 by Massimo Piccioni + +*/ + +#include +#include +#include + +#define AD1816A_REG(r) (chip->port + r) + +#define AD1816A_CHIP_STATUS 0x00 +#define AD1816A_INDIR_ADDR 0x00 +#define AD1816A_INTERRUPT_STATUS 0x01 +#define AD1816A_INDIR_DATA_LOW 0x02 +#define AD1816A_INDIR_DATA_HIGH 0x03 +#define AD1816A_PIO_DEBUG 0x04 +#define AD1816A_PIO_STATUS 0x05 +#define AD1816A_PIO_DATA 0x06 +#define AD1816A_RESERVED_7 0x07 +#define AD1816A_PLAYBACK_CONFIG 0x08 +#define AD1816A_CAPTURE_CONFIG 0x09 +#define AD1816A_RESERVED_10 0x0a +#define AD1816A_RESERVED_11 0x0b +#define AD1816A_JOYSTICK_RAW_DATA 0x0c +#define AD1816A_JOYSTICK_CTRL 0x0d +#define AD1816A_JOY_POS_DATA_LOW 0x0e +#define AD1816A_JOY_POS_DATA_HIGH 0x0f + +#define AD1816A_LOW_BYTE_TMP 0x00 +#define AD1816A_INTERRUPT_ENABLE 0x01 +#define AD1816A_EXTERNAL_CTRL 0x01 +#define AD1816A_PLAYBACK_SAMPLE_RATE 0x02 +#define AD1816A_CAPTURE_SAMPLE_RATE 0x03 +#define AD1816A_VOICE_ATT 0x04 +#define AD1816A_FM_ATT 0x05 +#define AD1816A_I2S_1_ATT 0x06 +#define AD1816A_I2S_0_ATT 0x07 +#define AD1816A_PLAYBACK_BASE_COUNT 0x08 +#define AD1816A_PLAYBACK_CURR_COUNT 0x09 +#define AD1816A_CAPTURE_BASE_COUNT 0x0a +#define AD1816A_CAPTURE_CURR_COUNT 0x0b +#define AD1816A_TIMER_BASE_COUNT 0x0c +#define AD1816A_TIMER_CURR_COUNT 0x0d +#define AD1816A_MASTER_ATT 0x0e +#define AD1816A_CD_GAIN_ATT 0x0f +#define AD1816A_SYNTH_GAIN_ATT 0x10 +#define AD1816A_VID_GAIN_ATT 0x11 +#define AD1816A_LINE_GAIN_ATT 0x12 +#define AD1816A_MIC_GAIN_ATT 0x13 +#define AD1816A_PHONE_IN_GAIN_ATT 0x13 +#define AD1816A_ADC_SOURCE_SEL 0x14 +#define AD1816A_ADC_PGA 0x14 +#define AD1816A_CHIP_CONFIG 0x20 +#define AD1816A_DSP_CONFIG 0x21 +#define AD1816A_FM_SAMPLE_RATE 0x22 +#define AD1816A_I2S_1_SAMPLE_RATE 0x23 +#define AD1816A_I2S_0_SAMPLE_RATE 0x24 +#define AD1816A_RESERVED_37 0x25 +#define AD1816A_PROGRAM_CLOCK_RATE 0x26 +#define AD1816A_3D_PHAT_CTRL 0x27 +#define AD1816A_PHONE_OUT_ATT 0x27 +#define AD1816A_RESERVED_40 0x28 +#define AD1816A_HW_VOL_BUT 0x29 +#define AD1816A_DSP_MAILBOX_0 0x2a +#define AD1816A_DSP_MAILBOX_1 0x2b +#define AD1816A_POWERDOWN_CTRL 0x2c +#define AD1816A_TIMER_CTRL 0x2c +#define AD1816A_VERSION_ID 0x2d +#define AD1816A_RESERVED_46 0x2e + +#define AD1816A_READY 0x80 + +#define AD1816A_PLAYBACK_IRQ_PENDING 0x80 +#define AD1816A_CAPTURE_IRQ_PENDING 0x40 +#define AD1816A_TIMER_IRQ_PENDING 0x20 + +#define AD1816A_PLAYBACK_ENABLE 0x01 +#define AD1816A_PLAYBACK_PIO 0x02 +#define AD1816A_CAPTURE_ENABLE 0x01 +#define AD1816A_CAPTURE_PIO 0x02 + +#define AD1816A_FMT_LINEAR_8 0x00 +#define AD1816A_FMT_ULAW_8 0x08 +#define AD1816A_FMT_LINEAR_16_LIT 0x10 +#define AD1816A_FMT_ALAW_8 0x18 +#define AD1816A_FMT_LINEAR_16_BIG 0x30 +#define AD1816A_FMT_ALL 0x38 +#define AD1816A_FMT_STEREO 0x04 + +#define AD1816A_PLAYBACK_IRQ_ENABLE 0x8000 +#define AD1816A_CAPTURE_IRQ_ENABLE 0x4000 +#define AD1816A_TIMER_IRQ_ENABLE 0x2000 +#define AD1816A_TIMER_ENABLE 0x0080 + +#define AD1816A_SRC_LINE 0x00 +#define AD1816A_SRC_OUT 0x10 +#define AD1816A_SRC_CD 0x20 +#define AD1816A_SRC_SYNTH 0x30 +#define AD1816A_SRC_VIDEO 0x40 +#define AD1816A_SRC_MIC 0x50 +#define AD1816A_SRC_MONO 0x50 +#define AD1816A_SRC_PHONE_IN 0x60 +#define AD1816A_SRC_MASK 0x70 + +#define AD1816A_CAPTURE_NOT_EQUAL 0x1000 +#define AD1816A_WSS_ENABLE 0x8000 + +struct snd_ad1816a { + unsigned long port; + struct resource *res_port; + int irq; + int dma1; + int dma2; + + unsigned short hardware; + unsigned short version; + + spinlock_t lock; + + unsigned short mode; + unsigned int clock_freq; + + struct snd_card *card; + struct snd_pcm *pcm; + + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + unsigned int p_dma_size; + unsigned int c_dma_size; + + struct snd_timer *timer; +#ifdef CONFIG_PM + unsigned short image[48]; +#endif +}; + + +#define AD1816A_HW_AUTO 0 +#define AD1816A_HW_AD1816A 1 +#define AD1816A_HW_AD1815 2 +#define AD1816A_HW_AD18MAX10 3 + +#define AD1816A_MODE_PLAYBACK 0x01 +#define AD1816A_MODE_CAPTURE 0x02 +#define AD1816A_MODE_TIMER 0x04 +#define AD1816A_MODE_OPEN (AD1816A_MODE_PLAYBACK | \ + AD1816A_MODE_CAPTURE | \ + AD1816A_MODE_TIMER) + + +extern int snd_ad1816a_create(struct snd_card *card, unsigned long port, + int irq, int dma1, int dma2, + struct snd_ad1816a *chip); + +extern int snd_ad1816a_pcm(struct snd_ad1816a *chip, int device); +extern int snd_ad1816a_mixer(struct snd_ad1816a *chip); +extern int snd_ad1816a_timer(struct snd_ad1816a *chip, int device); +#ifdef CONFIG_PM +extern void snd_ad1816a_suspend(struct snd_ad1816a *chip); +extern void snd_ad1816a_resume(struct snd_ad1816a *chip); +#endif + +#endif /* __SOUND_AD1816A_H */ diff --git a/include/sound/ad1843.h b/include/sound/ad1843.h new file mode 100644 index 000000000..b236a9d1d --- /dev/null +++ b/include/sound/ad1843.h @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright 2003 Vivien Chappelier + * Copyright 2008 Thomas Bogendoerfer + */ + +#ifndef __SOUND_AD1843_H +#define __SOUND_AD1843_H + +struct snd_ad1843 { + void *chip; + int (*read)(void *chip, int reg); + int (*write)(void *chip, int reg, int val); +}; + +#define AD1843_GAIN_RECLEV 0 +#define AD1843_GAIN_LINE 1 +#define AD1843_GAIN_LINE_2 2 +#define AD1843_GAIN_MIC 3 +#define AD1843_GAIN_PCM_0 4 +#define AD1843_GAIN_PCM_1 5 +#define AD1843_GAIN_SIZE (AD1843_GAIN_PCM_1+1) + +int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id); +int ad1843_get_gain(struct snd_ad1843 *ad1843, int id); +int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval); +int ad1843_get_recsrc(struct snd_ad1843 *ad1843); +int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc); +void ad1843_setup_dac(struct snd_ad1843 *ad1843, + unsigned int id, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, + unsigned int id); +void ad1843_setup_adc(struct snd_ad1843 *ad1843, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_adc(struct snd_ad1843 *ad1843); +int ad1843_init(struct snd_ad1843 *ad1843); + +#endif /* __SOUND_AD1843_H */ diff --git a/include/sound/ak4113.h b/include/sound/ak4113.h new file mode 100644 index 000000000..9ac342ba8 --- /dev/null +++ b/include/sound/ak4113.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4113_H +#define __SOUND_AK4113_H + +/* + * Routines for Asahi Kasei AK4113 + * Copyright (c) by Jaroslav Kysela , + * Copyright (c) by Pavel Hofman , + */ + +/* AK4113 registers */ +/* power down */ +#define AK4113_REG_PWRDN 0x00 +/* format control */ +#define AK4113_REG_FORMAT 0x01 +/* input/output control */ +#define AK4113_REG_IO0 0x02 +/* input/output control */ +#define AK4113_REG_IO1 0x03 +/* interrupt0 mask */ +#define AK4113_REG_INT0_MASK 0x04 +/* interrupt1 mask */ +#define AK4113_REG_INT1_MASK 0x05 +/* DAT mask & DTS select */ +#define AK4113_REG_DATDTS 0x06 +/* receiver status 0 */ +#define AK4113_REG_RCS0 0x07 +/* receiver status 1 */ +#define AK4113_REG_RCS1 0x08 +/* receiver status 2 */ +#define AK4113_REG_RCS2 0x09 +/* RX channel status byte 0 */ +#define AK4113_REG_RXCSB0 0x0a +/* RX channel status byte 1 */ +#define AK4113_REG_RXCSB1 0x0b +/* RX channel status byte 2 */ +#define AK4113_REG_RXCSB2 0x0c +/* RX channel status byte 3 */ +#define AK4113_REG_RXCSB3 0x0d +/* RX channel status byte 4 */ +#define AK4113_REG_RXCSB4 0x0e +/* burst preamble Pc byte 0 */ +#define AK4113_REG_Pc0 0x0f +/* burst preamble Pc byte 1 */ +#define AK4113_REG_Pc1 0x10 +/* burst preamble Pd byte 0 */ +#define AK4113_REG_Pd0 0x11 +/* burst preamble Pd byte 1 */ +#define AK4113_REG_Pd1 0x12 +/* Q-subcode address + control */ +#define AK4113_REG_QSUB_ADDR 0x13 +/* Q-subcode track */ +#define AK4113_REG_QSUB_TRACK 0x14 +/* Q-subcode index */ +#define AK4113_REG_QSUB_INDEX 0x15 +/* Q-subcode minute */ +#define AK4113_REG_QSUB_MINUTE 0x16 +/* Q-subcode second */ +#define AK4113_REG_QSUB_SECOND 0x17 +/* Q-subcode frame */ +#define AK4113_REG_QSUB_FRAME 0x18 +/* Q-subcode zero */ +#define AK4113_REG_QSUB_ZERO 0x19 +/* Q-subcode absolute minute */ +#define AK4113_REG_QSUB_ABSMIN 0x1a +/* Q-subcode absolute second */ +#define AK4113_REG_QSUB_ABSSEC 0x1b +/* Q-subcode absolute frame */ +#define AK4113_REG_QSUB_ABSFRM 0x1c + +/* sizes */ +#define AK4113_REG_RXCSB_SIZE ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1) +#define AK4113_REG_QSUB_SIZE ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\ + +1) + +#define AK4113_WRITABLE_REGS (AK4113_REG_DATDTS + 1) + +/* AK4113_REG_PWRDN bits */ +/* Channel Status Select */ +#define AK4113_CS12 (1<<7) +/* Block Start & C/U Output Mode */ +#define AK4113_BCU (1<<6) +/* Master Clock Operation Select */ +#define AK4113_CM1 (1<<5) +/* Master Clock Operation Select */ +#define AK4113_CM0 (1<<4) +/* Master Clock Frequency Select */ +#define AK4113_OCKS1 (1<<3) +/* Master Clock Frequency Select */ +#define AK4113_OCKS0 (1<<2) +/* 0 = power down, 1 = normal operation */ +#define AK4113_PWN (1<<1) +/* 0 = reset & initialize (except thisregister), 1 = normal operation */ +#define AK4113_RST (1<<0) + +/* AK4113_REQ_FORMAT bits */ +/* V/TX Output select: 0 = Validity Flag Output, 1 = TX */ +#define AK4113_VTX (1<<7) +/* Audio Data Control */ +#define AK4113_DIF2 (1<<6) +/* Audio Data Control */ +#define AK4113_DIF1 (1<<5) +/* Audio Data Control */ +#define AK4113_DIF0 (1<<4) +/* Deemphasis Autodetect Enable (1 = enable) */ +#define AK4113_DEAU (1<<3) +/* 32kHz-48kHz Deemphasis Control */ +#define AK4113_DEM1 (1<<2) +/* 32kHz-48kHz Deemphasis Control */ +#define AK4113_DEM0 (1<<1) +#define AK4113_DEM_OFF (AK4113_DEM0) +#define AK4113_DEM_44KHZ (0) +#define AK4113_DEM_48KHZ (AK4113_DEM1) +#define AK4113_DEM_32KHZ (AK4113_DEM0|AK4113_DEM1) +/* STDO: 16-bit, right justified */ +#define AK4113_DIF_16R (0) +/* STDO: 18-bit, right justified */ +#define AK4113_DIF_18R (AK4113_DIF0) +/* STDO: 20-bit, right justified */ +#define AK4113_DIF_20R (AK4113_DIF1) +/* STDO: 24-bit, right justified */ +#define AK4113_DIF_24R (AK4113_DIF1|AK4113_DIF0) +/* STDO: 24-bit, left justified */ +#define AK4113_DIF_24L (AK4113_DIF2) +/* STDO: I2S */ +#define AK4113_DIF_24I2S (AK4113_DIF2|AK4113_DIF0) +/* STDO: 24-bit, left justified; LRCLK, BICK = Input */ +#define AK4113_DIF_I24L (AK4113_DIF2|AK4113_DIF1) +/* STDO: I2S; LRCLK, BICK = Input */ +#define AK4113_DIF_I24I2S (AK4113_DIF2|AK4113_DIF1|AK4113_DIF0) + +/* AK4113_REG_IO0 */ +/* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ +#define AK4113_XTL1 (1<<6) +/* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ +#define AK4113_XTL0 (1<<5) +/* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */ +#define AK4113_UCE (1<<4) +/* TX Output Enable (1 = enable) */ +#define AK4113_TXE (1<<3) +/* Output Through Data Selector for TX pin */ +#define AK4113_OPS2 (1<<2) +/* Output Through Data Selector for TX pin */ +#define AK4113_OPS1 (1<<1) +/* Output Through Data Selector for TX pin */ +#define AK4113_OPS0 (1<<0) +/* 11.2896 MHz ref. Xtal freq. */ +#define AK4113_XTL_11_2896M (0) +/* 12.288 MHz ref. Xtal freq. */ +#define AK4113_XTL_12_288M (AK4113_XTL0) +/* 24.576 MHz ref. Xtal freq. */ +#define AK4113_XTL_24_576M (AK4113_XTL1) + +/* AK4113_REG_IO1 */ +/* Interrupt 0 pin Hold */ +#define AK4113_EFH1 (1<<7) +/* Interrupt 0 pin Hold */ +#define AK4113_EFH0 (1<<6) +#define AK4113_EFH_512LRCLK (0) +#define AK4113_EFH_1024LRCLK (AK4113_EFH0) +#define AK4113_EFH_2048LRCLK (AK4113_EFH1) +#define AK4113_EFH_4096LRCLK (AK4113_EFH1|AK4113_EFH0) +/* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */ +#define AK4113_FAST (1<<5) +/* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */ +#define AK4113_XMCK (1<<4) +/* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5 (req. XMCK = 1) */ +#define AK4113_DIV (1<<3) +/* Input Recovery Data Select */ +#define AK4113_IPS2 (1<<2) +/* Input Recovery Data Select */ +#define AK4113_IPS1 (1<<1) +/* Input Recovery Data Select */ +#define AK4113_IPS0 (1<<0) +#define AK4113_IPS(x) ((x)&7) + +/* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/ +/* mask enable for QINT bit */ +#define AK4113_MQI (1<<7) +/* mask enable for AUTO bit */ +#define AK4113_MAUT (1<<6) +/* mask enable for CINT bit */ +#define AK4113_MCIT (1<<5) +/* mask enable for UNLOCK bit */ +#define AK4113_MULK (1<<4) +/* mask enable for V bit */ +#define AK4113_V (1<<3) +/* mask enable for STC bit */ +#define AK4113_STC (1<<2) +/* mask enable for AUDN bit */ +#define AK4113_MAN (1<<1) +/* mask enable for PAR bit */ +#define AK4113_MPR (1<<0) + +/* AK4113_REG_DATDTS */ +/* DAT Start ID Counter */ +#define AK4113_DCNT (1<<4) +/* DTS-CD 16-bit Sync Word Detect */ +#define AK4113_DTS16 (1<<3) +/* DTS-CD 14-bit Sync Word Detect */ +#define AK4113_DTS14 (1<<2) +/* mask enable for DAT bit (if 1, no INT1 effect */ +#define AK4113_MDAT1 (1<<1) +/* mask enable for DAT bit (if 1, no INT0 effect */ +#define AK4113_MDAT0 (1<<0) + +/* AK4113_REG_RCS0 */ +/* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ +#define AK4113_QINT (1<<7) +/* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ +#define AK4113_AUTO (1<<6) +/* channel status buffer interrupt, 0 = no change, 1 = change */ +#define AK4113_CINT (1<<5) +/* PLL lock status, 0 = lock, 1 = unlock */ +#define AK4113_UNLCK (1<<4) +/* Validity bit, 0 = valid, 1 = invalid */ +#define AK4113_V (1<<3) +/* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ +#define AK4113_STC (1<<2) +/* audio bit output, 0 = audio, 1 = non-audio */ +#define AK4113_AUDION (1<<1) +/* parity error or biphase error status, 0 = no error, 1 = error */ +#define AK4113_PAR (1<<0) + +/* AK4113_REG_RCS1 */ +/* sampling frequency detection */ +#define AK4113_FS3 (1<<7) +#define AK4113_FS2 (1<<6) +#define AK4113_FS1 (1<<5) +#define AK4113_FS0 (1<<4) +/* Pre-emphasis detect, 0 = OFF, 1 = ON */ +#define AK4113_PEM (1<<3) +/* DAT Start ID Detect, 0 = no detect, 1 = detect */ +#define AK4113_DAT (1<<2) +/* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ +#define AK4113_DTSCD (1<<1) +/* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ +#define AK4113_NPCM (1<<0) +#define AK4113_FS_8000HZ (AK4113_FS3|AK4113_FS0) +#define AK4113_FS_11025HZ (AK4113_FS2|AK4113_FS0) +#define AK4113_FS_16000HZ (AK4113_FS2|AK4113_FS1|AK4113_FS0) +#define AK4113_FS_22050HZ (AK4113_FS2) +#define AK4113_FS_24000HZ (AK4113_FS2|AK4113_FS1) +#define AK4113_FS_32000HZ (AK4113_FS1|AK4113_FS0) +#define AK4113_FS_44100HZ (0) +#define AK4113_FS_48000HZ (AK4113_FS1) +#define AK4113_FS_64000HZ (AK4113_FS3|AK4113_FS1|AK4113_FS0) +#define AK4113_FS_88200HZ (AK4113_FS3) +#define AK4113_FS_96000HZ (AK4113_FS3|AK4113_FS1) +#define AK4113_FS_176400HZ (AK4113_FS3|AK4113_FS2) +#define AK4113_FS_192000HZ (AK4113_FS3|AK4113_FS2|AK4113_FS1) + +/* AK4113_REG_RCS2 */ +/* CRC for Q-subcode, 0 = no error, 1 = error */ +#define AK4113_QCRC (1<<1) +/* CRC for channel status, 0 = no error, 1 = error */ +#define AK4113_CCRC (1<<0) + +/* flags for snd_ak4113_check_rate_and_errors() */ +#define AK4113_CHECK_NO_STAT (1<<0) /* no statistics */ +#define AK4113_CHECK_NO_RATE (1<<1) /* no rate check */ + +#define AK4113_CONTROLS 13 + +typedef void (ak4113_write_t)(void *private_data, unsigned char addr, + unsigned char data); +typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr); + +enum { + AK4113_PARITY_ERRORS, + AK4113_V_BIT_ERRORS, + AK4113_QCRC_ERRORS, + AK4113_CCRC_ERRORS, + AK4113_NUM_ERRORS +}; + +struct ak4113 { + struct snd_card *card; + ak4113_write_t *write; + ak4113_read_t *read; + void *private_data; + atomic_t wq_processing; + struct mutex reinit_mutex; + spinlock_t lock; + unsigned char regmap[AK4113_WRITABLE_REGS]; + struct snd_kcontrol *kctls[AK4113_CONTROLS]; + struct snd_pcm_substream *substream; + unsigned long errors[AK4113_NUM_ERRORS]; + unsigned char rcs0; + unsigned char rcs1; + unsigned char rcs2; + struct delayed_work work; + unsigned int check_flags; + void *change_callback_private; + void (*change_callback)(struct ak4113 *ak4113, unsigned char c0, + unsigned char c1); +}; + +int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read, + ak4113_write_t *write, + const unsigned char *pgm, + void *private_data, struct ak4113 **r_ak4113); +void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg, + unsigned char mask, unsigned char val); +void snd_ak4113_reinit(struct ak4113 *ak4113); +int snd_ak4113_build(struct ak4113 *ak4113, + struct snd_pcm_substream *capture_substream); +int snd_ak4113_external_rate(struct ak4113 *ak4113); +int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags); + +#ifdef CONFIG_PM +void snd_ak4113_suspend(struct ak4113 *chip); +void snd_ak4113_resume(struct ak4113 *chip); +#else +static inline void snd_ak4113_suspend(struct ak4113 *chip) {} +static inline void snd_ak4113_resume(struct ak4113 *chip) {} +#endif + +#endif /* __SOUND_AK4113_H */ + diff --git a/include/sound/ak4114.h b/include/sound/ak4114.h new file mode 100644 index 000000000..c478a806f --- /dev/null +++ b/include/sound/ak4114.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4114_H +#define __SOUND_AK4114_H + +/* + * Routines for Asahi Kasei AK4114 + * Copyright (c) by Jaroslav Kysela , + */ + +/* AK4114 registers */ +#define AK4114_REG_PWRDN 0x00 /* power down */ +#define AK4114_REG_FORMAT 0x01 /* format control */ +#define AK4114_REG_IO0 0x02 /* input/output control */ +#define AK4114_REG_IO1 0x03 /* input/output control */ +#define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */ +#define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */ +#define AK4114_REG_RCS0 0x06 /* receiver status 0 */ +#define AK4114_REG_RCS1 0x07 /* receiver status 1 */ +#define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */ +#define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */ +#define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */ +#define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */ +#define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */ +#define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */ +#define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */ +#define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */ +#define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */ +#define AK4114_REG_TXCSB4 0x11 /* TX channel status byte 4 */ +#define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */ +#define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */ +#define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */ +#define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */ +#define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */ +#define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */ +#define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */ +#define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */ +#define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */ +#define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */ +#define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */ +#define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */ +#define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */ +#define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */ + +/* sizes */ +#define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1) +#define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1) +#define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1) + +/* AK4117_REG_PWRDN bits */ +#define AK4114_CS12 (1<<7) /* Channel Status Select */ +#define AK4114_BCU (1<<6) /* Block Start & C/U Output Mode */ +#define AK4114_CM1 (1<<5) /* Master Clock Operation Select */ +#define AK4114_CM0 (1<<4) /* Master Clock Operation Select */ +#define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */ +#define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */ +#define AK4114_PWN (1<<1) /* 0 = power down, 1 = normal operation */ +#define AK4114_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */ + +/* AK4114_REQ_FORMAT bits */ +#define AK4114_MONO (1<<7) /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */ +#define AK4114_DIF2 (1<<6) /* Audio Data Control */ +#define AK4114_DIF1 (1<<5) /* Audio Data Control */ +#define AK4114_DIF0 (1<<4) /* Audio Data Control */ +#define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */ +#define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */ +#define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */ +#define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */ +#define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */ +#define AK4114_DIF_24I2S (AK4114_DIF2|AK4114_DIF0) /* STDO: I2S */ +#define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ +#define AK4114_DIF_I24I2S (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S; LRCLK, BICK = Input */ +#define AK4114_DEAU (1<<3) /* Deemphasis Autodetect Enable (1 = enable) */ +#define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */ +#define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */ +#define AK4114_DEM_44KHZ (0) +#define AK4114_DEM_48KHZ (AK4114_DEM1) +#define AK4114_DEM_32KHZ (AK4114_DEM0|AK4114_DEM1) +#define AK4114_DEM_96KHZ (AK4114_DEM1) /* DFS must be set */ +#define AK4114_DFS (1<<0) /* 96kHz Deemphasis Control */ + +/* AK4114_REG_IO0 */ +#define AK4114_TX1E (1<<7) /* TX1 Output Enable (1 = enable) */ +#define AK4114_OPS12 (1<<6) /* Output Data Selector for TX1 pin */ +#define AK4114_OPS11 (1<<5) /* Output Data Selector for TX1 pin */ +#define AK4114_OPS10 (1<<4) /* Output Data Selector for TX1 pin */ +#define AK4114_TX0E (1<<3) /* TX0 Output Enable (1 = enable) */ +#define AK4114_OPS02 (1<<2) /* Output Data Selector for TX0 pin */ +#define AK4114_OPS01 (1<<1) /* Output Data Selector for TX0 pin */ +#define AK4114_OPS00 (1<<0) /* Output Data Selector for TX0 pin */ + +/* AK4114_REG_IO1 */ +#define AK4114_EFH1 (1<<7) /* Interrupt 0 pin Hold */ +#define AK4114_EFH0 (1<<6) /* Interrupt 0 pin Hold */ +#define AK4114_EFH_512 (0) +#define AK4114_EFH_1024 (AK4114_EFH0) +#define AK4114_EFH_2048 (AK4114_EFH1) +#define AK4114_EFH_4096 (AK4114_EFH1|AK4114_EFH0) +#define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */ +#define AK4114_TLR (1<<4) /* Double Sampling Frequency Select for DIT (0 = L channel, 1 = R channel) */ +#define AK4114_DIT (1<<3) /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */ +#define AK4114_IPS2 (1<<2) /* Input Recovery Data Select */ +#define AK4114_IPS1 (1<<1) /* Input Recovery Data Select */ +#define AK4114_IPS0 (1<<0) /* Input Recovery Data Select */ +#define AK4114_IPS(x) ((x)&7) + +/* AK4114_REG_INT0_MASK && AK4114_REG_INT1_MASK*/ +#define AK4117_MQI (1<<7) /* mask enable for QINT bit */ +#define AK4117_MAT (1<<6) /* mask enable for AUTO bit */ +#define AK4117_MCI (1<<5) /* mask enable for CINT bit */ +#define AK4117_MUL (1<<4) /* mask enable for UNLOCK bit */ +#define AK4117_MDTS (1<<3) /* mask enable for DTSCD bit */ +#define AK4117_MPE (1<<2) /* mask enable for PEM bit */ +#define AK4117_MAN (1<<1) /* mask enable for AUDN bit */ +#define AK4117_MPR (1<<0) /* mask enable for PAR bit */ + +/* AK4114_REG_RCS0 */ +#define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ +#define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ +#define AK4114_CINT (1<<5) /* channel status buffer interrupt, 0 = no change, 1 = change */ +#define AK4114_UNLCK (1<<4) /* PLL lock status, 0 = lock, 1 = unlock */ +#define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */ +#define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */ +#define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */ +#define AK4114_PAR (1<<0) /* parity error or biphase error status, 0 = no error, 1 = error */ + +/* AK4114_REG_RCS1 */ +#define AK4114_FS3 (1<<7) /* sampling frequency detection */ +#define AK4114_FS2 (1<<6) +#define AK4114_FS1 (1<<5) +#define AK4114_FS0 (1<<4) +#define AK4114_FS_44100HZ (0) +#define AK4114_FS_48000HZ (AK4114_FS1) +#define AK4114_FS_32000HZ (AK4114_FS1|AK4114_FS0) +#define AK4114_FS_88200HZ (AK4114_FS3) +#define AK4114_FS_96000HZ (AK4114_FS3|AK4114_FS1) +#define AK4114_FS_176400HZ (AK4114_FS3|AK4114_FS2) +#define AK4114_FS_192000HZ (AK4114_FS3|AK4114_FS2|AK4114_FS1) +#define AK4114_V (1<<3) /* Validity of Channel Status, 0 = Valid, 1 = Invalid */ +#define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */ +#define AK4114_CCRC (1<<0) /* CRC for channel status, 0 = no error, 1 = error */ + +/* flags for snd_ak4114_check_rate_and_errors() */ +#define AK4114_CHECK_NO_STAT (1<<0) /* no statistics */ +#define AK4114_CHECK_NO_RATE (1<<1) /* no rate check */ + +#define AK4114_CONTROLS 15 + +typedef void (ak4114_write_t)(void *private_data, unsigned char addr, unsigned char data); +typedef unsigned char (ak4114_read_t)(void *private_data, unsigned char addr); + +enum { + AK4114_PARITY_ERRORS, + AK4114_V_BIT_ERRORS, + AK4114_QCRC_ERRORS, + AK4114_CCRC_ERRORS, + AK4114_NUM_ERRORS +}; + +struct ak4114 { + struct snd_card *card; + ak4114_write_t * write; + ak4114_read_t * read; + void * private_data; + atomic_t wq_processing; + struct mutex reinit_mutex; + spinlock_t lock; + unsigned char regmap[6]; + unsigned char txcsb[5]; + struct snd_kcontrol *kctls[AK4114_CONTROLS]; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + unsigned long errors[AK4114_NUM_ERRORS]; + unsigned char rcs0; + unsigned char rcs1; + struct delayed_work work; + unsigned int check_flags; + void *change_callback_private; + void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1); +}; + +int snd_ak4114_create(struct snd_card *card, + ak4114_read_t *read, ak4114_write_t *write, + const unsigned char pgm[6], const unsigned char txcsb[5], + void *private_data, struct ak4114 **r_ak4114); +void snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val); +void snd_ak4114_reinit(struct ak4114 *ak4114); +int snd_ak4114_build(struct ak4114 *ak4114, + struct snd_pcm_substream *playback_substream, + struct snd_pcm_substream *capture_substream); +int snd_ak4114_external_rate(struct ak4114 *ak4114); +int snd_ak4114_check_rate_and_errors(struct ak4114 *ak4114, unsigned int flags); + +#ifdef CONFIG_PM +void snd_ak4114_suspend(struct ak4114 *chip); +void snd_ak4114_resume(struct ak4114 *chip); +#else +static inline void snd_ak4114_suspend(struct ak4114 *chip) {} +static inline void snd_ak4114_resume(struct ak4114 *chip) {} +#endif + +#endif /* __SOUND_AK4114_H */ + diff --git a/include/sound/ak4117.h b/include/sound/ak4117.h new file mode 100644 index 000000000..3f6bf74d9 --- /dev/null +++ b/include/sound/ak4117.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4117_H +#define __SOUND_AK4117_H + +/* + * Routines for Asahi Kasei AK4117 + * Copyright (c) by Jaroslav Kysela , + */ + +#define AK4117_REG_PWRDN 0x00 /* power down */ +#define AK4117_REG_CLOCK 0x01 /* clock control */ +#define AK4117_REG_IO 0x02 /* input/output control */ +#define AK4117_REG_INT0_MASK 0x03 /* interrupt0 mask */ +#define AK4117_REG_INT1_MASK 0x04 /* interrupt1 mask */ +#define AK4117_REG_RCS0 0x05 /* receiver status 0 */ +#define AK4117_REG_RCS1 0x06 /* receiver status 1 */ +#define AK4117_REG_RCS2 0x07 /* receiver status 2 */ +#define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */ +#define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */ +#define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */ +#define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */ +#define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */ +#define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */ +#define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */ +#define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */ +#define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */ +#define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */ +#define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */ +#define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */ +#define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */ +#define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */ +#define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */ +#define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */ +#define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */ +#define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */ +#define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */ + +/* sizes */ +#define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1) +#define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1) + +/* AK4117_REG_PWRDN bits */ +#define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */ +#define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ +#define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ +#define AK4117_XTL_11_2896M (0) +#define AK4117_XTL_12_288M AK4117_XTL0 +#define AK4117_XTL_24_576M AK4117_XTL1 +#define AK4117_XTL_EXT (AK4117_XTL1|AK4117_XTL0) +#define AK4117_PWN (1<<1) /* 0 = power down, 1 = normal operation */ +#define AK4117_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */ + +/* AK4117_REQ_CLOCK bits */ +#define AK4117_LP (1<<7) /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */ +#define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */ +#define AK4117_PKCS0 (1<<5) +#define AK4117_PKCS_512fs (0) +#define AK4117_PKCS_256fs AK4117_PKCS0 +#define AK4117_PKCS_128fs AK4117_PKCS1 +#define AK4117_DIV (1<<4) /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */ +#define AK4117_XCKS1 (1<<3) /* master clock frequency at X'tal mode */ +#define AK4117_XCKS0 (1<<2) +#define AK4117_XCKS_128fs (0) +#define AK4117_XCKS_256fs AK4117_XCKS0 +#define AK4117_XCKS_512fs AK4117_XCKS1 +#define AK4117_XCKS_1024fs (AK4117_XCKS1|AK4117_XCKS0) +#define AK4117_CM1 (1<<1) /* MCKO operation mode select */ +#define AK4117_CM0 (1<<0) +#define AK4117_CM_PLL (0) /* use RX input as master clock */ +#define AK4117_CM_XTAL (AK4117_CM0) /* use X'tal as master clock */ +#define AK4117_CM_PLL_XTAL (AK4117_CM1) /* use Rx input but X'tal when PLL loses lock */ +#define AK4117_CM_MONITOR (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */ + +/* AK4117_REG_IO */ +#define AK4117_IPS (1<<7) /* Input Recovery Data Select, 0 = RX0, 1 = RX1 */ +#define AK4117_UOUTE (1<<6) /* U-bit output enable to UOUT, 0 = disable, 1 = enable */ +#define AK4117_CS12 (1<<5) /* channel status select, 0 = channel1, 1 = channel2 */ +#define AK4117_EFH2 (1<<4) /* INT0 pin hold count select */ +#define AK4117_EFH1 (1<<3) +#define AK4117_EFH_512LRCLK (0) +#define AK4117_EFH_1024LRCLK (AK4117_EFH1) +#define AK4117_EFH_2048LRCLK (AK4117_EFH2) +#define AK4117_EFH_4096LRCLK (AK4117_EFH1|AK4117_EFH2) +#define AK4117_DIF2 (1<<2) /* audio data format control */ +#define AK4117_DIF1 (1<<1) +#define AK4117_DIF0 (1<<0) +#define AK4117_DIF_16R (0) /* STDO: 16-bit, right justified */ +#define AK4117_DIF_18R (AK4117_DIF0) /* STDO: 18-bit, right justified */ +#define AK4117_DIF_20R (AK4117_DIF1) /* STDO: 20-bit, right justified */ +#define AK4117_DIF_24R (AK4117_DIF1|AK4117_DIF0) /* STDO: 24-bit, right justified */ +#define AK4117_DIF_24L (AK4117_DIF2) /* STDO: 24-bit, left justified */ +#define AK4117_DIF_24I2S (AK4117_DIF2|AK4117_DIF0) /* STDO: I2S */ + +/* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */ +#define AK4117_MULK (1<<7) /* mask enable for UNLOCK bit */ +#define AK4117_MPAR (1<<6) /* mask enable for PAR bit */ +#define AK4117_MAUTO (1<<5) /* mask enable for AUTO bit */ +#define AK4117_MV (1<<4) /* mask enable for V bit */ +#define AK4117_MAUD (1<<3) /* mask enable for AUDION bit */ +#define AK4117_MSTC (1<<2) /* mask enable for STC bit */ +#define AK4117_MCIT (1<<1) /* mask enable for CINT bit */ +#define AK4117_MQIT (1<<0) /* mask enable for QINT bit */ + +/* AK4117_REG_RCS0 */ +#define AK4117_UNLCK (1<<7) /* PLL lock status, 0 = lock, 1 = unlock */ +#define AK4117_PAR (1<<6) /* parity error or biphase error status, 0 = no error, 1 = error */ +#define AK4117_AUTO (1<<5) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ +#define AK4117_V (1<<4) /* Validity bit, 0 = valid, 1 = invalid */ +#define AK4117_AUDION (1<<3) /* audio bit output, 0 = audio, 1 = non-audio */ +#define AK4117_STC (1<<2) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ +#define AK4117_CINT (1<<1) /* channel status buffer interrupt, 0 = no change, 1 = change */ +#define AK4117_QINT (1<<0) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ + +/* AK4117_REG_RCS1 */ +#define AK4117_DTSCD (1<<6) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ +#define AK4117_NPCM (1<<5) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ +#define AK4117_PEM (1<<4) /* Pre-emphasis detect, 0 = OFF, 1 = ON */ +#define AK4117_FS3 (1<<3) /* sampling frequency detection */ +#define AK4117_FS2 (1<<2) +#define AK4117_FS1 (1<<1) +#define AK4117_FS0 (1<<0) +#define AK4117_FS_44100HZ (0) +#define AK4117_FS_48000HZ (AK4117_FS1) +#define AK4117_FS_32000HZ (AK4117_FS1|AK4117_FS0) +#define AK4117_FS_88200HZ (AK4117_FS3) +#define AK4117_FS_96000HZ (AK4117_FS3|AK4117_FS1) +#define AK4117_FS_176400HZ (AK4117_FS3|AK4117_FS2) +#define AK4117_FS_192000HZ (AK4117_FS3|AK4117_FS2|AK4117_FS1) + +/* AK4117_REG_RCS2 */ +#define AK4117_CCRC (1<<1) /* CRC for channel status, 0 = no error, 1 = error */ +#define AK4117_QCRC (1<<0) /* CRC for Q-subcode, 0 = no error, 1 = error */ + +/* flags for snd_ak4117_check_rate_and_errors() */ +#define AK4117_CHECK_NO_STAT (1<<0) /* no statistics */ +#define AK4117_CHECK_NO_RATE (1<<1) /* no rate check */ + +#define AK4117_CONTROLS 13 + +typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data); +typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr); + +enum { + AK4117_PARITY_ERRORS, + AK4117_V_BIT_ERRORS, + AK4117_QCRC_ERRORS, + AK4117_CCRC_ERRORS, + AK4117_NUM_ERRORS +}; + +struct ak4117 { + struct snd_card *card; + ak4117_write_t * write; + ak4117_read_t * read; + void * private_data; + unsigned int init: 1; + spinlock_t lock; + unsigned char regmap[5]; + struct snd_kcontrol *kctls[AK4117_CONTROLS]; + struct snd_pcm_substream *substream; + unsigned long errors[AK4117_NUM_ERRORS]; + unsigned char rcs0; + unsigned char rcs1; + unsigned char rcs2; + struct timer_list timer; /* statistic timer */ + void *change_callback_private; + void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1); +}; + +int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write, + const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117); +void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val); +void snd_ak4117_reinit(struct ak4117 *ak4117); +int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream); +int snd_ak4117_external_rate(struct ak4117 *ak4117); +int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags); + +#endif /* __SOUND_AK4117_H */ + diff --git a/include/sound/ak4531_codec.h b/include/sound/ak4531_codec.h new file mode 100644 index 000000000..64402347d --- /dev/null +++ b/include/sound/ak4531_codec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4531_CODEC_H +#define __SOUND_AK4531_CODEC_H + +/* + * Copyright (c) by Jaroslav Kysela + * Universal interface for Audio Codec '97 + * + * For more details look to AC '97 component specification revision 2.1 + * by Intel Corporation (http://developer.intel.com). + */ + +#include +#include + +/* + * ASAHI KASEI - AK4531 codec + * - not really AC'97 codec, but it uses very similar interface as AC'97 + */ + +/* + * AK4531 codec registers + */ + +#define AK4531_LMASTER 0x00 /* master volume left */ +#define AK4531_RMASTER 0x01 /* master volume right */ +#define AK4531_LVOICE 0x02 /* channel volume left */ +#define AK4531_RVOICE 0x03 /* channel volume right */ +#define AK4531_LFM 0x04 /* FM volume left */ +#define AK4531_RFM 0x05 /* FM volume right */ +#define AK4531_LCD 0x06 /* CD volume left */ +#define AK4531_RCD 0x07 /* CD volume right */ +#define AK4531_LLINE 0x08 /* LINE volume left */ +#define AK4531_RLINE 0x09 /* LINE volume right */ +#define AK4531_LAUXA 0x0a /* AUXA volume left */ +#define AK4531_RAUXA 0x0b /* AUXA volume right */ +#define AK4531_MONO1 0x0c /* MONO1 volume left */ +#define AK4531_MONO2 0x0d /* MONO1 volume right */ +#define AK4531_MIC 0x0e /* MIC volume */ +#define AK4531_MONO_OUT 0x0f /* Mono-out volume */ +#define AK4531_OUT_SW1 0x10 /* Output mixer switch 1 */ +#define AK4531_OUT_SW2 0x11 /* Output mixer switch 2 */ +#define AK4531_LIN_SW1 0x12 /* Input left mixer switch 1 */ +#define AK4531_RIN_SW1 0x13 /* Input right mixer switch 1 */ +#define AK4531_LIN_SW2 0x14 /* Input left mixer switch 2 */ +#define AK4531_RIN_SW2 0x15 /* Input right mixer switch 2 */ +#define AK4531_RESET 0x16 /* Reset & power down */ +#define AK4531_CLOCK 0x17 /* Clock select */ +#define AK4531_AD_IN 0x18 /* AD input select */ +#define AK4531_MIC_GAIN 0x19 /* MIC amplified gain */ + +struct snd_ak4531 { + void (*write) (struct snd_ak4531 *ak4531, unsigned short reg, + unsigned short val); + void *private_data; + void (*private_free) (struct snd_ak4531 *ak4531); + /* --- */ + unsigned char regs[0x20]; + struct mutex reg_mutex; +}; + +int snd_ak4531_mixer(struct snd_card *card, struct snd_ak4531 *_ak4531, + struct snd_ak4531 **rak4531); + +#ifdef CONFIG_PM +void snd_ak4531_suspend(struct snd_ak4531 *ak4531); +void snd_ak4531_resume(struct snd_ak4531 *ak4531); +#else +static inline void snd_ak4531_suspend(struct snd_ak4531 *ak4531) {} +static inline void snd_ak4531_resume(struct snd_ak4531 *ak4531) {} +#endif + +#endif /* __SOUND_AK4531_CODEC_H */ diff --git a/include/sound/ak4xxx-adda.h b/include/sound/ak4xxx-adda.h new file mode 100644 index 000000000..4f574cefe --- /dev/null +++ b/include/sound/ak4xxx-adda.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4XXX_ADDA_H +#define __SOUND_AK4XXX_ADDA_H + +/* + * ALSA driver for AK4524 / AK4528 / AK4529 / AK4355 / AK4381 + * AD and DA converters + * + * Copyright (c) 2000 Jaroslav Kysela + */ + +#ifndef AK4XXX_MAX_CHIPS +#define AK4XXX_MAX_CHIPS 4 +#endif + +struct snd_akm4xxx; + +struct snd_ak4xxx_ops { + void (*lock)(struct snd_akm4xxx *ak, int chip); + void (*unlock)(struct snd_akm4xxx *ak, int chip); + void (*write)(struct snd_akm4xxx *ak, int chip, unsigned char reg, + unsigned char val); + void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate); +}; + +#define AK4XXX_IMAGE_SIZE (AK4XXX_MAX_CHIPS * 16) /* 64 bytes */ + +/* DAC label and channels */ +struct snd_akm4xxx_dac_channel { + char *name; /* mixer volume name */ + unsigned int num_channels; + char *switch_name; /* mixer switch*/ +}; + +/* ADC labels and channels */ +struct snd_akm4xxx_adc_channel { + char *name; /* capture gain volume label */ + char *switch_name; /* capture switch */ + unsigned int num_channels; + char *selector_name; /* capture source select label */ + const char **input_names; /* capture source names (NULL terminated) */ +}; + +struct snd_akm4xxx { + struct snd_card *card; + unsigned int num_adcs; /* AK4524 or AK4528 ADCs */ + unsigned int num_dacs; /* AK4524 or AK4528 DACs */ + unsigned char images[AK4XXX_IMAGE_SIZE]; /* saved register image */ + unsigned char volumes[AK4XXX_IMAGE_SIZE]; /* saved volume values */ + unsigned long private_value[AK4XXX_MAX_CHIPS]; /* helper for driver */ + void *private_data[AK4XXX_MAX_CHIPS]; /* helper for driver */ + /* template should fill the following fields */ + unsigned int idx_offset; /* control index offset */ + enum { + SND_AK4524, SND_AK4528, SND_AK4529, + SND_AK4355, SND_AK4358, SND_AK4381, + SND_AK5365, SND_AK4620, + } type; + + /* (array) information of combined codecs */ + const struct snd_akm4xxx_dac_channel *dac_info; + const struct snd_akm4xxx_adc_channel *adc_info; + + struct snd_ak4xxx_ops ops; + unsigned int num_chips; + unsigned int total_regs; + const char *name; +}; + +void snd_akm4xxx_write(struct snd_akm4xxx *ak, int chip, unsigned char reg, + unsigned char val); +void snd_akm4xxx_reset(struct snd_akm4xxx *ak, int state); +void snd_akm4xxx_init(struct snd_akm4xxx *ak); +int snd_akm4xxx_build_controls(struct snd_akm4xxx *ak); + +#define snd_akm4xxx_get(ak,chip,reg) \ + (ak)->images[(chip) * 16 + (reg)] +#define snd_akm4xxx_set(ak,chip,reg,val) \ + ((ak)->images[(chip) * 16 + (reg)] = (val)) +#define snd_akm4xxx_get_vol(ak,chip,reg) \ + (ak)->volumes[(chip) * 16 + (reg)] +#define snd_akm4xxx_set_vol(ak,chip,reg,val) \ + ((ak)->volumes[(chip) * 16 + (reg)] = (val)) + +#endif /* __SOUND_AK4XXX_ADDA_H */ diff --git a/include/sound/alc5623.h b/include/sound/alc5623.h new file mode 100644 index 000000000..0ebb0f6fc --- /dev/null +++ b/include/sound/alc5623.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _INCLUDE_SOUND_ALC5623_H +#define _INCLUDE_SOUND_ALC5623_H +struct alc5623_platform_data { + /* configure : */ + /* Lineout/Speaker Amps Vmid ratio control */ + /* enable/disable adc/dac high pass filters */ + unsigned int add_ctrl; + /* configure : */ + /* output to enable when jack is low */ + /* output to enable when jack is high */ + /* jack detect (gpio/nc/jack detect [12] */ + unsigned int jack_det_ctrl; +}; +#endif + diff --git a/include/sound/asequencer.h b/include/sound/asequencer.h new file mode 100644 index 000000000..efad36673 --- /dev/null +++ b/include/sound/asequencer.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Main header file for the ALSA sequencer + * Copyright (c) 1998-1999 by Frank van de Pol + * (c) 1998-1999 by Jaroslav Kysela + */ +#ifndef __SOUND_ASEQUENCER_H +#define __SOUND_ASEQUENCER_H + +#include +#include +#include + +/* + * type check macros + */ +/* result events: 0-4 */ +#define snd_seq_ev_is_result_type(ev) ((ev)->type < 5) +/* channel specific events: 5-19 */ +#define snd_seq_ev_is_channel_type(ev) ((ev)->type >= 5 && (ev)->type < 20) +/* note events: 5-9 */ +#define snd_seq_ev_is_note_type(ev) ((ev)->type >= 5 && (ev)->type < 10) +/* control events: 10-19 */ +#define snd_seq_ev_is_control_type(ev) ((ev)->type >= 10 && (ev)->type < 20) +/* queue control events: 30-39 */ +#define snd_seq_ev_is_queue_type(ev) ((ev)->type >= 30 && (ev)->type < 40) +/* system status messages */ +#define snd_seq_ev_is_message_type(ev) ((ev)->type >= 60 && (ev)->type < 69) +/* sample messages */ +#define snd_seq_ev_is_sample_type(ev) ((ev)->type >= 70 && (ev)->type < 79) +/* user-defined messages */ +#define snd_seq_ev_is_user_type(ev) ((ev)->type >= 90 && (ev)->type < 99) +/* fixed length events: 0-99 */ +#define snd_seq_ev_is_fixed_type(ev) ((ev)->type < 100) +/* variable length events: 130-139 */ +#define snd_seq_ev_is_variable_type(ev) ((ev)->type >= 130 && (ev)->type < 140) +/* reserved for kernel */ +#define snd_seq_ev_is_reserved(ev) ((ev)->type >= 150) + +/* direct dispatched events */ +#define snd_seq_ev_is_direct(ev) ((ev)->queue == SNDRV_SEQ_QUEUE_DIRECT) + +/* + * macros to check event flags + */ +/* prior events */ +#define snd_seq_ev_is_prior(ev) (((ev)->flags & SNDRV_SEQ_PRIORITY_MASK) == SNDRV_SEQ_PRIORITY_HIGH) + +/* event length type */ +#define snd_seq_ev_length_type(ev) ((ev)->flags & SNDRV_SEQ_EVENT_LENGTH_MASK) +#define snd_seq_ev_is_fixed(ev) (snd_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_FIXED) +#define snd_seq_ev_is_variable(ev) (snd_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_VARIABLE) +#define snd_seq_ev_is_varusr(ev) (snd_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_VARUSR) + +/* time-stamp type */ +#define snd_seq_ev_timestamp_type(ev) ((ev)->flags & SNDRV_SEQ_TIME_STAMP_MASK) +#define snd_seq_ev_is_tick(ev) (snd_seq_ev_timestamp_type(ev) == SNDRV_SEQ_TIME_STAMP_TICK) +#define snd_seq_ev_is_real(ev) (snd_seq_ev_timestamp_type(ev) == SNDRV_SEQ_TIME_STAMP_REAL) + +/* time-mode type */ +#define snd_seq_ev_timemode_type(ev) ((ev)->flags & SNDRV_SEQ_TIME_MODE_MASK) +#define snd_seq_ev_is_abstime(ev) (snd_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_ABS) +#define snd_seq_ev_is_reltime(ev) (snd_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_REL) + +/* check whether the given event is a UMP event */ +#define snd_seq_ev_is_ump(ev) \ + (IS_ENABLED(CONFIG_SND_SEQ_UMP) && ((ev)->flags & SNDRV_SEQ_EVENT_UMP)) + +/* queue sync port */ +#define snd_seq_queue_sync_port(q) ((q) + 16) + +#endif /* __SOUND_ASEQUENCER_H */ diff --git a/include/sound/asound.h b/include/sound/asound.h new file mode 100644 index 000000000..3fc5b216c --- /dev/null +++ b/include/sound/asound.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 1994-2003 by Jaroslav Kysela , + * Abramo Bagnara + */ +#ifndef __SOUND_ASOUND_H +#define __SOUND_ASOUND_H + +#include +#include +#include + +#ifdef __LITTLE_ENDIAN +#define SNDRV_LITTLE_ENDIAN +#else +#ifdef __BIG_ENDIAN +#define SNDRV_BIG_ENDIAN +#else +#error "Unsupported endian..." +#endif +#endif + +#include +#endif /* __SOUND_ASOUND_H */ diff --git a/include/sound/asoundef.h b/include/sound/asoundef.h new file mode 100644 index 000000000..c4a929d4f --- /dev/null +++ b/include/sound/asoundef.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_ASOUNDEF_H +#define __SOUND_ASOUNDEF_H + +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 1994-2000 by Jaroslav Kysela + */ + +/**************************************************************************** + * * + * Digital audio interface * + * * + ****************************************************************************/ +/* IEC958 subframe format */ +#define IEC958_SUBFRAME_PREAMBLE_MASK (0xfU) +#define IEC958_SUBFRAME_AUXILIARY_MASK (0xfU << 4) +#define IEC958_SUBFRAME_SAMPLE_24_MASK (0xffffffU << 4) +#define IEC958_SUBFRAME_SAMPLE_20_MASK (0xfffffU << 8) +#define IEC958_SUBFRAME_VALIDITY (0x1U << 28) +#define IEC958_SUBFRAME_USER_DATA (0x1U << 29) +#define IEC958_SUBFRAME_CHANNEL_STATUS (0x1U << 30) +#define IEC958_SUBFRAME_PARITY (0x1U << 31) + +/* AES/IEC958 channel status bits */ +#define IEC958_AES0_PROFESSIONAL (1<<0) /* 0 = consumer, 1 = professional */ +#define IEC958_AES0_NONAUDIO (1<<1) /* 0 = audio, 1 = non-audio */ +#define IEC958_AES0_PRO_EMPHASIS (7<<2) /* mask - emphasis */ +#define IEC958_AES0_PRO_EMPHASIS_NOTID (0<<2) /* emphasis not indicated */ +#define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */ +#define IEC958_AES0_PRO_EMPHASIS_5015 (3<<2) /* 50/15us emphasis */ +#define IEC958_AES0_PRO_EMPHASIS_CCITT (7<<2) /* CCITT J.17 emphasis */ +#define IEC958_AES0_PRO_FREQ_UNLOCKED (1<<5) /* source sample frequency: 0 = locked, 1 = unlocked */ +#define IEC958_AES0_PRO_FS (3<<6) /* mask - sample frequency */ +#define IEC958_AES0_PRO_FS_NOTID (0<<6) /* fs not indicated */ +#define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */ +#define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */ +#define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */ +#define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */ +#define IEC958_AES0_CON_EMPHASIS (7<<3) /* mask - emphasis */ +#define IEC958_AES0_CON_EMPHASIS_NONE (0<<3) /* none emphasis */ +#define IEC958_AES0_CON_EMPHASIS_5015 (1<<3) /* 50/15us emphasis */ +#define IEC958_AES0_CON_MODE (3<<6) /* mask - mode */ +#define IEC958_AES1_PRO_MODE (15<<0) /* mask - channel mode */ +#define IEC958_AES1_PRO_MODE_NOTID (0<<0) /* not indicated */ +#define IEC958_AES1_PRO_MODE_STEREOPHONIC (2<<0) /* stereophonic - ch A is left */ +#define IEC958_AES1_PRO_MODE_SINGLE (4<<0) /* single channel */ +#define IEC958_AES1_PRO_MODE_TWO (8<<0) /* two channels */ +#define IEC958_AES1_PRO_MODE_PRIMARY (12<<0) /* primary/secondary */ +#define IEC958_AES1_PRO_MODE_BYTE3 (15<<0) /* vector to byte 3 */ +#define IEC958_AES1_PRO_USERBITS (15<<4) /* mask - user bits */ +#define IEC958_AES1_PRO_USERBITS_NOTID (0<<4) /* not indicated */ +#define IEC958_AES1_PRO_USERBITS_192 (8<<4) /* 192-bit structure */ +#define IEC958_AES1_PRO_USERBITS_UDEF (12<<4) /* user defined application */ +#define IEC958_AES1_CON_CATEGORY 0x7f +#define IEC958_AES1_CON_GENERAL 0x00 +#define IEC958_AES1_CON_LASEROPT_MASK 0x07 +#define IEC958_AES1_CON_LASEROPT_ID 0x01 +#define IEC958_AES1_CON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x00) +#define IEC958_AES1_CON_NON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x08) +#define IEC958_AES1_CON_MINI_DISC (IEC958_AES1_CON_LASEROPT_ID|0x48) +#define IEC958_AES1_CON_DVD (IEC958_AES1_CON_LASEROPT_ID|0x18) +#define IEC958_AES1_CON_LASTEROPT_OTHER (IEC958_AES1_CON_LASEROPT_ID|0x78) +#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07 +#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02 +#define IEC958_AES1_CON_PCM_CODER (IEC958_AES1_CON_DIGDIGCONV_ID|0x00) +#define IEC958_AES1_CON_MIXER (IEC958_AES1_CON_DIGDIGCONV_ID|0x10) +#define IEC958_AES1_CON_RATE_CONVERTER (IEC958_AES1_CON_DIGDIGCONV_ID|0x18) +#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20) +#define IEC958_AES1_CON_DSP (IEC958_AES1_CON_DIGDIGCONV_ID|0x28) +#define IEC958_AES1_CON_DIGDIGCONV_OTHER (IEC958_AES1_CON_DIGDIGCONV_ID|0x78) +#define IEC958_AES1_CON_MAGNETIC_MASK 0x07 +#define IEC958_AES1_CON_MAGNETIC_ID 0x03 +#define IEC958_AES1_CON_DAT (IEC958_AES1_CON_MAGNETIC_ID|0x00) +#define IEC958_AES1_CON_VCR (IEC958_AES1_CON_MAGNETIC_ID|0x08) +#define IEC958_AES1_CON_DCC (IEC958_AES1_CON_MAGNETIC_ID|0x40) +#define IEC958_AES1_CON_MAGNETIC_DISC (IEC958_AES1_CON_MAGNETIC_ID|0x18) +#define IEC958_AES1_CON_MAGNETIC_OTHER (IEC958_AES1_CON_MAGNETIC_ID|0x78) +#define IEC958_AES1_CON_BROADCAST1_MASK 0x07 +#define IEC958_AES1_CON_BROADCAST1_ID 0x04 +#define IEC958_AES1_CON_DAB_JAPAN (IEC958_AES1_CON_BROADCAST1_ID|0x00) +#define IEC958_AES1_CON_DAB_EUROPE (IEC958_AES1_CON_BROADCAST1_ID|0x08) +#define IEC958_AES1_CON_DAB_USA (IEC958_AES1_CON_BROADCAST1_ID|0x60) +#define IEC958_AES1_CON_SOFTWARE (IEC958_AES1_CON_BROADCAST1_ID|0x40) +#define IEC958_AES1_CON_IEC62105 (IEC958_AES1_CON_BROADCAST1_ID|0x20) +#define IEC958_AES1_CON_BROADCAST1_OTHER (IEC958_AES1_CON_BROADCAST1_ID|0x78) +#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f +#define IEC958_AES1_CON_BROADCAST2_ID 0x0e +#define IEC958_AES1_CON_MUSICAL_MASK 0x07 +#define IEC958_AES1_CON_MUSICAL_ID 0x05 +#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00) +#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08) +#define IEC958_AES1_CON_MUSICAL_OTHER (IEC958_AES1_CON_MUSICAL_ID|0x78) +#define IEC958_AES1_CON_ADC_MASK 0x1f +#define IEC958_AES1_CON_ADC_ID 0x06 +#define IEC958_AES1_CON_ADC (IEC958_AES1_CON_ADC_ID|0x00) +#define IEC958_AES1_CON_ADC_OTHER (IEC958_AES1_CON_ADC_ID|0x60) +#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f +#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x16 +#define IEC958_AES1_CON_ADC_COPYRIGHT (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x00) +#define IEC958_AES1_CON_ADC_COPYRIGHT_OTHER (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x60) +#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f +#define IEC958_AES1_CON_SOLIDMEM_ID 0x08 +#define IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER (IEC958_AES1_CON_SOLIDMEM_ID|0x00) +#define IEC958_AES1_CON_SOLIDMEM_OTHER (IEC958_AES1_CON_SOLIDMEM_ID|0x70) +#define IEC958_AES1_CON_EXPERIMENTAL 0x40 +#define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */ +#define IEC958_AES2_PRO_SBITS (7<<0) /* mask - sample bits */ +#define IEC958_AES2_PRO_SBITS_20 (2<<0) /* 20-bit - coordination */ +#define IEC958_AES2_PRO_SBITS_24 (4<<0) /* 24-bit - main audio */ +#define IEC958_AES2_PRO_SBITS_UDEF (6<<0) /* user defined application */ +#define IEC958_AES2_PRO_WORDLEN (7<<3) /* mask - source word length */ +#define IEC958_AES2_PRO_WORDLEN_NOTID (0<<3) /* not indicated */ +#define IEC958_AES2_PRO_WORDLEN_22_18 (2<<3) /* 22-bit or 18-bit */ +#define IEC958_AES2_PRO_WORDLEN_23_19 (4<<3) /* 23-bit or 19-bit */ +#define IEC958_AES2_PRO_WORDLEN_24_20 (5<<3) /* 24-bit or 20-bit */ +#define IEC958_AES2_PRO_WORDLEN_20_16 (6<<3) /* 20-bit or 16-bit */ +#define IEC958_AES2_CON_SOURCE (15<<0) /* mask - source number */ +#define IEC958_AES2_CON_SOURCE_UNSPEC (0<<0) /* unspecified */ +#define IEC958_AES2_CON_CHANNEL (15<<4) /* mask - channel number */ +#define IEC958_AES2_CON_CHANNEL_UNSPEC (0<<4) /* unspecified */ +#define IEC958_AES3_CON_FS ((1<<7) | (15<<0)) /* mask - sample frequency */ +#define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */ +#define IEC958_AES3_CON_FS_NOTID (1<<0) /* non indicated */ +#define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */ +#define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */ +#define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */ +#define IEC958_AES3_CON_FS_384000 (5<<0) /* 384kHz */ +#define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */ +#define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */ +#define IEC958_AES3_CON_FS_768000 (9<<0) /* 768kHz */ +#define IEC958_AES3_CON_FS_96000 (10<<0) /* 96kHz */ +#define IEC958_AES3_CON_FS_176400 (12<<0) /* 176.4kHz */ +#define IEC958_AES3_CON_FS_352400 (13<<0) /* 352.4kHz */ +#define IEC958_AES3_CON_FS_192000 (14<<0) /* 192kHz */ +#define IEC958_AES3_CON_FS_128000 ((1<<7) | (11<<0)) /* 128kHz */ +#define IEC958_AES3_CON_FS_705600 ((1<<7) | (13<<0)) /* 705.6kHz */ +#define IEC958_AES3_CON_CLOCK (3<<4) /* mask - clock accuracy */ +#define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /* 1000 ppm */ +#define IEC958_AES3_CON_CLOCK_50PPM (1<<4) /* 50 ppm */ +#define IEC958_AES3_CON_CLOCK_VARIABLE (2<<4) /* variable pitch */ +#define IEC958_AES4_CON_MAX_WORDLEN_24 (1<<0) /* 0 = 20-bit, 1 = 24-bit */ +#define IEC958_AES4_CON_WORDLEN (7<<1) /* mask - sample word length */ +#define IEC958_AES4_CON_WORDLEN_NOTID (0<<1) /* not indicated */ +#define IEC958_AES4_CON_WORDLEN_20_16 (1<<1) /* 20-bit or 16-bit */ +#define IEC958_AES4_CON_WORDLEN_22_18 (2<<1) /* 22-bit or 18-bit */ +#define IEC958_AES4_CON_WORDLEN_23_19 (4<<1) /* 23-bit or 19-bit */ +#define IEC958_AES4_CON_WORDLEN_24_20 (5<<1) /* 24-bit or 20-bit */ +#define IEC958_AES4_CON_WORDLEN_21_17 (6<<1) /* 21-bit or 17-bit */ +#define IEC958_AES4_CON_ORIGFS (15<<4) /* mask - original sample frequency */ +#define IEC958_AES4_CON_ORIGFS_NOTID (0<<4) /* not indicated */ +#define IEC958_AES4_CON_ORIGFS_192000 (1<<4) /* 192kHz */ +#define IEC958_AES4_CON_ORIGFS_12000 (2<<4) /* 12kHz */ +#define IEC958_AES4_CON_ORIGFS_176400 (3<<4) /* 176.4kHz */ +#define IEC958_AES4_CON_ORIGFS_96000 (5<<4) /* 96kHz */ +#define IEC958_AES4_CON_ORIGFS_8000 (6<<4) /* 8kHz */ +#define IEC958_AES4_CON_ORIGFS_88200 (7<<4) /* 88.2kHz */ +#define IEC958_AES4_CON_ORIGFS_16000 (8<<4) /* 16kHz */ +#define IEC958_AES4_CON_ORIGFS_24000 (9<<4) /* 24kHz */ +#define IEC958_AES4_CON_ORIGFS_11025 (10<<4) /* 11.025kHz */ +#define IEC958_AES4_CON_ORIGFS_22050 (11<<4) /* 22.05kHz */ +#define IEC958_AES4_CON_ORIGFS_32000 (12<<4) /* 32kHz */ +#define IEC958_AES4_CON_ORIGFS_48000 (13<<4) /* 48kHz */ +#define IEC958_AES4_CON_ORIGFS_44100 (15<<4) /* 44.1kHz */ +#define IEC958_AES5_CON_CGMSA (3<<0) /* mask - CGMS-A */ +#define IEC958_AES5_CON_CGMSA_COPYFREELY (0<<0) /* copying is permitted without restriction */ +#define IEC958_AES5_CON_CGMSA_COPYONCE (1<<0) /* one generation of copies may be made */ +#define IEC958_AES5_CON_CGMSA_COPYNOMORE (2<<0) /* condition not be used */ +#define IEC958_AES5_CON_CGMSA_COPYNEVER (3<<0) /* no copying is permitted */ + +/**************************************************************************** + * * + * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort * + * * + ****************************************************************************/ +#define CEA861_AUDIO_INFOFRAME_DB1CC (7<<0) /* mask - channel count */ +#define CEA861_AUDIO_INFOFRAME_DB1CT (0xf<<4) /* mask - coding type */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_FROM_STREAM (0<<4) /* refer to stream */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_IEC60958 (1<<4) /* IEC-60958 L-PCM */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_AC3 (2<<4) /* AC-3 */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MPEG1 (3<<4) /* MPEG1 Layers 1 & 2 */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MP3 (4<<4) /* MPEG1 Layer 3 */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MPEG2_MULTICH (5<<4) /* MPEG2 Multichannel */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_AAC (6<<4) /* AAC */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DTS (7<<4) /* DTS */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_ATRAC (8<<4) /* ATRAC */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_ONEBIT (9<<4) /* One Bit Audio */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DOLBY_DIG_PLUS (10<<4) /* Dolby Digital + */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DTS_HD (11<<4) /* DTS-HD */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MAT (12<<4) /* MAT (MLP) */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DST (13<<4) /* DST */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_WMA_PRO (14<<4) /* WMA Pro */ +#define CEA861_AUDIO_INFOFRAME_DB2SF (7<<2) /* mask - sample frequency */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_FROM_STREAM (0<<2) /* refer to stream */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_32000 (1<<2) /* 32kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_44100 (2<<2) /* 44.1kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_48000 (3<<2) /* 48kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_88200 (4<<2) /* 88.2kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_96000 (5<<2) /* 96kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_176400 (6<<2) /* 176.4kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_192000 (7<<2) /* 192kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SS (3<<0) /* mask - sample size */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_FROM_STREAM (0<<0) /* refer to stream */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_16BIT (1<<0) /* 16 bits */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_20BIT (2<<0) /* 20 bits */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_24BIT (3<<0) /* 24 bits */ +#define CEA861_AUDIO_INFOFRAME_DB5_DM_INH (1<<7) /* mask - inhibit downmixing */ +#define CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PERMITTED (0<<7) /* stereo downmix permitted */ +#define CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PROHIBITED (1<<7) /* stereo downmis prohibited */ +#define CEA861_AUDIO_INFOFRAME_DB5_LSV (0xf<<3) /* mask - level-shift values */ + +/***************************************************************************** + * * + * MIDI v1.0 interface * + * * + *****************************************************************************/ + +#define MIDI_CHANNELS 16 +#define MIDI_GM_DRUM_CHANNEL (10-1) + +/* + * MIDI commands + */ + +#define MIDI_CMD_NOTE_OFF 0x80 +#define MIDI_CMD_NOTE_ON 0x90 +#define MIDI_CMD_NOTE_PRESSURE 0xa0 +#define MIDI_CMD_CONTROL 0xb0 +#define MIDI_CMD_PGM_CHANGE 0xc0 +#define MIDI_CMD_CHANNEL_PRESSURE 0xd0 +#define MIDI_CMD_BENDER 0xe0 + +#define MIDI_CMD_COMMON_SYSEX 0xf0 +#define MIDI_CMD_COMMON_MTC_QUARTER 0xf1 +#define MIDI_CMD_COMMON_SONG_POS 0xf2 +#define MIDI_CMD_COMMON_SONG_SELECT 0xf3 +#define MIDI_CMD_COMMON_TUNE_REQUEST 0xf6 +#define MIDI_CMD_COMMON_SYSEX_END 0xf7 +#define MIDI_CMD_COMMON_CLOCK 0xf8 +#define MIDI_CMD_COMMON_START 0xfa +#define MIDI_CMD_COMMON_CONTINUE 0xfb +#define MIDI_CMD_COMMON_STOP 0xfc +#define MIDI_CMD_COMMON_SENSING 0xfe +#define MIDI_CMD_COMMON_RESET 0xff + +/* + * MIDI controllers + */ + +#define MIDI_CTL_MSB_BANK 0x00 +#define MIDI_CTL_MSB_MODWHEEL 0x01 +#define MIDI_CTL_MSB_BREATH 0x02 +#define MIDI_CTL_MSB_FOOT 0x04 +#define MIDI_CTL_MSB_PORTAMENTO_TIME 0x05 +#define MIDI_CTL_MSB_DATA_ENTRY 0x06 +#define MIDI_CTL_MSB_MAIN_VOLUME 0x07 +#define MIDI_CTL_MSB_BALANCE 0x08 +#define MIDI_CTL_MSB_PAN 0x0a +#define MIDI_CTL_MSB_EXPRESSION 0x0b +#define MIDI_CTL_MSB_EFFECT1 0x0c +#define MIDI_CTL_MSB_EFFECT2 0x0d +#define MIDI_CTL_MSB_GENERAL_PURPOSE1 0x10 +#define MIDI_CTL_MSB_GENERAL_PURPOSE2 0x11 +#define MIDI_CTL_MSB_GENERAL_PURPOSE3 0x12 +#define MIDI_CTL_MSB_GENERAL_PURPOSE4 0x13 +#define MIDI_CTL_LSB_BANK 0x20 +#define MIDI_CTL_LSB_MODWHEEL 0x21 +#define MIDI_CTL_LSB_BREATH 0x22 +#define MIDI_CTL_LSB_FOOT 0x24 +#define MIDI_CTL_LSB_PORTAMENTO_TIME 0x25 +#define MIDI_CTL_LSB_DATA_ENTRY 0x26 +#define MIDI_CTL_LSB_MAIN_VOLUME 0x27 +#define MIDI_CTL_LSB_BALANCE 0x28 +#define MIDI_CTL_LSB_PAN 0x2a +#define MIDI_CTL_LSB_EXPRESSION 0x2b +#define MIDI_CTL_LSB_EFFECT1 0x2c +#define MIDI_CTL_LSB_EFFECT2 0x2d +#define MIDI_CTL_LSB_GENERAL_PURPOSE1 0x30 +#define MIDI_CTL_LSB_GENERAL_PURPOSE2 0x31 +#define MIDI_CTL_LSB_GENERAL_PURPOSE3 0x32 +#define MIDI_CTL_LSB_GENERAL_PURPOSE4 0x33 +#define MIDI_CTL_SUSTAIN 0x40 +#define MIDI_CTL_PORTAMENTO 0x41 +#define MIDI_CTL_SOSTENUTO 0x42 +#define MIDI_CTL_SOFT_PEDAL 0x43 +#define MIDI_CTL_LEGATO_FOOTSWITCH 0x44 +#define MIDI_CTL_HOLD2 0x45 +#define MIDI_CTL_SC1_SOUND_VARIATION 0x46 +#define MIDI_CTL_SC2_TIMBRE 0x47 +#define MIDI_CTL_SC3_RELEASE_TIME 0x48 +#define MIDI_CTL_SC4_ATTACK_TIME 0x49 +#define MIDI_CTL_SC5_BRIGHTNESS 0x4a +#define MIDI_CTL_SC6 0x4b +#define MIDI_CTL_SC7 0x4c +#define MIDI_CTL_SC8 0x4d +#define MIDI_CTL_SC9 0x4e +#define MIDI_CTL_SC10 0x4f +#define MIDI_CTL_GENERAL_PURPOSE5 0x50 +#define MIDI_CTL_GENERAL_PURPOSE6 0x51 +#define MIDI_CTL_GENERAL_PURPOSE7 0x52 +#define MIDI_CTL_GENERAL_PURPOSE8 0x53 +#define MIDI_CTL_PORTAMENTO_CONTROL 0x54 +#define MIDI_CTL_E1_REVERB_DEPTH 0x5b +#define MIDI_CTL_E2_TREMOLO_DEPTH 0x5c +#define MIDI_CTL_E3_CHORUS_DEPTH 0x5d +#define MIDI_CTL_E4_DETUNE_DEPTH 0x5e +#define MIDI_CTL_E5_PHASER_DEPTH 0x5f +#define MIDI_CTL_DATA_INCREMENT 0x60 +#define MIDI_CTL_DATA_DECREMENT 0x61 +#define MIDI_CTL_NONREG_PARM_NUM_LSB 0x62 +#define MIDI_CTL_NONREG_PARM_NUM_MSB 0x63 +#define MIDI_CTL_REGIST_PARM_NUM_LSB 0x64 +#define MIDI_CTL_REGIST_PARM_NUM_MSB 0x65 +#define MIDI_CTL_ALL_SOUNDS_OFF 0x78 +#define MIDI_CTL_RESET_CONTROLLERS 0x79 +#define MIDI_CTL_LOCAL_CONTROL_SWITCH 0x7a +#define MIDI_CTL_ALL_NOTES_OFF 0x7b +#define MIDI_CTL_OMNI_OFF 0x7c +#define MIDI_CTL_OMNI_ON 0x7d +#define MIDI_CTL_MONO1 0x7e +#define MIDI_CTL_MONO2 0x7f + +#endif /* __SOUND_ASOUNDEF_H */ diff --git a/include/sound/aw88399.h b/include/sound/aw88399.h new file mode 100644 index 000000000..a1e0de6be --- /dev/null +++ b/include/sound/aw88399.h @@ -0,0 +1,621 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * linux/sound/aw88399.h -- Platform data for AW88399 + * + * Copyright (c) 2023 AWINIC Technology CO., LTD + * + * Author: Weidong Wang + */ + +#ifndef __SOUND_AW88399_H +#define __SOUND_AW88399_H + +#include +#include + +/* registers list */ +#define AW88399_ID_REG (0x00) +#define AW88399_SYSST_REG (0x01) +#define AW88399_SYSINT_REG (0x02) +#define AW88399_SYSINTM_REG (0x03) +#define AW88399_SYSCTRL_REG (0x04) +#define AW88399_SYSCTRL2_REG (0x05) +#define AW88399_I2SCTRL1_REG (0x06) +#define AW88399_I2SCTRL2_REG (0x07) +#define AW88399_I2SCTRL3_REG (0x08) +#define AW88399_DACCFG1_REG (0x09) +#define AW88399_DACCFG2_REG (0x0A) +#define AW88399_DACCFG3_REG (0x0B) +#define AW88399_DACCFG4_REG (0x0C) +#define AW88399_DACCFG5_REG (0x0D) +#define AW88399_DACCFG6_REG (0x0E) +#define AW88399_DACCFG7_REG (0x0F) +#define AW88399_MPDCFG1_REG (0x10) +#define AW88399_MPDCFG2_REG (0x11) +#define AW88399_MPDCFG3_REG (0x12) +#define AW88399_MPDCFG4_REG (0x13) +#define AW88399_PWMCTRL1_REG (0x14) +#define AW88399_PWMCTRL2_REG (0x15) +#define AW88399_PWMCTRL3_REG (0x16) +#define AW88399_I2SCFG1_REG (0x17) +#define AW88399_DBGCTRL_REG (0x18) +#define AW88399_HAGCST_REG (0x20) +#define AW88399_VBAT_REG (0x21) +#define AW88399_TEMP_REG (0x22) +#define AW88399_PVDD_REG (0x23) +#define AW88399_ISNDAT_REG (0x24) +#define AW88399_VSNDAT_REG (0x25) +#define AW88399_I2SINT_REG (0x26) +#define AW88399_I2SCAPCNT_REG (0x27) +#define AW88399_ANASTA1_REG (0x28) +#define AW88399_ANASTA2_REG (0x29) +#define AW88399_ANASTA3_REG (0x2A) +#define AW88399_TESTDET_REG (0x2B) +#define AW88399_DSMCFG1_REG (0x30) +#define AW88399_DSMCFG2_REG (0x31) +#define AW88399_DSMCFG3_REG (0x32) +#define AW88399_DSMCFG4_REG (0x33) +#define AW88399_DSMCFG5_REG (0x34) +#define AW88399_DSMCFG6_REG (0x35) +#define AW88399_DSMCFG7_REG (0x36) +#define AW88399_DSMCFG8_REG (0x37) +#define AW88399_TESTIN_REG (0x38) +#define AW88399_TESTOUT_REG (0x39) +#define AW88399_MEMTEST_REG (0x3A) +#define AW88399_VSNCTRL1_REG (0x3B) +#define AW88399_ISNCTRL1_REG (0x3C) +#define AW88399_ISNCTRL2_REG (0x3D) +#define AW88399_DSPMADD_REG (0x40) +#define AW88399_DSPMDAT_REG (0x41) +#define AW88399_WDT_REG (0x42) +#define AW88399_ACR1_REG (0x43) +#define AW88399_ACR2_REG (0x44) +#define AW88399_ASR1_REG (0x45) +#define AW88399_ASR2_REG (0x46) +#define AW88399_DSPCFG_REG (0x47) +#define AW88399_ASR3_REG (0x48) +#define AW88399_ASR4_REG (0x49) +#define AW88399_DSPVCALB_REG (0x4A) +#define AW88399_CRCCTRL_REG (0x4B) +#define AW88399_DSPDBG1_REG (0x4C) +#define AW88399_DSPDBG2_REG (0x4D) +#define AW88399_DSPDBG3_REG (0x4E) +#define AW88399_PLLCTRL1_REG (0x50) +#define AW88399_PLLCTRL2_REG (0x51) +#define AW88399_PLLCTRL3_REG (0x52) +#define AW88399_CDACTRL1_REG (0x53) +#define AW88399_CDACTRL2_REG (0x54) +#define AW88399_CDACTRL3_REG (0x55) +#define AW88399_SADCCTRL1_REG (0x56) +#define AW88399_SADCCTRL2_REG (0x57) +#define AW88399_BOPCTRL1_REG (0x58) +#define AW88399_BOPCTRL2_REG (0x5A) +#define AW88399_BOPCTRL3_REG (0x5B) +#define AW88399_BOPCTRL4_REG (0x5C) +#define AW88399_BOPCTRL5_REG (0x5D) +#define AW88399_BOPCTRL6_REG (0x5E) +#define AW88399_BOPCTRL7_REG (0x5F) +#define AW88399_BSTCTRL1_REG (0x60) +#define AW88399_BSTCTRL2_REG (0x61) +#define AW88399_BSTCTRL3_REG (0x62) +#define AW88399_BSTCTRL4_REG (0x63) +#define AW88399_BSTCTRL5_REG (0x64) +#define AW88399_BSTCTRL6_REG (0x65) +#define AW88399_BSTCTRL7_REG (0x66) +#define AW88399_BSTCTRL8_REG (0x67) +#define AW88399_BSTCTRL9_REG (0x68) +#define AW88399_BSTCTRL10_REG (0x69) +#define AW88399_CPCTRL_REG (0x6A) +#define AW88399_EFWH_REG (0x6C) +#define AW88399_EFWM2_REG (0x6D) +#define AW88399_EFWM1_REG (0x6E) +#define AW88399_EFWL_REG (0x6F) +#define AW88399_TESTCTRL1_REG (0x70) +#define AW88399_TESTCTRL2_REG (0x71) +#define AW88399_EFCTRL1_REG (0x72) +#define AW88399_EFCTRL2_REG (0x73) +#define AW88399_EFRH4_REG (0x74) +#define AW88399_EFRH3_REG (0x75) +#define AW88399_EFRH2_REG (0x76) +#define AW88399_EFRH1_REG (0x77) +#define AW88399_EFRL4_REG (0x78) +#define AW88399_EFRL3_REG (0x79) +#define AW88399_EFRL2_REG (0x7A) +#define AW88399_EFRL1_REG (0x7B) +#define AW88399_TM_REG (0x7C) +#define AW88399_TM2_REG (0x7D) + +#define AW88399_REG_MAX (0x7E) +#define AW88399_MUTE_VOL (1023) + +#define AW88399_DSP_CFG_ADDR (0x9B00) +#define AW88399_DSP_REG_CFG_ADPZ_RA (0x9B68) +#define AW88399_DSP_FW_ADDR (0x8980) +#define AW88399_DSP_ROM_CHECK_ADDR (0x1F40) +#define AW88399_DSP_ROM_CHECK_DATA (0x4638) + +#define AW88399_CALI_RE_HBITS_MASK (~(0xFFFF0000)) +#define AW88399_CALI_RE_HBITS_SHIFT (16) + +#define AW88399_CALI_RE_LBITS_MASK (~(0xFFFF)) +#define AW88399_CALI_RE_LBITS_SHIFT (0) + +#define AW88399_I2STXEN_START_BIT (9) +#define AW88399_I2STXEN_BITS_LEN (1) +#define AW88399_I2STXEN_MASK \ + (~(((1<> (shift)) +#define AW88399_SHOW_RE_TO_DSP_RE(re, shift) (((re) << shift) / (1000)) +#define AW88399_CRC_CHECK_PASS_VAL (0x4) + +#define AW88399_CRC_CFG_BASE_ADDR (0xD80) +#define AW88399_CRC_FW_BASE_ADDR (0x4C0) +#define AW88399_ACF_FILE "aw88399_acf.bin" +#define AW88399_DEV_SYSST_CHECK_MAX (10) +#define AW88399_CHIP_ID 0x2183 + +#define AW88399_START_RETRIES (5) +#define AW88399_START_WORK_DELAY_MS (0) + +enum { + AW_EF_AND_CHECK = 0, + AW_EF_OR_CHECK, +}; + +enum { + AW88399_DEV_VDSEL_DAC = 0, + AW88399_DEV_VDSEL_VSENSE = 32, +}; + +enum { + AW88399_DSP_CRC_NA = 0, + AW88399_DSP_CRC_OK = 1, +}; + +enum { + AW88399_DSP_FW_UPDATE_OFF = 0, + AW88399_DSP_FW_UPDATE_ON = 1, +}; + +enum { + AW88399_FORCE_UPDATE_OFF = 0, + AW88399_FORCE_UPDATE_ON = 1, +}; + +enum { + AW88399_1000_US = 1000, + AW88399_2000_US = 2000, + AW88399_3000_US = 3000, + AW88399_4000_US = 4000, +}; + +enum AW88399_DEV_STATUS { + AW88399_DEV_PW_OFF = 0, + AW88399_DEV_PW_ON, +}; + +enum AW88399_DEV_FW_STATUS { + AW88399_DEV_FW_FAILED = 0, + AW88399_DEV_FW_OK, +}; + +enum AW88399_DEV_MEMCLK { + AW88399_DEV_MEMCLK_OSC = 0, + AW88399_DEV_MEMCLK_PLL = 1, +}; + +enum AW88399_DEV_DSP_CFG { + AW88399_DEV_DSP_WORK = 0, + AW88399_DEV_DSP_BYPASS = 1, +}; + +enum { + AW88399_NOT_RCV_MODE = 0, + AW88399_RCV_MODE = 1, +}; + +enum { + AW88399_SYNC_START = 0, + AW88399_ASYNC_START, +}; + +struct aw_device; +struct aw_container; +struct aw_cali_desc; +struct gpio_desc; +struct i2c_client; +struct regmap; + +struct aw88399 { + struct aw_device *aw_pa; + struct mutex lock; + struct gpio_desc *reset_gpio; + struct delayed_work start_work; + struct regmap *regmap; + struct aw_container *aw_cfg; + + unsigned int check_val; + unsigned int crc_init_val; + unsigned int vcalb_init_val; + unsigned int dither_st; + bool bsts_unreliable; + bool fw_needs_reload; +}; + +int aw_dev_check_syspll(struct aw_device *aw_dev); +void aw_dev_dsp_enable(struct aw_device *aw_dev, bool is_enable); +int aw_dev_get_dsp_status(struct aw_device *aw_dev); +int aw_dev_set_volume(struct aw_device *aw_dev, unsigned int value); +int aw_dev_update_cali_re(struct aw_cali_desc *cali_desc); +int aw88399_dev_get_prof_name(struct aw_device *aw_dev, int index, char **prof_name); +void aw88399_dev_mute(struct aw_device *aw_dev, bool is_mute); +void aw88399_dev_set_channel(struct aw88399 *aw88399, int channel); +void aw88399_hw_reset(struct aw88399 *aw88399); +int aw88399_init(struct aw88399 *aw88399, struct i2c_client *i2c, struct regmap *regmap); +extern const struct regmap_config aw88399_remap_config; +int aw88399_request_firmware_file(struct aw88399 *aw88399); +void aw88399_start(struct aw88399 *aw88399, bool sync_start); +void aw88399_startup_work(struct work_struct *work); +int aw88399_stop(struct aw_device *aw_dev); + +#endif /* __SOUND_AW88399_H */ diff --git a/include/sound/compress_driver.h b/include/sound/compress_driver.h new file mode 100644 index 000000000..9e3d801e4 --- /dev/null +++ b/include/sound/compress_driver.h @@ -0,0 +1,295 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * compress_driver.h - compress offload driver definations + * + * Copyright (C) 2011 Intel Corporation + * Authors: Vinod Koul + * Pierre-Louis Bossart + */ + +#ifndef __COMPRESS_DRIVER_H +#define __COMPRESS_DRIVER_H + +#include +#include +#include +#include +#include +#include + +struct snd_compr_ops; + +/** + * struct snd_compr_task_runtime: task runtime description + * @list: list of all managed tasks + * @input: input DMA buffer + * @output: output DMA buffer + * @seqno: sequence number + * @input_size: really used data in the input buffer + * @output_size: really used data in the output buffer + * @flags: see SND_COMPRESS_TFLG_* + * @state: actual task state + * @private_value: used by the lowlevel driver (opaque) + */ +struct snd_compr_task_runtime { + struct list_head list; + struct dma_buf *input; + struct dma_buf *output; + u64 seqno; + u64 input_size; + u64 output_size; + u32 flags; + u8 state; + void *private_value; +}; + +/** + * struct snd_compr_runtime: runtime stream description + * @state: stream state + * @ops: pointer to DSP callbacks + * @buffer: pointer to kernel buffer, valid only when not in mmap mode or + * DSP doesn't implement copy + * @buffer_size: size of the above buffer + * @fragment_size: size of buffer fragment in bytes + * @fragments: number of such fragments + * @total_bytes_available: cumulative number of bytes made available in + * the ring buffer + * @total_bytes_transferred: cumulative bytes transferred by offload DSP + * @sleep: poll sleep + * @private_data: driver private data pointer + * @dma_area: virtual buffer address + * @dma_addr: physical buffer address (not accessible from main CPU) + * @dma_bytes: size of DMA area + * @dma_buffer_p: runtime dma buffer pointer + * @active_tasks: count of active tasks + * @total_tasks: count of all tasks + * @task_seqno: last task sequence number (!= 0) + * @tasks: list of all tasks + */ +struct snd_compr_runtime { + snd_pcm_state_t state; + struct snd_compr_ops *ops; + void *buffer; + u64 buffer_size; + u32 fragment_size; + u32 fragments; + u64 total_bytes_available; + u64 total_bytes_transferred; + wait_queue_head_t sleep; + void *private_data; + + unsigned char *dma_area; + dma_addr_t dma_addr; + size_t dma_bytes; + struct snd_dma_buffer *dma_buffer_p; + +#if IS_ENABLED(CONFIG_SND_COMPRESS_ACCEL) + u32 active_tasks; + u32 total_tasks; + u64 task_seqno; + struct list_head tasks; +#endif +}; + +/** + * struct snd_compr_stream: compressed stream + * @name: device name + * @ops: pointer to DSP callbacks + * @runtime: pointer to runtime structure + * @device: device pointer + * @error_work: delayed work used when closing the stream due to an error + * @direction: stream direction, playback/recording + * @metadata_set: metadata set flag, true when set + * @next_track: has userspace signal next track transition, true when set + * @partial_drain: undergoing partial_drain for stream, true when set + * @pause_in_draining: paused during draining state, true when set + * @private_data: pointer to DSP private data + * @dma_buffer: allocated buffer if any + */ +struct snd_compr_stream { + const char *name; + struct snd_compr_ops *ops; + struct snd_compr_runtime *runtime; + struct snd_compr *device; + struct delayed_work error_work; + enum snd_compr_direction direction; + bool metadata_set; + bool next_track; + bool partial_drain; + bool pause_in_draining; + void *private_data; + struct snd_dma_buffer dma_buffer; +}; + +/** + * struct snd_compr_ops: compressed path DSP operations + * @open: Open the compressed stream + * This callback is mandatory and shall keep dsp ready to receive the stream + * parameter + * @free: Close the compressed stream, mandatory + * @set_params: Sets the compressed stream parameters, mandatory + * This can be called in during stream creation only to set codec params + * and the stream properties + * @get_params: retrieve the codec parameters, mandatory + * @set_metadata: Set the metadata values for a stream + * @get_metadata: retrieves the requested metadata values from stream + * @trigger: Trigger operations like start, pause, resume, drain, stop. + * This callback is mandatory + * @pointer: Retrieve current h/w pointer information. Mandatory + * @copy: Copy the compressed data to/from userspace, Optional + * Can't be implemented if DSP supports mmap + * @mmap: DSP mmap method to mmap DSP memory + * @ack: Ack for DSP when data is written to audio buffer, Optional + * Not valid if copy is implemented + * @get_caps: Retrieve DSP capabilities, mandatory + * @get_codec_caps: Retrieve capabilities for a specific codec, mandatory + * @task_create: Create a set of input/output buffers for accel operations + * @task_start: Start (queue) a task for accel operations + * @task_stop: Stop (dequeue) a task for accel operations + * @task_free: Free a set of input/output buffers for accel operations + */ +struct snd_compr_ops { + int (*open)(struct snd_compr_stream *stream); + int (*free)(struct snd_compr_stream *stream); + int (*set_params)(struct snd_compr_stream *stream, + struct snd_compr_params *params); + int (*get_params)(struct snd_compr_stream *stream, + struct snd_codec *params); + int (*set_metadata)(struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*get_metadata)(struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*trigger)(struct snd_compr_stream *stream, int cmd); + int (*pointer)(struct snd_compr_stream *stream, + struct snd_compr_tstamp64 *tstamp); + int (*copy)(struct snd_compr_stream *stream, char __user *buf, + size_t count); + int (*mmap)(struct snd_compr_stream *stream, + struct vm_area_struct *vma); + int (*ack)(struct snd_compr_stream *stream, size_t bytes); + int (*get_caps) (struct snd_compr_stream *stream, + struct snd_compr_caps *caps); + int (*get_codec_caps) (struct snd_compr_stream *stream, + struct snd_compr_codec_caps *codec); +#if IS_ENABLED(CONFIG_SND_COMPRESS_ACCEL) + int (*task_create) (struct snd_compr_stream *stream, struct snd_compr_task_runtime *task); + int (*task_start) (struct snd_compr_stream *stream, struct snd_compr_task_runtime *task); + int (*task_stop) (struct snd_compr_stream *stream, struct snd_compr_task_runtime *task); + int (*task_free) (struct snd_compr_stream *stream, struct snd_compr_task_runtime *task); +#endif +}; + +/** + * struct snd_compr: Compressed device + * @name: DSP device name + * @dev: associated device instance + * @ops: pointer to DSP callbacks + * @private_data: pointer to DSP pvt data + * @card: sound card pointer + * @direction: Playback or capture direction + * @lock: device lock + * @device: device id + * @use_pause_in_draining: allow pause in draining, true when set + */ +struct snd_compr { + const char *name; + struct device *dev; + struct snd_compr_ops *ops; + void *private_data; + struct snd_card *card; + unsigned int direction; + struct mutex lock; + int device; + bool use_pause_in_draining; +#ifdef CONFIG_SND_VERBOSE_PROCFS + /* private: */ + char id[64]; + struct snd_info_entry *proc_root; + struct snd_info_entry *proc_info_entry; +#endif +}; + +/* compress device register APIs */ +int snd_compress_new(struct snd_card *card, int device, + int type, const char *id, struct snd_compr *compr); + +/** + * snd_compr_use_pause_in_draining - Allow pause and resume in draining state + * @substream: compress substream to set + * + * Allow pause and resume in draining state. + * Only HW driver supports this transition can call this API. + */ +static inline void snd_compr_use_pause_in_draining(struct snd_compr_stream *substream) +{ + substream->device->use_pause_in_draining = true; +} + +/* dsp driver callback apis + * For playback: driver should call snd_compress_fragment_elapsed() to let the + * framework know that a fragment has been consumed from the ring buffer + * + * For recording: we want to know when a frame is available or when + * at least one frame is available so snd_compress_frame_elapsed() + * callback should be called when a encodeded frame is available + */ +static inline void snd_compr_fragment_elapsed(struct snd_compr_stream *stream) +{ + wake_up(&stream->runtime->sleep); +} + +static inline void snd_compr_drain_notify(struct snd_compr_stream *stream) +{ + if (snd_BUG_ON(!stream)) + return; + + /* for partial_drain case we are back to running state on success */ + if (stream->partial_drain) { + stream->runtime->state = SNDRV_PCM_STATE_RUNNING; + stream->partial_drain = false; /* clear this flag as well */ + } else { + stream->runtime->state = SNDRV_PCM_STATE_SETUP; + } + + wake_up(&stream->runtime->sleep); +} + +/** + * snd_compr_set_runtime_buffer - Set the Compress runtime buffer + * @stream: compress stream to set + * @bufp: the buffer information, NULL to clear + * + * Copy the buffer information to runtime buffer when @bufp is non-NULL. + * Otherwise it clears the current buffer information. + */ +static inline void +snd_compr_set_runtime_buffer(struct snd_compr_stream *stream, + struct snd_dma_buffer *bufp) +{ + struct snd_compr_runtime *runtime = stream->runtime; + + if (bufp) { + runtime->dma_buffer_p = bufp; + runtime->dma_area = bufp->area; + runtime->dma_addr = bufp->addr; + runtime->dma_bytes = bufp->bytes; + } else { + runtime->dma_buffer_p = NULL; + runtime->dma_area = NULL; + runtime->dma_addr = 0; + runtime->dma_bytes = 0; + } +} + +int snd_compr_malloc_pages(struct snd_compr_stream *stream, size_t size); +int snd_compr_free_pages(struct snd_compr_stream *stream); + +int snd_compr_stop_error(struct snd_compr_stream *stream, + snd_pcm_state_t state); + +#if IS_ENABLED(CONFIG_SND_COMPRESS_ACCEL) +void snd_compr_task_finished(struct snd_compr_stream *stream, + struct snd_compr_task_runtime *task); +#endif + +#endif diff --git a/include/sound/control.h b/include/sound/control.h new file mode 100644 index 000000000..909db0d04 --- /dev/null +++ b/include/sound/control.h @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CONTROL_H +#define __SOUND_CONTROL_H + +/* + * Header file for control interface + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include +#include +#include + +#define snd_kcontrol_chip(kcontrol) ((kcontrol)->private_data) + +struct snd_kcontrol; +typedef int (snd_kcontrol_info_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_info * uinfo); +typedef int (snd_kcontrol_get_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol); +typedef int (snd_kcontrol_put_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol); +typedef int (snd_kcontrol_tlv_rw_t)(struct snd_kcontrol *kcontrol, + int op_flag, /* SNDRV_CTL_TLV_OP_XXX */ + unsigned int size, + unsigned int __user *tlv); + +/* internal flag for skipping validations */ +#ifdef CONFIG_SND_CTL_DEBUG +#define SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK (1 << 24) +#define snd_ctl_skip_validation(info) \ + ((info)->access & SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK) +#else +#define SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK 0 +#define snd_ctl_skip_validation(info) true +#endif + +/* kernel only - LED bits */ +#define SNDRV_CTL_ELEM_ACCESS_LED_SHIFT 25 +#define SNDRV_CTL_ELEM_ACCESS_LED_MASK (7<<25) /* kernel three bits - LED group */ +#define SNDRV_CTL_ELEM_ACCESS_SPK_LED (1<<25) /* kernel speaker (output) LED flag */ +#define SNDRV_CTL_ELEM_ACCESS_MIC_LED (2<<25) /* kernel microphone (input) LED flag */ + +enum { + SNDRV_CTL_TLV_OP_READ = 0, + SNDRV_CTL_TLV_OP_WRITE = 1, + SNDRV_CTL_TLV_OP_CMD = -1, +}; + +struct snd_kcontrol_new { + snd_ctl_elem_iface_t iface; /* interface identifier */ + unsigned int device; /* device/client number */ + unsigned int subdevice; /* subdevice (substream) number */ + const char *name; /* ASCII name of item */ + unsigned int index; /* index of item */ + unsigned int access; /* access rights */ + unsigned int count; /* count of same elements */ + snd_kcontrol_info_t *info; + snd_kcontrol_get_t *get; + snd_kcontrol_put_t *put; + union { + snd_kcontrol_tlv_rw_t *c; + const unsigned int *p; + } tlv; + unsigned long private_value; +}; + +struct snd_kcontrol_volatile { + struct snd_ctl_file *owner; /* locked */ + unsigned int access; /* access rights */ +}; + +struct snd_kcontrol { + struct list_head list; /* list of controls */ + struct snd_ctl_elem_id id; + unsigned int count; /* count of same elements */ + snd_kcontrol_info_t *info; + snd_kcontrol_get_t *get; + snd_kcontrol_put_t *put; + union { + snd_kcontrol_tlv_rw_t *c; + const unsigned int *p; + } tlv; + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_kcontrol *kcontrol); + struct snd_kcontrol_volatile vd[] __counted_by(count); /* volatile data */ +}; + +#define snd_kcontrol(n) list_entry(n, struct snd_kcontrol, list) + +struct snd_kctl_event { + struct list_head list; /* list of events */ + struct snd_ctl_elem_id id; + unsigned int mask; +}; + +#define snd_kctl_event(n) list_entry(n, struct snd_kctl_event, list) + +struct pid; + +enum { + SND_CTL_SUBDEV_PCM, + SND_CTL_SUBDEV_RAWMIDI, + SND_CTL_SUBDEV_ITEMS, +}; + +struct snd_ctl_file { + struct list_head list; /* list of all control files */ + struct snd_card *card; + struct pid *pid; + int preferred_subdevice[SND_CTL_SUBDEV_ITEMS]; + wait_queue_head_t change_sleep; + spinlock_t read_lock; + struct snd_fasync *fasync; + int subscribed; /* read interface is activated */ + struct list_head events; /* waiting events for read */ +}; + +struct snd_ctl_layer_ops { + struct snd_ctl_layer_ops *next; + const char *module_name; + void (*lregister)(struct snd_card *card); + void (*ldisconnect)(struct snd_card *card); + void (*lnotify)(struct snd_card *card, unsigned int mask, struct snd_kcontrol *kctl, unsigned int ioff); +}; + +#define snd_ctl_file(n) list_entry(n, struct snd_ctl_file, list) + +typedef int (*snd_kctl_ioctl_func_t) (struct snd_card * card, + struct snd_ctl_file * control, + unsigned int cmd, unsigned long arg); + +void snd_ctl_notify(struct snd_card * card, unsigned int mask, struct snd_ctl_elem_id * id); +void snd_ctl_notify_one(struct snd_card * card, unsigned int mask, struct snd_kcontrol * kctl, unsigned int ioff); + +struct snd_kcontrol *snd_ctl_new1(const struct snd_kcontrol_new * kcontrolnew, void * private_data); +void snd_ctl_free_one(struct snd_kcontrol * kcontrol); +int snd_ctl_add(struct snd_card * card, struct snd_kcontrol * kcontrol); +int snd_ctl_remove(struct snd_card * card, struct snd_kcontrol * kcontrol); +int snd_ctl_replace(struct snd_card *card, struct snd_kcontrol *kcontrol, bool add_on_replace); +int snd_ctl_remove_id(struct snd_card * card, struct snd_ctl_elem_id *id); +int snd_ctl_rename_id(struct snd_card * card, struct snd_ctl_elem_id *src_id, struct snd_ctl_elem_id *dst_id); +void snd_ctl_rename(struct snd_card *card, struct snd_kcontrol *kctl, const char *name); +int snd_ctl_activate_id(struct snd_card *card, struct snd_ctl_elem_id *id, int active); +struct snd_kcontrol *snd_ctl_find_numid(struct snd_card *card, unsigned int numid); +struct snd_kcontrol *snd_ctl_find_id(struct snd_card *card, const struct snd_ctl_elem_id *id); + +/** + * snd_ctl_find_id_mixer - find the control instance with the given name string + * @card: the card instance + * @name: the name string + * + * Finds the control instance with the given name and + * @SNDRV_CTL_ELEM_IFACE_MIXER. Other fields are set to zero. + * + * This is merely a wrapper to snd_ctl_find_id(). + * + * Return: The pointer of the instance if found, or %NULL if not. + */ +static inline struct snd_kcontrol * +snd_ctl_find_id_mixer(struct snd_card *card, const char *name) +{ + struct snd_ctl_elem_id id = {}; + + id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; + strscpy(id.name, name, sizeof(id.name)); + return snd_ctl_find_id(card, &id); +} + +int snd_ctl_create(struct snd_card *card); + +extern struct rw_semaphore snd_ioctl_rwsem; + +int snd_ctl_register_ioctl(snd_kctl_ioctl_func_t fcn); +int snd_ctl_unregister_ioctl(snd_kctl_ioctl_func_t fcn); +#ifdef CONFIG_COMPAT +int snd_ctl_register_ioctl_compat(snd_kctl_ioctl_func_t fcn); +int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn); +#else +#define snd_ctl_register_ioctl_compat(fcn) +#define snd_ctl_unregister_ioctl_compat(fcn) +#endif + +int snd_ctl_request_layer(const char *module_name); +void snd_ctl_register_layer(struct snd_ctl_layer_ops *lops); +void snd_ctl_disconnect_layer(struct snd_ctl_layer_ops *lops); + +int snd_ctl_get_preferred_subdevice(struct snd_card *card, int type); + +static inline unsigned int snd_ctl_get_ioffnum(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) +{ + unsigned int ioff = id->numid - kctl->id.numid; + return array_index_nospec(ioff, kctl->count); +} + +static inline unsigned int snd_ctl_get_ioffidx(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) +{ + unsigned int ioff = id->index - kctl->id.index; + return array_index_nospec(ioff, kctl->count); +} + +static inline unsigned int snd_ctl_get_ioff(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) +{ + if (id->numid) { + return snd_ctl_get_ioffnum(kctl, id); + } else { + return snd_ctl_get_ioffidx(kctl, id); + } +} + +static inline struct snd_ctl_elem_id *snd_ctl_build_ioff(struct snd_ctl_elem_id *dst_id, + struct snd_kcontrol *src_kctl, + unsigned int offset) +{ + *dst_id = src_kctl->id; + dst_id->index += offset; + dst_id->numid += offset; + return dst_id; +} + +/* + * Frequently used control callbacks/helpers + */ +int snd_ctl_boolean_mono_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_ctl_boolean_stereo_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_ctl_enum_info(struct snd_ctl_elem_info *info, unsigned int channels, + unsigned int items, const char *const names[]); + +/* + * virtual master control + */ +struct snd_kcontrol *snd_ctl_make_virtual_master(char *name, + const unsigned int *tlv); +int _snd_ctl_add_follower(struct snd_kcontrol *master, + struct snd_kcontrol *follower, + unsigned int flags); +/* optional flags for follower */ +#define SND_CTL_FOLLOWER_NEED_UPDATE (1 << 0) + +/** + * snd_ctl_add_follower - Add a virtual follower control + * @master: vmaster element + * @follower: follower element to add + * + * Add a virtual follower control to the given master element created via + * snd_ctl_create_virtual_master() beforehand. + * + * All followers must be the same type (returning the same information + * via info callback). The function doesn't check it, so it's your + * responsibility. + * + * Also, some additional limitations: + * at most two channels, + * logarithmic volume control (dB level) thus no linear volume, + * master can only attenuate the volume without gain + * + * Return: Zero if successful or a negative error code. + */ +static inline int +snd_ctl_add_follower(struct snd_kcontrol *master, struct snd_kcontrol *follower) +{ + return _snd_ctl_add_follower(master, follower, 0); +} + +int snd_ctl_add_followers(struct snd_card *card, struct snd_kcontrol *master, + const char * const *list); + +/** + * snd_ctl_add_follower_uncached - Add a virtual follower control + * @master: vmaster element + * @follower: follower element to add + * + * Add a virtual follower control to the given master. + * Unlike snd_ctl_add_follower(), the element added via this function + * is supposed to have volatile values, and get callback is called + * at each time queried from the master. + * + * When the control peeks the hardware values directly and the value + * can be changed by other means than the put callback of the element, + * this function should be used to keep the value always up-to-date. + * + * Return: Zero if successful or a negative error code. + */ +static inline int +snd_ctl_add_follower_uncached(struct snd_kcontrol *master, + struct snd_kcontrol *follower) +{ + return _snd_ctl_add_follower(master, follower, SND_CTL_FOLLOWER_NEED_UPDATE); +} + +int snd_ctl_add_vmaster_hook(struct snd_kcontrol *kctl, + void (*hook)(void *private_data, int), + void *private_data); +void snd_ctl_sync_vmaster(struct snd_kcontrol *kctl, bool hook_only); +#define snd_ctl_sync_vmaster_hook(kctl) snd_ctl_sync_vmaster(kctl, true) +int snd_ctl_apply_vmaster_followers(struct snd_kcontrol *kctl, + int (*func)(struct snd_kcontrol *vfollower, + struct snd_kcontrol *follower, + void *arg), + void *arg); + +/* + * Control LED trigger layer + */ +#define SND_CTL_LAYER_MODULE_LED "snd-ctl-led" + +#if IS_MODULE(CONFIG_SND_CTL_LED) +static inline int snd_ctl_led_request(void) { return snd_ctl_request_layer(SND_CTL_LAYER_MODULE_LED); } +#else +static inline int snd_ctl_led_request(void) { return 0; } +#endif + +/* + * Helper functions for jack-detection controls + */ +struct snd_kcontrol * +snd_kctl_jack_new(const char *name, struct snd_card *card); +void snd_kctl_jack_report(struct snd_card *card, + struct snd_kcontrol *kctl, bool status); + +#endif /* __SOUND_CONTROL_H */ diff --git a/include/sound/core.h b/include/sound/core.h new file mode 100644 index 000000000..2ca24ac7e --- /dev/null +++ b/include/sound/core.h @@ -0,0 +1,476 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CORE_H +#define __SOUND_CORE_H + +/* + * Main header file for the ALSA driver + * Copyright (c) 1994-2001 by Jaroslav Kysela + */ + +#include +#include /* wake_up() */ +#include /* struct mutex */ +#include /* struct rw_semaphore */ +#include /* pm_message_t */ +#include +#include +#include + +/* number of supported soundcards */ +#ifdef CONFIG_SND_DYNAMIC_MINORS +#define SNDRV_CARDS CONFIG_SND_MAX_CARDS +#else +#define SNDRV_CARDS 8 /* don't change - minor numbers */ +#endif + +#define CONFIG_SND_MAJOR 116 /* standard configuration */ + +/* forward declarations */ +struct pci_dev; +struct module; +struct completion; + +/* device allocation stuff */ + +/* type of the object used in snd_device_*() + * this also defines the calling order + */ +enum snd_device_type { + SNDRV_DEV_LOWLEVEL, + SNDRV_DEV_INFO, + SNDRV_DEV_BUS, + SNDRV_DEV_CODEC, + SNDRV_DEV_PCM, + SNDRV_DEV_COMPRESS, + SNDRV_DEV_RAWMIDI, + SNDRV_DEV_TIMER, + SNDRV_DEV_SEQUENCER, + SNDRV_DEV_HWDEP, + SNDRV_DEV_JACK, + SNDRV_DEV_CONTROL, /* NOTE: this must be the last one */ +}; + +enum snd_device_state { + SNDRV_DEV_BUILD, + SNDRV_DEV_REGISTERED, + SNDRV_DEV_DISCONNECTED, +}; + +struct snd_device; + +struct snd_device_ops { + int (*dev_free)(struct snd_device *dev); + int (*dev_register)(struct snd_device *dev); + int (*dev_disconnect)(struct snd_device *dev); +}; + +struct snd_device { + struct list_head list; /* list of registered devices */ + struct snd_card *card; /* card which holds this device */ + enum snd_device_state state; /* state of the device */ + enum snd_device_type type; /* device type */ + void *device_data; /* device structure */ + const struct snd_device_ops *ops; /* operations */ +}; + +#define snd_device(n) list_entry(n, struct snd_device, list) + +/* + * A simple reference counter with a wait queue; + * typically used for usage counts, and you can synchronize at finishing + * via snd_refcount_sync(), which is woken up when the refcount reaches to + * zero again. + */ +struct snd_refcount { + atomic_t count; + wait_queue_head_t waiter; +}; + +void snd_refcount_init(struct snd_refcount *ref); + +static inline void snd_refcount_get(struct snd_refcount *ref) +{ + atomic_inc(&ref->count); +} + +void snd_refcount_put(struct snd_refcount *ref); +void snd_refcount_sync(struct snd_refcount *ref); + +/* main structure for soundcard */ + +struct snd_card { + int number; /* number of soundcard (index to + snd_cards) */ + + char id[16]; /* id string of this card */ + char driver[16]; /* driver name */ + char shortname[32]; /* short name of this soundcard */ + char longname[80]; /* name of this soundcard */ + char irq_descr[32]; /* Interrupt description */ + char mixername[80]; /* mixer name */ + char *components; /* card components, space-delimited */ + unsigned int components_alloc_size; /* current allocation size of components */ + struct module *module; /* top-level module */ + + void *private_data; /* private data for soundcard */ + void (*private_free) (struct snd_card *card); /* callback for freeing of + private data */ + struct list_head devices; /* devices */ + + struct device *ctl_dev; /* control device */ + unsigned int last_numid; /* last used numeric ID */ + struct rw_semaphore controls_rwsem; /* controls lock (list and values) */ + rwlock_t controls_rwlock; /* lock for lookup and ctl_files list */ + int controls_count; /* count of all controls */ + size_t user_ctl_alloc_size; // current memory allocation by user controls. + struct list_head controls; /* all controls for this card */ + struct list_head ctl_files; /* active control files */ +#ifdef CONFIG_SND_CTL_FAST_LOOKUP + struct xarray ctl_numids; /* hash table for numids */ + struct xarray ctl_hash; /* hash table for ctl id matching */ + bool ctl_hash_collision; /* ctl_hash collision seen? */ +#endif + + struct snd_info_entry *proc_root; /* root for soundcard specific files */ + struct proc_dir_entry *proc_root_link; /* number link to real id */ + + struct list_head files_list; /* all files associated to this card */ + struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown + state */ + spinlock_t files_lock; /* lock the files for this card */ + int shutdown; /* this card is going down */ + struct completion *release_completion; + struct device *dev; /* device assigned to this card */ + struct device card_dev; /* cardX object for sysfs */ + const struct attribute_group *dev_groups[4]; /* assigned sysfs attr */ + bool registered; /* card_dev is registered? */ + bool managed; /* managed via devres */ + bool releasing; /* during card free process */ + int sync_irq; /* assigned irq, used for PCM sync */ + wait_queue_head_t remove_sleep; + + size_t total_pcm_alloc_bytes; /* total amount of allocated buffers */ + struct mutex memory_mutex; /* protection for the above */ +#ifdef CONFIG_SND_DEBUG + struct dentry *debugfs_root; /* debugfs root for card */ +#endif +#ifdef CONFIG_SND_CTL_DEBUG + struct snd_ctl_elem_value *value_buf; /* buffer for kctl->put() verification */ +#endif + +#ifdef CONFIG_PM + unsigned int power_state; /* power state */ + wait_queue_head_t power_sleep; + struct snd_refcount power_ref; +#endif + +#if IS_ENABLED(CONFIG_SND_MIXER_OSS) + struct snd_mixer_oss *mixer_oss; + int mixer_oss_change_count; +#endif + + unsigned char private_data_area[] __aligned(__alignof__(unsigned long long)); +}; + +#define dev_to_snd_card(p) container_of(p, struct snd_card, card_dev) + +#ifdef CONFIG_PM +static inline unsigned int snd_power_get_state(struct snd_card *card) +{ + return READ_ONCE(card->power_state); +} + +static inline void snd_power_change_state(struct snd_card *card, unsigned int state) +{ + WRITE_ONCE(card->power_state, state); + wake_up(&card->power_sleep); +} + +/** + * snd_power_ref - Take the reference count for power control + * @card: sound card object + * + * The power_ref reference of the card is used for managing to block + * the snd_power_sync_ref() operation. This function increments the reference. + * The counterpart snd_power_unref() has to be called appropriately later. + */ +static inline void snd_power_ref(struct snd_card *card) +{ + snd_refcount_get(&card->power_ref); +} + +/** + * snd_power_unref - Release the reference count for power control + * @card: sound card object + */ +static inline void snd_power_unref(struct snd_card *card) +{ + snd_refcount_put(&card->power_ref); +} + +/** + * snd_power_sync_ref - wait until the card power_ref is freed + * @card: sound card object + * + * This function is used to synchronize with the pending power_ref being + * released. + */ +static inline void snd_power_sync_ref(struct snd_card *card) +{ + snd_refcount_sync(&card->power_ref); +} + +/* init.c */ +int snd_power_wait(struct snd_card *card); +int snd_power_ref_and_wait(struct snd_card *card); + +#else /* ! CONFIG_PM */ + +static inline int snd_power_wait(struct snd_card *card) { return 0; } +static inline void snd_power_ref(struct snd_card *card) {} +static inline void snd_power_unref(struct snd_card *card) {} +static inline int snd_power_ref_and_wait(struct snd_card *card) { return 0; } +static inline void snd_power_sync_ref(struct snd_card *card) {} +#define snd_power_get_state(card) ({ (void)(card); SNDRV_CTL_POWER_D0; }) +#define snd_power_change_state(card, state) do { (void)(card); } while (0) + +#endif /* CONFIG_PM */ + +struct snd_minor { + int type; /* SNDRV_DEVICE_TYPE_XXX */ + int card; /* card number */ + int device; /* device number */ + const struct file_operations *f_ops; /* file operations */ + void *private_data; /* private data for f_ops->open */ + struct device *dev; /* device for sysfs */ + struct snd_card *card_ptr; /* assigned card instance */ +}; + +/* return a device pointer linked to each sound device as a parent */ +static inline struct device *snd_card_get_device_link(struct snd_card *card) +{ + return card ? &card->card_dev : NULL; +} + +/* sound.c */ + +extern int snd_major; +extern int snd_ecards_limit; +extern const struct class sound_class; +#ifdef CONFIG_SND_DEBUG +extern struct dentry *sound_debugfs_root; +#endif + +void snd_request_card(int card); + +int snd_device_alloc(struct device **dev_p, struct snd_card *card); + +int snd_register_device(int type, struct snd_card *card, int dev, + const struct file_operations *f_ops, + void *private_data, struct device *device); +int snd_unregister_device(struct device *dev); +void *snd_lookup_minor_data(unsigned int minor, int type); + +#ifdef CONFIG_SND_OSSEMUL +int snd_register_oss_device(int type, struct snd_card *card, int dev, + const struct file_operations *f_ops, void *private_data); +int snd_unregister_oss_device(int type, struct snd_card *card, int dev); +void *snd_lookup_oss_minor_data(unsigned int minor, int type); +#endif + +int snd_minor_info_init(void); + +/* sound_oss.c */ + +#ifdef CONFIG_SND_OSSEMUL +int snd_minor_info_oss_init(void); +#else +static inline int snd_minor_info_oss_init(void) { return 0; } +#endif + +/* memory.c */ + +int copy_to_user_fromio(void __user *dst, const volatile void __iomem *src, size_t count); +int copy_from_user_toio(volatile void __iomem *dst, const void __user *src, size_t count); + +/* init.c */ + +int snd_card_locked(int card); +#if IS_ENABLED(CONFIG_SND_MIXER_OSS) +#define SND_MIXER_OSS_NOTIFY_REGISTER 0 +#define SND_MIXER_OSS_NOTIFY_DISCONNECT 1 +#define SND_MIXER_OSS_NOTIFY_FREE 2 +extern int (*snd_mixer_oss_notify_callback)(struct snd_card *card, int cmd); +#endif + +int snd_card_new(struct device *parent, int idx, const char *xid, + struct module *module, int extra_size, + struct snd_card **card_ret); +int snd_devm_card_new(struct device *parent, int idx, const char *xid, + struct module *module, size_t extra_size, + struct snd_card **card_ret); + +void snd_card_disconnect(struct snd_card *card); +void snd_card_disconnect_sync(struct snd_card *card); +void snd_card_free(struct snd_card *card); +void snd_card_free_when_closed(struct snd_card *card); +int snd_card_free_on_error(struct device *dev, int ret); +void snd_card_set_id(struct snd_card *card, const char *id); +int snd_card_register(struct snd_card *card); +int snd_card_info_init(void); +int snd_card_add_dev_attr(struct snd_card *card, + const struct attribute_group *group); +int snd_component_add(struct snd_card *card, const char *component); +int snd_card_file_add(struct snd_card *card, struct file *file); +int snd_card_file_remove(struct snd_card *card, struct file *file); + +struct snd_card *snd_card_ref(int card); + +/** + * snd_card_unref - Unreference the card object + * @card: the card object to unreference + * + * Call this function for the card object that was obtained via snd_card_ref() + * or snd_lookup_minor_data(). + */ +static inline void snd_card_unref(struct snd_card *card) +{ + put_device(&card->card_dev); +} + +DEFINE_FREE(snd_card_unref, struct snd_card *, if (_T) snd_card_unref(_T)) + +#define snd_card_set_dev(card, devptr) ((card)->dev = (devptr)) + +/* device.c */ + +int snd_device_new(struct snd_card *card, enum snd_device_type type, + void *device_data, const struct snd_device_ops *ops); +int snd_device_register(struct snd_card *card, void *device_data); +int snd_device_register_all(struct snd_card *card); +void snd_device_disconnect(struct snd_card *card, void *device_data); +void snd_device_disconnect_all(struct snd_card *card); +void snd_device_free(struct snd_card *card, void *device_data); +void snd_device_free_all(struct snd_card *card); + +/* isadma.c */ + +#ifdef CONFIG_ISA_DMA_API +#define DMA_MODE_NO_ENABLE 0x0100 + +void snd_dma_program(unsigned long dma, unsigned long addr, unsigned int size, unsigned short mode); +void snd_dma_disable(unsigned long dma); +unsigned int snd_dma_pointer(unsigned long dma, unsigned int size); +int snd_devm_request_dma(struct device *dev, int dma, const char *name); +#endif + +/* misc.c */ +struct resource; +void release_and_free_resource(struct resource *res); + +/* --- */ + +#ifdef CONFIG_SND_DEBUG +/** + * snd_BUG - give a BUG warning message and stack trace + * + * Calls WARN() if CONFIG_SND_DEBUG is set. + * Ignored when CONFIG_SND_DEBUG is not set. + */ +#define snd_BUG() WARN(1, "BUG?\n") + +/** + * snd_BUG_ON - debugging check macro + * @cond: condition to evaluate + * + * Has the same behavior as WARN_ON when CONFIG_SND_DEBUG is set, + * otherwise just evaluates the conditional and returns the value. + */ +#define snd_BUG_ON(cond) WARN_ON((cond)) + +#else /* !CONFIG_SND_DEBUG */ + +#define snd_BUG() do { } while (0) + +#define snd_BUG_ON(condition) ({ \ + int __ret_warn_on = !!(condition); \ + unlikely(__ret_warn_on); \ +}) + +#endif /* CONFIG_SND_DEBUG */ + +#define SNDRV_OSS_VERSION ((3<<16)|(8<<8)|(1<<4)|(0)) /* 3.8.1a */ + +/* for easier backward-porting */ +#if IS_ENABLED(CONFIG_GAMEPORT) +#define gameport_set_dev_parent(gp,xdev) ((gp)->dev.parent = (xdev)) +#define gameport_set_port_data(gp,r) ((gp)->port_data = (r)) +#define gameport_get_port_data(gp) (gp)->port_data +#endif + +/* PCI quirk list helper */ +struct snd_pci_quirk { + unsigned short subvendor; /* PCI subvendor ID */ + unsigned short subdevice; /* PCI subdevice ID */ + unsigned short subdevice_mask; /* bitmask to match */ + int value; /* value */ +#ifdef CONFIG_SND_DEBUG_VERBOSE + const char *name; /* name of the device (optional) */ +#endif +}; + +#define _SND_PCI_QUIRK_ID_MASK(vend, mask, dev) \ + .subvendor = (vend), .subdevice = (dev), .subdevice_mask = (mask) +#define _SND_PCI_QUIRK_ID(vend, dev) \ + _SND_PCI_QUIRK_ID_MASK(vend, 0xffff, dev) +#define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)} +#ifdef CONFIG_SND_DEBUG_VERBOSE +#define SND_PCI_QUIRK(vend,dev,xname,val) \ + {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)} +#define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val), .name = (xname)} +#define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), \ + .value = (val), .name = (xname)} +#define snd_pci_quirk_name(q) ((q)->name) +#else +#define SND_PCI_QUIRK(vend,dev,xname,val) \ + {_SND_PCI_QUIRK_ID(vend, dev), .value = (val)} +#define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), .value = (val)} +#define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val)} +#define snd_pci_quirk_name(q) "" +#endif + +#ifdef CONFIG_PCI +const struct snd_pci_quirk * +snd_pci_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list); + +const struct snd_pci_quirk * +snd_pci_quirk_lookup_id(u16 vendor, u16 device, + const struct snd_pci_quirk *list); +#else +static inline const struct snd_pci_quirk * +snd_pci_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list) +{ + return NULL; +} + +static inline const struct snd_pci_quirk * +snd_pci_quirk_lookup_id(u16 vendor, u16 device, + const struct snd_pci_quirk *list) +{ + return NULL; +} +#endif + +/* async signal helpers */ +struct snd_fasync; + +int snd_fasync_helper(int fd, struct file *file, int on, + struct snd_fasync **fasyncp); +void snd_kill_fasync(struct snd_fasync *fasync, int signal, int poll); +void snd_fasync_free(struct snd_fasync *fasync); + +#endif /* __SOUND_CORE_H */ diff --git a/include/sound/cs-amp-lib.h b/include/sound/cs-amp-lib.h new file mode 100644 index 000000000..e9aa86d76 --- /dev/null +++ b/include/sound/cs-amp-lib.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS_AMP_LIB_H +#define CS_AMP_LIB_H + +#include +#include + +struct cs_dsp; + +struct cirrus_amp_cal_data { + u32 calTarget[2]; + u32 calTime[2]; + s8 calAmbient; + u8 calStatus; + u16 calR; +} __packed; + +struct cirrus_amp_efi_data { + u32 size; + u32 count; + struct cirrus_amp_cal_data data[] __counted_by(count); +} __packed; + +/** + * struct cirrus_amp_cal_controls - definition of firmware calibration controls + * @alg_id: ID of algorithm containing the controls. + * @mem_region: DSP memory region containing the controls. + * @ambient: Name of control for calAmbient value. + * @calr: Name of control for calR value. + * @status: Name of control for calStatus value. + * @checksum: Name of control for checksum value. + */ +struct cirrus_amp_cal_controls { + unsigned int alg_id; + int mem_region; + const char *ambient; + const char *calr; + const char *status; + const char *checksum; +}; + +int cs_amp_write_cal_coeffs(struct cs_dsp *dsp, + const struct cirrus_amp_cal_controls *controls, + const struct cirrus_amp_cal_data *data); +int cs_amp_read_cal_coeffs(struct cs_dsp *dsp, + const struct cirrus_amp_cal_controls *controls, + struct cirrus_amp_cal_data *data); +int cs_amp_write_ambient_temp(struct cs_dsp *dsp, + const struct cirrus_amp_cal_controls *controls, + u32 temp); +int cs_amp_get_efi_calibration_data(struct device *dev, u64 target_uid, int amp_index, + struct cirrus_amp_cal_data *out_data); +int cs_amp_set_efi_calibration_data(struct device *dev, int amp_index, int num_amps, + const struct cirrus_amp_cal_data *in_data); +int cs_amp_get_vendor_spkid(struct device *dev); +const char *cs_amp_devm_get_vendor_specific_variant_id(struct device *dev, + int ssid_vendor, + int ssid_device); +struct dentry *cs_amp_create_debugfs(struct device *dev); + +static inline u64 cs_amp_cal_target_u64(const struct cirrus_amp_cal_data *data) +{ + return ((u64)data->calTarget[1] << 32) | data->calTarget[0]; +} + +struct cs_amp_test_hooks { + efi_status_t (*get_efi_variable)(efi_char16_t *name, + efi_guid_t *guid, + u32 *returned_attr, + unsigned long *size, + void *buf); + efi_status_t (*set_efi_variable)(efi_char16_t *name, + efi_guid_t *guid, + u32 attr, + unsigned long size, + void *buf); + + int (*write_cal_coeff)(struct cs_dsp *dsp, + const struct cirrus_amp_cal_controls *controls, + const char *ctl_name, u32 val); + + int (*read_cal_coeff)(struct cs_dsp *dsp, + const struct cirrus_amp_cal_controls *controls, + const char *ctl_name, u32 *val); +}; +extern const struct cs_amp_test_hooks * const cs_amp_test_hooks; + +#endif /* CS_AMP_LIB_H */ diff --git a/include/sound/cs35l33.h b/include/sound/cs35l33.h new file mode 100644 index 000000000..a25084c4f --- /dev/null +++ b/include/sound/cs35l33.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs35l33.h -- Platform data for CS35l33 + * + * Copyright (c) 2016 Cirrus Logic Inc. + */ + +#ifndef __CS35L33_H +#define __CS35L33_H + +struct cs35l33_hg { + bool enable_hg_algo; + unsigned int mem_depth; + unsigned int release_rate; + unsigned int hd_rm; + unsigned int ldo_thld; + unsigned int ldo_path_disable; + unsigned int ldo_entry_delay; + bool vp_hg_auto; + unsigned int vp_hg; + unsigned int vp_hg_rate; + unsigned int vp_hg_va; +}; + +struct cs35l33_pdata { + /* Boost Controller Voltage Setting */ + unsigned int boost_ctl; + + /* Boost Controller Peak Current */ + unsigned int boost_ipk; + + /* Amplifier Drive Select */ + unsigned int amp_drv_sel; + + /* soft volume ramp */ + unsigned int ramp_rate; + + /* IMON adc scale */ + unsigned int imon_adc_scale; + + /* H/G algo configuration */ + struct cs35l33_hg hg_config; +}; + +#endif /* __CS35L33_H */ diff --git a/include/sound/cs35l34.h b/include/sound/cs35l34.h new file mode 100644 index 000000000..8b0c4d94d --- /dev/null +++ b/include/sound/cs35l34.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs35l34.h -- Platform data for CS35l34 + * + * Copyright (c) 2016 Cirrus Logic Inc. + */ + +#ifndef __CS35L34_H +#define __CS35L34_H + +struct cs35l34_platform_data { + /* Set AIF to half drive strength */ + bool aif_half_drv; + /* Digital Soft Ramp Disable */ + bool digsft_disable; + /* Amplifier Invert */ + bool amp_inv; + /* Peak current (mA) */ + unsigned int boost_peak; + /* Boost inductor value (nH) */ + unsigned int boost_ind; + /* Boost Controller Voltage Setting (mV) */ + unsigned int boost_vtge; + /* Gain Change Zero Cross */ + bool gain_zc_disable; + /* SDIN Left/Right Selection */ + unsigned int i2s_sdinloc; + /* TDM Rising Edge */ + bool tdm_rising_edge; +}; + +#endif /* __CS35L34_H */ diff --git a/include/sound/cs35l35.h b/include/sound/cs35l35.h new file mode 100644 index 000000000..3a770e40e --- /dev/null +++ b/include/sound/cs35l35.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs35l35.h -- Platform data for CS35l35 + * + * Copyright (c) 2016 Cirrus Logic Inc. + */ + +#ifndef __CS35L35_H +#define __CS35L35_H + +struct classh_cfg { + /* + * Class H Algorithm Control Variables + * You can either have it done + * automatically or you can adjust + * these variables for tuning + * + * if you do not enable the internal algorithm + * you will get a set of mixer controls for + * Class H tuning + * + * Section 4.3 of the datasheet + */ + bool classh_bst_override; + bool classh_algo_enable; + int classh_bst_max_limit; + int classh_mem_depth; + int classh_release_rate; + int classh_headroom; + int classh_wk_fet_disable; + int classh_wk_fet_delay; + int classh_wk_fet_thld; + int classh_vpch_auto; + int classh_vpch_rate; + int classh_vpch_man; +}; + +struct monitor_cfg { + /* + * Signal Monitor Data + * highly configurable signal monitoring + * data positioning and different types of + * monitoring data. + * + * Section 4.8.2 - 4.8.4 of the datasheet + */ + bool is_present; + bool imon_specs; + bool vmon_specs; + bool vpmon_specs; + bool vbstmon_specs; + bool vpbrstat_specs; + bool zerofill_specs; + u8 imon_dpth; + u8 imon_loc; + u8 imon_frm; + u8 imon_scale; + u8 vmon_dpth; + u8 vmon_loc; + u8 vmon_frm; + u8 vpmon_dpth; + u8 vpmon_loc; + u8 vpmon_frm; + u8 vbstmon_dpth; + u8 vbstmon_loc; + u8 vbstmon_frm; + u8 vpbrstat_dpth; + u8 vpbrstat_loc; + u8 vpbrstat_frm; + u8 zerofill_dpth; + u8 zerofill_loc; + u8 zerofill_frm; +}; + +struct cs35l35_platform_data { + + /* Stereo (2 Device) */ + bool stereo; + /* serial port drive strength */ + int sp_drv_str; + /* serial port drive in unused slots */ + int sp_drv_unused; + /* Boost Power Down with FET */ + bool bst_pdn_fet_on; + /* Boost Voltage : used if ClassH Algo Enabled */ + int bst_vctl; + /* Boost Converter Peak Current CTRL */ + int bst_ipk; + /* Amp Gain Zero Cross */ + bool gain_zc; + /* Audio Input Location */ + int aud_channel; + /* Advisory Input Location */ + int adv_channel; + /* Shared Boost for stereo */ + bool shared_bst; + /* Specifies this amp is using an external boost supply */ + bool ext_bst; + /* Inductor Value */ + int boost_ind; + /* ClassH Algorithm */ + struct classh_cfg classh_algo; + /* Monitor Config */ + struct monitor_cfg mon_cfg; +}; + +#endif /* __CS35L35_H */ diff --git a/include/sound/cs35l36.h b/include/sound/cs35l36.h new file mode 100644 index 000000000..8f8049d39 --- /dev/null +++ b/include/sound/cs35l36.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/sound/cs35l36.h -- Platform data for CS35L36 + * + * Copyright 2018 Cirrus Logic, Inc. + * + * Author: James Schulman + * + */ + +#ifndef __CS35L36_H +#define __CS35L36_H + +struct cs35l36_vpbr_cfg { + bool is_present; + bool vpbr_en; + int vpbr_thld; + int vpbr_atk_rate; + int vpbr_atk_vol; + int vpbr_max_attn; + int vpbr_wait; + int vpbr_rel_rate; + int vpbr_mute_en; +}; + +struct cs35l36_platform_data { + bool multi_amp_mode; + bool dcm_mode; + bool amp_pcm_inv; + bool imon_pol_inv; + bool vmon_pol_inv; + int boost_ind; + int bst_vctl; + int bst_vctl_sel; + int bst_ipk; + bool extern_boost; + int temp_warn_thld; + int irq_drv_sel; + int irq_gpio_sel; + struct cs35l36_vpbr_cfg vpbr_config; +}; + +#endif /* __CS35L36_H */ diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h new file mode 100644 index 000000000..7542cabfa --- /dev/null +++ b/include/sound/cs35l41.h @@ -0,0 +1,928 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/cs35l41.h -- Platform data for CS35L41 + * + * Copyright (c) 2017-2021 Cirrus Logic Inc. + * + * Author: David Rhodes + */ + +#ifndef __CS35L41_H +#define __CS35L41_H + +#include +#include + +#define CS35L41_FIRSTREG 0x00000000 +#define CS35L41_LASTREG 0x03804FE8 +#define CS35L41_DEVID 0x00000000 +#define CS35L41_REVID 0x00000004 +#define CS35L41_FABID 0x00000008 +#define CS35L41_RELID 0x0000000C +#define CS35L41_OTPID 0x00000010 +#define CS35L41_SFT_RESET 0x00000020 +#define CS35L41_TEST_KEY_CTL 0x00000040 +#define CS35L41_USER_KEY_CTL 0x00000044 +#define CS35L41_OTP_MEM0 0x00000400 +#define CS35L41_OTP_MEM31 0x0000047C +#define CS35L41_OTP_CTRL0 0x00000500 +#define CS35L41_OTP_CTRL1 0x00000504 +#define CS35L41_OTP_CTRL3 0x00000508 +#define CS35L41_OTP_CTRL4 0x0000050C +#define CS35L41_OTP_CTRL5 0x00000510 +#define CS35L41_OTP_CTRL6 0x00000514 +#define CS35L41_OTP_CTRL7 0x00000518 +#define CS35L41_OTP_CTRL8 0x0000051C +#define CS35L41_PWR_CTRL1 0x00002014 +#define CS35L41_PWR_CTRL2 0x00002018 +#define CS35L41_PWR_CTRL3 0x0000201C +#define CS35L41_CTRL_OVRRIDE 0x00002020 +#define CS35L41_AMP_OUT_MUTE 0x00002024 +#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034 +#define CS35L41_GPIO_PAD_CONTROL 0x0000242C +#define CS35L41_JTAG_CONTROL 0x00002438 +#define CS35L41_PWRMGT_CTL 0x00002900 +#define CS35L41_WAKESRC_CTL 0x00002904 +#define CS35L41_PWRMGT_STS 0x00002908 +#define CS35L41_PLL_CLK_CTRL 0x00002C04 +#define CS35L41_DSP_CLK_CTRL 0x00002C08 +#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C +#define CS35L41_DATA_FS_SEL 0x00002C10 +#define CS35L41_TST_FS_MON0 0x00002D10 +#define CS35L41_MDSYNC_EN 0x00003400 +#define CS35L41_MDSYNC_TX_ID 0x00003408 +#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C +#define CS35L41_MDSYNC_DATA_TX 0x00003410 +#define CS35L41_MDSYNC_TX_STATUS 0x00003414 +#define CS35L41_MDSYNC_DATA_RX 0x0000341C +#define CS35L41_MDSYNC_RX_STATUS 0x00003420 +#define CS35L41_MDSYNC_ERR_STATUS 0x00003424 +#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528 +#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C +#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C +#define CS35L41_BSTCVRT_VCTRL1 0x00003800 +#define CS35L41_BSTCVRT_VCTRL2 0x00003804 +#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808 +#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C +#define CS35L41_BSTCVRT_COEFF 0x00003810 +#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814 +#define CS35L41_BSTCVRT_SW_FREQ 0x00003818 +#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C +#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820 +#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830 +#define CS35L41_VI_VOL_POL 0x00004000 +#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100 +#define CS35L41_DTEMP_WARN_THLD 0x00004220 +#define CS35L41_DTEMP_CFG 0x00004224 +#define CS35L41_DTEMP_EN 0x00004308 +#define CS35L41_VPVBST_FS_SEL 0x00004400 +#define CS35L41_SP_ENABLES 0x00004800 +#define CS35L41_SP_RATE_CTRL 0x00004804 +#define CS35L41_SP_FORMAT 0x00004808 +#define CS35L41_SP_HIZ_CTRL 0x0000480C +#define CS35L41_SP_FRAME_TX_SLOT 0x00004810 +#define CS35L41_SP_FRAME_RX_SLOT 0x00004820 +#define CS35L41_SP_TX_WL 0x00004830 +#define CS35L41_SP_RX_WL 0x00004840 +#define CS35L41_ASP_CONTROL4 0x00004854 +#define CS35L41_DAC_PCM1_SRC 0x00004C00 +#define CS35L41_ASP_TX1_SRC 0x00004C20 +#define CS35L41_ASP_TX2_SRC 0x00004C24 +#define CS35L41_ASP_TX3_SRC 0x00004C28 +#define CS35L41_ASP_TX4_SRC 0x00004C2C +#define CS35L41_DSP1_RX1_SRC 0x00004C40 +#define CS35L41_DSP1_RX2_SRC 0x00004C44 +#define CS35L41_DSP1_RX3_SRC 0x00004C48 +#define CS35L41_DSP1_RX4_SRC 0x00004C4C +#define CS35L41_DSP1_RX5_SRC 0x00004C50 +#define CS35L41_DSP1_RX6_SRC 0x00004C54 +#define CS35L41_DSP1_RX7_SRC 0x00004C58 +#define CS35L41_DSP1_RX8_SRC 0x00004C5C +#define CS35L41_NGATE1_SRC 0x00004C60 +#define CS35L41_NGATE2_SRC 0x00004C64 +#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000 +#define CS35L41_VPBR_CFG 0x00006404 +#define CS35L41_VBBR_CFG 0x00006408 +#define CS35L41_VPBR_STATUS 0x0000640C +#define CS35L41_VBBR_STATUS 0x00006410 +#define CS35L41_OVERTEMP_CFG 0x00006414 +#define CS35L41_AMP_ERR_VOL 0x00006418 +#define CS35L41_VOL_STATUS_TO_DSP 0x00006450 +#define CS35L41_CLASSH_CFG 0x00006800 +#define CS35L41_WKFET_CFG 0x00006804 +#define CS35L41_NG_CFG 0x00006808 +#define CS35L41_AMP_GAIN_CTRL 0x00006C04 +#define CS35L41_DAC_MSM_CFG 0x00007400 +#define CS35L41_IRQ1_CFG 0x00010000 +#define CS35L41_IRQ1_STATUS 0x00010004 +#define CS35L41_IRQ1_STATUS1 0x00010010 +#define CS35L41_IRQ1_STATUS2 0x00010014 +#define CS35L41_IRQ1_STATUS3 0x00010018 +#define CS35L41_IRQ1_STATUS4 0x0001001C +#define CS35L41_IRQ1_RAW_STATUS1 0x00010090 +#define CS35L41_IRQ1_RAW_STATUS2 0x00010094 +#define CS35L41_IRQ1_RAW_STATUS3 0x00010098 +#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C +#define CS35L41_IRQ1_MASK1 0x00010110 +#define CS35L41_IRQ1_MASK2 0x00010114 +#define CS35L41_IRQ1_MASK3 0x00010118 +#define CS35L41_IRQ1_MASK4 0x0001011C +#define CS35L41_IRQ1_FRC1 0x00010190 +#define CS35L41_IRQ1_FRC2 0x00010194 +#define CS35L41_IRQ1_FRC3 0x00010198 +#define CS35L41_IRQ1_FRC4 0x0001019C +#define CS35L41_IRQ1_EDGE1 0x00010210 +#define CS35L41_IRQ1_EDGE4 0x0001021C +#define CS35L41_IRQ1_POL1 0x00010290 +#define CS35L41_IRQ1_POL2 0x00010294 +#define CS35L41_IRQ1_POL3 0x00010298 +#define CS35L41_IRQ1_POL4 0x0001029C +#define CS35L41_IRQ1_DB3 0x00010318 +#define CS35L41_IRQ2_CFG 0x00010800 +#define CS35L41_IRQ2_STATUS 0x00010804 +#define CS35L41_IRQ2_STATUS1 0x00010810 +#define CS35L41_IRQ2_STATUS2 0x00010814 +#define CS35L41_IRQ2_STATUS3 0x00010818 +#define CS35L41_IRQ2_STATUS4 0x0001081C +#define CS35L41_IRQ2_RAW_STATUS1 0x00010890 +#define CS35L41_IRQ2_RAW_STATUS2 0x00010894 +#define CS35L41_IRQ2_RAW_STATUS3 0x00010898 +#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C +#define CS35L41_IRQ2_MASK1 0x00010910 +#define CS35L41_IRQ2_MASK2 0x00010914 +#define CS35L41_IRQ2_MASK3 0x00010918 +#define CS35L41_IRQ2_MASK4 0x0001091C +#define CS35L41_IRQ2_FRC1 0x00010990 +#define CS35L41_IRQ2_FRC2 0x00010994 +#define CS35L41_IRQ2_FRC3 0x00010998 +#define CS35L41_IRQ2_FRC4 0x0001099C +#define CS35L41_IRQ2_EDGE1 0x00010A10 +#define CS35L41_IRQ2_EDGE4 0x00010A1C +#define CS35L41_IRQ2_POL1 0x00010A90 +#define CS35L41_IRQ2_POL2 0x00010A94 +#define CS35L41_IRQ2_POL3 0x00010A98 +#define CS35L41_IRQ2_POL4 0x00010A9C +#define CS35L41_IRQ2_DB3 0x00010B18 +#define CS35L41_GPIO_STATUS1 0x00011000 +#define CS35L41_GPIO1_CTRL1 0x00011008 +#define CS35L41_GPIO2_CTRL1 0x0001100C +#define CS35L41_MIXER_NGATE_CFG 0x00012000 +#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004 +#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008 +#define CS35L41_DSP_MBOX_1 0x00013000 +#define CS35L41_DSP_MBOX_2 0x00013004 +#define CS35L41_DSP_MBOX_3 0x00013008 +#define CS35L41_DSP_MBOX_4 0x0001300C +#define CS35L41_DSP_MBOX_5 0x00013010 +#define CS35L41_DSP_MBOX_6 0x00013014 +#define CS35L41_DSP_MBOX_7 0x00013018 +#define CS35L41_DSP_MBOX_8 0x0001301C +#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020 +#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024 +#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028 +#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C +#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030 +#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034 +#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038 +#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C +#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040 +#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044 +#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048 +#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C +#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050 +#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054 +#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058 +#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C +#define CS35L41_CLOCK_DETECT_1 0x00014000 +#define CS35L41_TIMER1_CONTROL 0x00015000 +#define CS35L41_TIMER1_COUNT_PRESET 0x00015004 +#define CS35L41_TIMER1_START_STOP 0x0001500C +#define CS35L41_TIMER1_STATUS 0x00015010 +#define CS35L41_TIMER1_COUNT_READBACK 0x00015014 +#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018 +#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C +#define CS35L41_TIMER2_CONTROL 0x00015100 +#define CS35L41_TIMER2_COUNT_PRESET 0x00015104 +#define CS35L41_TIMER2_START_STOP 0x0001510C +#define CS35L41_TIMER2_STATUS 0x00015110 +#define CS35L41_TIMER2_COUNT_READBACK 0x00015114 +#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118 +#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C +#define CS35L41_DFT_JTAG_CONTROL 0x00016000 +#define CS35L41_DIE_STS1 0x00017040 +#define CS35L41_DIE_STS2 0x00017044 +#define CS35L41_TEMP_CAL1 0x00017048 +#define CS35L41_TEMP_CAL2 0x0001704C +#define CS35L41_DSP1_XMEM_PACK_0 0x02000000 +#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0 +#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000 +#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8 +#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800 +#define CS35L41_DSP1_SYS_ID 0x025E0000 +#define CS35L41_DSP1_SYS_VERSION 0x025E0004 +#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008 +#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C +#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010 +#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018 +#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020 +#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028 +#define CS35L41_DSP1_SYS_FEATURES 0x025E002C +#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030 +#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034 +#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038 +#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C +#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040 +#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000 +#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004 +#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008 +#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C +#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010 +#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014 +#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018 +#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C +#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020 +#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024 +#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028 +#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C +#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030 +#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034 +#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038 +#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040 +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044 +#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000 +#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4 +#define CS35L41_DSP1_CTRL_BASE 0x02B80000 +#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010 +#define CS35L41_DSP1_DEBUG 0x02B80040 +#define CS35L41_DSP1_TIMER_CTRL 0x02B80048 +#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050 +#define CS35L41_DSP1_RX1_RATE 0x02B80080 +#define CS35L41_DSP1_RX2_RATE 0x02B80088 +#define CS35L41_DSP1_RX3_RATE 0x02B80090 +#define CS35L41_DSP1_RX4_RATE 0x02B80098 +#define CS35L41_DSP1_RX5_RATE 0x02B800A0 +#define CS35L41_DSP1_RX6_RATE 0x02B800A8 +#define CS35L41_DSP1_RX7_RATE 0x02B800B0 +#define CS35L41_DSP1_RX8_RATE 0x02B800B8 +#define CS35L41_DSP1_TX1_RATE 0x02B80280 +#define CS35L41_DSP1_TX2_RATE 0x02B80288 +#define CS35L41_DSP1_TX3_RATE 0x02B80290 +#define CS35L41_DSP1_TX4_RATE 0x02B80298 +#define CS35L41_DSP1_TX5_RATE 0x02B802A0 +#define CS35L41_DSP1_TX6_RATE 0x02B802A8 +#define CS35L41_DSP1_TX7_RATE 0x02B802B0 +#define CS35L41_DSP1_TX8_RATE 0x02B802B8 +#define CS35L41_DSP1_NMI_CTRL1 0x02B80480 +#define CS35L41_DSP1_NMI_CTRL2 0x02B80488 +#define CS35L41_DSP1_NMI_CTRL3 0x02B80490 +#define CS35L41_DSP1_NMI_CTRL4 0x02B80498 +#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0 +#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8 +#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0 +#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8 +#define CS35L41_DSP1_RESUME_CTRL 0x02B80500 +#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508 +#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510 +#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518 +#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520 +#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528 +#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530 +#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538 +#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540 +#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548 +#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550 +#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558 +#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560 +#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568 +#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570 +#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578 +#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580 +#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588 +#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590 +#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598 +#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0 +#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8 +#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0 +#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8 +#define CS35L41_DSP1_SCRATCH1 0x02B805C0 +#define CS35L41_DSP1_SCRATCH2 0x02B805C8 +#define CS35L41_DSP1_SCRATCH3 0x02B805D0 +#define CS35L41_DSP1_SCRATCH4 0x02B805D8 +#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000 +#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008 +#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000 +#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008 +#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010 +#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018 +#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020 +#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078 +#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0 +#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8 +#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0 +#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8 +#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0 +#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138 +#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180 +#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188 +#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C +#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190 +#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194 +#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198 +#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C +#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0 +#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4 +#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8 +#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC +#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0 +#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4 +#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8 +#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC +#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0 +#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4 +#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8 +#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC +#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0 +#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4 +#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8 +#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC +#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0 +#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4 +#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8 +#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC +#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0 +#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4 +#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8 +#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC +#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200 +#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204 +#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000 +#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004 +#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008 +#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C +#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014 +#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018 +#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C +#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020 +#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024 +#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C +#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030 +#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034 +#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038 +#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C +#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044 +#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048 +#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C +#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050 +#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054 +#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C +#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100 +#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104 +#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108 +#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C +#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110 +#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114 +#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140 +#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078 +#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200 +#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204 +#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208 +#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C +#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210 +#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214 +#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218 +#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C +#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220 +#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224 +#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228 +#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C +#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230 +#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234 +#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238 +#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C +#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400 +#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404 +#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408 +#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C +#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410 +#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414 +#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418 +#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C +#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420 +#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424 +#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428 +#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C +#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430 +#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434 +#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438 +#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C +#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678 +#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00 +#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08 +#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000 +#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004 +#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008 +#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010 +#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014 +#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018 +#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C +#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024 +#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C +#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030 +#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034 +#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038 +#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040 +#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000 +#define CS35L41_DSP1_WDT_STATUS 0x02BC7008 +#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000 +#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0 +#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000 +#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8 +#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000 +#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4 +#define CS35L41_DSP1_PMEM_0 0x03800000 +#define CS35L41_DSP1_PMEM_5114 0x03804FE8 + +/*test regs for emulation bringup*/ +#define CS35L41_PLL_OVR 0x00003018 +#define CS35L41_BST_TEST_DUTY 0x00003900 +#define CS35L41_DIGPWM_IOCTRL 0x0000706C + +/*registers populated by OTP*/ +#define CS35L41_OTP_TRIM_1 0x0000208c +#define CS35L41_OTP_TRIM_2 0x00002090 +#define CS35L41_OTP_TRIM_3 0x00003010 +#define CS35L41_OTP_TRIM_4 0x0000300C +#define CS35L41_OTP_TRIM_5 0x0000394C +#define CS35L41_OTP_TRIM_6 0x00003950 +#define CS35L41_OTP_TRIM_7 0x00003954 +#define CS35L41_OTP_TRIM_8 0x00003958 +#define CS35L41_OTP_TRIM_9 0x0000395C +#define CS35L41_OTP_TRIM_10 0x0000416C +#define CS35L41_OTP_TRIM_11 0x00004160 +#define CS35L41_OTP_TRIM_12 0x00004170 +#define CS35L41_OTP_TRIM_13 0x00004360 +#define CS35L41_OTP_TRIM_14 0x00004448 +#define CS35L41_OTP_TRIM_15 0x0000444C +#define CS35L41_OTP_TRIM_16 0x00006E30 +#define CS35L41_OTP_TRIM_17 0x00006E34 +#define CS35L41_OTP_TRIM_18 0x00006E38 +#define CS35L41_OTP_TRIM_19 0x00006E3C +#define CS35L41_OTP_TRIM_20 0x00006E40 +#define CS35L41_OTP_TRIM_21 0x00006E44 +#define CS35L41_OTP_TRIM_22 0x00006E48 +#define CS35L41_OTP_TRIM_23 0x00006E4C +#define CS35L41_OTP_TRIM_24 0x00006E50 +#define CS35L41_OTP_TRIM_25 0x00006E54 +#define CS35L41_OTP_TRIM_26 0x00006E58 +#define CS35L41_OTP_TRIM_27 0x00006E5C +#define CS35L41_OTP_TRIM_28 0x00006E60 +#define CS35L41_OTP_TRIM_29 0x00006E64 +#define CS35L41_OTP_TRIM_30 0x00007418 +#define CS35L41_OTP_TRIM_31 0x0000741C +#define CS35L41_OTP_TRIM_32 0x00007434 +#define CS35L41_OTP_TRIM_33 0x00007068 +#define CS35L41_OTP_TRIM_34 0x0000410C +#define CS35L41_OTP_TRIM_35 0x0000400C +#define CS35L41_OTP_TRIM_36 0x00002030 + +#define CS35L41_MAX_CACHE_REG 36 +#define CS35L41_OTP_SIZE_WORDS 32 + +#define CS35L41_NUM_SUPPLIES 2 + +#define CS35L41_SCLK_MSTR_MASK 0x10 +#define CS35L41_SCLK_MSTR_SHIFT 4 +#define CS35L41_LRCLK_MSTR_MASK 0x01 +#define CS35L41_LRCLK_MSTR_SHIFT 0 +#define CS35L41_SCLK_INV_MASK 0x40 +#define CS35L41_SCLK_INV_SHIFT 6 +#define CS35L41_LRCLK_INV_MASK 0x04 +#define CS35L41_LRCLK_INV_SHIFT 2 +#define CS35L41_SCLK_FRC_MASK 0x20 +#define CS35L41_SCLK_FRC_SHIFT 5 +#define CS35L41_LRCLK_FRC_MASK 0x02 +#define CS35L41_LRCLK_FRC_SHIFT 1 + +#define CS35L41_AMP_GAIN_PCM_MASK 0x3E0 +#define CS35L41_AMP_GAIN_PCM_SHIFT 5 +#define CS35L41_AMP_GAIN_PDM_MASK 0x1F +#define CS35L41_AMP_GAIN_PDM_SHIFT 0 +#define CS35L41_AMP_GAIN_PCM_MAX 20 +#define CS35L41_AMP_GAIN_PDM_MAX 20 +#define CS35L41_AMP_GAIN_ZC_MASK 0x0400 +#define CS35L41_AMP_GAIN_ZC_SHIFT 10 + +#define CS35L41_BST_CTL_MASK 0xFF +#define CS35L41_BST_CTL_SEL_MASK 0x03 +#define CS35L41_BST_CTL_SEL_REG 0x00 +#define CS35L41_BST_CTL_SEL_CLASSH 0x01 +#define CS35L41_BST_IPK_MASK 0x7F +#define CS35L41_BST_IPK_SHIFT 0 +#define CS35L41_BST_LIM_MASK 0x4 +#define CS35L41_BST_LIM_SHIFT 2 +#define CS35L41_BST_K1_MASK 0x000000FF +#define CS35L41_BST_K1_SHIFT 0 +#define CS35L41_BST_K2_MASK 0x0000FF00 +#define CS35L41_BST_K2_SHIFT 8 +#define CS35L41_BST_SLOPE_MASK 0x0000FF00 +#define CS35L41_BST_SLOPE_SHIFT 8 +#define CS35L41_BST_LBST_VAL_MASK 0x00000003 +#define CS35L41_BST_LBST_VAL_SHIFT 0 + +#define CS35L41_TEMP_THLD_MASK 0x03 +#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF +#define CS35L41_PDM_MODE_MASK 0x01 +#define CS35L41_PDM_MODE_SHIFT 0 + +#define CS35L41_CH_MEM_DEPTH_MASK 0x07 +#define CS35L41_CH_MEM_DEPTH_SHIFT 0 +#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000 +#define CS35L41_CH_HDRM_CTL_SHIFT 16 +#define CS35L41_CH_REL_RATE_MASK 0xFF00 +#define CS35L41_CH_REL_RATE_SHIFT 8 +#define CS35L41_CH_WKFET_DLY_MASK 0x001C +#define CS35L41_CH_WKFET_DLY_SHIFT 2 +#define CS35L41_CH_WKFET_THLD_MASK 0x0F00 +#define CS35L41_CH_WKFET_THLD_SHIFT 8 + +#define CS35L41_HW_NG_SEL_MASK 0x3F00 +#define CS35L41_HW_NG_SEL_SHIFT 8 +#define CS35L41_HW_NG_DLY_MASK 0x0070 +#define CS35L41_HW_NG_DLY_SHIFT 4 +#define CS35L41_HW_NG_THLD_MASK 0x0007 +#define CS35L41_HW_NG_THLD_SHIFT 0 + +#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000 +#define CS35L41_DSP_NG_ENABLE_SHIFT 16 +#define CS35L41_DSP_NG_THLD_MASK 0x7 +#define CS35L41_DSP_NG_THLD_SHIFT 0 +#define CS35L41_DSP_NG_DELAY_MASK 0x0F00 +#define CS35L41_DSP_NG_DELAY_SHIFT 8 + +#define CS35L41_ASP_RX1_EN_MASK 0x00010000 +#define CS35L41_ASP_RX1_EN_SHIFT 16 +#define CS35L41_ASP_RX2_EN_MASK 0x00020000 +#define CS35L41_ASP_RX2_EN_SHIFT 17 +#define CS35L41_ASP_TX1_EN_MASK 0x00000001 +#define CS35L41_ASP_TX1_EN_SHIFT 0 +#define CS35L41_ASP_TX2_EN_MASK 0x00000002 +#define CS35L41_ASP_TX2_EN_SHIFT 1 +#define CS35L41_ASP_TX3_EN_MASK 0x00000004 +#define CS35L41_ASP_TX3_EN_SHIFT 2 +#define CS35L41_ASP_TX4_EN_MASK 0x00000008 +#define CS35L41_ASP_TX4_EN_SHIFT 3 +#define CS35L41_ASP_FMT_MASK 0x0700 +#define CS35L41_ASP_FMT_SHIFT 8 +#define CS35L41_ASP_DOUT_HIZ_MASK 0x03 +#define CS35L41_ASP_DOUT_HIZ_SHIFT 0 +#define CS35L41_ASP_WIDTH_16 0x10 +#define CS35L41_ASP_WIDTH_24 0x18 +#define CS35L41_ASP_WIDTH_32 0x20 +#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000 +#define CS35L41_ASP_WIDTH_TX_SHIFT 16 +#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000 +#define CS35L41_ASP_WIDTH_RX_SHIFT 24 +#define CS35L41_ASP_RX1_SLOT_MASK 0x3F +#define CS35L41_ASP_RX1_SLOT_SHIFT 0 +#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00 +#define CS35L41_ASP_RX2_SLOT_SHIFT 8 +#define CS35L41_ASP_RX_WL_MASK 0x3F +#define CS35L41_ASP_TX_WL_MASK 0x3F +#define CS35L41_ASP_RX_WL_SHIFT 0 +#define CS35L41_ASP_TX_WL_SHIFT 0 +#define CS35L41_ASP_SOURCE_MASK 0x7F + +#define CS35L41_INPUT_SRC_ASPRX1 0x08 +#define CS35L41_INPUT_SRC_ASPRX2 0x09 +#define CS35L41_INPUT_SRC_VMON 0x18 +#define CS35L41_INPUT_SRC_IMON 0x19 +#define CS35L41_INPUT_SRC_CLASSH 0x21 +#define CS35L41_INPUT_SRC_VPMON 0x28 +#define CS35L41_INPUT_SRC_VBSTMON 0x29 +#define CS35L41_INPUT_SRC_TEMPMON 0x3A +#define CS35L41_INPUT_SRC_RSVD 0x3B +#define CS35L41_INPUT_DSP_TX1 0x32 +#define CS35L41_INPUT_DSP_TX2 0x33 + +#define CS35L41_WR_PEND_STS_MASK 0x2 + +#define CS35L41_PLL_CLK_SEL_MASK 0x07 +#define CS35L41_PLL_CLK_SEL_SHIFT 0 +#define CS35L41_PLL_CLK_EN_MASK 0x10 +#define CS35L41_PLL_CLK_EN_SHIFT 4 +#define CS35L41_PLL_OPENLOOP_MASK 0x0800 +#define CS35L41_PLL_OPENLOOP_SHIFT 11 +#define CS35L41_PLLSRC_SCLK 0 +#define CS35L41_PLLSRC_LRCLK 1 +#define CS35L41_PLLSRC_SELF 3 +#define CS35L41_PLLSRC_PDMCLK 4 +#define CS35L41_PLLSRC_MCLK 5 +#define CS35L41_PLLSRC_SWIRE 7 +#define CS35L41_REFCLK_FREQ_MASK 0x7E0 +#define CS35L41_REFCLK_FREQ_SHIFT 5 + +#define CS35L41_GLOBAL_FS_MASK 0x1F +#define CS35L41_GLOBAL_FS_SHIFT 0 + +#define CS35L41_GLOBAL_EN_MASK 0x01 +#define CS35L41_GLOBAL_EN_SHIFT 0 +#define CS35L41_BST_EN_MASK 0x0030 +#define CS35L41_BST_EN_SHIFT 4 +#define CS35L41_BST_DIS_FET_OFF 0x00 +#define CS35L41_BST_EN_DEFAULT 0x2 +#define CS35L41_AMP_EN_SHIFT 0 +#define CS35L41_AMP_EN_MASK 1 +#define CS35L41_VMON_EN_MASK 0x1000 +#define CS35L41_VMON_EN_SHIFT 12 +#define CS35L41_IMON_EN_MASK 0x2000 +#define CS35L41_IMON_EN_SHIFT 13 + +#define CS35L41_PDN_DONE_MASK 0x00800000 +#define CS35L41_PDN_DONE_SHIFT 23 +#define CS35L41_PUP_DONE_MASK 0x01000000 +#define CS35L41_PUP_DONE_SHIFT 24 + +#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F +#define CS35L36_PUP_DONE_IRQ_MASK 0xBF +#define CS35L41_SYNC_EN_MASK BIT(8) + +#define CS35L41_AMP_SHORT_ERR 0x80000000 +#define CS35L41_BST_SHORT_ERR 0x0100 +#define CS35L41_TEMP_WARN 0x8000 +#define CS35L41_TEMP_ERR 0x00020000 +#define CS35L41_BST_OVP_ERR 0x40 +#define CS35L41_BST_DCM_UVP_ERR 0x80 +#define CS35L41_OTP_BOOT_DONE 0x02 +#define CS35L41_PLL_UNLOCK 0x10 +#define CS35L41_PLL_LOCK BIT(1) +#define CS35L41_OTP_BOOT_ERR 0x80000000 + +#define CS35L41_AMP_SHORT_ERR_RLS 0x02 +#define CS35L41_BST_SHORT_ERR_RLS 0x04 +#define CS35L41_BST_OVP_ERR_RLS 0x08 +#define CS35L41_BST_UVP_ERR_RLS 0x10 +#define CS35L41_TEMP_WARN_ERR_RLS 0x20 +#define CS35L41_TEMP_ERR_RLS 0x40 + +#define CS35L41_AMP_SHORT_ERR_RLS_SHIFT 1 +#define CS35L41_BST_SHORT_ERR_RLS_SHIFT 2 +#define CS35L41_BST_OVP_ERR_RLS_SHIFT 3 +#define CS35L41_BST_UVP_ERR_RLS_SHIFT 4 +#define CS35L41_TEMP_WARN_ERR_RLS_SHIFT 5 +#define CS35L41_TEMP_ERR_RLS_SHIFT 6 + +#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F +#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF +#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF +#define CS35L41_INT3_PLL_LOCK_SHIFT 1 +#define CS35L41_INT3_PLL_LOCK_MASK BIT(CS35L41_INT3_PLL_LOCK_SHIFT) + +#define CS35L41_GPIO_DIR_MASK 0x80000000 +#define CS35L41_GPIO_DIR_SHIFT 31 +#define CS35L41_GPIO1_CTRL_MASK 0x00030000 +#define CS35L41_GPIO1_CTRL_SHIFT 16 +#define CS35L41_GPIO2_CTRL_MASK 0x07000000 +#define CS35L41_GPIO2_CTRL_SHIFT 24 +#define CS35L41_GPIO_LVL_SHIFT 15 +#define CS35L41_GPIO_LVL_MASK BIT(CS35L41_GPIO_LVL_SHIFT) +#define CS35L41_GPIO_POL_MASK 0x1000 +#define CS35L41_GPIO_POL_SHIFT 12 + +#define CS35L41_AMP_INV_PCM_SHIFT 14 +#define CS35L41_AMP_INV_PCM_MASK BIT(CS35L41_AMP_INV_PCM_SHIFT) +#define CS35L41_AMP_PCM_VOL_SHIFT 3 +#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3) +#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF + +#define CS35L41_CHIP_ID 0x35a40 +#define CS35L41R_CHIP_ID 0x35b40 +#define CS35L41_MTLREVID_MASK 0x0F +#define CS35L41_REVID_A0 0xA0 +#define CS35L41_REVID_B0 0xB0 +#define CS35L41_REVID_B2 0xB2 + +#define CS35L41_HALO_CORE_RESET 0x00000200 +#define CS35L41_SOFTWARE_RESET 0x5A000000 + +#define CS35L41_FS1_WINDOW_MASK 0x000007FF +#define CS35L41_FS2_WINDOW_MASK 0x00FFF800 +#define CS35L41_FS2_WINDOW_SHIFT 12 + +#define CS35L41_SPI_MAX_FREQ 4000000 +#define CS35L41_REGSTRIDE 4 + +enum cs35l41_boost_type { + CS35L41_INT_BOOST, + CS35L41_EXT_BOOST, + CS35L41_SHD_BOOST_ACTV, + CS35L41_SHD_BOOST_PASS, + + // Not present in Binding Documentation, so no system should use this value. + // This value is only used in CLSA0100 Laptop + CS35L41_EXT_BOOST_NO_VSPK_SWITCH, +}; + +enum cs35l41_clk_ids { + CS35L41_CLKID_SCLK = 0, + CS35L41_CLKID_LRCLK = 1, + CS35L41_CLKID_MCLK = 4, +}; + +enum cs35l41_gpio1_func { + CS35L41_GPIO1_HIZ, + CS35L41_GPIO1_GPIO, + CS35L41_GPIO1_MDSYNC, + CS35L41_GPIO1_MCLK, + CS35L41_GPIO1_PDM_CLK, + CS35L41_GPIO1_PDM_DATA, +}; + +enum cs35l41_gpio2_func { + CS35L41_GPIO2_HIZ, + CS35L41_GPIO2_GPIO, + CS35L41_GPIO2_INT_OPEN_DRAIN, + CS35L41_GPIO2_MCLK, + CS35L41_GPIO2_INT_PUSH_PULL_LOW, + CS35L41_GPIO2_INT_PUSH_PULL_HIGH, + CS35L41_GPIO2_PDM_CLK, + CS35L41_GPIO2_PDM_DATA, +}; + +struct cs35l41_gpio_cfg { + bool valid; + bool pol_inv; + bool out_en; + unsigned int func; +}; + +struct cs35l41_hw_cfg { + bool valid; + int bst_ind; + int bst_ipk; + int bst_cap; + int dout_hiz; + struct cs35l41_gpio_cfg gpio1; + struct cs35l41_gpio_cfg gpio2; + unsigned int spk_pos; + + enum cs35l41_boost_type bst_type; +}; + +struct cs35l41_otp_packed_element_t { + u32 reg; + u8 shift; + u8 size; +}; + +struct cs35l41_otp_map_element_t { + u32 id; + u32 num_elements; + const struct cs35l41_otp_packed_element_t *map; + u32 bit_offset; + u32 word_offset; +}; + +enum cs35l41_cspl_mbox_status { + CSPL_MBOX_STS_ERROR = U32_MAX, + CSPL_MBOX_STS_ERROR2 = 0x00ffffff, // firmware not always sign-extending 24-bit value + CSPL_MBOX_STS_RUNNING = 0, + CSPL_MBOX_STS_PAUSED = 1, + CSPL_MBOX_STS_RDY_FOR_REINIT = 2, +}; + +enum cs35l41_cspl_mbox_cmd { + CSPL_MBOX_CMD_NONE = 0, + CSPL_MBOX_CMD_PAUSE = 1, + CSPL_MBOX_CMD_RESUME = 2, + CSPL_MBOX_CMD_REINIT = 3, + CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, + CSPL_MBOX_CMD_HIBERNATE = 5, + CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, + CSPL_MBOX_CMD_SPK_OUT_ENABLE = 7, + CSPL_MBOX_CMD_UNKNOWN_CMD = -1, + CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, +}; + +/* + * IRQs + */ +#define CS35L41_IRQ(_irq, _name, _hand) \ + { \ + .irq = CS35L41_ ## _irq ## _IRQ,\ + .name = _name, \ + .handler = _hand, \ + } + +struct cs35l41_irq { + int irq; + const char *name; + irqreturn_t (*handler)(int irq, void *data); +}; + +#define CS35L41_REG_IRQ(_reg, _irq) \ + [CS35L41_ ## _irq ## _IRQ] = { \ + .reg_offset = (CS35L41_ ## _reg) - CS35L41_IRQ1_STATUS1,\ + .mask = CS35L41_ ## _irq ## _MASK \ + } + +/* (0x0000E010) CS35L41_IRQ1_STATUS1 */ +#define CS35L41_BST_OVP_ERR_SHIFT 6 +#define CS35L41_BST_OVP_ERR_MASK BIT(CS35L41_BST_OVP_ERR_SHIFT) +#define CS35L41_BST_DCM_UVP_ERR_SHIFT 7 +#define CS35L41_BST_DCM_UVP_ERR_MASK BIT(CS35L41_BST_DCM_UVP_ERR_SHIFT) +#define CS35L41_BST_SHORT_ERR_SHIFT 8 +#define CS35L41_BST_SHORT_ERR_MASK BIT(CS35L41_BST_SHORT_ERR_SHIFT) +#define CS35L41_TEMP_WARN_SHIFT 15 +#define CS35L41_TEMP_WARN_MASK BIT(CS35L41_TEMP_WARN_SHIFT) +#define CS35L41_TEMP_ERR_SHIFT 17 +#define CS35L41_TEMP_ERR_MASK BIT(CS35L41_TEMP_ERR_SHIFT) +#define CS35L41_AMP_SHORT_ERR_SHIFT 31 +#define CS35L41_AMP_SHORT_ERR_MASK BIT(CS35L41_AMP_SHORT_ERR_SHIFT) + +enum cs35l41_irq_list { + CS35L41_BST_OVP_ERR_IRQ, + CS35L41_BST_DCM_UVP_ERR_IRQ, + CS35L41_BST_SHORT_ERR_IRQ, + CS35L41_TEMP_WARN_IRQ, + CS35L41_TEMP_ERR_IRQ, + CS35L41_AMP_SHORT_ERR_IRQ, + + CS35L41_NUM_IRQ +}; + +extern struct regmap_config cs35l41_regmap_i2c; +extern struct regmap_config cs35l41_regmap_spi; + +int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap); +int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap); +int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap); +int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid); +int cs35l41_set_channels(struct device *dev, struct regmap *reg, + unsigned int tx_num, const unsigned int *tx_slot, + unsigned int rx_num, const unsigned int *rx_slot); +int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); +void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp); +int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap, + enum cs35l41_cspl_mbox_cmd cmd); +int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap); +int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap, + enum cs35l41_boost_type b_type); +int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap); +int cs35l41_init_boost(struct device *dev, struct regmap *regmap, + struct cs35l41_hw_cfg *hw_cfg); +bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type); +int cs35l41_mdsync_up(struct regmap *regmap); +int cs35l41_global_enable(struct device *dev, struct regmap *regmap, enum cs35l41_boost_type b_type, + int enable, struct cs_dsp *dsp); + +#endif /* __CS35L41_H */ diff --git a/include/sound/cs35l56.h b/include/sound/cs35l56.h new file mode 100644 index 000000000..45a5df574 --- /dev/null +++ b/include/sound/cs35l56.h @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common definitions for Cirrus Logic CS35L56 smart amp + * + * Copyright (C) 2023 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __CS35L56_H +#define __CS35L56_H + +#include +#include +#include +#include +#include +#include +#include + +struct snd_ctl_elem_value; + +#define CS35L56_DEVID 0x0000000 +#define CS35L56_REVID 0x0000004 +#define CS35L56_RELID 0x000000C +#define CS35L56_OTPID 0x0000010 +#define CS35L56_SFT_RESET 0x0000020 +#define CS35L56_GLOBAL_ENABLES 0x0002014 +#define CS35L56_BLOCK_ENABLES 0x0002018 +#define CS35L56_BLOCK_ENABLES2 0x000201C +#define CS35L56_SYNC_GPIO1_CFG 0x0002410 +#define CS35L56_ASP2_DIO_GPIO13_CFG 0x0002440 +#define CS35L56_UPDATE_REGS 0x0002A0C +#define CS35L56_REFCLK_INPUT 0x0002C04 +#define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C +#define CS35L56_ASP1_ENABLES1 0x0004800 +#define CS35L56_ASP1_CONTROL1 0x0004804 +#define CS35L56_ASP1_CONTROL2 0x0004808 +#define CS35L56_ASP1_CONTROL3 0x000480C +#define CS35L56_ASP1_FRAME_CONTROL1 0x0004810 +#define CS35L56_ASP1_FRAME_CONTROL5 0x0004820 +#define CS35L56_ASP1_DATA_CONTROL1 0x0004830 +#define CS35L56_ASP1_DATA_CONTROL5 0x0004840 +#define CS35L56_DACPCM1_INPUT 0x0004C00 +#define CS35L56_DACPCM2_INPUT 0x0004C08 +#define CS35L56_ASP1TX1_INPUT 0x0004C20 +#define CS35L56_ASP1TX2_INPUT 0x0004C24 +#define CS35L56_ASP1TX3_INPUT 0x0004C28 +#define CS35L56_ASP1TX4_INPUT 0x0004C2C +#define CS35L56_DSP1RX1_INPUT 0x0004C40 +#define CS35L56_DSP1RX2_INPUT 0x0004C44 +#define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70 +#define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74 +#define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78 +#define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C +#define CS35L56_IRQ1_CFG 0x000E000 +#define CS35L56_IRQ1_STATUS 0x000E004 +#define CS35L56_IRQ1_EINT_1 0x000E010 +#define CS35L56_IRQ1_EINT_2 0x000E014 +#define CS35L56_IRQ1_EINT_4 0x000E01C +#define CS35L56_IRQ1_EINT_8 0x000E02C +#define CS35L56_IRQ1_EINT_18 0x000E054 +#define CS35L56_IRQ1_EINT_20 0x000E05C +#define CS35L56_IRQ1_MASK_1 0x000E090 +#define CS35L56_IRQ1_MASK_2 0x000E094 +#define CS35L56_IRQ1_MASK_4 0x000E09C +#define CS35L56_IRQ1_MASK_8 0x000E0AC +#define CS35L56_IRQ1_MASK_18 0x000E0D4 +#define CS35L56_IRQ1_MASK_20 0x000E0DC +#define CS35L56_GPIO_STATUS1 0x000F000 +#define CS35L56_GPIO1_CTRL1 0x000F008 +#define CS35L56_GPIO13_CTRL1 0x000F038 +#define CS35L56_MIXER_NGATE_CH1_CFG 0x0010004 +#define CS35L56_MIXER_NGATE_CH2_CFG 0x0010008 +#define CS35L56_DSP_MBOX_1_RAW 0x0011000 +#define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020 +#define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024 +#define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028 +#define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C +#define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030 +#define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034 +#define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038 +#define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C +#define CS35L56_DIE_STS1 0x0017040 +#define CS35L56_DIE_STS2 0x0017044 +#define CS35L56_DSP_RESTRICT_STS1 0x00190F0 +#define CS35L56_OTP_MEM_53 0x00300D4 +#define CS35L56_OTP_MEM_54 0x00300D8 +#define CS35L56_OTP_MEM_55 0x00300DC +#define CS35L56_DSP1_XMEM_PACKED_0 0x2000000 +#define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC +#define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000 +#define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC +#define CS35L56_DSP1_SYS_INFO_ID 0x25E0000 +#define CS35L56_DSP1_SYS_INFO_END 0x25E004C +#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 +#define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 +#define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000 +#define CS35L56_DSP1_FW_VER 0x2800010 +#define CS35L56_DSP1_HALO_STATE 0x28021E0 +#define CS35L56_B2_DSP1_HALO_STATE 0x2803D20 +#define CS35L56_DSP1_PM_CUR_STATE 0x2804308 +#define CS35L56_B2_DSP1_PM_CUR_STATE 0x2804678 +#define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC +#define CS35L56_DSP1_CORE_BASE 0x2B80000 +#define CS35L56_DSP1_SCRATCH1 0x2B805C0 +#define CS35L56_DSP1_SCRATCH2 0x2B805C8 +#define CS35L56_DSP1_SCRATCH3 0x2B805D0 +#define CS35L56_DSP1_SCRATCH4 0x2B805D8 +#define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000 +#define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0 +#define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000 +#define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8 +#define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000 +#define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024 +#define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C +#define CS35L56_MAIN_POSTURE_NUMBER 0x3400094 +#define CS35L56_PROTECTION_STATUS 0x34000D8 +#define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150 +#define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4 +#define CS35L56_DSP1_PMEM_0 0x3800000 +#define CS35L56_DSP1_PMEM_5114 0x3804FE8 + +#define CS35L63_DSP1_FW_VER CS35L56_DSP1_FW_VER +#define CS35L63_DSP1_HALO_STATE 0x2803C04 +#define CS35L63_DSP1_PM_CUR_STATE 0x2804518 +#define CS35L63_PROTECTION_STATUS 0x340009C +#define CS35L63_TRANSDUCER_ACTUAL_PS 0x34000F4 +#define CS35L63_MAIN_RENDER_USER_MUTE 0x3400020 +#define CS35L63_MAIN_RENDER_USER_VOLUME 0x3400028 +#define CS35L63_MAIN_POSTURE_NUMBER 0x3400068 + +/* DEVID */ +#define CS35L56_DEVID_MASK 0x00FFFFFF + +/* REVID */ +#define CS35L56_AREVID_MASK 0x000000F0 +#define CS35L56_MTLREVID_MASK 0x0000000F +#define CS35L56_REVID_B0 0x000000B0 + +/* PAD_INTF */ +#define CS35L56_PAD_GPIO_PULL_MASK GENMASK(3, 2) +#define CS35L56_PAD_GPIO_IE BIT(0) + +#define CS35L56_PAD_PULL_NONE 0 +#define CS35L56_PAD_PULL_UP 1 +#define CS35L56_PAD_PULL_DOWN 2 + +/* UPDATE_REGS */ +#define CS35L56_UPDT_GPIO_PRES BIT(6) + +/* ASP_ENABLES1 */ +#define CS35L56_ASP_RX2_EN_SHIFT 17 +#define CS35L56_ASP_RX1_EN_SHIFT 16 +#define CS35L56_ASP_TX4_EN_SHIFT 3 +#define CS35L56_ASP_TX3_EN_SHIFT 2 +#define CS35L56_ASP_TX2_EN_SHIFT 1 +#define CS35L56_ASP_TX1_EN_SHIFT 0 + +/* ASP_CONTROL1 */ +#define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F +#define CS35L56_ASP_BCLK_FREQ_SHIFT 0 + +/* ASP_CONTROL2 */ +#define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000 +#define CS35L56_ASP_RX_WIDTH_SHIFT 24 +#define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000 +#define CS35L56_ASP_TX_WIDTH_SHIFT 16 +#define CS35L56_ASP_FMT_MASK 0x00000700 +#define CS35L56_ASP_FMT_SHIFT 8 +#define CS35L56_ASP_BCLK_INV_MASK 0x00000040 +#define CS35L56_ASP_FSYNC_INV_MASK 0x00000004 + +/* ASP_CONTROL3 */ +#define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003 + +/* ASP_DATA_CONTROL1 */ +#define CS35L56_ASP_TX_WL_MASK 0x0000003F + +/* ASP_DATA_CONTROL5 */ +#define CS35L56_ASP_RX_WL_MASK 0x0000003F + +/* ASPTXn_INPUT */ +#define CS35L56_ASP_TXn_SRC_MASK 0x0000007F + +/* SWIRETX[1..7]_SRC SDWTXn INPUT */ +#define CS35L56_SWIRETXn_SRC_MASK 0x0000007F + +/* IRQ1_STATUS */ +#define CS35L56_IRQ1_STS_MASK 0x00000001 + +/* IRQ1_EINT_1 */ +#define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000 + +/* IRQ1_EINT_2 */ +#define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000 + +/* IRQ1_EINT_4 */ +#define CS35L56_OTP_BOOT_DONE_MASK 0x00000002 + +/* IRQ1_EINT_8 */ +#define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000 + +/* MIXER_NGATE_CHn_CFG */ +#define CS35L56_AUX_NGATE_CHn_EN 0x00000001 + +/* GPIOn_CTRL1 */ +#define CS35L56_GPIO_DIR_MASK BIT(31) +#define CS35L56_GPIO_FN_MASK GENMASK(2, 0) + +#define CS35L56_GPIO_FN_GPIO 0x00000001 + +/* Mixer input sources */ +#define CS35L56_INPUT_SRC_NONE 0x00 +#define CS35L56_INPUT_SRC_ASP1RX1 0x08 +#define CS35L56_INPUT_SRC_ASP1RX2 0x09 +#define CS35L56_INPUT_SRC_VMON 0x18 +#define CS35L56_INPUT_SRC_IMON 0x19 +#define CS35L56_INPUT_SRC_ERR_VOL 0x20 +#define CS35L56_INPUT_SRC_CLASSH 0x21 +#define CS35L56_INPUT_SRC_VDDBMON 0x28 +#define CS35L56_INPUT_SRC_VBSTMON 0x29 +#define CS35L56_INPUT_SRC_DSP1TX1 0x32 +#define CS35L56_INPUT_SRC_DSP1TX2 0x33 +#define CS35L56_INPUT_SRC_DSP1TX3 0x34 +#define CS35L56_INPUT_SRC_DSP1TX4 0x35 +#define CS35L56_INPUT_SRC_DSP1TX5 0x36 +#define CS35L56_INPUT_SRC_DSP1TX6 0x37 +#define CS35L56_INPUT_SRC_DSP1TX7 0x38 +#define CS35L56_INPUT_SRC_DSP1TX8 0x39 +#define CS35L56_INPUT_SRC_TEMPMON 0x3A +#define CS35L56_INPUT_SRC_INTERPOLATOR 0x40 +#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44 +#define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45 +#define CS35L56_INPUT_MASK 0x7F + +#define CS35L56_NUM_INPUT_SRC 21 + +/* ASP formats */ +#define CS35L56_ASP_FMT_DSP_A 0 +#define CS35L56_ASP_FMT_I2S 2 + +/* ASP HiZ modes */ +#define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3 + +/* MAIN_RENDER_ACTUAL_PS */ +#define CS35L56_PS0 0 +#define CS35L56_PS3 3 + +/* CS35L56_DSP_RESTRICT_STS1 */ +#define CS35L56_RESTRICTED_MASK 0x7 + +/* CS35L56_MAIN_RENDER_USER_MUTE */ +#define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1 + +/* CS35L56_MAIN_RENDER_USER_VOLUME */ +#define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400 +#define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 48 +#define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0 +#define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6 +#define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9 + +/* CS35L56_MAIN_POSTURE_NUMBER */ +#define CS35L56_MAIN_POSTURE_MIN 0 +#define CS35L56_MAIN_POSTURE_MAX 255 +#define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX + +/* CS35L56_PROTECTION_STATUS */ +#define CS35L56_FIRMWARE_MISSING BIT(0) + +/* Software Values */ +#define CS35L56_HALO_STATE_SHUTDOWN 1 +#define CS35L56_HALO_STATE_BOOT_DONE 2 + +#define CS35L56_MBOX_CMD_PING 0x0A000000 +#define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001 +#define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002 +#define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003 +#define CS35L56_MBOX_CMD_AUDIO_CALIBRATION 0x0B000006 +#define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001 +#define CS35L56_MBOX_CMD_WAKEUP 0x02000002 +#define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003 +#define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004 +#define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005 +#define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007 + +#define CS35L56_MBOX_TIMEOUT_US 5000 +#define CS35L56_MBOX_POLL_US 250 + +#define CS35L56_FW_REQ_ACTIVE_TIMEOUT_MS 250 + +#define CS35L56_PS0_POLL_US 500 +#define CS35L56_PS0_TIMEOUT_US 50000 +#define CS35L56_PS3_POLL_US 500 +#define CS35L56_PS3_TIMEOUT_US 300000 + +#define CS35L56_CAL_STATUS_SUCCESS 1 +#define CS35L56_CAL_STATUS_OUT_OF_RANGE 3 + +#define CS35L56_CAL_SET_STATUS_UNKNOWN 0 +#define CS35L56_CAL_SET_STATUS_DEFAULT 1 +#define CS35L56_CAL_SET_STATUS_SET 2 + +#define CS35L56_CONTROL_PORT_READY_US 2200 +#define CS35L56_HALO_STATE_POLL_US 1000 +#define CS35L56_HALO_STATE_TIMEOUT_US 250000 +#define CS35L56_RESET_PULSE_MIN_US 1100 +#define CS35L56_WAKE_HOLD_TIME_US 1000 +#define CS35L56_PAD_PULL_SETTLE_US 10 + +#define CS35L56_CALIBRATION_POLL_US (100 * USEC_PER_MSEC) +#define CS35L56_CALIBRATION_TIMEOUT_US (5 * USEC_PER_SEC) + +#define CS35L56_SDW1_PLAYBACK_PORT 1 +#define CS35L56_SDW1_CAPTURE_PORT 3 + +#define CS35L56_NUM_BULK_SUPPLIES 3 +#define CS35L56_NUM_DSP_REGIONS 5 + +#define CS35L56_MAX_GPIO 13 +#define CS35L63_MAX_GPIO 9 + +/* Additional margin for SYSTEM_RESET to control port ready on SPI */ +#define CS35L56_SPI_RESET_TO_PORT_READY_US (CS35L56_CONTROL_PORT_READY_US + 2500) + +struct cs35l56_spi_payload { + __be32 addr; + __be16 pad; + __be32 value; +} __packed; +static_assert(sizeof(struct cs35l56_spi_payload) == 10); + +struct cs35l56_fw_reg { + unsigned int fw_ver; + unsigned int halo_state; + unsigned int pm_cur_stat; + unsigned int prot_sts; + unsigned int transducer_actual_ps; + unsigned int user_mute; + unsigned int user_volume; + unsigned int posture_number; +}; + +struct cs35l56_cal_debugfs_fops { + const struct debugfs_short_fops calibrate; + const struct debugfs_short_fops cal_temperature; + const struct debugfs_short_fops cal_data; +}; + +struct cs35l56_base { + struct device *dev; + struct regmap *regmap; + struct cs_dsp *dsp; + int irq; + struct mutex irq_lock; + u8 type; + u8 rev; + bool init_done; + bool fw_patched; + bool secured; + bool can_hibernate; + bool cal_data_valid; + s8 cal_index; + u8 num_amps; + struct cirrus_amp_cal_data cal_data; + struct gpio_desc *reset_gpio; + struct cs35l56_spi_payload *spi_payload_buf; + const struct cs35l56_fw_reg *fw_reg; + const struct cirrus_amp_cal_controls *calibration_controls; + struct dentry *debugfs; + u64 silicon_uid; + u8 onchip_spkid_gpios[5]; + u8 num_onchip_spkid_gpios; + u8 onchip_spkid_pulls[5]; + u8 num_onchip_spkid_pulls; +}; + +static inline bool cs35l56_is_otp_register(unsigned int reg) +{ + return (reg >> 16) == 3; +} + +static inline int cs35l56_init_config_for_spi(struct cs35l56_base *cs35l56, + struct spi_device *spi) +{ + cs35l56->spi_payload_buf = devm_kzalloc(&spi->dev, + sizeof(*cs35l56->spi_payload_buf), + GFP_KERNEL | GFP_DMA); + if (!cs35l56->spi_payload_buf) + return -ENOMEM; + + return 0; +} + +static inline bool cs35l56_is_spi(struct cs35l56_base *cs35l56) +{ + return IS_ENABLED(CONFIG_SPI_MASTER) && !!cs35l56->spi_payload_buf; +} + +extern const struct regmap_config cs35l56_regmap_i2c; +extern const struct regmap_config cs35l56_regmap_spi; +extern const struct regmap_config cs35l56_regmap_sdw; +extern const struct regmap_config cs35l63_regmap_i2c; +extern const struct regmap_config cs35l63_regmap_sdw; + +extern const struct cirrus_amp_cal_controls cs35l56_calibration_controls; +extern const char * const cs35l56_cal_set_status_text[3]; + +extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC]; +extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; + +int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base); +int cs35l56_set_patch(struct cs35l56_base *cs35l56_base); +int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command); +int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base); +int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base); +void cs35l56_wait_control_port_ready(void); +void cs35l56_wait_min_reset_pulse(void); +void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); +int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); +int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); +int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); +int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); +void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); +int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base); +int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, + const struct cirrus_amp_cal_data *data); +ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, + const char __user *from, size_t count, + loff_t *ppos); +ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, + const char __user *from, size_t count, + loff_t *ppos); +ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, + char __user *to, size_t count, + loff_t *ppos); +ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, + const char __user *from, size_t count, + loff_t *ppos); +int cs35l56_factory_calibrate(struct cs35l56_base *cs35l56_base); +void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, + const struct cs35l56_cal_debugfs_fops *fops); +void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base); +int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, + struct snd_ctl_elem_value *uvalue); +int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, + bool *fw_missing, unsigned int *fw_version); +void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base); +void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); +int cs35l56_hw_init(struct cs35l56_base *cs35l56_base); +int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base); +int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, + const u32 *gpios, int num_gpios, + const u32 *pulls, int num_pulls); +int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base); +int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base); +int cs35l56_get_bclk_freq_id(unsigned int freq); +void cs35l56_fill_supply_names(struct regulator_bulk_data *data); + +#endif /* ifndef __CS35L56_H */ diff --git a/include/sound/cs4231-regs.h b/include/sound/cs4231-regs.h new file mode 100644 index 000000000..806a55104 --- /dev/null +++ b/include/sound/cs4231-regs.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CS4231_REGS_H +#define __SOUND_CS4231_REGS_H + +/* + * Copyright (c) by Jaroslav Kysela + * Definitions for CS4231 & InterWave chips & compatible chips registers + */ + +/* IO ports */ + +#define CS4231P(x) (c_d_c_CS4231##x) + +#define c_d_c_CS4231REGSEL 0 +#define c_d_c_CS4231REG 1 +#define c_d_c_CS4231STATUS 2 +#define c_d_c_CS4231PIO 3 + +/* codec registers */ + +#define CS4231_LEFT_INPUT 0x00 /* left input control */ +#define CS4231_RIGHT_INPUT 0x01 /* right input control */ +#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ +#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ +#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ +#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ +#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ +#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ +#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ +#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ +#define CS4231_PIN_CTRL 0x0a /* pin control */ +#define CS4231_TEST_INIT 0x0b /* test and initialization */ +#define CS4231_MISC_INFO 0x0c /* miscellaneous information */ +#define CS4231_LOOPBACK 0x0d /* loopback control */ +#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ +#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ +#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ +#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ +#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ +#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ +#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ +#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ +#define CS4231_TIMER_LOW 0x14 /* timer low byte */ +#define CS4231_TIMER_HIGH 0x15 /* timer high byte */ +#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ +#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ +#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ +#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ +#define CS4236_EXT_REG 0x17 /* extended register access */ +#define CS4231_IRQ_STATUS 0x18 /* irq status register */ +#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ +#define CS4231_VERSION 0x19 /* CS4231(A) - version values */ +#define CS4231_MONO_CTRL 0x1a /* mono input/output control */ +#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ +#define AD1845_PWR_DOWN 0x1b /* power down control */ +#define CS4235_LEFT_MASTER 0x1b /* left master output control */ +#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ +#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ +#define CS4235_RIGHT_MASTER 0x1d /* right master output control */ +#define CS4231_REC_UPR_CNT 0x1e /* record upper count */ +#define CS4231_REC_LWR_CNT 0x1f /* record lower count */ + +/* definitions for codec register select port - CODECP( REGSEL ) */ + +#define CS4231_INIT 0x80 /* CODEC is initializing */ +#define CS4231_MCE 0x40 /* mode change enable */ +#define CS4231_TRD 0x20 /* transfer request disable */ + +/* definitions for codec status register - CODECP( STATUS ) */ + +#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ + +/* definitions for codec irq status */ + +#define CS4231_PLAYBACK_IRQ 0x10 +#define CS4231_RECORD_IRQ 0x20 +#define CS4231_TIMER_IRQ 0x40 +#define CS4231_ALL_IRQS 0x70 +#define CS4231_REC_UNDERRUN 0x08 +#define CS4231_REC_OVERRUN 0x04 +#define CS4231_PLY_OVERRUN 0x02 +#define CS4231_PLY_UNDERRUN 0x01 + +/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ + +#define CS4231_ENABLE_MIC_GAIN 0x20 + +#define CS4231_MIXS_LINE 0x00 +#define CS4231_MIXS_AUX1 0x40 +#define CS4231_MIXS_MIC 0x80 +#define CS4231_MIXS_ALL 0xc0 + +/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ + +#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ +#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ +#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ +#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ +#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ +#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ +#define CS4231_STEREO 0x10 /* stereo mode */ +/* bits 3-1 define frequency divisor */ +#define CS4231_XTAL1 0x00 /* 24.576 crystal */ +#define CS4231_XTAL2 0x01 /* 16.9344 crystal */ + +/* definitions for interface control register - CS4231_IFACE_CTRL */ + +#define CS4231_RECORD_PIO 0x80 /* record PIO enable */ +#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ +#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ +#define CS4231_AUTOCALIB 0x08 /* auto calibrate */ +#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ +#define CS4231_RECORD_ENABLE 0x02 /* record enable */ +#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ + +/* definitions for pin control register - CS4231_PIN_CTRL */ + +#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ +#define CS4231_XCTL1 0x40 /* external control #1 */ +#define CS4231_XCTL0 0x80 /* external control #0 */ + +/* definitions for test and init register - CS4231_TEST_INIT */ + +#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ +#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ + +/* definitions for misc control register - CS4231_MISC_INFO */ + +#define CS4231_MODE2 0x40 /* MODE 2 */ +#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ +#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ + +/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ + +#define CS4231_DACZ 0x01 /* zero DAC when underrun */ +#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ +#define CS4231_OLB 0x80 /* output level bit */ + +/* definitions for Extended Registers - CS4236+ */ + +#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) +#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) + +#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ +#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ +#define CS4236_LEFT_MIC 0x28 /* left MIC volume */ +#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ +#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ +#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ +#define CS4236_LEFT_FM 0x68 /* left FM volume */ +#define CS4236_RIGHT_FM 0x78 /* right FM volume */ +#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ +#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ +#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ +#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ +#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ +#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ +#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ +#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ +#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ +#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ +#define CS4236_VERSION 0x9c /* chip version and ID */ + +/* definitions for extended registers - OPTI93X */ +#define OPTi931_AUX_LEFT_INPUT 0x10 +#define OPTi931_AUX_RIGHT_INPUT 0x11 +#define OPTi93X_MIC_LEFT_INPUT 0x14 +#define OPTi93X_MIC_RIGHT_INPUT 0x15 +#define OPTi93X_OUT_LEFT 0x16 +#define OPTi93X_OUT_RIGHT 0x17 + +#endif /* __SOUND_CS4231_REGS_H */ diff --git a/include/sound/cs4271.h b/include/sound/cs4271.h new file mode 100644 index 000000000..5a55d135b --- /dev/null +++ b/include/sound/cs4271.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Definitions for CS4271 ASoC codec driver + * + * Copyright (c) 2010 Alexander Sverdlin + */ + +#ifndef __CS4271_H +#define __CS4271_H + +struct cs4271_platform_data { + bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ + + /* + * The CS4271 requires its LRCLK and MCLK to be stable before its RESET + * line is de-asserted. That also means that clocks cannot be changed + * without putting the chip back into hardware reset, which also requires + * a complete re-initialization of all registers. + * + * One (undocumented) workaround is to assert and de-assert the PDN bit + * in the MODE2 register. This workaround can be enabled with the + * following flag. + * + * Note that this is not needed in case the clocks are stable + * throughout the entire runtime of the codec. + */ + bool enable_soft_reset; +}; + +#endif /* __CS4271_H */ diff --git a/include/sound/cs42l42.h b/include/sound/cs42l42.h new file mode 100644 index 000000000..1bd8eee54 --- /dev/null +++ b/include/sound/cs42l42.h @@ -0,0 +1,815 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs42l42.h -- Platform data for CS42L42 ALSA SoC audio driver header + * + * Copyright 2016-2022 Cirrus Logic, Inc. + * + * Author: James Schulman + * Author: Brian Austin + * Author: Michael White + */ + +#ifndef __CS42L42_H +#define __CS42L42_H + +#define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */ +#define CS42L42_WIN_START 0x00 +#define CS42L42_WIN_LEN 0x100 +#define CS42L42_RANGE_MIN 0x00 +#define CS42L42_RANGE_MAX 0x7F + +#define CS42L42_PAGE_10 0x1000 +#define CS42L42_PAGE_11 0x1100 +#define CS42L42_PAGE_12 0x1200 +#define CS42L42_PAGE_13 0x1300 +#define CS42L42_PAGE_15 0x1500 +#define CS42L42_PAGE_19 0x1900 +#define CS42L42_PAGE_1B 0x1B00 +#define CS42L42_PAGE_1C 0x1C00 +#define CS42L42_PAGE_1D 0x1D00 +#define CS42L42_PAGE_1F 0x1F00 +#define CS42L42_PAGE_20 0x2000 +#define CS42L42_PAGE_21 0x2100 +#define CS42L42_PAGE_23 0x2300 +#define CS42L42_PAGE_24 0x2400 +#define CS42L42_PAGE_25 0x2500 +#define CS42L42_PAGE_26 0x2600 +#define CS42L42_PAGE_27 0x2700 +#define CS42L42_PAGE_28 0x2800 +#define CS42L42_PAGE_29 0x2900 +#define CS42L42_PAGE_2A 0x2A00 +#define CS42L42_PAGE_30 0x3000 + +#define CS42L42_CHIP_ID 0x42A42 +#define CS42L83_CHIP_ID 0x42A83 + +/* Page 0x10 Global Registers */ +#define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01) +#define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02) +#define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03) +#define CS42L42_FABID (CS42L42_PAGE_10 + 0x04) +#define CS42L42_REVID (CS42L42_PAGE_10 + 0x05) +#define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06) + +#define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07) +#define CS42L42_SRC_BYPASS_DAC_SHIFT 1 +#define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT) + +#define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08) + +#define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09) +#define CS42L42_INTERNAL_FS_SHIFT 1 +#define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT) + +#define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A) +#define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B) +#define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4) +#define CS42L42_SLOW_START_EN_SHIFT 4 +#define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E) +#define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F) +#define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10) + +/* Page 0x11 Power and Headset Detect Registers */ +#define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01) +#define CS42L42_ASP_DAO_PDN_SHIFT 7 +#define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT) +#define CS42L42_ASP_DAI_PDN_SHIFT 6 +#define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT) +#define CS42L42_MIXER_PDN_SHIFT 5 +#define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT) +#define CS42L42_EQ_PDN_SHIFT 4 +#define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT) +#define CS42L42_HP_PDN_SHIFT 3 +#define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT) +#define CS42L42_ADC_PDN_SHIFT 2 +#define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT) +#define CS42L42_PDN_ALL_SHIFT 0 +#define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT) + +#define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02) +#define CS42L42_ADC_SRC_PDNB_SHIFT 0 +#define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT) +#define CS42L42_DAC_SRC_PDNB_SHIFT 1 +#define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT) +#define CS42L42_ASP_DAI1_PDN_SHIFT 2 +#define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT) +#define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3 +#define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT) +#define CS42L42_DISCHARGE_FILT_SHIFT 4 +#define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT) + +#define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03) +#define CS42L42_RING_SENSE_PDNB_SHIFT 1 +#define CS42L42_RING_SENSE_PDNB_MASK (1 << CS42L42_RING_SENSE_PDNB_SHIFT) +#define CS42L42_VPMON_PDNB_SHIFT 2 +#define CS42L42_VPMON_PDNB_MASK (1 << CS42L42_VPMON_PDNB_SHIFT) +#define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5 +#define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << CS42L42_SW_CLK_STP_STAT_SEL_SHIFT) + +#define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04) +#define CS42L42_RS_TRIM_R_SHIFT 0 +#define CS42L42_RS_TRIM_R_MASK (1 << CS42L42_RS_TRIM_R_SHIFT) +#define CS42L42_RS_TRIM_T_SHIFT 1 +#define CS42L42_RS_TRIM_T_MASK (1 << CS42L42_RS_TRIM_T_SHIFT) +#define CS42L42_HPREF_RS_SHIFT 2 +#define CS42L42_HPREF_RS_MASK (1 << CS42L42_HPREF_RS_SHIFT) +#define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3 +#define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << CS42L42_HSBIAS_FILT_REF_RS_SHIFT) +#define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6 +#define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << CS42L42_RING_SENSE_PU_HIZ_SHIFT) + +#define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05) +#define CS42L42_TS_RS_GATE_SHIFT 7 +#define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT) + +#define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07) +#define CS42L42_SCLK_PRESENT_SHIFT 0 +#define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT) + +#define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09) +#define CS42L42_OSC_SW_SEL_STAT_SHIFT 0 +#define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT) +#define CS42L42_OSC_PDNB_STAT_SHIFT 2 +#define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT) + +#define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12) +#define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0 +#define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << CS42L42_RS_RISE_DBNCE_TIME_SHIFT) +#define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3 +#define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << CS42L42_RS_FALL_DBNCE_TIME_SHIFT) +#define CS42L42_RS_PU_EN_SHIFT 6 +#define CS42L42_RS_PU_EN_MASK (1 << CS42L42_RS_PU_EN_SHIFT) +#define CS42L42_RS_INV_SHIFT 7 +#define CS42L42_RS_INV_MASK (1 << CS42L42_RS_INV_SHIFT) + +#define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13) +#define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0 +#define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << CS42L42_TS_RISE_DBNCE_TIME_SHIFT) +#define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3 +#define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << CS42L42_TS_FALL_DBNCE_TIME_SHIFT) +#define CS42L42_TS_INV_SHIFT 7 +#define CS42L42_TS_INV_MASK (1 << CS42L42_TS_INV_SHIFT) + +#define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14) +#define CS42L42_D_RS_PLUG_DBNC_SHIFT 0 +#define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT) +#define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1 +#define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT) +#define CS42L42_D_TS_PLUG_DBNC_SHIFT 2 +#define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT) +#define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3 +#define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT) + +#define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15) +#define CS42L42_RS_PLUG_DBNC_SHIFT 0 +#define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT) +#define CS42L42_RS_UNPLUG_DBNC_SHIFT 1 +#define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT) +#define CS42L42_TS_PLUG_DBNC_SHIFT 2 +#define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT) +#define CS42L42_TS_UNPLUG_DBNC_SHIFT 3 +#define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT) + +#define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F) +#define CS42L42_HSDET_COMP1_LVL_SHIFT 0 +#define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT) +#define CS42L42_HSDET_COMP2_LVL_SHIFT 4 +#define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT) + +#define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 1.25V Comparator */ +#define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 1.75V Comparator */ +#define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 1V Comparator */ +#define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 2V Comparator */ + +#define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20) +#define CS42L42_HSDET_AUTO_TIME_SHIFT 0 +#define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT) +#define CS42L42_HSBIAS_REF_SHIFT 3 +#define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT) +#define CS42L42_HSDET_SET_SHIFT 4 +#define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT) +#define CS42L42_HSDET_CTRL_SHIFT 6 +#define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT) + +#define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21) +#define CS42L42_SW_GNDHS_HS4_SHIFT 0 +#define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT) +#define CS42L42_SW_GNDHS_HS3_SHIFT 1 +#define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT) +#define CS42L42_SW_HSB_HS4_SHIFT 2 +#define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT) +#define CS42L42_SW_HSB_HS3_SHIFT 3 +#define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT) +#define CS42L42_SW_HSB_FILT_HS4_SHIFT 4 +#define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) +#define CS42L42_SW_HSB_FILT_HS3_SHIFT 5 +#define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) +#define CS42L42_SW_REF_HS4_SHIFT 6 +#define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT) +#define CS42L42_SW_REF_HS3_SHIFT 7 +#define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT) + +#define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24) +#define CS42L42_HSDET_TYPE_SHIFT 0 +#define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT) +#define CS42L42_HSDET_COMP1_OUT_SHIFT 6 +#define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT) +#define CS42L42_HSDET_COMP2_OUT_SHIFT 7 +#define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT) +#define CS42L42_PLUG_CTIA 0 +#define CS42L42_PLUG_OMTP 1 +#define CS42L42_PLUG_HEADPHONE 2 +#define CS42L42_PLUG_INVALID 3 + +#define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (0 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_COMP2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (1 << CS42L42_SW_REF_HS4_SHIFT) | \ + (0 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (0 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (1 << CS42L42_SW_REF_HS4_SHIFT) | \ + (0 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE3 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (1 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (0 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) + +#define CS42L42_HSDET_COMP_TYPE1 1 +#define CS42L42_HSDET_COMP_TYPE2 2 +#define CS42L42_HSDET_COMP_TYPE3 0 +#define CS42L42_HSDET_COMP_TYPE4 3 + +#define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29) +#define CS42L42_HS_CLAMP_DISABLE_SHIFT 0 +#define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT) + +/* Page 0x12 Clocking Registers */ +#define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01) +#define CS42L42_MCLKDIV_SHIFT 1 +#define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT) +#define CS42L42_MCLK_SRC_SEL_SHIFT 0 +#define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT) + +#define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02) +#define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03) + +#define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04) +#define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0 +#define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \ + CS42L42_FSYNC_PULSE_WIDTH_SHIFT) + +#define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05) + +#define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06) +#define CS42L42_FSYNC_PERIOD_SHIFT 0 +#define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT) + +#define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07) +#define CS42L42_ASP_SCLK_EN_SHIFT 5 +#define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT) +#define CS42L42_ASP_MASTER_MODE 0x01 +#define CS42L42_ASP_SLAVE_MODE 0x00 +#define CS42L42_ASP_MODE_SHIFT 4 +#define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT) +#define CS42L42_ASP_SCPOL_SHIFT 2 +#define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT) +#define CS42L42_ASP_SCPOL_NOR 3 +#define CS42L42_ASP_LCPOL_SHIFT 0 +#define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT) +#define CS42L42_ASP_LCPOL_INV 3 + +#define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08) +#define CS42L42_ASP_STP_SHIFT 4 +#define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT) +#define CS42L42_ASP_5050_SHIFT 3 +#define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT) +#define CS42L42_ASP_FSD_SHIFT 0 +#define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT) +#define CS42L42_ASP_FSD_0_5 1 +#define CS42L42_ASP_FSD_1_0 2 +#define CS42L42_ASP_FSD_1_5 3 +#define CS42L42_ASP_FSD_2_0 4 + +#define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09) +#define CS42L42_FS_EN_SHIFT 0 +#define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT) +#define CS42L42_FS_EN_IASRC_96K 0x1 +#define CS42L42_FS_EN_OASRC_96K 0x2 + +#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A) +#define CS42L42_CLK_IASRC_SEL_SHIFT 0 +#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT) +#define CS42L42_CLK_IASRC_SEL_6 0 +#define CS42L42_CLK_IASRC_SEL_12 1 + +#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B) +#define CS42L42_CLK_OASRC_SEL_SHIFT 0 +#define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT) +#define CS42L42_CLK_OASRC_SEL_12 1 + +#define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C) +#define CS42L42_SCLK_PREDIV_SHIFT 0 +#define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT) + +/* Page 0x13 Interrupt Registers */ +/* Interrupts */ +#define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01) +#define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02) +#define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03) +#define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04) +#define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05) +#define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08) +#define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09) +#define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A) +#define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B) +#define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D) +#define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E) +#define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F) +/* Masks */ +#define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16) +#define CS42L42_ADC_OVFL_SHIFT 0 +#define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT) +#define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK + +#define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17) +#define CS42L42_MIX_CHB_OVFL_SHIFT 0 +#define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT) +#define CS42L42_MIX_CHA_OVFL_SHIFT 1 +#define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT) +#define CS42L42_EQ_OVFL_SHIFT 2 +#define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT) +#define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3 +#define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT) +#define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \ + CS42L42_MIX_CHA_OVFL_MASK | \ + CS42L42_EQ_OVFL_MASK | \ + CS42L42_EQ_BIQUAD_OVFL_MASK) + +#define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18) +#define CS42L42_SRC_ILK_SHIFT 0 +#define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT) +#define CS42L42_SRC_OLK_SHIFT 1 +#define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT) +#define CS42L42_SRC_IUNLK_SHIFT 2 +#define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT) +#define CS42L42_SRC_OUNLK_SHIFT 3 +#define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT) +#define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \ + CS42L42_SRC_OLK_MASK | \ + CS42L42_SRC_IUNLK_MASK | \ + CS42L42_SRC_OUNLK_MASK) + +#define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19) +#define CS42L42_ASPRX_NOLRCK_SHIFT 0 +#define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT) +#define CS42L42_ASPRX_EARLY_SHIFT 1 +#define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT) +#define CS42L42_ASPRX_LATE_SHIFT 2 +#define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT) +#define CS42L42_ASPRX_ERROR_SHIFT 3 +#define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT) +#define CS42L42_ASPRX_OVLD_SHIFT 4 +#define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT) +#define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \ + CS42L42_ASPRX_EARLY_MASK | \ + CS42L42_ASPRX_LATE_MASK | \ + CS42L42_ASPRX_ERROR_MASK | \ + CS42L42_ASPRX_OVLD_MASK) + +#define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A) +#define CS42L42_ASPTX_NOLRCK_SHIFT 0 +#define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT) +#define CS42L42_ASPTX_EARLY_SHIFT 1 +#define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT) +#define CS42L42_ASPTX_LATE_SHIFT 2 +#define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT) +#define CS42L42_ASPTX_SMERROR_SHIFT 3 +#define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT) +#define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \ + CS42L42_ASPTX_EARLY_MASK | \ + CS42L42_ASPTX_LATE_MASK | \ + CS42L42_ASPTX_SMERROR_MASK) + +#define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B) +#define CS42L42_PDN_DONE_SHIFT 0 +#define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT) +#define CS42L42_HSDET_AUTO_DONE_SHIFT 1 +#define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT) +#define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \ + CS42L42_HSDET_AUTO_DONE_MASK) + +#define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C) +#define CS42L42_SRCPL_ADC_LK_SHIFT 0 +#define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT) +#define CS42L42_SRCPL_DAC_LK_SHIFT 2 +#define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT) +#define CS42L42_SRCPL_ADC_UNLK_SHIFT 5 +#define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) +#define CS42L42_SRCPL_DAC_UNLK_SHIFT 6 +#define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT) +#define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \ + CS42L42_SRCPL_DAC_LK_MASK | \ + CS42L42_SRCPL_ADC_UNLK_MASK | \ + CS42L42_SRCPL_DAC_UNLK_MASK) + +#define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E) +#define CS42L42_VPMON_SHIFT 0 +#define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT) +#define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK + +#define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F) +#define CS42L42_PLL_LOCK_SHIFT 0 +#define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT) +#define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK + +#define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20) +#define CS42L42_RS_PLUG_SHIFT 0 +#define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT) +#define CS42L42_RS_UNPLUG_SHIFT 1 +#define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT) +#define CS42L42_TS_PLUG_SHIFT 2 +#define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT) +#define CS42L42_TS_UNPLUG_SHIFT 3 +#define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT) +#define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \ + CS42L42_RS_UNPLUG_MASK | \ + CS42L42_TS_PLUG_MASK | \ + CS42L42_TS_UNPLUG_MASK) +#define CS42L42_TS_PLUG 3 +#define CS42L42_TS_UNPLUG 0 +#define CS42L42_TS_TRANS 1 + +/* + * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1. + * Otherwise it will prevent FILT+ from charging properly. + */ +#define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01) +#define CS42L42_PLL_START_SHIFT 0 +#define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT) + +#define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02) +#define CS42L42_PLL_DIV_FRAC_SHIFT 0 +#define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT) + +#define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03) +#define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04) + +#define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05) +#define CS42L42_PLL_DIV_INT_SHIFT 0 +#define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT) + +#define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08) +#define CS42L42_PLL_DIVOUT_SHIFT 0 +#define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT) + +#define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A) +#define CS42L42_PLL_CAL_RATIO_SHIFT 0 +#define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT) + +#define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B) +#define CS42L42_PLL_MODE_SHIFT 0 +#define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT) + +/* Page 0x19 HP Load Detect Registers */ +#define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25) +#define CS42L42_RLA_STAT_SHIFT 0 +#define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT) +#define CS42L42_RLA_STAT_15_OHM 0 + +#define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26) +#define CS42L42_HPLOAD_DET_DONE_SHIFT 0 +#define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT) + +#define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27) +#define CS42L42_HP_LD_EN_SHIFT 0 +#define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT) + +/* Page 0x1B Headset Interface Registers */ +#define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70) +#define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0 +#define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT) +#define CS42L42_TIP_SENSE_EN_SHIFT 5 +#define CS42L42_TIP_SENSE_EN_MASK (1 << CS42L42_TIP_SENSE_EN_SHIFT) +#define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6 +#define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) +#define CS42L42_HSBIAS_SENSE_EN_SHIFT 7 +#define CS42L42_HSBIAS_SENSE_EN_MASK (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) + +#define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71) +#define CS42L42_WAKEB_CLEAR_SHIFT 0 +#define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT) +#define CS42L42_WAKEB_MODE_SHIFT 5 +#define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT) +#define CS42L42_M_HP_WAKE_SHIFT 6 +#define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT) +#define CS42L42_M_MIC_WAKE_SHIFT 7 +#define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT) + +#define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72) +#define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7 +#define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << CS42L42_ADC_DISABLE_S0_MUTE_SHIFT) + +#define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73) +#define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0 +#define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT) +#define CS42L42_TIP_SENSE_INV_SHIFT 5 +#define CS42L42_TIP_SENSE_INV_MASK (1 << CS42L42_TIP_SENSE_INV_SHIFT) +#define CS42L42_TIP_SENSE_CTRL_SHIFT 6 +#define CS42L42_TIP_SENSE_CTRL_MASK (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) + +/* + * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1. + * Otherwise it will prevent FILT+ from charging properly. + */ +#define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74) +#define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 +#define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT) +#define CS42L42_HSBIAS_CTL_SHIFT 1 +#define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT) +#define CS42L42_DETECT_MODE_SHIFT 3 +#define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT) + +#define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75) +#define CS42L42_HS_DET_LEVEL_SHIFT 0 +#define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT) +#define CS42L42_EVENT_STAT_SEL_SHIFT 6 +#define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT) +#define CS42L42_LATCH_TO_VP_SHIFT 7 +#define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT) + +#define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76) +#define CS42L42_DEBOUNCE_TIME_SHIFT 5 +#define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT) + +#define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77) +#define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6 +#define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT) +#define CS42L42_TIP_SENSE_SHIFT 7 +#define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT) + +#define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78) +#define CS42L42_SHORT_TRUE_SHIFT 0 +#define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT) +#define CS42L42_HS_TRUE_SHIFT 1 +#define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT) + +#define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79) +#define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5 +#define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) +#define CS42L42_TIP_SENSE_PLUG_SHIFT 6 +#define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) +#define CS42L42_HSBIAS_SENSE_SHIFT 7 +#define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT) +#define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \ + CS42L42_TIP_SENSE_PLUG_MASK | \ + CS42L42_HSBIAS_SENSE_MASK) + +#define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A) +#define CS42L42_M_SHORT_DET_SHIFT 0 +#define CS42L42_M_SHORT_DET_MASK (1 << CS42L42_M_SHORT_DET_SHIFT) +#define CS42L42_M_SHORT_RLS_SHIFT 1 +#define CS42L42_M_SHORT_RLS_MASK (1 << CS42L42_M_SHORT_RLS_SHIFT) +#define CS42L42_M_HSBIAS_HIZ_SHIFT 2 +#define CS42L42_M_HSBIAS_HIZ_MASK (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) +#define CS42L42_M_DETECT_FT_SHIFT 6 +#define CS42L42_M_DETECT_FT_MASK (1 << CS42L42_M_DETECT_FT_SHIFT) +#define CS42L42_M_DETECT_TF_SHIFT 7 +#define CS42L42_M_DETECT_TF_MASK (1 << CS42L42_M_DETECT_TF_SHIFT) +#define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \ + CS42L42_M_SHORT_RLS_MASK | \ + CS42L42_M_HSBIAS_HIZ_MASK | \ + CS42L42_M_DETECT_FT_MASK | \ + CS42L42_M_DETECT_TF_MASK) + +/* Page 0x1C Headset Bias Registers */ +#define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03) +#define CS42L42_HSBIAS_RAMP_SHIFT 0 +#define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT) +#define CS42L42_HSBIAS_PD_SHIFT 4 +#define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT) +#define CS42L42_HSBIAS_CAPLESS_SHIFT 7 +#define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT) + +/* Page 0x1D ADC Registers */ +#define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01) +#define CS42L42_ADC_NOTCH_DIS_SHIFT 5 +#define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4 +#define CS42L42_ADC_INV_SHIFT 2 +#define CS42L42_ADC_DIG_BOOST_SHIFT 0 + +#define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03) +#define CS42L42_ADC_VOL_SHIFT 0 + +#define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04) +#define CS42L42_ADC_WNF_CF_SHIFT 4 +#define CS42L42_ADC_WNF_EN_SHIFT 3 +#define CS42L42_ADC_HPF_CF_SHIFT 1 +#define CS42L42_ADC_HPF_EN_SHIFT 0 + +/* Page 0x1F DAC Registers */ +#define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01) +#define CS42L42_DACB_INV_SHIFT 1 +#define CS42L42_DACA_INV_SHIFT 0 + +#define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06) +#define CS42L42_HPOUT_PULLDOWN_SHIFT 4 +#define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT) +#define CS42L42_HPOUT_LOAD_SHIFT 3 +#define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT) +#define CS42L42_HPOUT_CLAMP_SHIFT 2 +#define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT) +#define CS42L42_DAC_HPF_EN_SHIFT 1 +#define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT) +#define CS42L42_DAC_MON_EN_SHIFT 0 +#define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT) + +/* Page 0x20 HP CTL Registers */ +#define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01) +#define CS42L42_HP_ANA_BMUTE_SHIFT 3 +#define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT) +#define CS42L42_HP_ANA_AMUTE_SHIFT 2 +#define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT) +#define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1 +#define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT) + +/* Page 0x21 Class H Registers */ +#define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01) + +/* Page 0x23 Mixer Volume Registers */ +#define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01) +#define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02) + +#define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03) +#define CS42L42_MIXER_CH_VOL_SHIFT 0 +#define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT) + +/* Page 0x24 EQ Registers */ +#define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01) +#define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02) +#define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03) +#define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04) +#define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06) +#define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07) +#define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08) +#define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09) +#define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A) +#define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B) +#define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C) +#define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E) + +/* Page 0x25 Audio Port Registers */ +#define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01) +#define CS42L42_SP_RX_CHB_SEL_SHIFT 2 +#define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT) + +#define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02) +#define CS42L42_SP_RX_RSYNC_SHIFT 6 +#define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT) +#define CS42L42_SP_RX_NSB_POS_SHIFT 3 +#define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT) +#define CS42L42_SP_RX_NFS_NSBB_SHIFT 2 +#define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT) +#define CS42L42_SP_RX_ISOC_MODE_SHIFT 0 +#define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT) + +#define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03) +#define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04) +#define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05) +#define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06) +#define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07) + +/* Page 0x26 SRC Registers */ +#define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01) +#define CS42L42_SRC_SDIN_FS_SHIFT 0 +#define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT) + +#define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09) + +/* Page 0x27 DMA */ +#define CS42L42_SOFT_RESET_REBOOT (CS42L42_PAGE_27 + 0x01) +#define CS42L42_SFT_RST_REBOOT_MASK BIT(1) + +/* Page 0x28 S/PDIF Registers */ +#define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01) +#define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02) +#define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03) +#define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04) + +/* Page 0x29 Serial Port TX Registers */ +#define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01) +#define CS42L42_ASP_TX_EN_SHIFT 0 +#define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02) +#define CS42L42_ASP_TX0_CH2_SHIFT 1 +#define CS42L42_ASP_TX0_CH1_SHIFT 0 + +#define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03) +#define CS42L42_ASP_TX_CH1_AP_SHIFT 7 +#define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT) +#define CS42L42_ASP_TX_CH2_AP_SHIFT 6 +#define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT) +#define CS42L42_ASP_TX_CH2_RES_SHIFT 2 +#define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT) +#define CS42L42_ASP_TX_CH1_RES_SHIFT 0 +#define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT) +#define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04) +#define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05) +#define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06) +#define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A) +#define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B) + +/* Page 0x2A Serial Port RX Registers */ +#define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01) +#define CS42L42_ASP_RX0_CH_EN_SHIFT 2 +#define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT) +#define CS42L42_ASP_RX0_CH1_SHIFT 2 +#define CS42L42_ASP_RX0_CH2_SHIFT 3 +#define CS42L42_ASP_RX0_CH3_SHIFT 4 +#define CS42L42_ASP_RX0_CH4_SHIFT 5 + +#define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02) +#define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03) +#define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04) +#define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05) +#define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06) +#define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07) +#define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08) +#define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09) +#define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A) +#define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B) +#define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C) +#define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D) +#define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E) +#define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F) +#define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10) +#define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11) +#define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12) +#define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13) + +#define CS42L42_ASP_RX_CH_AP_SHIFT 6 +#define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT) +#define CS42L42_ASP_RX_CH_AP_LOW 0 +#define CS42L42_ASP_RX_CH_AP_HI 1 +#define CS42L42_ASP_RX_CH_RES_SHIFT 0 +#define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT) +#define CS42L42_ASP_RX_CH_RES_32 3 +#define CS42L42_ASP_RX_CH_RES_16 1 +#define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0 +#define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT) + +/* Page 0x30 ID Registers */ +#define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14) +#define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14) + +/* Defines for fracturing values spread across multiple registers */ +#define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff) +#define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8) +#define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16) + +#define CS42L42_NUM_SUPPLIES 5 +#define CS42L42_BOOT_TIME_US 3000 +#define CS42L42_PLL_DIVOUT_TIME_US 800 +#define CS42L42_CLOCK_SWITCH_DELAY_US 150 +#define CS42L42_PLL_LOCK_POLL_US 250 +#define CS42L42_PLL_LOCK_TIMEOUT_US 1250 +#define CS42L42_HP_ADC_EN_TIME_US 20000 +#define CS42L42_PDN_DONE_POLL_US 1000 +#define CS42L42_PDN_DONE_TIMEOUT_US 235000 +#define CS42L42_PDN_DONE_TIME_MS 65 + +#endif /* __CS42L42_H */ diff --git a/include/sound/cs42l43.h b/include/sound/cs42l43.h new file mode 100644 index 000000000..deb337fc4 --- /dev/null +++ b/include/sound/cs42l43.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CS42L43 CODEC driver external data + * + * Copyright (C) 2022-2023 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS42L43_ASOC_EXT_H +#define CS42L43_ASOC_EXT_H + +#define CS42L43_SYSCLK 0 + +#define CS42L43_SYSCLK_MCLK 0 +#define CS42L43_SYSCLK_SDW 1 + +#endif /* CS42L43_ASOC_EXT_H */ diff --git a/include/sound/cs48l32.h b/include/sound/cs48l32.h new file mode 100644 index 000000000..27b3e7cf9 --- /dev/null +++ b/include/sound/cs48l32.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions for Cirrus Logic CS48L32 + * + * Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_H +#define CS48L32_H + +/* pll_id for snd_soc_component_set_pll() */ +#define CS48L32_FLL1_REFCLK 1 + +/* source for snd_soc_component_set_pll() */ +#define CS48L32_FLL_SRC_NONE -1 +#define CS48L32_FLL_SRC_MCLK1 0 +#define CS48L32_FLL_SRC_PDMCLK 5 +#define CS48L32_FLL_SRC_ASP1_BCLK 8 +#define CS48L32_FLL_SRC_ASP2_BCLK 9 +#define CS48L32_FLL_SRC_ASP1_FSYNC 12 +#define CS48L32_FLL_SRC_ASP2_FSYNC 13 + +/* clk_id for snd_soc_component_set_sysclk() and snd_soc_dai_set_sysclk() */ +#define CS48L32_CLK_SYSCLK_1 1 +#define CS48L32_CLK_SYSCLK_2 2 +#define CS48L32_CLK_SYSCLK_3 3 +#define CS48L32_CLK_SYSCLK_4 4 +#define CS48L32_CLK_DSPCLK 7 +#define CS48L32_CLK_PDM_FLLCLK 13 + +/* source for snd_soc_component_set_sysclk() */ +#define CS48L32_CLK_SRC_MCLK1 0x0 +#define CS48L32_CLK_SRC_FLL1 0x4 +#define CS48L32_CLK_SRC_ASP1_BCLK 0x8 +#define CS48L32_CLK_SRC_ASP2_BCLK 0x9 + +struct cs48l32 { + struct regmap *regmap; + struct device *dev; + struct gpio_desc *reset_gpio; + struct clk *mclk1; + struct regulator_bulk_data core_supplies[2]; + struct regulator *vdd_d; + int irq; +}; +#endif diff --git a/include/sound/cs48l32_registers.h b/include/sound/cs48l32_registers.h new file mode 100644 index 000000000..f29410fdf --- /dev/null +++ b/include/sound/cs48l32_registers.h @@ -0,0 +1,530 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions for Cirrus Logic CS48L32 + * + * Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_REGISTERS_H +#define CS48L32_REGISTERS_H + +/* Register Addresses. */ +#define CS48L32_DEVID 0x0 +#define CS48L32_REVID 0x4 +#define CS48L32_OTPID 0x10 +#define CS48L32_SFT_RESET 0x20 +#define CS48L32_CTRL_IF_DEBUG3 0xA8 +#define CS48L32_MCU_CTRL1 0x804 +#define CS48L32_GPIO1_CTRL1 0xc08 +#define CS48L32_GPIO3_CTRL1 0xc10 +#define CS48L32_GPIO7_CTRL1 0xc20 +#define CS48L32_GPIO16_CTRL1 0xc44 +#define CS48L32_OUTPUT_SYS_CLK 0x1020 +#define CS48L32_AUXPDM_CTRL 0x1044 +#define CS48L32_AUXPDM_CTRL2 0x105c +#define CS48L32_CLOCK32K 0x1400 +#define CS48L32_SYSTEM_CLOCK1 0x1404 +#define CS48L32_SYSTEM_CLOCK2 0x1408 +#define CS48L32_SAMPLE_RATE1 0x1420 +#define CS48L32_SAMPLE_RATE2 0x1424 +#define CS48L32_SAMPLE_RATE3 0x1428 +#define CS48L32_SAMPLE_RATE4 0x142c +#define CS48L32_DSP_CLOCK1 0x1510 +#define CS48L32_FLL1_CONTROL1 0x1c00 +#define CS48L32_FLL1_CONTROL5 0x1c10 +#define CS48L32_FLL1_CONTROL6 0x1c14 +#define CS48L32_FLL1_GPIO_CLOCK 0x1ca0 +#define CS48L32_CHARGE_PUMP1 0x2000 +#define CS48L32_LDO2_CTRL1 0x2408 +#define CS48L32_MICBIAS_CTRL1 0x2410 +#define CS48L32_MICBIAS_CTRL5 0x2418 +#define CS48L32_IRQ1_CTRL_AOD 0x2710 +#define CS48L32_AOD_PAD_CTRL 0x2718 +#define CS48L32_INPUT_CONTROL 0x4000 +#define CS48L32_INPUT_STATUS 0x4004 +#define CS48L32_INPUT_RATE_CONTROL 0x4008 +#define CS48L32_INPUT_CONTROL2 0x400c +#define CS48L32_INPUT_CONTROL3 0x4014 +#define CS48L32_INPUT1_CONTROL1 0x4020 +#define CS48L32_IN1L_CONTROL1 0x4024 +#define CS48L32_IN1L_CONTROL2 0x4028 +#define CS48L32_IN1R_CONTROL1 0x4044 +#define CS48L32_IN1R_CONTROL2 0x4048 +#define CS48L32_INPUT2_CONTROL1 0x4060 +#define CS48L32_IN2L_CONTROL1 0x4064 +#define CS48L32_IN2L_CONTROL2 0x4068 +#define CS48L32_IN2R_CONTROL1 0x4084 +#define CS48L32_IN2R_CONTROL2 0x4088 +#define CS48L32_INPUT_HPF_CONTROL 0x4244 +#define CS48L32_INPUT_VOL_CONTROL 0x4248 +#define CS48L32_AUXPDM_CONTROL1 0x4300 +#define CS48L32_AUXPDM_CONTROL2 0x4304 +#define CS48L32_AUXPDM1_CONTROL1 0x4308 +#define CS48L32_AUXPDM2_CONTROL1 0x4310 +#define CS48L32_ADC1L_ANA_CONTROL1 0x4688 +#define CS48L32_ADC1R_ANA_CONTROL1 0x468c +#define CS48L32_ASP1_ENABLES1 0x6000 +#define CS48L32_ASP1_CONTROL3 0x600C +#define CS48L32_ASP1_DATA_CONTROL5 0x6040 +#define CS48L32_ASP2_ENABLES1 0x6080 +#define CS48L32_ASP2_CONTROL3 0x608C +#define CS48L32_ASP2_DATA_CONTROL5 0x60c0 +#define CS48L32_ASP1TX1_INPUT1 0x8200 +#define CS48L32_ASP1TX2_INPUT1 0x8210 +#define CS48L32_ASP1TX3_INPUT1 0x8220 +#define CS48L32_ASP1TX4_INPUT1 0x8230 +#define CS48L32_ASP1TX5_INPUT1 0x8240 +#define CS48L32_ASP1TX6_INPUT1 0x8250 +#define CS48L32_ASP1TX7_INPUT1 0x8260 +#define CS48L32_ASP1TX8_INPUT1 0x8270 +#define CS48L32_ASP1TX8_INPUT4 0x827c +#define CS48L32_ASP2TX1_INPUT1 0x8300 +#define CS48L32_ASP2TX2_INPUT1 0x8310 +#define CS48L32_ASP2TX3_INPUT1 0x8320 +#define CS48L32_ASP2TX4_INPUT1 0x8330 +#define CS48L32_ASP2TX4_INPUT4 0x833c +#define CS48L32_ISRC1INT1_INPUT1 0x8980 +#define CS48L32_ISRC1INT2_INPUT1 0x8990 +#define CS48L32_ISRC1INT3_INPUT1 0x89a0 +#define CS48L32_ISRC1INT4_INPUT1 0x89b0 +#define CS48L32_ISRC1DEC1_INPUT1 0x89c0 +#define CS48L32_ISRC1DEC2_INPUT1 0x89d0 +#define CS48L32_ISRC1DEC3_INPUT1 0x89e0 +#define CS48L32_ISRC1DEC4_INPUT1 0x89f0 +#define CS48L32_ISRC2INT1_INPUT1 0x8a00 +#define CS48L32_ISRC2INT2_INPUT1 0x8a10 +#define CS48L32_ISRC2DEC1_INPUT1 0x8a40 +#define CS48L32_ISRC2DEC2_INPUT1 0x8a50 +#define CS48L32_ISRC3INT1_INPUT1 0x8a80 +#define CS48L32_ISRC3INT2_INPUT1 0x8a90 +#define CS48L32_ISRC3DEC1_INPUT1 0x8ac0 +#define CS48L32_ISRC3DEC2_INPUT1 0x8ad0 +#define CS48L32_EQ1_INPUT1 0x8b80 +#define CS48L32_EQ2_INPUT1 0x8b90 +#define CS48L32_EQ3_INPUT1 0x8ba0 +#define CS48L32_EQ4_INPUT1 0x8bb0 +#define CS48L32_EQ4_INPUT4 0x8bbc +#define CS48L32_DRC1L_INPUT1 0x8c00 +#define CS48L32_DRC1R_INPUT1 0x8c10 +#define CS48L32_DRC1R_INPUT4 0x8c1c +#define CS48L32_DRC2L_INPUT1 0x8c20 +#define CS48L32_DRC2R_INPUT1 0x8c30 +#define CS48L32_DRC2R_INPUT4 0x8c3c +#define CS48L32_LHPF1_INPUT1 0x8c80 +#define CS48L32_LHPF1_INPUT4 0x8c8c +#define CS48L32_LHPF2_INPUT1 0x8c90 +#define CS48L32_LHPF2_INPUT4 0x8c9c +#define CS48L32_LHPF3_INPUT1 0x8ca0 +#define CS48L32_LHPF3_INPUT4 0x8cac +#define CS48L32_LHPF4_INPUT1 0x8cb0 +#define CS48L32_LHPF4_INPUT4 0x8cbc +#define CS48L32_DSP1RX1_INPUT1 0x9000 +#define CS48L32_DSP1RX2_INPUT1 0x9010 +#define CS48L32_DSP1RX3_INPUT1 0x9020 +#define CS48L32_DSP1RX4_INPUT1 0x9030 +#define CS48L32_DSP1RX5_INPUT1 0x9040 +#define CS48L32_DSP1RX6_INPUT1 0x9050 +#define CS48L32_DSP1RX7_INPUT1 0x9060 +#define CS48L32_DSP1RX8_INPUT1 0x9070 +#define CS48L32_DSP1RX8_INPUT4 0x907c +#define CS48L32_ISRC1_CONTROL1 0xa400 +#define CS48L32_ISRC1_CONTROL2 0xa404 +#define CS48L32_ISRC2_CONTROL1 0xa510 +#define CS48L32_ISRC2_CONTROL2 0xa514 +#define CS48L32_ISRC3_CONTROL1 0xa620 +#define CS48L32_ISRC3_CONTROL2 0xa624 +#define CS48L32_FX_SAMPLE_RATE 0xa800 +#define CS48L32_EQ_CONTROL1 0xa808 +#define CS48L32_EQ_CONTROL2 0xa80c +#define CS48L32_EQ1_GAIN1 0xa810 +#define CS48L32_EQ1_GAIN2 0xa814 +#define CS48L32_EQ1_BAND1_COEFF1 0xa818 +#define CS48L32_EQ1_BAND1_COEFF2 0xa81c +#define CS48L32_EQ1_BAND1_PG 0xa820 +#define CS48L32_EQ1_BAND2_COEFF1 0xa824 +#define CS48L32_EQ1_BAND2_COEFF2 0xa828 +#define CS48L32_EQ1_BAND2_PG 0xa82c +#define CS48L32_EQ1_BAND3_COEFF1 0xa830 +#define CS48L32_EQ1_BAND3_COEFF2 0xa834 +#define CS48L32_EQ1_BAND3_PG 0xa838 +#define CS48L32_EQ1_BAND4_COEFF1 0xa83c +#define CS48L32_EQ1_BAND4_COEFF2 0xa840 +#define CS48L32_EQ1_BAND4_PG 0xa844 +#define CS48L32_EQ1_BAND5_COEFF1 0xa848 +#define CS48L32_EQ1_BAND5_PG 0xa850 +#define CS48L32_EQ2_GAIN1 0xa854 +#define CS48L32_EQ2_GAIN2 0xa858 +#define CS48L32_EQ2_BAND1_COEFF1 0xa85c +#define CS48L32_EQ2_BAND1_COEFF2 0xa860 +#define CS48L32_EQ2_BAND1_PG 0xa864 +#define CS48L32_EQ2_BAND2_COEFF1 0xa868 +#define CS48L32_EQ2_BAND2_COEFF2 0xa86c +#define CS48L32_EQ2_BAND2_PG 0xa870 +#define CS48L32_EQ2_BAND3_COEFF1 0xa874 +#define CS48L32_EQ2_BAND3_COEFF2 0xa878 +#define CS48L32_EQ2_BAND3_PG 0xa87c +#define CS48L32_EQ2_BAND4_COEFF1 0xa880 +#define CS48L32_EQ2_BAND4_COEFF2 0xa884 +#define CS48L32_EQ2_BAND4_PG 0xa888 +#define CS48L32_EQ2_BAND5_COEFF1 0xa88c +#define CS48L32_EQ2_BAND5_PG 0xa894 +#define CS48L32_EQ3_GAIN1 0xa898 +#define CS48L32_EQ3_GAIN2 0xa89c +#define CS48L32_EQ3_BAND1_COEFF1 0xa8a0 +#define CS48L32_EQ3_BAND1_COEFF2 0xa8a4 +#define CS48L32_EQ3_BAND1_PG 0xa8a8 +#define CS48L32_EQ3_BAND2_COEFF1 0xa8ac +#define CS48L32_EQ3_BAND2_COEFF2 0xa8b0 +#define CS48L32_EQ3_BAND2_PG 0xa8b4 +#define CS48L32_EQ3_BAND3_COEFF1 0xa8b8 +#define CS48L32_EQ3_BAND3_COEFF2 0xa8bc +#define CS48L32_EQ3_BAND3_PG 0xa8c0 +#define CS48L32_EQ3_BAND4_COEFF1 0xa8c4 +#define CS48L32_EQ3_BAND4_COEFF2 0xa8c8 +#define CS48L32_EQ3_BAND4_PG 0xa8cc +#define CS48L32_EQ3_BAND5_COEFF1 0xa8d0 +#define CS48L32_EQ3_BAND5_PG 0xa8d8 +#define CS48L32_EQ4_GAIN1 0xa8dc +#define CS48L32_EQ4_GAIN2 0xa8e0 +#define CS48L32_EQ4_BAND1_COEFF1 0xa8e4 +#define CS48L32_EQ4_BAND1_COEFF2 0xa8e8 +#define CS48L32_EQ4_BAND1_PG 0xa8ec +#define CS48L32_EQ4_BAND2_COEFF1 0xa8f0 +#define CS48L32_EQ4_BAND2_COEFF2 0xa8f4 +#define CS48L32_EQ4_BAND2_PG 0xa8f8 +#define CS48L32_EQ4_BAND3_COEFF1 0xa8fc +#define CS48L32_EQ4_BAND3_COEFF2 0xa900 +#define CS48L32_EQ4_BAND3_PG 0xa904 +#define CS48L32_EQ4_BAND4_COEFF1 0xa908 +#define CS48L32_EQ4_BAND4_COEFF2 0xa90c +#define CS48L32_EQ4_BAND4_PG 0xa910 +#define CS48L32_EQ4_BAND5_COEFF1 0xa914 +#define CS48L32_EQ4_BAND5_PG 0xa91c +#define CS48L32_LHPF_CONTROL1 0xaa30 +#define CS48L32_LHPF_CONTROL2 0xaa34 +#define CS48L32_LHPF1_COEFF 0xaa38 +#define CS48L32_LHPF2_COEFF 0xaa3c +#define CS48L32_LHPF3_COEFF 0xaa40 +#define CS48L32_LHPF4_COEFF 0xaa44 +#define CS48L32_DRC1_CONTROL1 0xab00 +#define CS48L32_DRC1_CONTROL4 0xab0c +#define CS48L32_DRC2_CONTROL1 0xab14 +#define CS48L32_DRC2_CONTROL4 0xab20 +#define CS48L32_TONE_GENERATOR1 0xb000 +#define CS48L32_TONE_GENERATOR2 0xb004 +#define CS48L32_COMFORT_NOISE_GENERATOR 0xb400 +#define CS48L32_US_CONTROL 0xb800 +#define CS48L32_US1_CONTROL 0xb804 +#define CS48L32_US1_DET_CONTROL 0xb808 +#define CS48L32_US2_CONTROL 0xb814 +#define CS48L32_US2_DET_CONTROL 0xb818 +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 0x1700c +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1 0x17010 +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 0x1706c +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 0x17070 +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1 0x17074 +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 0x17090 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 0x17094 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1 0x17098 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 0x170b0 +#define CS48L32_IRQ1_STATUS 0x18004 +#define CS48L32_IRQ1_EINT_1 0x18010 +#define CS48L32_IRQ1_EINT_2 0x18014 +#define CS48L32_IRQ1_EINT_7 0x18028 +#define CS48L32_IRQ1_EINT_9 0x18030 +#define CS48L32_IRQ1_EINT_11 0x18038 +#define CS48L32_IRQ1_STS_1 0x18090 +#define CS48L32_IRQ1_STS_6 0x180a4 +#define CS48L32_IRQ1_STS_11 0x180b8 +#define CS48L32_IRQ1_MASK_1 0x18110 +#define CS48L32_IRQ1_MASK_2 0x18114 +#define CS48L32_IRQ1_MASK_7 0x18128 +#define CS48L32_IRQ1_MASK_9 0x18130 +#define CS48L32_IRQ1_MASK_11 0x18138 +#define CS48L32_DSP1_XMEM_PACKED_0 0x2000000 +#define CS48L32_DSP1_XMEM_PACKED_LAST 0x208fff0 +#define CS48L32_DSP1_SYS_INFO_ID 0x25e0000 +#define CS48L32_DSP1_AHBM_WINDOW_DEBUG_1 0x25e2044 +#define CS48L32_DSP1_XMEM_UNPACKED24_0 0x2800000 +#define CS48L32_DSP1_XMEM_UNPACKED24_LAST 0x28bfff4 +#define CS48L32_DSP1_CLOCK_FREQ 0x2b80000 +#define CS48L32_DSP1_SAMPLE_RATE_TX8 0x2b802b8 +#define CS48L32_DSP1_SCRATCH1 0x2b805c0 +#define CS48L32_DSP1_SCRATCH4 0x2b805d8 +#define CS48L32_DSP1_CCM_CORE_CONTROL 0x2bc1000 +#define CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1 0x2bc5a00 +#define CS48L32_DSP1_YMEM_PACKED_0 0x2c00000 +#define CS48L32_DSP1_YMEM_PACKED_LAST 0x2c2fff0 +#define CS48L32_DSP1_YMEM_UNPACKED24_0 0x3400000 +#define CS48L32_DSP1_YMEM_UNPACKED24_LAST 0x343fff4 +#define CS48L32_DSP1_PMEM_0 0x3800000 +#define CS48L32_DSP1_PMEM_LAST 0x3845fe8 + +/* (0x0) DEVID */ +#define CS48L32_DEVID_MASK 0x00ffffff +#define CS48L32_DEVID_SHIFT 0 + +/* (0x4) REVID */ +#define CS48L32_AREVID_MASK 0x000000f0 +#define CS48L32_AREVID_SHIFT 4 +#define CS48L32_MTLREVID_MASK 0x0000000f +#define CS48L32_MTLREVID_SHIFT 0 + +/* (0x10) OTPID */ +#define CS48L32_OTPID_MASK 0x0000000f + +/* (0x0804) MCU_CTRL1 */ +#define CS48L32_MCU_STS_MASK 0x0000ff00 +#define CS48L32_MCU_STS_SHIFT 8 + +/* (0xc08) GPIO1_CTRL1 */ +#define CS48L32_GPIOX_CTRL1_FN_MASK 0x000003ff + +/* (0x1020) OUTPUT_SYS_CLK */ +#define CS48L32_OPCLK_EN_SHIFT 15 +#define CS48L32_OPCLK_DIV_MASK 0x000000f8 +#define CS48L32_OPCLK_DIV_SHIFT 3 +#define CS48L32_OPCLK_SEL_MASK 0x00000007 + +/* (0x105c) AUXPDM_CTRL2 */ +#define CS48L32_AUXPDMDAT2_SRC_SHIFT 4 +#define CS48L32_AUXPDMDAT1_SRC_SHIFT 0 + +/* (0x1400) CLOCK32K */ +#define CS48L32_CLK_32K_EN_MASK 0x00000040 +#define CS48L32_CLK_32K_SRC_MASK 0x00000003 + +/* (0x1404) SYSTEM_CLOCK1 */ +#define CS48L32_SYSCLK_FRAC_MASK 0x00008000 +#define CS48L32_SYSCLK_FREQ_MASK 0x00000700 +#define CS48L32_SYSCLK_FREQ_SHIFT 8 +#define CS48L32_SYSCLK_EN_SHIFT 6 +#define CS48L32_SYSCLK_SRC_MASK 0x0000001f +#define CS48L32_SYSCLK_SRC_SHIFT 0 + +/* (0x1408) SYSTEM_CLOCK2 */ +#define CS48L32_SYSCLK_FREQ_STS_MASK 0x00000700 +#define CS48L32_SYSCLK_FREQ_STS_SHIFT 8 + +/* (0x1420) SAMPLE_RATE1 */ +#define CS48L32_SAMPLE_RATE_1_MASK 0x0000001f +#define CS48L32_SAMPLE_RATE_1_SHIFT 0 + +/* (0x1510) DSP_CLOCK1 */ +#define CS48L32_DSP_CLK_FREQ_MASK 0xffff0000 +#define CS48L32_DSP_CLK_FREQ_SHIFT 16 + +/* (0x1c00) FLL_CONTROL1 */ +#define CS48L32_FLL_CTRL_UPD_MASK 0x00000004 +#define CS48L32_FLL_HOLD_MASK 0x00000002 +#define CS48L32_FLL_EN_MASK 0x00000001 + +/* (0x1c04) FLL_CONTROL2 */ +#define CS48L32_FLL_LOCKDET_THR_MASK 0xf0000000 +#define CS48L32_FLL_LOCKDET_THR_SHIFT 28 +#define CS48L32_FLL_LOCKDET_MASK 0x08000000 +#define CS48L32_FLL_PHASEDET_MASK 0x00400000 +#define CS48L32_FLL_PHASEDET_SHIFT 22 +#define CS48L32_FLL_REFCLK_DIV_MASK 0x00030000 +#define CS48L32_FLL_REFCLK_DIV_SHIFT 16 +#define CS48L32_FLL_REFCLK_SRC_MASK 0x0000f000 +#define CS48L32_FLL_REFCLK_SRC_SHIFT 12 +#define CS48L32_FLL_N_MASK 0x000003ff +#define CS48L32_FLL_N_SHIFT 0 + +/* (0x1c08) FLL_CONTROL3 */ +#define CS48L32_FLL_LAMBDA_MASK 0xffff0000 +#define CS48L32_FLL_LAMBDA_SHIFT 16 +#define CS48L32_FLL_THETA_MASK 0x0000ffff +#define CS48L32_FLL_THETA_SHIFT 0 + +/* (0x1c0c) FLL_CONTROL4 */ +#define CS48L32_FLL_FD_GAIN_COARSE_SHIFT 16 +#define CS48L32_FLL_HP_MASK 0x00003000 +#define CS48L32_FLL_HP_SHIFT 12 +#define CS48L32_FLL_FB_DIV_MASK 0x000003ff +#define CS48L32_FLL_FB_DIV_SHIFT 0 + +/* (0x1c10) FLL_CONTROL5 */ +#define CS48L32_FLL_FRC_INTEG_UPD_MASK 0x00008000 + +/* (0x2000) CHARGE_PUMP1 */ +#define CS48L32_CP2_BYPASS_SHIFT 1 +#define CS48L32_CP2_EN_SHIFT 0 + +/* (0x2408) LDO2_CTRL1 */ +#define CS48L32_LDO2_VSEL_MASK 0x000007e0 +#define CS48L32_LDO2_VSEL_SHIFT 5 + +/* (0x2410) MICBIAS_CTRL1 */ +#define CS48L32_MICB1_LVL_MASK 0x000001e0 +#define CS48L32_MICB1_LVL_SHIFT 5 +#define CS48L32_MICB1_EN_SHIFT 0 + +/* (0x2418) MICBIAS_CTRL5 */ +#define CS48L32_MICB1C_EN_SHIFT 8 +#define CS48L32_MICB1B_EN_SHIFT 4 +#define CS48L32_MICB1A_EN_SHIFT 0 + +/* (0x2710) IRQ1_CTRL_AOD */ +#define CS48L32_IRQ_POL_MASK 0x00000400 + +/* (0x4000) INPUT_CONTROL */ +#define CS48L32_IN2L_EN_SHIFT 3 +#define CS48L32_IN2R_EN_SHIFT 2 +#define CS48L32_IN1L_EN_SHIFT 1 +#define CS48L32_IN1R_EN_SHIFT 0 + +/* (0x400c) INPUT_CONTROL2 */ +#define CS48L32_PDM_FLLCLK_SRC_MASK 0x0000000f +#define CS48L32_PDM_FLLCLK_SRC_SHIFT 0 + +/* (0x4014) INPUT_CONTROL3 */ +#define CS48L32_IN_VU 0x20000000 +#define CS48L32_IN_VU_MASK 0x20000000 +#define CS48L32_IN_VU_SHIFT 29 +#define CS48L32_IN_VU_WIDTH 1 + +/* (0x4020) INPUT1_CONTROL1 */ +#define CS48L32_IN1_OSR_SHIFT 16 +#define CS48L32_IN1_PDM_SUP_MASK 0x00000300 +#define CS48L32_IN1_PDM_SUP_SHIFT 8 +#define CS48L32_IN1_MODE_SHIFT 0 + +/* + * (0x4024) IN1L_CONTROL1 + * (0x4044) IN1R_CONTROL1 + */ +#define CS48L32_INx_SRC_MASK 0x30000000 +#define CS48L32_INx_SRC_SHIFT 28 +#define CS48L32_INx_RATE_MASK 0x0000f800 +#define CS48L32_INx_RATE_SHIFT 11 +#define CS48L32_INx_HPF_SHIFT 2 +#define CS48L32_INx_LP_MODE_SHIFT 0 + +/* + * (0x4028) IN1L_CONTROL2 + * (0x4048) IN1R_CONTROL2 + */ +#define CS48L32_INx_MUTE_MASK 0x10000000 +#define CS48L32_INx_VOL_SHIFT 16 +#define CS48L32_INx_PGA_VOL_SHIFT 1 + +/* (0x4244) INPUT_HPF_CONTROL */ +#define CS48L32_IN_HPF_CUT_SHIFT 0 + +/* (0x4248) INPUT_VOL_CONTROL */ +#define CS48L32_IN_VD_RAMP_SHIFT 4 +#define CS48L32_IN_VI_RAMP_SHIFT 0 + +/* (0x4308) AUXPDM1_CONTROL1 */ +#define CS48L32_AUXPDM1_FREQ_SHIFT 16 +#define CS48L32_AUXPDM1_SRC_MASK 0x00000f00 +#define CS48L32_AUXPDM1_SRC_SHIFT 8 + +/* (0x4688) ADC1L_ANA_CONTROL1 */ +/* (0x468c) ADC1R_ANA_CONTROL1 */ +#define CS48L32_ADC1x_INT_ENA_FRC_MASK 0x00000002 + +/* (0x6004) ASPn_CONTROL1 */ +#define CS48L32_ASP_RATE_MASK 0x00001f00 +#define CS48L32_ASP_RATE_SHIFT 8 +#define CS48L32_ASP_BCLK_FREQ_MASK 0x0000003f + +/* (0x6008) ASPn_CONTROL2 */ +#define CS48L32_ASP_RX_WIDTH_MASK 0xff000000 +#define CS48L32_ASP_RX_WIDTH_SHIFT 24 +#define CS48L32_ASP_TX_WIDTH_MASK 0x00ff0000 +#define CS48L32_ASP_TX_WIDTH_SHIFT 16 +#define CS48L32_ASP_FMT_MASK 0x00000700 +#define CS48L32_ASP_FMT_SHIFT 8 +#define CS48L32_ASP_BCLK_INV_MASK 0x00000040 +#define CS48L32_ASP_BCLK_MSTR_MASK 0x00000010 +#define CS48L32_ASP_FSYNC_INV_MASK 0x00000004 +#define CS48L32_ASP_FSYNC_MSTR_MASK 0x00000001 + +/* (0x6010) ASPn_CONTROL3 */ +#define CS48L32_ASP_DOUT_HIZ_MASK 0x00000003 + +/* (0x6030) ASPn_DATA_CONTROL1 */ +#define CS48L32_ASP_TX_WL_MASK 0x0000003f + +/* (0x6040) ASPn_DATA_CONTROL5 */ +#define CS48L32_ASP_RX_WL_MASK 0x0000003f + +/* (0x82xx - 0x90xx) *_INPUT[1-4] */ +#define CS48L32_MIXER_VOL_MASK 0x00FE0000 +#define CS48L32_MIXER_VOL_SHIFT 17 +#define CS48L32_MIXER_VOL_WIDTH 7 +#define CS48L32_MIXER_SRC_MASK 0x000001ff +#define CS48L32_MIXER_SRC_SHIFT 0 +#define CS48L32_MIXER_SRC_WIDTH 9 + +/* (0xa400) ISRC1_CONTROL1 */ +#define CS48L32_ISRC1_FSL_MASK 0xf8000000 +#define CS48L32_ISRC1_FSL_SHIFT 27 +#define CS48L32_ISRC1_FSH_MASK 0x0000f800 +#define CS48L32_ISRC1_FSH_SHIFT 11 + +/* (0xa404) ISRC1_CONTROL2 */ +#define CS48L32_ISRC1_INT4_EN_SHIFT 11 +#define CS48L32_ISRC1_INT3_EN_SHIFT 10 +#define CS48L32_ISRC1_INT2_EN_SHIFT 9 +#define CS48L32_ISRC1_INT1_EN_SHIFT 8 +#define CS48L32_ISRC1_DEC4_EN_SHIFT 3 +#define CS48L32_ISRC1_DEC3_EN_SHIFT 2 +#define CS48L32_ISRC1_DEC2_EN_SHIFT 1 +#define CS48L32_ISRC1_DEC1_EN_SHIFT 0 + +/* (0xa800) FX_SAMPLE_RATE */ +#define CS48L32_FX_RATE_MASK 0x0000f800 +#define CS48L32_FX_RATE_SHIFT 11 + +/* (0xab00) DRC1_CONTROL1 */ +#define CS48L32_DRC1L_EN_SHIFT 1 +#define CS48L32_DRC1R_EN_SHIFT 0 + +/* (0xb400) Comfort_Noise_Generator */ +#define CS48L32_NOISE_GEN_RATE_MASK 0x0000f800 +#define CS48L32_NOISE_GEN_RATE_SHIFT 11 +#define CS48L32_NOISE_GEN_EN_SHIFT 5 +#define CS48L32_NOISE_GEN_GAIN_SHIFT 0 + +/* (0xb800) US_CONTROL */ +#define CS48L32_US1_DET_EN_SHIFT 8 + +/* (0xb804) US1_CONTROL */ +#define CS48L32_US1_RATE_MASK 0xf8000000 +#define CS48L32_US1_RATE_SHIFT 27 +#define CS48L32_US1_GAIN_SHIFT 12 +#define CS48L32_US1_SRC_MASK 0x00000f00 +#define CS48L32_US1_SRC_SHIFT 8 +#define CS48L32_US1_FREQ_MASK 0x00000070 +#define CS48L32_US1_FREQ_SHIFT 4 + +/* (0xb808) US1_DET_CONTROL */ +#define CS48L32_US1_DET_DCY_SHIFT 28 +#define CS48L32_US1_DET_HOLD_SHIFT 24 +#define CS48L32_US1_DET_NUM_SHIFT 20 +#define CS48L32_US1_DET_THR_SHIFT 16 +#define CS48L32_US1_DET_LPF_CUT_SHIFT 5 +#define CS48L32_US1_DET_LPF_SHIFT 4 + +/* (0x18004) IRQ1_STATUS */ +#define CS48L32_IRQ1_STS_MASK 0x00000001 + +/* (0x18014) IRQ1_EINT_2 */ +#define CS48L32_BOOT_DONE_EINT1_MASK 0x00000008 + +/* (0x18028) IRQ1_EINT_7 */ +#define CS48L32_DSP1_MPU_ERR_EINT1_MASK 0x00200000 +#define CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK 0x00100000 + +/* (0x18030) IRQ1_EINT_9 */ +#define CS48L32_DSP1_IRQ0_EINT1_MASK 0x00000001 + +/* (0x180a4) IRQ1_STS_6 */ +#define CS48L32_FLL1_LOCK_STS1_MASK 0x00000001 + +#endif diff --git a/include/sound/cs8403.h b/include/sound/cs8403.h new file mode 100644 index 000000000..c27f77639 --- /dev/null +++ b/include/sound/cs8403.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CS8403_H +#define __SOUND_CS8403_H + +/* + * Routines for Cirrus Logic CS8403/CS8404A IEC958 (S/PDIF) Transmitter + * Copyright (c) by Jaroslav Kysela , + * Takashi Iwai + */ + +#ifdef SND_CS8403 + +#ifndef SND_CS8403_DECL +#define SND_CS8403_DECL static +#endif +#ifndef SND_CS8403_DECODE +#define SND_CS8403_DECODE snd_cs8403_decode_spdif_bits +#endif +#ifndef SND_CS8403_ENCODE +#define SND_CS8403_ENCODE snd_cs8403_encode_spdif_bits +#endif + + +SND_CS8403_DECL void SND_CS8403_DECODE(struct snd_aes_iec958 *diga, unsigned char bits) +{ + if (bits & 0x01) { /* consumer */ + if (!(bits & 0x02)) + diga->status[0] |= IEC958_AES0_NONAUDIO; + if (!(bits & 0x08)) + diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT; + switch (bits & 0x10) { + case 0x10: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_NONE; break; + case 0x00: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; break; + } + if (!(bits & 0x80)) + diga->status[1] |= IEC958_AES1_CON_ORIGINAL; + switch (bits & 0x60) { + case 0x00: diga->status[1] |= IEC958_AES1_CON_MAGNETIC_ID; break; + case 0x20: diga->status[1] |= IEC958_AES1_CON_DIGDIGCONV_ID; break; + case 0x40: diga->status[1] |= IEC958_AES1_CON_LASEROPT_ID; break; + case 0x60: diga->status[1] |= IEC958_AES1_CON_GENERAL; break; + } + switch (bits & 0x06) { + case 0x00: diga->status[3] |= IEC958_AES3_CON_FS_44100; break; + case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_48000; break; + case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_32000; break; + } + } else { + diga->status[0] = IEC958_AES0_PROFESSIONAL; + switch (bits & 0x18) { + case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break; + case 0x10: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break; + case 0x08: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break; + case 0x18: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break; + } + switch (bits & 0x60) { + case 0x20: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break; + case 0x40: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break; + case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break; + case 0x60: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break; + } + if (bits & 0x80) + diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC; + } +} + +SND_CS8403_DECL unsigned char SND_CS8403_ENCODE(struct snd_aes_iec958 *diga) +{ + unsigned char bits; + + if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) { + bits = 0x01; /* consumer mode */ + if (diga->status[0] & IEC958_AES0_NONAUDIO) + bits &= ~0x02; + else + bits |= 0x02; + if (diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT) + bits &= ~0x08; + else + bits |= 0x08; + switch (diga->status[0] & IEC958_AES0_CON_EMPHASIS) { + default: + case IEC958_AES0_CON_EMPHASIS_NONE: bits |= 0x10; break; + case IEC958_AES0_CON_EMPHASIS_5015: bits |= 0x00; break; + } + if (diga->status[1] & IEC958_AES1_CON_ORIGINAL) + bits &= ~0x80; + else + bits |= 0x80; + if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL) + bits |= 0x60; + else { + switch(diga->status[1] & IEC958_AES1_CON_MAGNETIC_MASK) { + case IEC958_AES1_CON_MAGNETIC_ID: + bits |= 0x00; break; + case IEC958_AES1_CON_DIGDIGCONV_ID: + bits |= 0x20; break; + default: + case IEC958_AES1_CON_LASEROPT_ID: + bits |= 0x40; break; + } + } + switch (diga->status[3] & IEC958_AES3_CON_FS) { + default: + case IEC958_AES3_CON_FS_44100: bits |= 0x00; break; + case IEC958_AES3_CON_FS_48000: bits |= 0x02; break; + case IEC958_AES3_CON_FS_32000: bits |= 0x04; break; + } + } else { + bits = 0x00; /* professional mode */ + if (diga->status[0] & IEC958_AES0_NONAUDIO) + bits &= ~0x02; + else + bits |= 0x02; + /* CHECKME: I'm not sure about the bit order in val here */ + switch (diga->status[0] & IEC958_AES0_PRO_FS) { + case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break; + case IEC958_AES0_PRO_FS_44100: bits |= 0x10; break; /* 44.1kHz */ + case IEC958_AES0_PRO_FS_48000: bits |= 0x08; break; /* 48kHz */ + default: + case IEC958_AES0_PRO_FS_NOTID: bits |= 0x18; break; + } + switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) { + case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x20; break; + case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x40; break; + case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break; + default: + case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x60; break; + } + switch (diga->status[1] & IEC958_AES1_PRO_MODE) { + case IEC958_AES1_PRO_MODE_TWO: + case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break; + default: bits |= 0x80; break; + } + } + return bits; +} + +#endif /* SND_CS8403 */ + +#ifdef SND_CS8404 + +#ifndef SND_CS8404_DECL +#define SND_CS8404_DECL static +#endif +#ifndef SND_CS8404_DECODE +#define SND_CS8404_DECODE snd_cs8404_decode_spdif_bits +#endif +#ifndef SND_CS8404_ENCODE +#define SND_CS8404_ENCODE snd_cs8404_encode_spdif_bits +#endif + + +SND_CS8404_DECL void SND_CS8404_DECODE(struct snd_aes_iec958 *diga, unsigned char bits) +{ + if (bits & 0x10) { /* consumer */ + if (!(bits & 0x20)) + diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT; + if (!(bits & 0x40)) + diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; + if (!(bits & 0x80)) + diga->status[1] |= IEC958_AES1_CON_ORIGINAL; + switch (bits & 0x03) { + case 0x00: diga->status[1] |= IEC958_AES1_CON_DAT; break; + case 0x03: diga->status[1] |= IEC958_AES1_CON_GENERAL; break; + } + switch (bits & 0x06) { + case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_32000; break; + case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_48000; break; + case 0x06: diga->status[3] |= IEC958_AES3_CON_FS_44100; break; + } + } else { + diga->status[0] = IEC958_AES0_PROFESSIONAL; + if (!(bits & 0x04)) + diga->status[0] |= IEC958_AES0_NONAUDIO; + switch (bits & 0x60) { + case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break; + case 0x40: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break; + case 0x20: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break; + case 0x60: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break; + } + switch (bits & 0x03) { + case 0x02: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break; + case 0x01: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break; + case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break; + case 0x03: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break; + } + if (!(bits & 0x80)) + diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC; + } +} + +SND_CS8404_DECL unsigned char SND_CS8404_ENCODE(struct snd_aes_iec958 *diga) +{ + unsigned char bits; + + if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) { + bits = 0x10; /* consumer mode */ + if (!(diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT)) + bits |= 0x20; + if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) == IEC958_AES0_CON_EMPHASIS_NONE) + bits |= 0x40; + if (!(diga->status[1] & IEC958_AES1_CON_ORIGINAL)) + bits |= 0x80; + if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL) + bits |= 0x03; + switch (diga->status[3] & IEC958_AES3_CON_FS) { + default: + case IEC958_AES3_CON_FS_44100: bits |= 0x06; break; + case IEC958_AES3_CON_FS_48000: bits |= 0x04; break; + case IEC958_AES3_CON_FS_32000: bits |= 0x02; break; + } + } else { + bits = 0x00; /* professional mode */ + if (!(diga->status[0] & IEC958_AES0_NONAUDIO)) + bits |= 0x04; + switch (diga->status[0] & IEC958_AES0_PRO_FS) { + case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break; + case IEC958_AES0_PRO_FS_44100: bits |= 0x40; break; /* 44.1kHz */ + case IEC958_AES0_PRO_FS_48000: bits |= 0x20; break; /* 48kHz */ + default: + case IEC958_AES0_PRO_FS_NOTID: bits |= 0x00; break; + } + switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) { + case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x02; break; + case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x01; break; + case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break; + default: + case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x03; break; + } + switch (diga->status[1] & IEC958_AES1_PRO_MODE) { + case IEC958_AES1_PRO_MODE_TWO: + case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break; + default: bits |= 0x80; break; + } + } + return bits; +} + +#endif /* SND_CS8404 */ + +#endif /* __SOUND_CS8403_H */ diff --git a/include/sound/cs8427.h b/include/sound/cs8427.h new file mode 100644 index 000000000..38b730bd5 --- /dev/null +++ b/include/sound/cs8427.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CS8427_H +#define __SOUND_CS8427_H + +/* + * Routines for Cirrus Logic CS8427 + * Copyright (c) by Jaroslav Kysela , + */ + +#include + +#define CS8427_BASE_ADDR 0x10 /* base I2C address */ + +#define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */ +#define CS8427_REG_CONTROL1 0x01 +#define CS8427_REG_CONTROL2 0x02 +#define CS8427_REG_DATAFLOW 0x03 +#define CS8427_REG_CLOCKSOURCE 0x04 +#define CS8427_REG_SERIALINPUT 0x05 +#define CS8427_REG_SERIALOUTPUT 0x06 +#define CS8427_REG_INT1STATUS 0x07 +#define CS8427_REG_INT2STATUS 0x08 +#define CS8427_REG_INT1MASK 0x09 +#define CS8427_REG_INT1MODEMSB 0x0a +#define CS8427_REG_INT1MODELSB 0x0b +#define CS8427_REG_INT2MASK 0x0c +#define CS8427_REG_INT2MODEMSB 0x0d +#define CS8427_REG_INT2MODELSB 0x0e +#define CS8427_REG_RECVCSDATA 0x0f +#define CS8427_REG_RECVERRORS 0x10 +#define CS8427_REG_RECVERRMASK 0x11 +#define CS8427_REG_CSDATABUF 0x12 +#define CS8427_REG_UDATABUF 0x13 +#define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */ +#define CS8427_REG_OMCKRMCKRATIO 0x1e +#define CS8427_REG_CORU_DATABUF 0x20 /* 24 byte buffer area */ +#define CS8427_REG_ID_AND_VER 0x7f + +/* CS8427_REG_CONTROL1 bits */ +#define CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */ +#define CS8427_VSET (1<<6) /* 0 = valid PCM data, 1 = invalid PCM data */ +#define CS8427_MUTESAO (1<<5) /* mute control for the serial audio output port, 0 = disabled, 1 = enabled */ +#define CS8427_MUTEAES (1<<4) /* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */ +#define CS8427_INTMASK (3<<1) /* interrupt output pin setup mask */ +#define CS8427_INTACTHIGH (0<<1) /* active high */ +#define CS8427_INTACTLOW (1<<1) /* active low */ +#define CS8427_INTOPENDRAIN (2<<1) /* open drain, active low */ +#define CS8427_TCBLDIR (1<<0) /* 0 = TCBL is an input, 1 = TCBL is an output */ + +/* CS8427_REQ_CONTROL2 bits */ +#define CS8427_HOLDMASK (3<<5) /* action when a receiver error occurs */ +#define CS8427_HOLDLASTSAMPLE (0<<5) /* hold the last valid sample */ +#define CS8427_HOLDZERO (1<<5) /* replace the current audio sample with zero (mute) */ +#define CS8427_HOLDNOCHANGE (2<<5) /* do not change the received audio sample */ +#define CS8427_RMCKF (1<<4) /* 0 = 256*Fsi, 1 = 128*Fsi */ +#define CS8427_MMR (1<<3) /* AES3 receiver operation, 0 = stereo, 1 = mono */ +#define CS8427_MMT (1<<2) /* AES3 transmitter operation, 0 = stereo, 1 = mono */ +#define CS8427_MMTCS (1<<1) /* 0 = use A + B CS data, 1 = use MMTLR CS data */ +#define CS8427_MMTLR (1<<0) /* 0 = use A CS data, 1 = use B CS data */ + +/* CS8427_REG_DATAFLOW */ +#define CS8427_TXOFF (1<<6) /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */ +#define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */ +#define CS8427_TXDMASK (3<<3) /* AES3 Transmitter Data Source Mask */ +#define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */ +#define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */ +#define CS8427_SPDMASK (3<<1) /* Serial Audio Output Port Data Source Mask */ +#define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */ +#define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */ + +/* CS8427_REG_CLOCKSOURCE */ +#define CS8427_RUN (1<<6) /* 0 = clock off, 1 = clock on */ +#define CS8427_CLKMASK (3<<4) /* OMCK frequency mask */ +#define CS8427_CLK256 (0<<4) /* 256*Fso */ +#define CS8427_CLK384 (1<<4) /* 384*Fso */ +#define CS8427_CLK512 (2<<4) /* 512*Fso */ +#define CS8427_OUTC (1<<3) /* Output Time Base, 0 = OMCK, 1 = recovered input clock */ +#define CS8427_INC (1<<2) /* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */ +#define CS8427_RXDMASK (3<<0) /* Recovered Input Clock Source Mask */ +#define CS8427_RXDILRCK (0<<0) /* 256*Fsi from ILRCK pin */ +#define CS8427_RXDAES3INPUT (1<<0) /* 256*Fsi from AES3 input */ +#define CS8427_EXTCLOCKRESET (2<<0) /* bypass PLL, 256*Fsi clock, synchronous reset */ +#define CS8427_EXTCLOCK (3<<0) /* bypass PLL, 256*Fsi clock */ + +/* CS8427_REG_SERIALINPUT */ +#define CS8427_SIMS (1<<7) /* 0 = slave, 1 = master mode */ +#define CS8427_SISF (1<<6) /* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */ +#define CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */ +#define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */ +#define CS8427_SIRES20 (1<<4) /* SIRES 20-bit */ +#define CS8427_SIRES16 (2<<4) /* SIRES 16-bit */ +#define CS8427_SIJUST (1<<3) /* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */ +#define CS8427_SIDEL (1<<2) /* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */ +#define CS8427_SISPOL (1<<1) /* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */ +#define CS8427_SILRPOL (1<<0) /* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */ + +/* CS8427_REG_SERIALOUTPUT */ +#define CS8427_SOMS (1<<7) /* 0 = slave, 1 = master mode */ +#define CS8427_SOSF (1<<6) /* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */ +#define CS8427_SORESMASK (3<<4) /* Resolution of the output data on SDOUT and AES3 output */ +#define CS8427_SORES24 (0<<4) /* SIRES 24-bit */ +#define CS8427_SORES20 (1<<4) /* SIRES 20-bit */ +#define CS8427_SORES16 (2<<4) /* SIRES 16-bit */ +#define CS8427_SORESDIRECT (2<<4) /* SIRES direct copy from AES3 receiver */ +#define CS8427_SOJUST (1<<3) /* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */ +#define CS8427_SODEL (1<<2) /* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */ +#define CS8427_SOSPOL (1<<1) /* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */ +#define CS8427_SOLRPOL (1<<0) /* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */ + +/* CS8427_REG_INT1STATUS */ +#define CS8427_TSLIP (1<<7) /* AES3 transmitter source data slip interrupt */ +#define CS8427_OSLIP (1<<6) /* Serial audio output port data slip interrupt */ +#define CS8427_DETC (1<<2) /* D to E C-buffer transfer interrupt */ +#define CS8427_EFTC (1<<1) /* E to F C-buffer transfer interrupt */ +#define CS8427_RERR (1<<0) /* A receiver error has occurred */ + +/* CS8427_REG_INT2STATUS */ +#define CS8427_DETU (1<<3) /* D to E U-buffer transfer interrupt */ +#define CS8427_EFTU (1<<2) /* E to F U-buffer transfer interrupt */ +#define CS8427_QCH (1<<1) /* A new block of Q-subcode data is available for reading */ + +/* CS8427_REG_INT1MODEMSB && CS8427_REG_INT1MODELSB */ +/* bits are defined in CS8427_REG_INT1STATUS */ +/* CS8427_REG_INT2MODEMSB && CS8427_REG_INT2MODELSB */ +/* bits are defined in CS8427_REG_INT2STATUS */ +#define CS8427_INTMODERISINGMSB 0 +#define CS8427_INTMODERESINGLSB 0 +#define CS8427_INTMODEFALLINGMSB 0 +#define CS8427_INTMODEFALLINGLSB 1 +#define CS8427_INTMODELEVELMSB 1 +#define CS8427_INTMODELEVELLSB 0 + +/* CS8427_REG_RECVCSDATA */ +#define CS8427_AUXMASK (15<<4) /* auxiliary data field width */ +#define CS8427_AUXSHIFT 4 +#define CS8427_PRO (1<<3) /* Channel status block format indicator */ +#define CS8427_AUDIO (1<<2) /* Audio indicator (0 = audio, 1 = nonaudio */ +#define CS8427_COPY (1<<1) /* 0 = copyright asserted, 1 = copyright not asserted */ +#define CS8427_ORIG (1<<0) /* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */ + +/* CS8427_REG_RECVERRORS */ +/* CS8427_REG_RECVERRMASK for CS8427_RERR */ +#define CS8427_QCRC (1<<6) /* Q-subcode data CRC error indicator */ +#define CS8427_CCRC (1<<5) /* Chancnel Status Block Cyclick Redundancy Check Bit */ +#define CS8427_UNLOCK (1<<4) /* PLL lock status bit */ +#define CS8427_V (1<<3) /* 0 = valid data */ +#define CS8427_CONF (1<<2) /* Confidence bit */ +#define CS8427_BIP (1<<1) /* Bi-phase error bit */ +#define CS8427_PAR (1<<0) /* Parity error */ + +/* CS8427_REG_CSDATABUF */ +#define CS8427_BSEL (1<<5) /* 0 = CS data, 1 = U data */ +#define CS8427_CBMR (1<<4) /* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */ +#define CS8427_DETCI (1<<3) /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ +#define CS8427_EFTCI (1<<2) /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ +#define CS8427_CAM (1<<1) /* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */ +#define CS8427_CHS (1<<0) /* Channel select bit, 0 = Channel A, 1 = Channel B */ + +/* CS8427_REG_UDATABUF */ +#define CS8427_UD (1<<4) /* User data pin (U) direction, 0 = input, 1 = output */ +#define CS8427_UBMMASK (3<<2) /* Operating mode of the AES3 U bit manager */ +#define CS8427_UBMZEROS (0<<2) /* transmit all zeros mode */ +#define CS8427_UBMBLOCK (1<<2) /* block mode */ +#define CS8427_DETUI (1<<1) /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ +#define CS8427_EFTUI (1<<1) /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ + +/* CS8427_REG_ID_AND_VER */ +#define CS8427_IDMASK (15<<4) +#define CS8427_IDSHIFT 4 +#define CS8427_VERMASK (15<<0) +#define CS8427_VERSHIFT 0 +#define CS8427_VER8427A 0x71 + +struct snd_pcm_substream; + +int snd_cs8427_init(struct snd_i2c_bus *bus, struct snd_i2c_device *device); +int snd_cs8427_create(struct snd_i2c_bus *bus, unsigned char addr, + unsigned int reset_timeout, struct snd_i2c_device **r_cs8427); +int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg, + unsigned char val); +int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427, + struct snd_pcm_substream *playback_substream, + struct snd_pcm_substream *capture_substream); +int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active); +int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate); + +#endif /* __SOUND_CS8427_H */ diff --git a/include/sound/da7213.h b/include/sound/da7213.h new file mode 100644 index 000000000..6216a0a7b --- /dev/null +++ b/include/sound/da7213.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * da7213.h - DA7213 ASoC Codec Driver Platform Data + * + * Copyright (c) 2013 Dialog Semiconductor + * + * Author: Adam Thomson + */ + +#ifndef _DA7213_PDATA_H +#define _DA7213_PDATA_H + +enum da7213_micbias_voltage { + DA7213_MICBIAS_1_6V = 0, + DA7213_MICBIAS_2_2V = 1, + DA7213_MICBIAS_2_5V = 2, + DA7213_MICBIAS_3_0V = 3, +}; + +enum da7213_dmic_data_sel { + DA7213_DMIC_DATA_LRISE_RFALL = 0, + DA7213_DMIC_DATA_LFALL_RRISE = 1, +}; + +enum da7213_dmic_samplephase { + DA7213_DMIC_SAMPLE_ON_CLKEDGE = 0, + DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE = 1, +}; + +enum da7213_dmic_clk_rate { + DA7213_DMIC_CLK_3_0MHZ = 0, + DA7213_DMIC_CLK_1_5MHZ = 1, +}; + +struct da7213_platform_data { + /* Mic Bias voltage */ + enum da7213_micbias_voltage micbias1_lvl; + enum da7213_micbias_voltage micbias2_lvl; + + /* DMIC config */ + enum da7213_dmic_data_sel dmic_data_sel; + enum da7213_dmic_samplephase dmic_samplephase; + enum da7213_dmic_clk_rate dmic_clk_rate; +}; + +#endif /* _DA7213_PDATA_H */ diff --git a/include/sound/da7218.h b/include/sound/da7218.h new file mode 100644 index 000000000..9d0a82fbe --- /dev/null +++ b/include/sound/da7218.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * da7218.h - DA7218 ASoC Codec Driver Platform Data + * + * Copyright (c) 2015 Dialog Semiconductor + * + * Author: Adam Thomson + */ + +#ifndef _DA7218_PDATA_H +#define _DA7218_PDATA_H + +/* Mic Bias */ +enum da7218_micbias_voltage { + DA7218_MICBIAS_1_2V = -1, + DA7218_MICBIAS_1_6V, + DA7218_MICBIAS_1_8V, + DA7218_MICBIAS_2_0V, + DA7218_MICBIAS_2_2V, + DA7218_MICBIAS_2_4V, + DA7218_MICBIAS_2_6V, + DA7218_MICBIAS_2_8V, + DA7218_MICBIAS_3_0V, +}; + +enum da7218_mic_amp_in_sel { + DA7218_MIC_AMP_IN_SEL_DIFF = 0, + DA7218_MIC_AMP_IN_SEL_SE_P, + DA7218_MIC_AMP_IN_SEL_SE_N, +}; + +/* DMIC */ +enum da7218_dmic_data_sel { + DA7218_DMIC_DATA_LRISE_RFALL = 0, + DA7218_DMIC_DATA_LFALL_RRISE, +}; + +enum da7218_dmic_samplephase { + DA7218_DMIC_SAMPLE_ON_CLKEDGE = 0, + DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE, +}; + +enum da7218_dmic_clk_rate { + DA7218_DMIC_CLK_3_0MHZ = 0, + DA7218_DMIC_CLK_1_5MHZ, +}; + +/* Headphone Detect */ +enum da7218_hpldet_jack_rate { + DA7218_HPLDET_JACK_RATE_5US = 0, + DA7218_HPLDET_JACK_RATE_10US, + DA7218_HPLDET_JACK_RATE_20US, + DA7218_HPLDET_JACK_RATE_40US, + DA7218_HPLDET_JACK_RATE_80US, + DA7218_HPLDET_JACK_RATE_160US, + DA7218_HPLDET_JACK_RATE_320US, + DA7218_HPLDET_JACK_RATE_640US, +}; + +enum da7218_hpldet_jack_debounce { + DA7218_HPLDET_JACK_DEBOUNCE_OFF = 0, + DA7218_HPLDET_JACK_DEBOUNCE_2, + DA7218_HPLDET_JACK_DEBOUNCE_3, + DA7218_HPLDET_JACK_DEBOUNCE_4, +}; + +enum da7218_hpldet_jack_thr { + DA7218_HPLDET_JACK_THR_84PCT = 0, + DA7218_HPLDET_JACK_THR_88PCT, + DA7218_HPLDET_JACK_THR_92PCT, + DA7218_HPLDET_JACK_THR_96PCT, +}; + +struct da7218_hpldet_pdata { + enum da7218_hpldet_jack_rate jack_rate; + enum da7218_hpldet_jack_debounce jack_debounce; + enum da7218_hpldet_jack_thr jack_thr; + bool comp_inv; + bool hyst; + bool discharge; +}; + +struct da7218_pdata { + /* Mic */ + enum da7218_micbias_voltage micbias1_lvl; + enum da7218_micbias_voltage micbias2_lvl; + enum da7218_mic_amp_in_sel mic1_amp_in_sel; + enum da7218_mic_amp_in_sel mic2_amp_in_sel; + + /* DMIC */ + enum da7218_dmic_data_sel dmic1_data_sel; + enum da7218_dmic_data_sel dmic2_data_sel; + enum da7218_dmic_samplephase dmic1_samplephase; + enum da7218_dmic_samplephase dmic2_samplephase; + enum da7218_dmic_clk_rate dmic1_clk_rate; + enum da7218_dmic_clk_rate dmic2_clk_rate; + + /* HP Diff Supply - DA7217 only */ + bool hp_diff_single_supply; + + /* HP Detect - DA7218 only */ + struct da7218_hpldet_pdata *hpldet_pdata; +}; + +#endif /* _DA7218_PDATA_H */ diff --git a/include/sound/da7219-aad.h b/include/sound/da7219-aad.h new file mode 100644 index 000000000..41320522d --- /dev/null +++ b/include/sound/da7219-aad.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * da7219-aad.h - DA7322 ASoC Codec AAD Driver Platform Data + * + * Copyright (c) 2015 Dialog Semiconductor Ltd. + * + * Author: Adam Thomson + */ + +#ifndef __DA7219_AAD_PDATA_H +#define __DA7219_AAD_PDATA_H + +enum da7219_aad_micbias_pulse_lvl { + DA7219_AAD_MICBIAS_PULSE_LVL_OFF = 0, + DA7219_AAD_MICBIAS_PULSE_LVL_2_8V = 6, + DA7219_AAD_MICBIAS_PULSE_LVL_2_9V, +}; + +enum da7219_aad_btn_cfg { + DA7219_AAD_BTN_CFG_2MS = 1, + DA7219_AAD_BTN_CFG_5MS, + DA7219_AAD_BTN_CFG_10MS, + DA7219_AAD_BTN_CFG_50MS, + DA7219_AAD_BTN_CFG_100MS, + DA7219_AAD_BTN_CFG_200MS, + DA7219_AAD_BTN_CFG_500MS, +}; + +enum da7219_aad_mic_det_thr { + DA7219_AAD_MIC_DET_THR_200_OHMS = 0, + DA7219_AAD_MIC_DET_THR_500_OHMS, + DA7219_AAD_MIC_DET_THR_750_OHMS, + DA7219_AAD_MIC_DET_THR_1000_OHMS, +}; + +enum da7219_aad_jack_ins_deb { + DA7219_AAD_JACK_INS_DEB_5MS = 0, + DA7219_AAD_JACK_INS_DEB_10MS, + DA7219_AAD_JACK_INS_DEB_20MS, + DA7219_AAD_JACK_INS_DEB_50MS, + DA7219_AAD_JACK_INS_DEB_100MS, + DA7219_AAD_JACK_INS_DEB_200MS, + DA7219_AAD_JACK_INS_DEB_500MS, + DA7219_AAD_JACK_INS_DEB_1S, +}; + +enum da7219_aad_jack_ins_det_pty { + DA7219_AAD_JACK_INS_DET_PTY_LOW = 0, + DA7219_AAD_JACK_INS_DET_PTY_HIGH, +}; + +enum da7219_aad_jack_det_rate { + DA7219_AAD_JACK_DET_RATE_32_64MS = 0, + DA7219_AAD_JACK_DET_RATE_64_128MS, + DA7219_AAD_JACK_DET_RATE_128_256MS, + DA7219_AAD_JACK_DET_RATE_256_512MS, +}; + +enum da7219_aad_jack_rem_deb { + DA7219_AAD_JACK_REM_DEB_1MS = 0, + DA7219_AAD_JACK_REM_DEB_5MS, + DA7219_AAD_JACK_REM_DEB_10MS, + DA7219_AAD_JACK_REM_DEB_20MS, +}; + +enum da7219_aad_btn_avg { + DA7219_AAD_BTN_AVG_1 = 0, + DA7219_AAD_BTN_AVG_2, + DA7219_AAD_BTN_AVG_4, + DA7219_AAD_BTN_AVG_8, +}; + +enum da7219_aad_adc_1bit_rpt { + DA7219_AAD_ADC_1BIT_RPT_1 = 0, + DA7219_AAD_ADC_1BIT_RPT_2, + DA7219_AAD_ADC_1BIT_RPT_4, + DA7219_AAD_ADC_1BIT_RPT_8, +}; + +struct da7219_aad_pdata { + int irq; + + enum da7219_aad_micbias_pulse_lvl micbias_pulse_lvl; + u32 micbias_pulse_time; + enum da7219_aad_btn_cfg btn_cfg; + enum da7219_aad_mic_det_thr mic_det_thr; + enum da7219_aad_jack_ins_deb jack_ins_deb; + enum da7219_aad_jack_ins_det_pty jack_ins_det_pty; + enum da7219_aad_jack_det_rate jack_det_rate; + enum da7219_aad_jack_rem_deb jack_rem_deb; + + u8 a_d_btn_thr; + u8 d_b_btn_thr; + u8 b_c_btn_thr; + u8 c_mic_btn_thr; + + enum da7219_aad_btn_avg btn_avg; + enum da7219_aad_adc_1bit_rpt adc_1bit_rpt; +}; + +#endif /* __DA7219_AAD_PDATA_H */ diff --git a/include/sound/da7219.h b/include/sound/da7219.h new file mode 100644 index 000000000..dde4542b0 --- /dev/null +++ b/include/sound/da7219.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * da7219.h - DA7219 ASoC Codec Driver Platform Data + * + * Copyright (c) 2015 Dialog Semiconductor + * + * Author: Adam Thomson + */ + +#ifndef __DA7219_PDATA_H +#define __DA7219_PDATA_H + +/* Mic Bias */ +enum da7219_micbias_voltage { + DA7219_MICBIAS_1_6V = 0, + DA7219_MICBIAS_1_8V, + DA7219_MICBIAS_2_0V, + DA7219_MICBIAS_2_2V, + DA7219_MICBIAS_2_4V, + DA7219_MICBIAS_2_6V, +}; + +/* Mic input type */ +enum da7219_mic_amp_in_sel { + DA7219_MIC_AMP_IN_SEL_DIFF = 0, + DA7219_MIC_AMP_IN_SEL_SE_P, + DA7219_MIC_AMP_IN_SEL_SE_N, +}; + +struct da7219_aad_pdata; + +enum da7219_dai_clks { + DA7219_DAI_WCLK_IDX = 0, + DA7219_DAI_BCLK_IDX, + DA7219_DAI_NUM_CLKS, +}; + +struct da7219_pdata { + bool wakeup_source; + + const char *dai_clk_names[DA7219_DAI_NUM_CLKS]; + + /* Mic */ + enum da7219_micbias_voltage micbias_lvl; + enum da7219_mic_amp_in_sel mic_amp_in_sel; + + /* AAD */ + struct da7219_aad_pdata *aad_pdata; +}; + +#endif /* __DA7219_PDATA_H */ diff --git a/include/sound/da9055.h b/include/sound/da9055.h new file mode 100644 index 000000000..5c9a3c23e --- /dev/null +++ b/include/sound/da9055.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * DA9055 ALSA Soc codec driver + * + * Copyright (c) 2012 Dialog Semiconductor + * + * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C + * Written by David Chen and + * Ashish Chavan + */ + +#ifndef __SOUND_DA9055_H__ +#define __SOUND_DA9055_H__ + +enum da9055_micbias_voltage { + DA9055_MICBIAS_1_6V = 0, + DA9055_MICBIAS_1_8V = 1, + DA9055_MICBIAS_2_1V = 2, + DA9055_MICBIAS_2_2V = 3, +}; + +struct da9055_platform_data { + /* Selects which of the two MicBias pins acts as the bias source */ + bool micbias_source; + /* Selects the micbias voltage */ + enum da9055_micbias_voltage micbias; +}; + +#endif diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h new file mode 100644 index 000000000..f6803205a --- /dev/null +++ b/include/sound/designware_i2s.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) + */ + +#ifndef __SOUND_DESIGNWARE_I2S_H +#define __SOUND_DESIGNWARE_I2S_H + +#include +#include + +/* + * struct i2s_clk_config_data - represent i2s clk configuration data + * @chan_nr: number of channel + * @data_width: number of bits per sample (8/16/24/32 bit) + * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz) + */ +struct i2s_clk_config_data { + int chan_nr; + u32 data_width; + u32 sample_rate; +}; + +struct dw_i2s_dev; + +struct i2s_platform_data { + #define DWC_I2S_PLAY (1 << 0) + #define DWC_I2S_RECORD (1 << 1) + #define DW_I2S_SLAVE (1 << 2) + #define DW_I2S_MASTER (1 << 3) + unsigned int cap; + int channel; + u32 snd_fmts; + u32 snd_rates; + + #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) + #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) + #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) + unsigned int quirks; + unsigned int i2s_reg_comp1; + unsigned int i2s_reg_comp2; + + void *play_dma_data; + void *capture_dma_data; + bool (*filter)(struct dma_chan *chan, void *slave); + int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); + int (*i2s_pd_init)(struct dw_i2s_dev *dev); +}; + +struct i2s_dma_data { + void *data; + dma_addr_t addr; + u32 max_burst; + enum dma_slave_buswidth addr_width; + bool (*filter)(struct dma_chan *chan, void *slave); +}; + +/* I2S DMA registers */ +#define I2S_RXDMA 0x01C0 +#define I2S_TXDMA 0x01C8 + +#define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */ +#define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */ +#define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */ +#define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */ + +#endif /* __SOUND_DESIGNWARE_I2S_H */ diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h new file mode 100644 index 000000000..81422219e --- /dev/null +++ b/include/sound/dmaengine_pcm.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2012, Analog Devices Inc. + * Author: Lars-Peter Clausen + */ + +#ifndef __SOUND_DMAENGINE_PCM_H__ +#define __SOUND_DMAENGINE_PCM_H__ + +#include +#include +#include + +/** + * snd_pcm_substream_to_dma_direction - Get dma_transfer_direction for a PCM + * substream + * @substream: PCM substream + * + * Return: DMA transfer direction + */ +static inline enum dma_transfer_direction +snd_pcm_substream_to_dma_direction(const struct snd_pcm_substream *substream) +{ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + return DMA_MEM_TO_DEV; + else + return DMA_DEV_TO_MEM; +} + +int snd_hwparams_to_dma_slave_config(const struct snd_pcm_substream *substream, + const struct snd_pcm_hw_params *params, struct dma_slave_config *slave_config); +int snd_dmaengine_pcm_trigger(struct snd_pcm_substream *substream, int cmd); +snd_pcm_uframes_t snd_dmaengine_pcm_pointer(struct snd_pcm_substream *substream); +snd_pcm_uframes_t snd_dmaengine_pcm_pointer_no_residue(struct snd_pcm_substream *substream); + +int snd_dmaengine_pcm_open(struct snd_pcm_substream *substream, + struct dma_chan *chan); +int snd_dmaengine_pcm_close(struct snd_pcm_substream *substream); +int snd_dmaengine_pcm_sync_stop(struct snd_pcm_substream *substream); + +int snd_dmaengine_pcm_close_release_chan(struct snd_pcm_substream *substream); + +struct dma_chan *snd_dmaengine_pcm_request_channel(dma_filter_fn filter_fn, + void *filter_data); +struct dma_chan *snd_dmaengine_pcm_get_chan(struct snd_pcm_substream *substream); + +/* + * The DAI supports packed transfers, eg 2 16-bit samples in a 32-bit word. + * If this flag is set the dmaengine driver won't put any restriction on + * the supported sample formats and set the DMA transfer size to undefined. + * The DAI driver is responsible to disable any unsupported formats in it's + * configuration and catch corner cases that are not already handled in + * the ALSA core. + */ +#define SND_DMAENGINE_PCM_DAI_FLAG_PACK BIT(0) + +/** + * struct snd_dmaengine_dai_dma_data - DAI DMA configuration data + * @addr: Address of the DAI data source or destination register. + * @addr_width: Width of the DAI data source or destination register. + * @maxburst: Maximum number of words(note: words, as in units of the + * src_addr_width member, not bytes) that can be send to or received from the + * DAI in one burst. + * @filter_data: Custom DMA channel filter data, this will usually be used when + * requesting the DMA channel. + * @chan_name: Custom channel name to use when requesting DMA channel. + * @fifo_size: FIFO size of the DAI controller in bytes + * @flags: PCM_DAI flags, only SND_DMAENGINE_PCM_DAI_FLAG_PACK for now + * @peripheral_config: peripheral configuration for programming peripheral + * for dmaengine transfer + * @peripheral_size: peripheral configuration buffer size + * @port_window_size: The length of the register area in words the data need + * to be accessed on the device side. It is only used for devices which is using + * an area instead of a single register to send/receive the data. Typically the + * DMA loops in this area in order to transfer the data. + */ +struct snd_dmaengine_dai_dma_data { + dma_addr_t addr; + enum dma_slave_buswidth addr_width; + u32 maxburst; + void *filter_data; + const char *chan_name; + unsigned int fifo_size; + unsigned int flags; + void *peripheral_config; + size_t peripheral_size; + u32 port_window_size; +}; + +void snd_dmaengine_pcm_set_config_from_dai_data( + const struct snd_pcm_substream *substream, + const struct snd_dmaengine_dai_dma_data *dma_data, + struct dma_slave_config *config); + +int snd_dmaengine_pcm_refine_runtime_hwparams( + struct snd_pcm_substream *substream, + struct snd_dmaengine_dai_dma_data *dma_data, + struct snd_pcm_hardware *hw, + struct dma_chan *chan); + +/* + * Try to request the DMA channel using compat_request_channel or + * compat_filter_fn if it couldn't be requested through devicetree. + */ +#define SND_DMAENGINE_PCM_FLAG_COMPAT BIT(0) +/* + * Don't try to request the DMA channels through devicetree. This flag only + * makes sense if SND_DMAENGINE_PCM_FLAG_COMPAT is set as well. + */ +#define SND_DMAENGINE_PCM_FLAG_NO_DT BIT(1) +/* + * The PCM is half duplex and the DMA channel is shared between capture and + * playback. + */ +#define SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX BIT(3) + +/** + * struct snd_dmaengine_pcm_config - Configuration data for dmaengine based PCM + * @prepare_slave_config: Callback used to fill in the DMA slave_config for a + * PCM substream. Will be called from the PCM drivers hwparams callback. + * @compat_request_channel: Callback to request a DMA channel for platforms + * which do not use devicetree. + * @process: Callback used to apply processing on samples transferred from/to + * user space. + * @name: Component name. If null, dev_name will be used. + * @compat_filter_fn: Will be used as the filter function when requesting a + * channel for platforms which do not use devicetree. The filter parameter + * will be the DAI's DMA data. + * @dma_dev: If set, request DMA channel on this device rather than the DAI + * device. + * @chan_names: If set, these custom DMA channel names will be requested at + * registration time. + * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM. + * @prealloc_buffer_size: Size of the preallocated audio buffer. + * + * Note: If both compat_request_channel and compat_filter_fn are set + * compat_request_channel will be used to request the channel and + * compat_filter_fn will be ignored. Otherwise the channel will be requested + * using dma_request_channel with compat_filter_fn as the filter function. + */ +struct snd_dmaengine_pcm_config { + int (*prepare_slave_config)(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct dma_slave_config *slave_config); + struct dma_chan *(*compat_request_channel)( + struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_substream *substream); + int (*process)(struct snd_pcm_substream *substream, + int channel, unsigned long hwoff, + unsigned long bytes); + const char *name; + dma_filter_fn compat_filter_fn; + struct device *dma_dev; + const char *chan_names[SNDRV_PCM_STREAM_LAST + 1]; + + const struct snd_pcm_hardware *pcm_hardware; + unsigned int prealloc_buffer_size; +}; + +int snd_dmaengine_pcm_register(struct device *dev, + const struct snd_dmaengine_pcm_config *config, + unsigned int flags); +void snd_dmaengine_pcm_unregister(struct device *dev); + +int devm_snd_dmaengine_pcm_register(struct device *dev, + const struct snd_dmaengine_pcm_config *config, + unsigned int flags); + +int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct dma_slave_config *slave_config); + +#define SND_DMAENGINE_PCM_DRV_NAME "snd_dmaengine_pcm" + +struct dmaengine_pcm { + struct dma_chan *chan[SNDRV_PCM_STREAM_LAST + 1]; + const struct snd_dmaengine_pcm_config *config; + unsigned int flags; +}; +#endif diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h new file mode 100644 index 000000000..4f94565c9 --- /dev/null +++ b/include/sound/emu10k1.h @@ -0,0 +1,1921 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) by Jaroslav Kysela , + * Creative Labs, Inc. + * Definitions for EMU10K1 (SB Live!) chips + */ +#ifndef __SOUND_EMU10K1_H +#define __SOUND_EMU10K1_H + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* ------------------- DEFINES -------------------- */ + +#define EMUPAGESIZE 4096 +#define MAXPAGES0 4096 /* 32 bit mode */ +#define MAXPAGES1 8192 /* 31 bit mode */ +#define NUM_G 64 /* use all channels */ +#define NUM_EFX_PLAYBACK 16 + +/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ +#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */ +#define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */ + +#define TMEMSIZE 256*1024 + +#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) + +// This is used to define hardware bit-fields (sub-registers) by combining +// the bit shift and count with the actual register address. The passed +// mask must represent a single run of adjacent bits. +// The non-concatenating (_NC) variant should be used directly only for +// sub-registers that do not follow the _ naming pattern. +#define SUB_REG_NC(reg, field, mask) \ + enum { \ + field ## _MASK = mask, \ + field = reg | \ + (__builtin_ctz(mask) << 16) | \ + (__builtin_popcount(mask) << 24), \ + }; +#define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask) + +// Macros for manipulating values of bit-fields declared using the above macros. +// Best used with constant register addresses, as otherwise quite some code is +// generated. The actual register read/write functions handle combined addresses +// automatically, so use of these macros conveys no advantage when accessing a +// single sub-register at a time. +#define REG_SHIFT(r) (((r) >> 16) & 0x1f) +#define REG_SIZE(r) (((r) >> 24) & 0x1f) +#define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U) +#define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r)) +#define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r)) +#define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r)) + +// List terminator for snd_emu10k1_ptr_write_multiple() +#define REGLIST_END ~0 + +// Audigy specify registers are prefixed with 'A_' + +/************************************************************************************************/ +/* PCI function 0 registers, address = + PCIBASE0 */ +/************************************************************************************************/ + +#define PTR 0x00 /* Indexed register set pointer register */ + /* NOTE: The CHANNELNUM and ADDRESS words can */ + /* be modified independently of each other. */ +#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */ + /* channel number of the register to be */ + /* accessed. For non per-channel registers the */ + /* value should be set to zero. */ +#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */ +#define A_PTR_ADDRESS_MASK 0x0fff0000 + +#define DATA 0x04 /* Indexed register set data register */ + +#define IPR 0x08 /* Global interrupt pending register */ + /* Clear pending interrupts by writing a 1 to */ + /* the relevant bits and zero to the other bits */ +#define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes + to interrupt */ +#define IPR_WATERMARK_REACHED 0x40000000 +#define IPR_A_GPIO 0x20000000 /* GPIO input pin change */ + +/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ +#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */ +#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */ + +#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ +#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ + +#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ +#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ +#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */ +#define IPR_PCIERROR 0x00200000 /* PCI bus error */ +#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */ +#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */ +#define IPR_MUTE 0x00040000 /* Mute button pressed */ +#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */ +#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */ +#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */ +#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */ +#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */ +#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */ +#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */ +#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */ +#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */ +#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ +#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ +#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ + /* The interrupt is triggered shortly after */ + /* CCR_READADDRESS has crossed the boundary; */ + /* due to the cache, this runs ahead of the */ + /* actual playback position. */ +#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ + /* highest set channel in CLIPL, CLIPH, HLIPL, */ + /* or HLIPH. When IPR is written with CL set, */ + /* the bit in H/CLIPL or H/CLIPH corresponding */ + /* to the CN value written will be cleared. */ + +#define INTE 0x0c /* Interrupt enable register */ +#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ +#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */ +#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */ +#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */ +#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */ +#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */ +#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */ +#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */ +#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */ +#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */ +#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */ +#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */ +#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */ +#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */ +#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */ +#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */ +#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */ +#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */ + +#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */ + /* NOTE: There is no reason to use this under */ + /* Linux, and it will cause odd hardware */ + /* behavior and possibly random segfaults and */ + /* lockups if enabled. */ + +#define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */ + +/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ +#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ +#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ + +#define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000 +#define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000 + +#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ + /* NOTE: This bit must always be enabled */ +#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */ +#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */ +#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */ +#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */ +#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */ +#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */ +#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */ +#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */ +#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */ +#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */ +#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */ +#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */ +#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ + +#define WC 0x10 /* Wall Clock register */ +SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */ +SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */ + /* NOTE: Each channel takes 1/64th of a sample */ + /* period to be serviced. */ + +#define HCFG 0x14 /* Hardware config register */ + /* NOTE: There is no reason to use the legacy */ + /* SoundBlaster emulation stuff described below */ + /* under Linux, and all kinds of weird hardware */ + /* behavior can result if you try. Don't. */ +#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */ +#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */ +#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */ +#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */ +#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */ +#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */ +#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */ +#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */ +#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */ +#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */ +#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */ +#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */ + /* NOTE: The rest of the bits in this register */ + /* _are_ relevant under Linux. */ +#define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */ +#define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */ +#define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */ +#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */ + +/* Specific to Alice2, CA0102 */ + +#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */ +#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */ +#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */ + /* will automatically mute their output when */ + /* they are not rate-locked to the external */ + /* async audio source */ +#define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */ + /* will automatically mute their output when */ + /* the SPDIF V-bit indicates invalid audio */ +#define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */ +#define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */ +/* 0x00000800 not used on Alice2 */ +#define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */ + /* phase track the previous input. */ + /* I2S0 can phase track the last S/PDIF input */ +#define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */ + /* conversion for the corresponding */ + /* I2S format input */ +/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */ + +/* Older chips */ + +#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ +#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ +#define HCFG_GPINPUT0 0x00004000 /* External pin112 */ +#define HCFG_GPINPUT1 0x00002000 /* External pin110 */ +#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */ +#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */ +#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */ +#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */ +#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */ +#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */ + /* 1 = Force all 3 async digital inputs to use */ + /* the same async sample rate tracker (ZVIDEO) */ +#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */ +#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */ +#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */ +#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */ +#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */ + /* will automatically mute their output when */ + /* they are not rate-locked to the external */ + /* async audio source */ +#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ + /* NOTE: This should generally never be used. */ +SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */ + /* NOTE: This should generally never be used. */ +#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ + /* NOTE: This is a 'cheap' way to implement a */ + /* master mute function on the mute button, and */ + /* in general should not be used unless a more */ + /* sophisticated master mute function has not */ + /* been written. */ +#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ + /* Should be set to 1 when the EMU10K1 is */ + /* completely initialized. */ + +// On Audigy, the MPU port moved to the 0x70-0x74 ptr registers + +#define MUDATA 0x18 /* MPU401 data register (8 bits) */ + +#define MUCMD 0x19 /* MPU401 command register (8 bits) */ +#define MUCMD_RESET 0xff /* RESET command */ +#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */ + /* NOTE: All other commands are ignored */ + +#define MUSTAT MUCMD /* MPU401 status register (8 bits) */ +#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ +#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ + +#define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */ +#define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */ +#define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */ +#define A_GPOUTPUT_MASK 0x00ff + +// The GPIO port is used for I/O config on Sound Blasters; +// card-specific info can be found in the emu_chip_details table. +// On E-MU cards the port is used as the interface to the FPGA. + +// Audigy output/GPIO stuff taken from the kX drivers +#define A_IOCFG A_GPIO +#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ +#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ +#define A_IOCFG_ENABLE_DIGITAL 0x0004 +#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080 +#define A_IOCFG_UNKNOWN_20 0x0020 +#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */ +#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */ +#define A_IOCFG_GPOUT2 0x0001 /* IR */ +#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ + /* + digital for generic 10k2 */ +#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ +#define A_IOCFG_FRONT_JACK 0x4000 +#define A_IOCFG_REAR_JACK 0x8000 +#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ + +#define TIMER 0x1a /* Timer terminal count register */ + /* NOTE: After the rate is changed, a maximum */ + /* of 1024 sample periods should be allowed */ + /* before the new rate is guaranteed accurate. */ +#define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */ + /* 0 == 1024 periods, [1..4] are not useful */ + +#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ + +#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ +#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */ +#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */ + +/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */ +#define PTR2 0x20 /* Indexed register set pointer register */ +#define DATA2 0x24 /* Indexed register set data register */ +#define IPR2 0x28 /* P16V interrupt pending register */ +#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ +#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ +#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ +#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */ + /* 0x00000100 Playback. Only in once per period. + * 0x00110000 Capture. Int on half buffer. + */ +#define INTE2 0x2c /* P16V Interrupt enable register. */ +#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ +#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ +#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */ +#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */ +#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */ +#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */ +#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */ +#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */ +#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ +#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */ +#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */ + /* 0x00000000 2-channel output. */ + /* 0x00000200 8-channel output. */ + /* 0x00000004 pauses stream/irq fail. */ + /* Rest of bits do nothing to sound output */ + /* bit 0: Enable P16V audio. + * bit 1: Lock P16V record memory cache. + * bit 2: Lock P16V playback memory cache. + * bit 3: Dummy record insert zero samples. + * bit 8: Record 8-channel in phase. + * bit 9: Playback 8-channel in phase. + * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute. + * bit 13: Playback mixer enable. + * bit 14: Route SRC48 mixer output to fx engine. + * bit 15: Enable IEEE 1394 chip. + */ +#define IPR3 0x38 /* Cdif interrupt pending register */ +#define INTE3 0x3c /* Cdif interrupt enable register. */ + +/************************************************************************************************/ +/* PCI function 1 registers, address = + PCIBASE1 */ +/************************************************************************************************/ + +#define JOYSTICK1 0x00 /* Analog joystick port register */ +#define JOYSTICK2 0x01 /* Analog joystick port register */ +#define JOYSTICK3 0x02 /* Analog joystick port register */ +#define JOYSTICK4 0x03 /* Analog joystick port register */ +#define JOYSTICK5 0x04 /* Analog joystick port register */ +#define JOYSTICK6 0x05 /* Analog joystick port register */ +#define JOYSTICK7 0x06 /* Analog joystick port register */ +#define JOYSTICK8 0x07 /* Analog joystick port register */ + +/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */ +/* When reading, use these bitfields: */ +#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */ +#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ + +/********************************************************************************************************/ +/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ +/********************************************************************************************************/ + +// No official documentation was released for EMU10K1, but some info +// about playback can be extrapolated from the EMU8K documents: +// "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers +// "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view + +// The short version: +// - The engine has 64 playback channels, also called voices. The channels +// operate independently, except when paired for stereo (see below). +// - PCM samples are fetched into the cache; see description of CD0 below. +// - Samples are consumed at the rate CPF_CURRENTPITCH. +// - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8 +// - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated +// according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero +// CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim. +// - The value is multiplied by CVCF_CURRENTVOL. +// - The value goes through a filter with cutoff CVCF_CURRENTFILTER; +// delay stages Z1 and Z2. +// - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2) +// of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*, +// multiplied by a per-send amount (*_FXSENDAMOUNT_*). +// The scaling of the send amounts is exponential-ish. +// - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*. +// - The pitch, volume, and filter cutoff can be modulated by two envelope +// engines and two low frequency oscillators. +// - To avoid abrupt changes to the parameters (which may cause audible +// distortion), the modulation engine sets the target registers, towards +// which the current registers "swerve" gradually. + +// For the odd channel in a stereo pair, these registers are meaningless: +// CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE, +// PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR +// The somewhat non-obviously still meaningful ones are: +// CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!), +// CCCA_INTERPROM, CCCA_8BITSELECT (!) +// (The envelope engine is ignored here, as stereo matters only for verbatim playback.) + +#define CPF 0x00 /* Current pitch and fraction register */ +SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */ +#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ +SUB_REG(CPF, STOP, 0x00004000) /* 1 = Current pitch forced to 0 */ + /* Can be set only while matching bit in SOLEx is 1 */ +#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ + +#define PTRX 0x01 /* Pitch target and send A/B amounts register */ +SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */ +SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */ +SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */ + +// Note: the volumes are raw multpliers, so real 100% is impossible. +#define CVCF 0x02 /* Current volume and filter cutoff register */ +SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */ +SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */ + +#define VTFT 0x03 /* Volume target and filter cutoff target register */ +SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */ +SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */ + +#define Z1 0x05 /* Filter delay memory 1 register */ + +#define Z2 0x04 /* Filter delay memory 2 register */ + +#define PSST 0x06 /* Send C amount and loop start address register */ +SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */ +SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */ + +#define DSL 0x07 /* Send D amount and loop end address register */ +SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */ +SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */ + +#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ +SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */ +#define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */ + /* 1 == full band, 7 == lowpass */ + /* ROM 0 is used when pitch shifting downward or less */ + /* then 3 semitones upward. Increasingly higher ROM */ + /* numbers are used, typically in steps of 3 semitones, */ + /* as upward pitch shifting is performed. */ +#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */ +#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */ +#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */ +#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */ +#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */ +#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */ +#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ +#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ +#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ + /* 8-bit samples are unsigned, 16-bit ones signed */ +SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */ + +#define CCR 0x09 /* Cache control register */ +SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */ +#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ +#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ + /* Auto-set from CPF_STEREO_MASK */ +#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ + /* Auto-set from CCCA_8BITSELECT */ +SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */ +SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */ + /* NOTE: This is valid only if CACHELOOPFLAG is set */ +#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ +SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ + +#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ + /* NOTE: This register is normally not used */ +SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */ + +#define FXRT 0x0b /* Effects send routing register */ + /* NOTE: It is illegal to assign the same routing to */ + /* two effects sends. */ +#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */ +#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */ +#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ +#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ + +#define MAPA 0x0c /* Cache map A */ +#define MAPB 0x0d /* Cache map B */ + +#define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */ +#define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */ + +#define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ +#define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ + +/* 0x0e, 0x0f: Internal state, at least on Audigy */ + +#define ENVVOL 0x10 /* Volume envelope register */ +#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define ATKHLDV 0x11 /* Volume envelope hold and attack register */ +#define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ +#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ +#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ + /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ + +#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ +#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ +#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ +#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */ + /* this channel and from writing to pitch, filter and */ + /* volume targets. */ +#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ + /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ + +#define LFOVAL1 0x13 /* Modulation LFO value */ +#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define ENVVAL 0x14 /* Modulation envelope register */ +#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ +#define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */ +#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ +#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ + /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ + +#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ +#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */ +#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ +#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ + /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ + +#define LFOVAL2 0x17 /* Vibrato LFO register */ +#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define IP 0x18 /* Initial pitch register */ +#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */ + /* 4 bits of octave, 12 bits of fractional octave */ +#define IP_UNITY 0x0000e000 /* Unity pitch shift */ + +#define IFATN 0x19 /* Initial filter cutoff and attenuation register */ +SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */ + /* 6 most significant bits are semitones */ + /* 2 least significant bits are fractions */ +SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */ + +#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ +SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */ + /* Signed 2's complement, +/- one octave peak extremes */ +SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */ + /* Signed 2's complement, +/- six octaves peak extremes */ + + +#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ +#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ + /* Signed 2's complement, +/- one octave extremes */ +#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ + /* Signed 2's complement, +/- three octave extremes */ + +#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ +#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ + /* Signed 2's complement, with +/- 12dB extremes */ +#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ + /* ??Hz steps, maximum of ?? Hz. */ + +#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ +#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ + /* Signed 2's complement, +/- one octave extremes */ +#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */ + /* 0.039Hz steps, maximum of 9.85 Hz. */ + +#define TEMPENV 0x1e /* Tempory envelope register */ +#define TEMPENV_MASK 0x0000ffff /* 16-bit value */ + /* NOTE: All channels contain internal variables; do */ + /* not write to these locations. */ + +/* 0x1f: not used */ + +// 32 cache registers (== 128 bytes) per channel follow. +// In stereo mode, the two channels' caches are concatenated into one, +// and hold the interleaved frames. +// The cache holds 64 frames, so the upper half is not used in 8-bit mode. +// All registers mentioned below count in frames. Shortcuts: +// CA = CCCA_CURRADDR, CRA = CCR_READADDRESS, +// CLA = CCR_CACHELOOPADDRHI:CLP_CACHELOOPADDR, +// CIS = CCR_CACHEINVALIDSIZE, LIS = CCR_LOOPINVALSIZE, +// CLF = CCR_CACHELOOPFLAG, LF = CCR_LOOPFLAG +// The cache is a ring buffer; CRA operates modulo 64. +// The cache is filled from (CA - CIS) into (CRA - CIS). +// The engine has a fetch threshold of 32 bytes, so it tries to keep +// CIS below 8 (16-bit stereo), 16 (16-bit mono, 8-bit stereo), or +// 32 (8-bit mono). The actual transfers are pretty unpredictable, +// especially if several voices are running. +// Frames are consumed at CRA, which is incremented afterwards, +// along with CA and CIS. This implies that the actual playback +// position always lags CA by exactly 64 frames. +// When CA reaches DSL_LOOPENDADDR, LF is set for one frame's time. +// LF's rising edge causes the current values of CA and CIS to be +// copied into CLA and LIS, resp., and CLF to be set. +// If CLF is set, the first LIS of the CIS frames are instead +// filled from (CLA - LIS), and CLF is subsequently reset. +#define CD0 0x20 /* Cache data registers 0 .. 0x1f */ + +#define PTB 0x40 /* Page table base register */ +#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ + +#define TCB 0x41 /* Tank cache base register */ +#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */ + +#define ADCCR 0x42 /* ADC sample rate/stereo control register */ +#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */ +#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */ + /* NOTE: To guarantee phase coherency, both channels */ + /* must be disabled prior to enabling both channels. */ +#define A_ADCCR_RCHANENABLE 0x00000020 +#define A_ADCCR_LCHANENABLE 0x00000010 + +#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */ +#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */ +#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */ +#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */ +#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */ +#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */ +#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */ +#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */ +#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */ +#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */ +#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */ +#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */ +#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */ + +#define FXWC 0x43 /* FX output write channels register */ + /* When set, each bit enables the writing of the */ + /* corresponding FX output channel (internal registers */ + /* 0x20-0x3f) to host memory. This mode of recording */ + /* is 16bit, 48KHz only. All 32 channels can be enabled */ + /* simultaneously. */ + +#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ + +#define TCBS 0x44 /* Tank cache buffer size register */ +#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ +#define TCBS_BUFFSIZE_16K 0x00000000 +#define TCBS_BUFFSIZE_32K 0x00000001 +#define TCBS_BUFFSIZE_64K 0x00000002 +#define TCBS_BUFFSIZE_128K 0x00000003 +#define TCBS_BUFFSIZE_256K 0x00000004 +#define TCBS_BUFFSIZE_512K 0x00000005 +#define TCBS_BUFFSIZE_1024K 0x00000006 +#define TCBS_BUFFSIZE_2048K 0x00000007 + +#define MICBA 0x45 /* AC97 microphone buffer address register */ +#define MICBA_MASK 0xfffff000 /* 20 bit base address */ + +#define ADCBA 0x46 /* ADC buffer address register */ +#define ADCBA_MASK 0xfffff000 /* 20 bit base address */ + +#define FXBA 0x47 /* FX Buffer Address */ +#define FXBA_MASK 0xfffff000 /* 20 bit base address */ + +#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ + +#define MICBS 0x49 /* Microphone buffer size register */ + +#define ADCBS 0x4a /* ADC buffer size register */ + +#define FXBS 0x4b /* FX buffer size register */ + +/* The following mask values define the size of the ADC, MIC and FX buffers in bytes */ +#define ADCBS_BUFSIZE_NONE 0x00000000 +#define ADCBS_BUFSIZE_384 0x00000001 +#define ADCBS_BUFSIZE_448 0x00000002 +#define ADCBS_BUFSIZE_512 0x00000003 +#define ADCBS_BUFSIZE_640 0x00000004 +#define ADCBS_BUFSIZE_768 0x00000005 +#define ADCBS_BUFSIZE_896 0x00000006 +#define ADCBS_BUFSIZE_1024 0x00000007 +#define ADCBS_BUFSIZE_1280 0x00000008 +#define ADCBS_BUFSIZE_1536 0x00000009 +#define ADCBS_BUFSIZE_1792 0x0000000a +#define ADCBS_BUFSIZE_2048 0x0000000b +#define ADCBS_BUFSIZE_2560 0x0000000c +#define ADCBS_BUFSIZE_3072 0x0000000d +#define ADCBS_BUFSIZE_3584 0x0000000e +#define ADCBS_BUFSIZE_4096 0x0000000f +#define ADCBS_BUFSIZE_5120 0x00000010 +#define ADCBS_BUFSIZE_6144 0x00000011 +#define ADCBS_BUFSIZE_7168 0x00000012 +#define ADCBS_BUFSIZE_8192 0x00000013 +#define ADCBS_BUFSIZE_10240 0x00000014 +#define ADCBS_BUFSIZE_12288 0x00000015 +#define ADCBS_BUFSIZE_14366 0x00000016 +#define ADCBS_BUFSIZE_16384 0x00000017 +#define ADCBS_BUFSIZE_20480 0x00000018 +#define ADCBS_BUFSIZE_24576 0x00000019 +#define ADCBS_BUFSIZE_28672 0x0000001a +#define ADCBS_BUFSIZE_32768 0x0000001b +#define ADCBS_BUFSIZE_40960 0x0000001c +#define ADCBS_BUFSIZE_49152 0x0000001d +#define ADCBS_BUFSIZE_57344 0x0000001e +#define ADCBS_BUFSIZE_65536 0x0000001f + +// On Audigy, the FX send amounts are not applied instantly, but determine +// targets towards which the following registers swerve gradually. +#define A_CSBA 0x4c /* FX send B & A current amounts */ +#define A_CSDC 0x4d /* FX send D & C current amounts */ +#define A_CSFE 0x4e /* FX send F & E current amounts */ +#define A_CSHG 0x4f /* FX send H & G current amounts */ + +// NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1) +#define CDCS 0x50 /* CD-ROM digital channel status register */ + +#define GPSCS 0x51 /* General Purpose SPDIF channel status register */ + +// Corresponding EMU10K1_DBG_* constants are in the public header +#define DBG 0x52 + +#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */ + +#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ + +// Corresponding A_DBG_* constants are in the public header +#define A_DBG 0x53 + +// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1) +#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ + +#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ + +#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */ + +#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ +#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ +#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ +#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ +#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ +#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ +#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ +#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ +#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ +#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ +#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ +#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ +#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ +#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ +#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ +#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ +#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ +#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ +#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ +#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ +#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ +#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ +#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ + +/* 0x57: Not used */ + +/* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */ +#define CLIEL 0x58 /* Channel loop interrupt enable low register */ +#define CLIEH 0x59 /* Channel loop interrupt enable high register */ + +#define CLIPL 0x5a /* Channel loop interrupt pending low register */ +#define CLIPH 0x5b /* Channel loop interrupt pending high register */ + +// These cause CPF_STOP_MASK to be set shortly after CCCA_CURRADDR passes DSL_LOOPENDADDR. +// Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does. +// The registers are NOT synchronized; the next serviced channel picks up immediately. +#define SOLEL 0x5c /* Stop on loop enable low register */ +#define SOLEH 0x5d /* Stop on loop enable high register */ + +#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ +#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ +#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ +/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ +#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ + +#define AC97SLOT 0x5f /* additional AC97 slots enable bits */ +#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ +#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ +#define AC97SLOT_CNTR 0x10 /* Center enable */ +#define AC97SLOT_LFE 0x20 /* LFE enable */ + +#define A_PCB 0x5f /* PCB Revision */ + +// NOTE: 0x60,61,62: 64-bit +#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ + +#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */ + +#define ZVSRCS 0x62 /* ZVideo sample rate converter status */ + /* NOTE: This one has no SPDIFLOCKED field */ + /* Assumes sample lock */ + +/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ +#define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */ +#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ +#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ +#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */ + +/* Note that these values can vary +/- by a small amount */ +#define SRCS_SPDIFRATE_44 0x0003acd9 +#define SRCS_SPDIFRATE_48 0x00040000 +#define SRCS_SPDIFRATE_96 0x00080000 + +#define MICIDX 0x63 /* Microphone recording buffer index register */ +SUB_REG(MICIDX, IDX, 0x0000ffff) + +#define ADCIDX 0x64 /* ADC recording buffer index register */ +SUB_REG(ADCIDX, IDX, 0x0000ffff) + +#define A_ADCIDX 0x63 +SUB_REG(A_ADCIDX, IDX, 0x0000ffff) + +#define A_MICIDX 0x64 +SUB_REG(A_MICIDX, IDX, 0x0000ffff) + +#define FXIDX 0x65 /* FX recording buffer index register */ +SUB_REG(FXIDX, IDX, 0x0000ffff) + +/* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */ +#define HLIEL 0x66 /* Channel half loop interrupt enable low register */ +#define HLIEH 0x67 /* Channel half loop interrupt enable high register */ + +#define HLIPL 0x68 /* Channel half loop interrupt pending low register */ +#define HLIPH 0x69 /* Channel half loop interrupt pending high register */ + +#define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */ +#define A_SPRA 0x6b /* S/PDIF Host Record Address */ +#define A_SPRC 0x6c /* S/PDIF Host Record Control */ + +#define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */ + +#define A_TTB 0x6e /* Tank Table Base */ +#define A_TDOF 0x6f /* Tank Delay Offset */ + +/* This is the MPU port on the card (via the game port) */ +#define A_MUDATA1 0x70 +#define A_MUCMD1 0x71 +#define A_MUSTAT1 A_MUCMD1 + +/* This is the MPU port on the Audigy Drive */ +#define A_MUDATA2 0x72 +#define A_MUCMD2 0x73 +#define A_MUSTAT2 A_MUCMD2 + +/* The next two are the Audigy equivalent of FXWC */ +/* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */ +/* Each bit selects a channel for recording */ +#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ +#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ + +#define A_EHC 0x76 /* Extended Hardware Control */ + +#define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */ +#define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ +#define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */ +#define A_SPDIF_192000 0x00000020 +#define A_SPDIF_96000 0x00000040 +#define A_SPDIF_44100 0x00000080 +#define A_SPDIF_MUTED 0x000000c0 + +SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */ + /* unclear if this sets the ADC rate as well. */ +#define A_I2S_CAPTURE_48000 0x0 +#define A_I2S_CAPTURE_192000 0x1 +#define A_I2S_CAPTURE_96000 0x2 +#define A_I2S_CAPTURE_44100 0x4 + +#define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ +#define A_EHC_SRC48_BYPASS 0x00000000 +#define A_EHC_SRC48_192 0x00002000 +#define A_EHC_SRC48_96 0x00004000 +#define A_EHC_SRC48_44 0x00008000 +#define A_EHC_SRC48_MUTED 0x0000c000 + +#define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */ +#define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */ +#define A_EHC_P17V_SEL1_MASK 0x000c0000 +#define A_EHC_P17V_SEL2_MASK 0x00300000 +#define A_EHC_P17V_SEL3_MASK 0x00c00000 + +#define A_EHC_ASYNC_BYPASS 0x80000000 + +#define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */ +#define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */ +#define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */ +/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ + +#define A_SRT_ESTSAMPLERATE 0x001fffff +#define A_SRT_RATELOCKED 0x01000000 + +#define A_TTDA 0x7a /* Tank Table DMA Address */ +#define A_TTDD 0x7b /* Tank Table DMA Data */ + +// In A_FXRT1 & A_FXRT2, the 0x80 bit of each byte completely disables the +// filter (CVCF_CURRENTFILTER) for the corresponding channel. There is no +// effect on the volume (CVCF_CURRENTVOLUME) or the interpolator's filter +// (CCCA_INTERPROM_MASK). + +#define A_FXRT2 0x7c +#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ +#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */ +#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */ +#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */ + +#define A_SENDAMOUNTS 0x7d +#define A_FXSENDAMOUNT_E_MASK 0xFF000000 +#define A_FXSENDAMOUNT_F_MASK 0x00FF0000 +#define A_FXSENDAMOUNT_G_MASK 0x0000FF00 +#define A_FXSENDAMOUNT_H_MASK 0x000000FF + +/* The send amounts for this one are the same as used with the emu10k1 */ +#define A_FXRT1 0x7e +#define A_FXRT_CHANNELA 0x0000003f +#define A_FXRT_CHANNELB 0x00003f00 +#define A_FXRT_CHANNELC 0x003f0000 +#define A_FXRT_CHANNELD 0x3f000000 + +/* 0x7f: Not used */ + +/* The public header defines the GPR and TRAM base addresses that + * are valid for _both_ CPU and DSP addressing. */ + +/* Each DSP microcode instruction is mapped into 2 doublewords */ +/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ +#define MICROCODEBASE 0x400 /* Microcode data base address */ +#define A_MICROCODEBASE 0x600 + + +/************************************************************************************************/ +/* E-MU Digital Audio System overview */ +/************************************************************************************************/ + +// - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2); +// the PCIe variants simply put the Audigy chip behind a PCI bridge. +// - All physical PCM I/O is routed through an additional FPGA; the regular +// EXTIN/EXTOUT ports are unconnected. +// - The FPGA has a signal routing matrix, to connect each destination (output +// socket or capture channel) to a source (input socket or playback channel). +// - The FPGA is controlled via Audigy's GPIO port, while sample data is +// transmitted via proprietary EMU32 serial links. On first-generation +// E-MU 1010 cards, Audigy's I2S inputs are also used for sample data. +// - The Audio/Micro Dock is attached to Hana via EDI, a "network" link. +// - The Audigy chip operates in slave mode; the clock is supplied by the FPGA. +// Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples), +// while the later cards use a single crystal and a PLL chip. +// - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz +// sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels +// are bundled. +// - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total +// number of usable inputs/outputs is limited, esp. with ADAT in use. +// - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due +// to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels +// can overlap with the Dock's ADC/DAC's high channels. +// - The code names are mentioned below and in the emu_chip_details table. + +/************************************************************************************************/ +/* EMU1010 FPGA registers */ +/************************************************************************************************/ + +#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */ +#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */ + +#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */ +#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */ + +#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */ +#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */ + +#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */ + /* Must be written after power on to reset DLL */ + /* One is unable to detect the Audio dock without this */ +#define EMU_HANA_WCLOCK_SRC_MASK 0x07 +#define EMU_HANA_WCLOCK_INT_48K 0x00 +#define EMU_HANA_WCLOCK_INT_44_1K 0x01 +#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 +#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 +#define EMU_HANA_WCLOCK_SYNC_BNC 0x04 +#define EMU_HANA_WCLOCK_2ND_HANA 0x05 +#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 +#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */ +#define EMU_HANA_WCLOCK_MULT_MASK 0x18 +#define EMU_HANA_WCLOCK_1X 0x00 +#define EMU_HANA_WCLOCK_2X 0x08 +#define EMU_HANA_WCLOCK_4X 0x10 +#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 + +// If the selected external clock source is/becomes invalid or incompatible +// with the clock multiplier, the clock source is reset to this value, and +// a WCLK_CHANGED interrupt is raised. +#define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */ +#define EMU_HANA_DEFCLOCK_48K 0x00 +#define EMU_HANA_DEFCLOCK_44_1K 0x01 + +#define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */ +#define EMU_MUTE 0x00 +#define EMU_UNMUTE 0x01 + +#define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */ +#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */ +#define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */ + +#define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */ +#define EMU_HANA_IRQ_WCLK_CHANGED 0x01 +#define EMU_HANA_IRQ_ADAT 0x02 +#define EMU_HANA_IRQ_DOCK 0x04 +#define EMU_HANA_IRQ_DOCK_LOST 0x08 + +#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */ +#define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00 +#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 +#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 +#define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00 +#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 +#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 +#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10 + +#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */ +#define EMU_HANA_OPTICAL_IN_SPDIF 0x00 +#define EMU_HANA_OPTICAL_IN_ADAT 0x01 +#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00 +#define EMU_HANA_OPTICAL_OUT_ADAT 0x02 + +#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ +#define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */ +#define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */ +#define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */ +#define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */ +#define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */ +#define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */ + +#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */ +#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */ +#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */ +#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */ +#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */ + +#define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */ +#define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */ +#define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */ + +#define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */ +#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */ +#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */ + +#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ +#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ +#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ +#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ +#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ + +#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ +#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ +#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ +#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ +#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ +#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */ +#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */ +#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */ +#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */ + +#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ +#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ + +#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ +#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ +#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ + +/* 0x14 - 0x1f Unused R/W registers */ + +#define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */ + /* Same bits as for EMU_HANA_IRQ_ENABLE */ + /* Reading the register resets it. */ + +#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */ +#define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */ +#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ +#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */ +#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */ + +#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */ + /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */ + +#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */ +#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */ + +#define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */ +#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */ + +#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */ +#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ +#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ + +// The actual code disagrees about the bit width of the registers - +// the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1) + +#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ +#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */ + +#define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */ +#define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */ + +#define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */ +#define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */ + +#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */ +#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */ + +/* 0x30 - 0x3f Unused Read only registers */ + +// The meaning of this is not clear; kX-project just calls it "lock" in some info-only code. +#define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */ +#define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */ + +/************************************************************************************************/ +/* EMU1010 Audio Destinations */ +/************************************************************************************************/ +/* Hana, original 1010,1212m,1820[m] using Alice2 + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock + * 0x00: Dock DAC 1 Left + * 0x04: Dock DAC 1 Right + * 0x08: Dock DAC 2 Left + * 0x0c: Dock DAC 2 Right + * 0x10: Dock DAC 3 Left + * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left) + * 0x14: Dock DAC 3 Right + * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right) + * 0x18: Dock DAC 4 Left + * 0x1a: S/PDIF Left + * 0x1c: Dock DAC 4 Right + * 0x1e: S/PDIF Right + * 0x02, 0x00: Hana S/PDIF Left + * 0x02, 0x01: Hana S/PDIF Right + * 0x03, 0x00: Hamoa DAC Left + * 0x03, 0x01: Hamoa DAC Right + * 0x04, 0x00-0x07: Hana ADAT + * 0x05, 0x00: I2S0 Left to Alice2 + * 0x05, 0x01: I2S0 Right to Alice2 + * 0x06, 0x00: I2S0 Left to Alice2 + * 0x06, 0x01: I2S0 Right to Alice2 + * 0x07, 0x00: I2S0 Left to Alice2 + * 0x07, 0x01: I2S0 Right to Alice2 + * + * Hana2 never released, but used Tina + * Not needed. + * + * Hana3, rev2 1010,1212m,1616[m] using Tina + * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina + * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock + * 0x00: Dock DAC 1 Left + * 0x04: Dock DAC 1 Right + * 0x08: Dock DAC 2 Left + * 0x0c: Dock DAC 2 Right + * 0x10: Dock DAC 3 Left + * 0x12: Dock S/PDIF Left + * 0x14: Dock DAC 3 Right + * 0x16: Dock S/PDIF Right + * 0x18-0x1f: Dock ADAT 0-7 + * 0x02, 0x00: Hana3 S/PDIF Left + * 0x02, 0x01: Hana3 S/PDIF Right + * 0x03, 0x00: Hamoa DAC Left + * 0x03, 0x01: Hamoa DAC Right + * 0x04, 0x00-0x07: Hana3 ADAT 0-7 + * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina + * 0x06-0x07: Not used + * + * HanaLite, rev1 0404 using Alice2 + * HanaLiteLite, rev2 0404 using Tina + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina + * 0x01: Not used + * 0x02, 0x00: S/PDIF Left + * 0x02, 0x01: S/PDIF Right + * 0x03, 0x00: DAC Left + * 0x03, 0x01: DAC Right + * 0x04-0x07: Not used + * + * Mana, Cardbus 1616 using Tina2 + * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 + * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock + * (same as rev2 1010) + * 0x02: Not used + * 0x03, 0x00: Mana DAC Left + * 0x03, 0x01: Mana DAC Right + * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 + * 0x05-0x07: Not used + */ + +/* 32-bit destinations of signal in the Hana FPGA. Destinations are either + * physical outputs of Hana, or outputs going to Alice2/Tina for capture - + * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into + * a channel depends on the mixer control setting for each destination - see + * the register arrays in emumixer.c. + */ +#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ + /* This channel is delayed by one sample. */ +#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */ +#define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */ +#define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */ +#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */ +#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */ +#define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */ +#define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */ +#define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */ +#define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */ +#define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */ +#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */ +#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */ +#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */ +#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */ +// In S/MUX mode, the samples of one channel are adjacent. +#define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */ +#define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */ +#define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */ +#define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */ +#define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */ +#define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */ +#define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */ + +/* Additional destinations for 1616(M)/Microdock */ + +#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */ +#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */ +#define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */ + +#define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ +#define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ + +/************************************************************************************************/ +/* EMU1010 Audio Sources */ +/************************************************************************************************/ +/* Hana, original 1010,1212m,1820[m] using Alice2 + * 0x00, 0x00-0x1f: Silence + * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock + * 0x00: Dock Mic A + * 0x04: Dock Mic B + * 0x08: Dock ADC 1 Left + * 0x0c: Dock ADC 1 Right + * 0x10: Dock ADC 2 Left + * 0x14: Dock ADC 2 Right + * 0x18: Dock ADC 3 Left + * 0x1c: Dock ADC 3 Right + * 0x02, 0x00: Hamoa ADC Left + * 0x02, 0x01: Hamoa ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04, 0x00-0x07: Hana ADAT + * 0x05, 0x00: Hana S/PDIF Left + * 0x05, 0x01: Hana S/PDIF Right + * 0x06-0x07: Not used + * + * Hana2 never released, but used Tina + * Not needed. + * + * Hana3, rev2 1010,1212m,1616[m] using Tina + * 0x00, 0x00-0x1f: Silence + * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock + * 0x00: Dock Mic A + * 0x04: Dock Mic B + * 0x08: Dock ADC 1 Left + * 0x0c: Dock ADC 1 Right + * 0x10: Dock ADC 2 Left + * 0x12: Dock S/PDIF Left + * 0x14: Dock ADC 2 Right + * 0x16: Dock S/PDIF Right + * 0x18-0x1f: Dock ADAT 0-7 + * 0x02, 0x00: Hamoa ADC Left + * 0x02, 0x01: Hamoa ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output + * 0x04, 0x00-0x07: Hana3 ADAT + * 0x05, 0x00: Hana3 S/PDIF Left + * 0x05, 0x01: Hana3 S/PDIF Right + * 0x06-0x07: Not used + * + * HanaLite, rev1 0404 using Alice2 + * HanaLiteLite, rev2 0404 using Tina + * 0x00, 0x00-0x1f: Silence + * 0x01: Not used + * 0x02, 0x00: ADC Left + * 0x02, 0x01: ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output + * 0x04: Not used + * 0x05, 0x00: S/PDIF Left + * 0x05, 0x01: S/PDIF Right + * 0x06-0x07: Not used + * + * Mana, Cardbus 1616 using Tina2 + * 0x00, 0x00-0x1f: Silence + * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock + * (same as rev2 1010) + * 0x02: Not used + * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output + * 0x04-0x07: Not used + */ + +/* 32-bit sources of signal in the Hana FPGA. The sources are routed to + * destinations using a mixer control for each destination - see emumixer.c. + * Sources are either physical inputs of Hana, or inputs from Alice2/Tina - + * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B. + */ +#define EMU_SRC_SILENCE 0x0000 /* Silence */ +#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ +#define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */ +#define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */ +#define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */ +#define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */ +#define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */ +#define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */ +#define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */ +#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */ +#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */ +#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */ +#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */ +#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */ +#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */ +#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */ +#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */ +#define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */ +#define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */ +// In S/MUX mode, the samples of one channel are adjacent. +#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */ +#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */ +#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ +#define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */ +#define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */ +#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ +#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ +#define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */ +#define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */ + +/* Additional inputs for 1616(M)/Microdock */ + +#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */ + +/* 0x600 and 0x700 no used */ + + +/* ------------------- CONSTANTS -------------------- */ + +extern const char * const snd_emu10k1_fxbus[32]; +extern const char * const snd_emu10k1_sblive_ins[16]; +extern const char * const snd_emu10k1_audigy_ins[16]; +extern const char * const snd_emu10k1_sblive_outs[32]; +extern const char * const snd_emu10k1_audigy_outs[32]; +extern const s8 snd_emu10k1_sblive51_fxbus2_map[16]; + +/* ------------------- STRUCTURES -------------------- */ + +enum { + EMU10K1_UNUSED, // This must be zero + EMU10K1_EFX, + EMU10K1_EFX_IRQ, + EMU10K1_PCM, + EMU10K1_PCM_IRQ, + EMU10K1_SYNTH, + EMU10K1_NUM_TYPES +}; + +struct snd_emu10k1; + +struct snd_emu10k1_voice { + unsigned char number; + unsigned char use; + unsigned char dirty; + unsigned char last; + void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); + + struct snd_emu10k1_pcm *epcm; +}; + +enum { + PLAYBACK_EMUVOICE, + PLAYBACK_EFX, + CAPTURE_AC97ADC, + CAPTURE_AC97MIC, + CAPTURE_EFX +}; + +struct snd_emu10k1_pcm { + struct snd_emu10k1 *emu; + int type; + struct snd_pcm_substream *substream; + struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK]; + struct snd_emu10k1_voice *extra; + unsigned short running; + unsigned short first_ptr; + snd_pcm_uframes_t resume_pos; + struct snd_util_memblk *memblk; + unsigned int pitch_target; + unsigned int start_addr; + unsigned int ccca_start_addr; + unsigned int capture_ipr; /* interrupt acknowledge mask */ + unsigned int capture_inte; /* interrupt enable mask */ + unsigned int capture_ba_reg; /* buffer address register */ + unsigned int capture_bs_reg; /* buffer size register */ + unsigned int capture_idx_reg; /* buffer index register */ + unsigned int capture_cr_val; /* control value */ + unsigned int capture_cr_val2; /* control value2 (for audigy) */ + unsigned int capture_bs_val; /* buffer size value */ + unsigned int capture_bufsize; /* buffer size in bytes */ +}; + +struct snd_emu10k1_pcm_mixer { + /* mono, left, right x 8 sends (4 on emu10k1) */ + unsigned char send_routing[3][8]; + unsigned char send_volume[3][8]; + // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain + // backwards compatibility with user space. + unsigned short attn[3]; + struct snd_emu10k1_pcm *epcm; +}; + +#define snd_emu10k1_compose_send_routing(route) \ +((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16) + +#define snd_emu10k1_compose_audigy_fxrt1(route) \ +((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24) | 0x80808080) + +#define snd_emu10k1_compose_audigy_fxrt2(route) \ +((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24) | 0x80808080) + +#define snd_emu10k1_compose_audigy_sendamounts(vol) \ +(((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7]) + +struct snd_emu10k1_memblk { + struct snd_util_memblk mem; + /* private part */ + int first_page, last_page, pages, mapped_page; + unsigned int map_locked; + struct list_head mapped_link; + struct list_head mapped_order_link; +}; + +#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1))) + +#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16 + +struct snd_emu10k1_fx8010_ctl { + struct list_head list; /* list link container */ + unsigned int vcount; + unsigned int count; /* count of GPR (1..16) */ + unsigned short gpr[32]; /* GPR number(s) */ + int value[32]; + int min; /* minimum range */ + int max; /* maximum range */ + unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ + struct snd_kcontrol *kcontrol; +}; + +typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data); + +struct snd_emu10k1_fx8010_irq { + struct snd_emu10k1_fx8010_irq *next; + snd_fx8010_irq_handler_t *handler; + unsigned short gpr_running; + void *private_data; +}; + +struct snd_emu10k1_fx8010_pcm { + unsigned int valid: 1, + opened: 1, + active: 1; + unsigned int channels; /* 16-bit channels count */ + unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */ + unsigned int buffer_size; /* count of buffered samples */ + unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */ + unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ + unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ + unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ + unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ + unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ + unsigned char etram[32]; /* external TRAM address & data */ + struct snd_pcm_indirect pcm_rec; + unsigned int tram_pos; + unsigned int tram_shift; + struct snd_emu10k1_fx8010_irq irq; +}; + +struct snd_emu10k1_fx8010 { + unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */ + unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */ + unsigned int itram_size; /* internal TRAM size in samples */ + struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ + unsigned int dbg; /* FX debugger register */ + unsigned char name[128]; + int gpr_size; /* size of allocated GPR controls */ + int gpr_count; /* count of used kcontrols */ + struct list_head gpr_ctl; /* GPR controls */ + struct mutex lock; + struct snd_emu10k1_fx8010_pcm pcm[8]; + spinlock_t irq_lock; + struct snd_emu10k1_fx8010_irq *irq_handlers; +}; + +struct snd_emu10k1_midi { + struct snd_emu10k1 *emu; + struct snd_rawmidi *rmidi; + struct snd_rawmidi_substream *substream_input; + struct snd_rawmidi_substream *substream_output; + unsigned int midi_mode; + spinlock_t input_lock; + spinlock_t output_lock; + spinlock_t open_lock; + int tx_enable, rx_enable; + int port; + int ipr_tx, ipr_rx; + void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); +}; + +enum { + EMU_MODEL_SB, + EMU_MODEL_EMU1010, + EMU_MODEL_EMU1010B, + EMU_MODEL_EMU1616, + EMU_MODEL_EMU0404, +}; + +// Chip-o-logy: +// - All SB Live! cards use EMU10K1 chips +// - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver +// - Original Audigy uses CA0100 "Alice" +// - Audigy 2 uses CA0102/CA10200 "Alice2" +// - Has an interface for CA0151 (P16V) "Alice3" +// - Audigy 2 Value uses CA0108/CA10300 "Tina" +// - Approximately a CA0102 with an on-chip CA0151 (P17V) +// - Audigy 2 ZS NB uses CA0109 "Tina2" +// - Cardbus version of CA0108 +struct snd_emu_chip_details { + u32 vendor; + u32 device; + u32 subsystem; + unsigned char revision; + unsigned char emu_model; /* EMU model type */ + unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */ + /* Redundant with emu10k2_chip being unset. */ + unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */ + unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ + /* Redundant with ca0108_chip being unset. */ + unsigned int ca0108_chip:1; /* Audigy 2 Value */ + unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */ + unsigned int ca0151_chip:1; /* P16V */ + unsigned int spk20:1; /* Stereo only */ + unsigned int spk71:1; /* Has 7.1 speakers */ + unsigned int no_adat:1; /* Has no ADAT, only SPDIF */ + unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ + unsigned int spdif_bug:1; /* Has Spdif phasing bug */ + unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ + unsigned int ecard:1; /* APS EEPROM */ + unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */ + unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */ + unsigned int adc_1361t:1; /* Use Philips 1361T ADC */ + unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */ + const char *driver; + const char *name; + const char *id; /* for backward compatibility - can be NULL if not needed */ +}; + +#define NUM_OUTPUT_DESTS 28 +#define NUM_INPUT_DESTS 22 + +struct snd_emu1010 { + unsigned char output_source[NUM_OUTPUT_DESTS]; + unsigned char input_source[NUM_INPUT_DESTS]; + unsigned int adc_pads; /* bit mask */ + unsigned int dac_pads; /* bit mask */ + unsigned int wclock; /* Cached register value */ + unsigned int word_clock; /* Cached effective value */ + unsigned int clock_source; + unsigned int clock_fallback; + unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ + unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ + struct work_struct work; + struct mutex lock; +}; + +struct snd_emu10k1 { + int irq; + + unsigned long port; /* I/O port number */ + unsigned int tos_link: 1, /* tos link detected */ + rear_ac97: 1, /* rear channels are on AC'97 */ + enable_ir: 1; + unsigned int support_tlv :1; + /* Contains profile of card capabilities */ + const struct snd_emu_chip_details *card_capabilities; + unsigned int audigy; /* is Audigy? */ + unsigned int revision; /* chip revision */ + unsigned int serial; /* serial number */ + unsigned short model; /* subsystem id */ + unsigned int ecard_ctrl; /* ecard control bits */ + unsigned int address_mode; /* address mode */ + unsigned long dma_mask; /* PCI DMA mask */ + bool iommu_workaround; /* IOMMU workaround needed */ + int max_cache_pages; /* max memory size / PAGE_SIZE */ + struct snd_dma_buffer silent_page; /* silent page */ + struct snd_dma_buffer ptb_pages; /* page table pages */ + struct snd_dma_device p16v_dma_dev; + struct snd_dma_buffer *p16v_buffer; + + struct snd_util_memhdr *memhdr; /* page allocation list */ + + struct list_head mapped_link_head; + struct list_head mapped_order_link_head; + void **page_ptr_table; + unsigned long *page_addr_table; + spinlock_t memblk_lock; + + unsigned int spdif_bits[3]; /* s/pdif out setup */ + unsigned int i2c_capture_source; + u8 i2c_capture_volume[4][2]; + + struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ + int gpr_base; + + struct snd_ac97 *ac97; + + struct pci_dev *pci; + struct snd_card *card; + struct snd_pcm *pcm; + struct snd_pcm *pcm_mic; + struct snd_pcm *pcm_efx; + struct snd_pcm *pcm_multi; + struct snd_pcm *pcm_p16v; + + spinlock_t synth_lock; + void *synth; + int (*get_synth_voice)(struct snd_emu10k1 *emu); + + spinlock_t reg_lock; // high-level driver lock + spinlock_t emu_lock; // low-level i/o lock + spinlock_t voice_lock; // voice allocator lock + spinlock_t spi_lock; /* serialises access to spi port */ + spinlock_t i2c_lock; /* serialises access to i2c port */ + + struct snd_emu10k1_voice voices[NUM_G]; + int p16v_device_offset; + u32 p16v_capture_source; + u32 p16v_capture_channel; + struct snd_emu1010 emu1010; + struct snd_emu10k1_pcm_mixer pcm_mixer[32]; + struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK]; + struct snd_kcontrol *ctl_send_routing; + struct snd_kcontrol *ctl_send_volume; + struct snd_kcontrol *ctl_attn; + struct snd_kcontrol *ctl_efx_send_routing; + struct snd_kcontrol *ctl_efx_send_volume; + struct snd_kcontrol *ctl_efx_attn; + struct snd_kcontrol *ctl_clock_source; + + void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*dsp_interrupt)(struct snd_emu10k1 *emu); + void (*gpio_interrupt)(struct snd_emu10k1 *emu); + void (*p16v_interrupt)(struct snd_emu10k1 *emu); + + struct snd_pcm_substream *pcm_capture_substream; + struct snd_pcm_substream *pcm_capture_mic_substream; + struct snd_pcm_substream *pcm_capture_efx_substream; + + struct snd_timer *timer; + + struct snd_emu10k1_midi midi; + struct snd_emu10k1_midi midi2; /* for audigy */ + + unsigned int efx_voices_mask[2]; + unsigned int next_free_voice; + + const struct firmware *firmware; + const struct firmware *dock_fw; + +#ifdef CONFIG_PM_SLEEP + unsigned int *saved_ptr; + unsigned int *saved_gpr; + unsigned int *tram_val_saved; + unsigned int *tram_addr_saved; + unsigned int *saved_icode; + unsigned int *p16v_saved; + unsigned int saved_a_iocfg, saved_hcfg; + bool suspend; +#endif + +}; + +int snd_emu10k1_create(struct snd_card *card, + struct pci_dev *pci, + unsigned short extin_mask, + unsigned short extout_mask, + long max_cache_bytes, + int enable_ir, + uint subsystem); + +int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device); +int snd_p16v_pcm(struct snd_emu10k1 *emu, int device); +int snd_p16v_mixer(struct snd_emu10k1 * emu); +int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device); +int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device); +int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device); + +irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id); + +void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice); +int snd_emu10k1_init_efx(struct snd_emu10k1 *emu); +void snd_emu10k1_free_efx(struct snd_emu10k1 *emu); +int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size); +int snd_emu10k1_done(struct snd_emu10k1 * emu); + +/* I/O functions */ +unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); +void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); +void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...); +unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); +void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); +int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); +int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); +DEFINE_GUARD(snd_emu1010_fpga_lock, struct snd_emu10k1 *, mutex_lock(&(_T)->emu1010.lock), mutex_unlock(&(_T)->emu1010.lock)) +void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value); +void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value); +void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value); +void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src); +u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst); +int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src); +void snd_emu1010_update_clock(struct snd_emu10k1 *emu); +void snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, int dock, const struct firmware *fw_entry); +unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); +void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); +void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); +void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); +#if 0 +void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); +#endif +void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); +void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices); +int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices); +void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); +static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } +unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); +void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); + +#ifdef CONFIG_PM_SLEEP +void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); +void snd_emu10k1_resume_init(struct snd_emu10k1 *emu); +void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu); +int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu); +void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu); +void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu); +void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu); +int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu); +void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu); +void snd_p16v_suspend(struct snd_emu10k1 *emu); +void snd_p16v_resume(struct snd_emu10k1 *emu); +#endif + +/* memory allocation */ +struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream); +int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); +int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size, + struct snd_dma_buffer *dmab); +struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size); +int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); +int snd_emu10k1_synth_memset(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size, u8 value); +int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size, u32 xor); +int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); + +/* voice allocation */ +int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels, + struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice); +int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); + +/* MIDI uart */ +int snd_emu10k1_midi(struct snd_emu10k1 * emu); +int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu); + +/* proc interface */ +int snd_emu10k1_proc_init(struct snd_emu10k1 * emu); + +/* fx8010 irq handler */ +int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, + snd_fx8010_irq_handler_t *handler, + unsigned char gpr_running, + void *private_data, + struct snd_emu10k1_fx8010_irq *irq); +int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, + struct snd_emu10k1_fx8010_irq *irq); + +#endif /* __SOUND_EMU10K1_H */ diff --git a/include/sound/emu10k1_synth.h b/include/sound/emu10k1_synth.h new file mode 100644 index 000000000..05af4f921 --- /dev/null +++ b/include/sound/emu10k1_synth.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __EMU10K1_SYNTH_H +#define __EMU10K1_SYNTH_H +/* + * Defines for the Emu10k1 WaveTable synth + * + * Copyright (C) 2000 Takashi Iwai + */ + +#include +#include + +/* sequencer device id */ +#define SNDRV_SEQ_DEV_ID_EMU10K1_SYNTH "emu10k1-synth" + +/* argument for snd_seq_device_new */ +struct snd_emu10k1_synth_arg { + struct snd_emu10k1 *hwptr; /* chip */ + int index; /* sequencer client index */ + int seq_ports; /* number of sequencer ports to be created */ + int max_voices; /* maximum number of voices for wavetable */ +}; + +#define EMU10K1_MAX_MEMSIZE (32 * 1024 * 1024) /* 32MB */ + +#endif diff --git a/include/sound/emu8000.h b/include/sound/emu8000.h new file mode 100644 index 000000000..072791bbc --- /dev/null +++ b/include/sound/emu8000.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMU8000_H +#define __SOUND_EMU8000_H +/* + * Defines for the emu8000 (AWE32/64) + * + * Copyright (C) 1999 Steve Ratcliffe + * Copyright (C) 1999-2000 Takashi Iwai + */ + +#include +#include + +/* + * Hardware parameters. + */ +#define EMU8000_MAX_DRAM (28 * 1024 * 1024) /* Max on-board mem is 28Mb ???*/ +#define EMU8000_DRAM_OFFSET 0x200000 /* Beginning of on board ram */ +#define EMU8000_CHANNELS 32 /* Number of hardware channels */ +#define EMU8000_DRAM_VOICES 30 /* number of normal voices */ + +/* Flags to set a dma channel to read or write */ +#define EMU8000_RAM_READ 0 +#define EMU8000_RAM_WRITE 1 +#define EMU8000_RAM_CLOSE 2 +#define EMU8000_RAM_MODE_MASK 0x03 +#define EMU8000_RAM_RIGHT 0x10 /* use 'right' DMA channel */ + +enum { + EMU8000_CONTROL_BASS = 0, + EMU8000_CONTROL_TREBLE, + EMU8000_CONTROL_CHORUS_MODE, + EMU8000_CONTROL_REVERB_MODE, + EMU8000_CONTROL_FM_CHORUS_DEPTH, + EMU8000_CONTROL_FM_REVERB_DEPTH, + EMU8000_NUM_CONTROLS, +}; + +/* + * Structure to hold all state information for the emu8000 driver. + * + * Note 1: The chip supports 32 channels in hardware this is max_channels + * some of the channels may be used for other things so max_channels is + * the number in use for wave voices. + */ +struct snd_emu8000 { + + struct snd_emux *emu; + + int index; /* sequencer client index */ + int seq_ports; /* number of sequencer ports */ + int fm_chorus_depth; /* FM OPL3 chorus depth */ + int fm_reverb_depth; /* FM OPL3 reverb depth */ + + int mem_size; /* memory size */ + unsigned long port1; /* Port usually base+0 */ + unsigned long port2; /* Port usually at base+0x400 */ + unsigned long port3; /* Port usually at base+0x800 */ + unsigned short last_reg;/* Last register command */ + spinlock_t reg_lock; + + int dram_checked; + + struct snd_card *card; /* The card that this belongs to */ + + int chorus_mode; + int reverb_mode; + int bass_level; + int treble_level; + + struct snd_util_memhdr *memhdr; + + spinlock_t control_lock; + struct snd_kcontrol *controls[EMU8000_NUM_CONTROLS]; + + struct snd_pcm *pcm; /* pcm on emu8000 wavetable */ + +}; + +/* sequencer device id */ +#define SNDRV_SEQ_DEV_ID_EMU8000 "emu8000-synth" + + +/* exported functions */ +int snd_emu8000_new(struct snd_card *card, int device, long port, int seq_ports, + struct snd_seq_device **ret); +void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, + unsigned int val); +unsigned short snd_emu8000_peek(struct snd_emu8000 *emu, unsigned int port, + unsigned int reg); +void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, + unsigned int val); +unsigned int snd_emu8000_peek_dw(struct snd_emu8000 *emu, unsigned int port, + unsigned int reg); +void snd_emu8000_dma_chan(struct snd_emu8000 *emu, int ch, int mode); + +void snd_emu8000_init_fm(struct snd_emu8000 *emu); + +void snd_emu8000_update_chorus_mode(struct snd_emu8000 *emu); +void snd_emu8000_update_reverb_mode(struct snd_emu8000 *emu); +void snd_emu8000_update_equalizer(struct snd_emu8000 *emu); +int snd_emu8000_load_chorus_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len); +int snd_emu8000_load_reverb_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len); + +#endif /* __SOUND_EMU8000_H */ diff --git a/include/sound/emu8000_reg.h b/include/sound/emu8000_reg.h new file mode 100644 index 000000000..04cedff25 --- /dev/null +++ b/include/sound/emu8000_reg.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMU8000_REG_H +#define __SOUND_EMU8000_REG_H +/* + * Register operations for the EMU8000 + * + * Copyright (C) 1999 Steve Ratcliffe + * + * Based on awe_wave.c by Takashi Iwai + */ + +/* + * Data port addresses relative to the EMU base. + */ +#define EMU8000_DATA0(e) ((e)->port1) +#define EMU8000_DATA1(e) ((e)->port2) +#define EMU8000_DATA2(e) ((e)->port2+2) +#define EMU8000_DATA3(e) ((e)->port3) +#define EMU8000_PTR(e) ((e)->port3+2) + +/* + * Make a command from a register and channel. + */ +#define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan)) + +/* + * Commands to read and write the EMU8000 registers. + * These macros should be used for all register accesses. + */ +#define EMU8000_CPF_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan))) +#define EMU8000_PTRX_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan))) +#define EMU8000_CVCF_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_VTFT_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_PSST_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan))) +#define EMU8000_CSL_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan))) +#define EMU8000_CCCA_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan))) +#define EMU8000_HWCF4_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9)) +#define EMU8000_HWCF5_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10)) +#define EMU8000_HWCF6_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13)) +#define EMU8000_SMALR_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20)) +#define EMU8000_SMARR_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21)) +#define EMU8000_SMALW_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22)) +#define EMU8000_SMARW_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23)) +#define EMU8000_SMLD_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26)) +#define EMU8000_SMRD_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26)) +#define EMU8000_WC_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27)) +#define EMU8000_HWCF1_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29)) +#define EMU8000_HWCF2_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30)) +#define EMU8000_HWCF3_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31)) +#define EMU8000_INIT1_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_INIT2_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_INIT3_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_INIT4_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_ENVVOL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan))) +#define EMU8000_DCYSUSV_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan))) +#define EMU8000_ENVVAL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan))) +#define EMU8000_DCYSUS_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan))) +#define EMU8000_ATKHLDV_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan))) +#define EMU8000_LFO1VAL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan))) +#define EMU8000_ATKHLD_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan))) +#define EMU8000_LFO2VAL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan))) +#define EMU8000_IP_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan))) +#define EMU8000_IFATN_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan))) +#define EMU8000_PEFE_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_FMMOD_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_TREMFRQ_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan))) +#define EMU8000_FM2FRQ2_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan))) + + +#define EMU8000_CPF_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val)) +#define EMU8000_PTRX_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val)) +#define EMU8000_CVCF_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_VTFT_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_PSST_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val)) +#define EMU8000_CSL_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)), (val)) +#define EMU8000_CCCA_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)), (val)) +#define EMU8000_HWCF4_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9), (val)) +#define EMU8000_HWCF5_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10), (val)) +#define EMU8000_HWCF6_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13), (val)) +/* this register is not documented */ +#define EMU8000_HWCF7_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 14), (val)) +#define EMU8000_SMALR_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20), (val)) +#define EMU8000_SMARR_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21), (val)) +#define EMU8000_SMALW_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22), (val)) +#define EMU8000_SMARW_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23), (val)) +#define EMU8000_SMLD_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26), (val)) +#define EMU8000_SMRD_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26), (val)) +#define EMU8000_WC_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27), (val)) +#define EMU8000_HWCF1_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29), (val)) +#define EMU8000_HWCF2_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30), (val)) +#define EMU8000_HWCF3_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31), (val)) +#define EMU8000_INIT1_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_INIT2_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_INIT3_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_INIT4_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_ENVVOL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_DCYSUSV_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)), (val)) +#define EMU8000_ENVVAL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)), (val)) +#define EMU8000_DCYSUS_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)), (val)) +#define EMU8000_ATKHLDV_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_LFO1VAL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)), (val)) +#define EMU8000_ATKHLD_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)), (val)) +#define EMU8000_LFO2VAL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)), (val)) +#define EMU8000_IP_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)), (val)) +#define EMU8000_IFATN_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)), (val)) +#define EMU8000_PEFE_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_FMMOD_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_TREMFRQ_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_FM2FRQ2_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)), (val)) + +#define EMU8000_0080_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_00A0_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(5, (chan)), (val)) + +#endif /* __SOUND_EMU8000_REG_H */ diff --git a/include/sound/emux_legacy.h b/include/sound/emux_legacy.h new file mode 100644 index 000000000..1127e30d3 --- /dev/null +++ b/include/sound/emux_legacy.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMUX_LEGACY_H +#define __SOUND_EMUX_LEGACY_H + +/* + * Copyright (c) 1999-2000 Takashi Iwai + * + * Definitions of OSS compatible headers for Emu8000 device informations + */ + +#include + +/* + * awe hardware controls + */ + +#define _EMUX_OSS_DEBUG_MODE 0x00 +#define _EMUX_OSS_REVERB_MODE 0x01 +#define _EMUX_OSS_CHORUS_MODE 0x02 +#define _EMUX_OSS_REMOVE_LAST_SAMPLES 0x03 +#define _EMUX_OSS_INITIALIZE_CHIP 0x04 +#define _EMUX_OSS_SEND_EFFECT 0x05 +#define _EMUX_OSS_TERMINATE_CHANNEL 0x06 +#define _EMUX_OSS_TERMINATE_ALL 0x07 +#define _EMUX_OSS_INITIAL_VOLUME 0x08 +#define _EMUX_OSS_INITIAL_ATTEN _EMUX_OSS_INITIAL_VOLUME +#define _EMUX_OSS_RESET_CHANNEL 0x09 +#define _EMUX_OSS_CHANNEL_MODE 0x0a +#define _EMUX_OSS_DRUM_CHANNELS 0x0b +#define _EMUX_OSS_MISC_MODE 0x0c +#define _EMUX_OSS_RELEASE_ALL 0x0d +#define _EMUX_OSS_NOTEOFF_ALL 0x0e +#define _EMUX_OSS_CHN_PRESSURE 0x0f +#define _EMUX_OSS_EQUALIZER 0x11 + +#define _EMUX_OSS_MODE_FLAG 0x80 +#define _EMUX_OSS_COOKED_FLAG 0x40 /* not supported */ +#define _EMUX_OSS_MODE_VALUE_MASK 0x3F + + +/* + * mode type definitions + */ +enum { +/* 0*/ EMUX_MD_EXCLUSIVE_OFF, /* obsolete */ +/* 1*/ EMUX_MD_EXCLUSIVE_ON, /* obsolete */ +/* 2*/ EMUX_MD_VERSION, /* read only */ +/* 3*/ EMUX_MD_EXCLUSIVE_SOUND, /* 0/1: exclusive note on (default=1) */ +/* 4*/ EMUX_MD_REALTIME_PAN, /* 0/1: do realtime pan change (default=1) */ +/* 5*/ EMUX_MD_GUS_BANK, /* bank number for GUS patches (default=0) */ +/* 6*/ EMUX_MD_KEEP_EFFECT, /* 0/1: keep effect values, (default=0) */ +/* 7*/ EMUX_MD_ZERO_ATTEN, /* attenuation of max volume (default=32) */ +/* 8*/ EMUX_MD_CHN_PRIOR, /* 0/1: set MIDI channel priority mode (default=1) */ +/* 9*/ EMUX_MD_MOD_SENSE, /* integer: modwheel sensitivity (def=18) */ +/*10*/ EMUX_MD_DEF_PRESET, /* integer: default preset number (def=0) */ +/*11*/ EMUX_MD_DEF_BANK, /* integer: default bank number (def=0) */ +/*12*/ EMUX_MD_DEF_DRUM, /* integer: default drumset number (def=0) */ +/*13*/ EMUX_MD_TOGGLE_DRUM_BANK, /* 0/1: toggle drum flag with bank# (def=0) */ +/*14*/ EMUX_MD_NEW_VOLUME_CALC, /* 0/1: volume calculation mode (def=1) */ +/*15*/ EMUX_MD_CHORUS_MODE, /* integer: chorus mode (def=2) */ +/*16*/ EMUX_MD_REVERB_MODE, /* integer: chorus mode (def=4) */ +/*17*/ EMUX_MD_BASS_LEVEL, /* integer: bass level (def=5) */ +/*18*/ EMUX_MD_TREBLE_LEVEL, /* integer: treble level (def=9) */ +/*19*/ EMUX_MD_DEBUG_MODE, /* integer: debug level (def=0) */ +/*20*/ EMUX_MD_PAN_EXCHANGE, /* 0/1: exchange panning direction (def=0) */ + EMUX_MD_END, +}; + + +/* + * effect parameters + */ +enum { + +/* modulation envelope parameters */ +/* 0*/ EMUX_FX_ENV1_DELAY, /* WORD: ENVVAL */ +/* 1*/ EMUX_FX_ENV1_ATTACK, /* BYTE: up ATKHLD */ +/* 2*/ EMUX_FX_ENV1_HOLD, /* BYTE: lw ATKHLD */ +/* 3*/ EMUX_FX_ENV1_DECAY, /* BYTE: lw DCYSUS */ +/* 4*/ EMUX_FX_ENV1_RELEASE, /* BYTE: lw DCYSUS */ +/* 5*/ EMUX_FX_ENV1_SUSTAIN, /* BYTE: up DCYSUS */ +/* 6*/ EMUX_FX_ENV1_PITCH, /* BYTE: up PEFE */ +/* 7*/ EMUX_FX_ENV1_CUTOFF, /* BYTE: lw PEFE */ + +/* volume envelope parameters */ +/* 8*/ EMUX_FX_ENV2_DELAY, /* WORD: ENVVOL */ +/* 9*/ EMUX_FX_ENV2_ATTACK, /* BYTE: up ATKHLDV */ +/*10*/ EMUX_FX_ENV2_HOLD, /* BYTE: lw ATKHLDV */ +/*11*/ EMUX_FX_ENV2_DECAY, /* BYTE: lw DCYSUSV */ +/*12*/ EMUX_FX_ENV2_RELEASE, /* BYTE: lw DCYSUSV */ +/*13*/ EMUX_FX_ENV2_SUSTAIN, /* BYTE: up DCYSUSV */ + +/* LFO1 (tremolo & vibrato) parameters */ +/*14*/ EMUX_FX_LFO1_DELAY, /* WORD: LFO1VAL */ +/*15*/ EMUX_FX_LFO1_FREQ, /* BYTE: lo TREMFRQ */ +/*16*/ EMUX_FX_LFO1_VOLUME, /* BYTE: up TREMFRQ */ +/*17*/ EMUX_FX_LFO1_PITCH, /* BYTE: up FMMOD */ +/*18*/ EMUX_FX_LFO1_CUTOFF, /* BYTE: lo FMMOD */ + +/* LFO2 (vibrato) parameters */ +/*19*/ EMUX_FX_LFO2_DELAY, /* WORD: LFO2VAL */ +/*20*/ EMUX_FX_LFO2_FREQ, /* BYTE: lo FM2FRQ2 */ +/*21*/ EMUX_FX_LFO2_PITCH, /* BYTE: up FM2FRQ2 */ + +/* Other overall effect parameters */ +/*22*/ EMUX_FX_INIT_PITCH, /* SHORT: pitch offset */ +/*23*/ EMUX_FX_CHORUS, /* BYTE: chorus effects send (0-255) */ +/*24*/ EMUX_FX_REVERB, /* BYTE: reverb effects send (0-255) */ +/*25*/ EMUX_FX_CUTOFF, /* BYTE: up IFATN */ +/*26*/ EMUX_FX_FILTERQ, /* BYTE: up CCCA */ + +/* Sample / loop offset changes */ +/*27*/ EMUX_FX_SAMPLE_START, /* SHORT: offset */ +/*28*/ EMUX_FX_LOOP_START, /* SHORT: offset */ +/*29*/ EMUX_FX_LOOP_END, /* SHORT: offset */ +/*30*/ EMUX_FX_COARSE_SAMPLE_START, /* SHORT: upper word offset */ +/*31*/ EMUX_FX_COARSE_LOOP_START, /* SHORT: upper word offset */ +/*32*/ EMUX_FX_COARSE_LOOP_END, /* SHORT: upper word offset */ +/*33*/ EMUX_FX_ATTEN, /* BYTE: lo IFATN */ + + EMUX_FX_END, +}; +/* number of effects */ +#define EMUX_NUM_EFFECTS EMUX_FX_END + +/* effect flag values */ +#define EMUX_FX_FLAG_OFF 0 +#define EMUX_FX_FLAG_SET 1 +#define EMUX_FX_FLAG_ADD 2 + + +#endif /* __SOUND_EMUX_LEGACY_H */ diff --git a/include/sound/emux_synth.h b/include/sound/emux_synth.h new file mode 100644 index 000000000..2c0a976e0 --- /dev/null +++ b/include/sound/emux_synth.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMUX_SYNTH_H +#define __SOUND_EMUX_SYNTH_H + +/* + * Defines for the Emu-series WaveTable chip + * + * Copyright (C) 2000 Takashi Iwai + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * compile flags + */ +#define SNDRV_EMUX_USE_RAW_EFFECT + +struct snd_emux; +struct snd_emux_port; +struct snd_emux_voice; +struct snd_emux_effect_table; + +/* + * operators + */ +struct snd_emux_operators { + struct module *owner; + struct snd_emux_voice *(*get_voice)(struct snd_emux *emu, + struct snd_emux_port *port); + int (*prepare)(struct snd_emux_voice *vp); + void (*trigger)(struct snd_emux_voice *vp); + void (*release)(struct snd_emux_voice *vp); + void (*update)(struct snd_emux_voice *vp, int update); + void (*terminate)(struct snd_emux_voice *vp); + void (*free_voice)(struct snd_emux_voice *vp); + void (*reset)(struct snd_emux *emu, int ch); + /* the first parameters are struct snd_emux */ + int (*sample_new)(struct snd_emux *emu, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr, + const void __user *data, long count); + int (*sample_free)(struct snd_emux *emu, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr); + void (*sample_reset)(struct snd_emux *emu); + int (*load_fx)(struct snd_emux *emu, int type, int arg, + const void __user *data, long count); + void (*sysex)(struct snd_emux *emu, char *buf, int len, int parsed, + struct snd_midi_channel_set *chset); +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + int (*oss_ioctl)(struct snd_emux *emu, int cmd, int p1, int p2); +#endif + int (*get_pitch_shift)(struct snd_emux *emu); +}; + + +/* + * constant values + */ +#define SNDRV_EMUX_MAX_PORTS 32 /* max # of sequencer ports */ +#define SNDRV_EMUX_MAX_VOICES 64 /* max # of voices */ +#define SNDRV_EMUX_MAX_MULTI_VOICES 16 /* max # of playable voices + * simultineously + */ + +/* + * flags + */ +#define SNDRV_EMUX_ACCEPT_ROM (1<<0) + +/* + * emuX wavetable + */ +struct snd_emux { + + struct snd_card *card; /* assigned card */ + + /* following should be initialized before registration */ + int max_voices; /* Number of voices */ + int mem_size; /* memory size (in byte) */ + int num_ports; /* number of ports to be created */ + struct snd_emux_operators ops; /* operators */ + void *hw; /* hardware */ + unsigned long flags; /* other conditions */ + int midi_ports; /* number of virtual midi devices */ + int midi_devidx; /* device offset of virtual midi */ + unsigned int linear_panning: 1; /* panning is linear (sbawe = 1, emu10k1 = 0) */ + int hwdep_idx; /* hwdep device index */ + struct snd_hwdep *hwdep; /* hwdep device */ + + /* private */ + int num_voices; /* current number of voices */ + struct snd_sf_list *sflist; /* root of SoundFont list */ + struct snd_emux_voice *voices; /* Voices (EMU 'channel') */ + int use_time; /* allocation counter */ + spinlock_t voice_lock; /* Lock for voice access */ + struct mutex register_mutex; + int client; /* For the sequencer client */ + int ports[SNDRV_EMUX_MAX_PORTS]; /* The ports for this device */ + struct snd_emux_port *portptrs[SNDRV_EMUX_MAX_PORTS]; + int used; /* use counter */ + const char *name; /* name of the device (internal) */ + struct snd_rawmidi **vmidi; + struct timer_list tlist; /* for pending note-offs */ + int timer_active; + + struct snd_util_memhdr *memhdr; /* memory chunk information */ + +#ifdef CONFIG_SND_PROC_FS + struct snd_info_entry *proc; +#endif + +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + struct snd_seq_device *oss_synth; +#endif +}; + + +/* + * sequencer port information + */ +struct snd_emux_port { + + struct snd_emux *emu; + + char port_mode; /* operation mode */ + int volume_atten; /* emuX raw attenuation */ + unsigned long drum_flags; /* drum bitmaps */ + int ctrls[EMUX_MD_END]; /* control parameters */ +#ifdef SNDRV_EMUX_USE_RAW_EFFECT + struct snd_emux_effect_table *effect; +#endif +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + struct snd_seq_oss_arg *oss_arg; +#endif + struct snd_midi_channel_set chset; +}; + +/* port_mode */ +#define SNDRV_EMUX_PORT_MODE_MIDI 0 /* normal MIDI port */ +#define SNDRV_EMUX_PORT_MODE_OSS_SYNTH 1 /* OSS synth port */ +#define SNDRV_EMUX_PORT_MODE_OSS_MIDI 2 /* OSS multi channel synth port */ + +/* + * A structure to keep track of each hardware voice + */ +struct snd_emux_voice { + int ch; /* Hardware channel number */ + + int state; /* status */ +#define SNDRV_EMUX_ST_OFF 0x00 /* Not playing, and inactive */ +#define SNDRV_EMUX_ST_ON 0x01 /* Note on */ +#define SNDRV_EMUX_ST_RELEASED (0x02|SNDRV_EMUX_ST_ON) /* Note released */ +#define SNDRV_EMUX_ST_SUSTAINED (0x04|SNDRV_EMUX_ST_ON) /* Note sustained */ +#define SNDRV_EMUX_ST_STANDBY (0x08|SNDRV_EMUX_ST_ON) /* Waiting to be triggered */ +#define SNDRV_EMUX_ST_PENDING (0x10|SNDRV_EMUX_ST_ON) /* Note will be released */ +#define SNDRV_EMUX_ST_LOCKED 0x100 /* Not accessible */ + + unsigned int time; /* An allocation time */ + unsigned char note; /* Note currently assigned to this voice */ + unsigned char key; + unsigned char velocity; /* Velocity of current note */ + + struct snd_sf_zone *zone; /* Zone assigned to this note */ + void *block; /* sample block pointer (optional) */ + struct snd_midi_channel *chan; /* Midi channel for this note */ + struct snd_emux_port *port; /* associated port */ + struct snd_emux *emu; /* assigned root info */ + void *hw; /* hardware pointer (emu8000 or emu10k1) */ + unsigned long ontime; /* jiffies at note triggered */ + + /* Emu8k/Emu10k1 registers */ + struct soundfont_voice_info reg; + + /* additional registers */ + int avol; /* volume attenuation */ + int acutoff; /* cutoff target */ + int apitch; /* pitch offset */ + int apan; /* pan/aux pair */ + int aaux; + int ptarget; /* pitch target */ + int vtarget; /* volume target */ + int ftarget; /* filter target */ + +}; + +/* + * update flags (can be combined) + */ +#define SNDRV_EMUX_UPDATE_VOLUME (1<<0) +#define SNDRV_EMUX_UPDATE_PITCH (1<<1) +#define SNDRV_EMUX_UPDATE_PAN (1<<2) +#define SNDRV_EMUX_UPDATE_FMMOD (1<<3) +#define SNDRV_EMUX_UPDATE_TREMFREQ (1<<4) +#define SNDRV_EMUX_UPDATE_FM2FRQ2 (1<<5) +#define SNDRV_EMUX_UPDATE_Q (1<<6) + + +#ifdef SNDRV_EMUX_USE_RAW_EFFECT +/* + * effect table + */ +struct snd_emux_effect_table { + /* Emu8000 specific effects */ + short val[EMUX_NUM_EFFECTS]; + unsigned char flag[EMUX_NUM_EFFECTS]; +}; +#endif /* SNDRV_EMUX_USE_RAW_EFFECT */ + + +/* + * prototypes - interface to Emu10k1 and Emu8k routines + */ +int snd_emux_new(struct snd_emux **remu); +int snd_emux_register(struct snd_emux *emu, struct snd_card *card, int index, char *name); +int snd_emux_free(struct snd_emux *emu); + +/* + * exported functions + */ +void snd_emux_terminate_all(struct snd_emux *emu); +void snd_emux_lock_voice(struct snd_emux *emu, int voice); +void snd_emux_unlock_voice(struct snd_emux *emu, int voice); + +#endif /* __SOUND_EMUX_SYNTH_H */ diff --git a/include/sound/es1688.h b/include/sound/es1688.h new file mode 100644 index 000000000..425a3717d --- /dev/null +++ b/include/sound/es1688.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_ES1688_H +#define __SOUND_ES1688_H + +/* + * Header file for ES488/ES1688 + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include +#include + +#define ES1688_HW_AUTO 0x0000 +#define ES1688_HW_688 0x0001 +#define ES1688_HW_1688 0x0002 +#define ES1688_HW_UNDEF 0x0003 + +struct snd_es1688 { + struct snd_card *card; + unsigned long port; /* port of ESS chip */ + struct resource *res_port; + unsigned long mpu_port; /* MPU-401 port of ESS chip */ + int irq; /* IRQ number of ESS chip */ + int mpu_irq; /* MPU IRQ */ + int dma8; /* 8-bit DMA */ + unsigned short version; /* version of ESS chip */ + unsigned short hardware; /* see to ES1688_HW_XXXX */ + + unsigned short trigger_value; + unsigned char pad; + unsigned int dma_size; + + struct snd_pcm *pcm; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + + spinlock_t reg_lock; + spinlock_t mixer_lock; +}; + +/* I/O ports */ + +#define ES1688P(codec, x) ((codec)->port + e_s_s_ESS1688##x) + +#define e_s_s_ESS1688RESET 0x6 +#define e_s_s_ESS1688READ 0xa +#define e_s_s_ESS1688WRITE 0xc +#define e_s_s_ESS1688COMMAND 0xc +#define e_s_s_ESS1688STATUS 0xc +#define e_s_s_ESS1688DATA_AVAIL 0xe +#define e_s_s_ESS1688DATA_AVAIL_16 0xf +#define e_s_s_ESS1688MIXER_ADDR 0x4 +#define e_s_s_ESS1688MIXER_DATA 0x5 +#define e_s_s_ESS1688OPL3_LEFT 0x0 +#define e_s_s_ESS1688OPL3_RIGHT 0x2 +#define e_s_s_ESS1688OPL3_BOTH 0x8 +#define e_s_s_ESS1688ENABLE0 0x0 +#define e_s_s_ESS1688ENABLE1 0x9 +#define e_s_s_ESS1688ENABLE2 0xb +#define e_s_s_ESS1688INIT1 0x7 + +#define ES1688_DSP_CMD_DMAOFF 0xd0 +#define ES1688_DSP_CMD_SPKON 0xd1 +#define ES1688_DSP_CMD_SPKOFF 0xd3 +#define ES1688_DSP_CMD_DMAON 0xd4 + +#define ES1688_PCM_DEV 0x14 +#define ES1688_MIC_DEV 0x1a +#define ES1688_REC_DEV 0x1c +#define ES1688_MASTER_DEV 0x32 +#define ES1688_FM_DEV 0x36 +#define ES1688_CD_DEV 0x38 +#define ES1688_AUX_DEV 0x3a +#define ES1688_SPEAKER_DEV 0x3c +#define ES1688_LINE_DEV 0x3e +#define ES1688_RECLEV_DEV 0xb4 + +#define ES1688_MIXS_MASK 0x17 +#define ES1688_MIXS_MIC 0x00 +#define ES1688_MIXS_MIC_MASTER 0x01 +#define ES1688_MIXS_CD 0x02 +#define ES1688_MIXS_AOUT 0x03 +#define ES1688_MIXS_MIC1 0x04 +#define ES1688_MIXS_REC_MIX 0x05 +#define ES1688_MIXS_LINE 0x06 +#define ES1688_MIXS_MASTER 0x07 +#define ES1688_MIXS_MUTE 0x10 + +/* + + */ + +void snd_es1688_mixer_write(struct snd_es1688 *chip, unsigned char reg, unsigned char data); + +int snd_es1688_create(struct snd_card *card, + struct snd_es1688 *chip, + unsigned long port, + unsigned long mpu_port, + int irq, + int mpu_irq, + int dma8, + unsigned short hardware); +int snd_es1688_pcm(struct snd_card *card, struct snd_es1688 *chip, int device); +int snd_es1688_mixer(struct snd_card *card, struct snd_es1688 *chip); +int snd_es1688_reset(struct snd_es1688 *chip); + +#endif /* __SOUND_ES1688_H */ diff --git a/include/sound/graph_card.h b/include/sound/graph_card.h new file mode 100644 index 000000000..8e2e15dfc --- /dev/null +++ b/include/sound/graph_card.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * ASoC audio graph card support + * + */ + +#ifndef __GRAPH_CARD_H +#define __GRAPH_CARD_H + +#include + +typedef int (*GRAPH2_CUSTOM)(struct simple_util_priv *priv, + struct device_node *lnk, + struct link_info *li); + +struct graph2_custom_hooks { + int (*hook_pre)(struct simple_util_priv *priv); + int (*hook_post)(struct simple_util_priv *priv); + GRAPH2_CUSTOM custom_normal; + GRAPH2_CUSTOM custom_dpcm; + GRAPH2_CUSTOM custom_c2c; +}; + +int audio_graph_parse_of(struct simple_util_priv *priv, struct device *dev); +int audio_graph2_parse_of(struct simple_util_priv *priv, struct device *dev, + struct graph2_custom_hooks *hooks); + +int audio_graph2_link_normal(struct simple_util_priv *priv, + struct device_node *lnk, struct link_info *li); +int audio_graph2_link_dpcm(struct simple_util_priv *priv, + struct device_node *lnk, struct link_info *li); +int audio_graph2_link_c2c(struct simple_util_priv *priv, + struct device_node *lnk, struct link_info *li); + +#endif /* __GRAPH_CARD_H */ diff --git a/include/sound/gus.h b/include/sound/gus.h new file mode 100644 index 000000000..3feb42627 --- /dev/null +++ b/include/sound/gus.h @@ -0,0 +1,605 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_GUS_H +#define __SOUND_GUS_H + +/* + * Global structures used for GUS part of ALSA driver + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include +#include +#include +#include +#include + +/* IO ports */ + +#define GUSP(gus, x) ((gus)->gf1.port + SNDRV_g_u_s_##x) + +#define SNDRV_g_u_s_MIDICTRL (0x320-0x220) +#define SNDRV_g_u_s_MIDISTAT (0x320-0x220) +#define SNDRV_g_u_s_MIDIDATA (0x321-0x220) + +#define SNDRV_g_u_s_GF1PAGE (0x322-0x220) +#define SNDRV_g_u_s_GF1REGSEL (0x323-0x220) +#define SNDRV_g_u_s_GF1DATALOW (0x324-0x220) +#define SNDRV_g_u_s_GF1DATAHIGH (0x325-0x220) +#define SNDRV_g_u_s_IRQSTAT (0x226-0x220) +#define SNDRV_g_u_s_TIMERCNTRL (0x228-0x220) +#define SNDRV_g_u_s_TIMERDATA (0x229-0x220) +#define SNDRV_g_u_s_DRAM (0x327-0x220) +#define SNDRV_g_u_s_MIXCNTRLREG (0x220-0x220) +#define SNDRV_g_u_s_IRQDMACNTRLREG (0x22b-0x220) +#define SNDRV_g_u_s_REGCNTRLS (0x22f-0x220) +#define SNDRV_g_u_s_BOARDVERSION (0x726-0x220) +#define SNDRV_g_u_s_MIXCNTRLPORT (0x726-0x220) +#define SNDRV_g_u_s_IVER (0x325-0x220) +#define SNDRV_g_u_s_MIXDATAPORT (0x326-0x220) +#define SNDRV_g_u_s_MAXCNTRLPORT (0x326-0x220) + +/* GF1 registers */ + +/* global registers */ +#define SNDRV_GF1_GB_ACTIVE_VOICES 0x0e +#define SNDRV_GF1_GB_VOICES_IRQ 0x0f +#define SNDRV_GF1_GB_GLOBAL_MODE 0x19 +#define SNDRV_GF1_GW_LFO_BASE 0x1a +#define SNDRV_GF1_GB_VOICES_IRQ_READ 0x1f +#define SNDRV_GF1_GB_DRAM_DMA_CONTROL 0x41 +#define SNDRV_GF1_GW_DRAM_DMA_LOW 0x42 +#define SNDRV_GF1_GW_DRAM_IO_LOW 0x43 +#define SNDRV_GF1_GB_DRAM_IO_HIGH 0x44 +#define SNDRV_GF1_GB_SOUND_BLASTER_CONTROL 0x45 +#define SNDRV_GF1_GB_ADLIB_TIMER_1 0x46 +#define SNDRV_GF1_GB_ADLIB_TIMER_2 0x47 +#define SNDRV_GF1_GB_RECORD_RATE 0x48 +#define SNDRV_GF1_GB_REC_DMA_CONTROL 0x49 +#define SNDRV_GF1_GB_JOYSTICK_DAC_LEVEL 0x4b +#define SNDRV_GF1_GB_RESET 0x4c +#define SNDRV_GF1_GB_DRAM_DMA_HIGH 0x50 +#define SNDRV_GF1_GW_DRAM_IO16 0x51 +#define SNDRV_GF1_GW_MEMORY_CONFIG 0x52 +#define SNDRV_GF1_GB_MEMORY_CONTROL 0x53 +#define SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR 0x54 +#define SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR 0x55 +#define SNDRV_GF1_GW_FIFO_SIZE 0x56 +#define SNDRV_GF1_GW_INTERLEAVE 0x57 +#define SNDRV_GF1_GB_COMPATIBILITY 0x59 +#define SNDRV_GF1_GB_DECODE_CONTROL 0x5a +#define SNDRV_GF1_GB_VERSION_NUMBER 0x5b +#define SNDRV_GF1_GB_MPU401_CONTROL_A 0x5c +#define SNDRV_GF1_GB_MPU401_CONTROL_B 0x5d +#define SNDRV_GF1_GB_EMULATION_IRQ 0x60 +/* voice specific registers */ +#define SNDRV_GF1_VB_ADDRESS_CONTROL 0x00 +#define SNDRV_GF1_VW_FREQUENCY 0x01 +#define SNDRV_GF1_VW_START_HIGH 0x02 +#define SNDRV_GF1_VW_START_LOW 0x03 +#define SNDRV_GF1_VA_START SNDRV_GF1_VW_START_HIGH +#define SNDRV_GF1_VW_END_HIGH 0x04 +#define SNDRV_GF1_VW_END_LOW 0x05 +#define SNDRV_GF1_VA_END SNDRV_GF1_VW_END_HIGH +#define SNDRV_GF1_VB_VOLUME_RATE 0x06 +#define SNDRV_GF1_VB_VOLUME_START 0x07 +#define SNDRV_GF1_VB_VOLUME_END 0x08 +#define SNDRV_GF1_VW_VOLUME 0x09 +#define SNDRV_GF1_VW_CURRENT_HIGH 0x0a +#define SNDRV_GF1_VW_CURRENT_LOW 0x0b +#define SNDRV_GF1_VA_CURRENT SNDRV_GF1_VW_CURRENT_HIGH +#define SNDRV_GF1_VB_PAN 0x0c +#define SNDRV_GF1_VW_OFFSET_RIGHT 0x0c +#define SNDRV_GF1_VB_VOLUME_CONTROL 0x0d +#define SNDRV_GF1_VB_UPPER_ADDRESS 0x10 +#define SNDRV_GF1_VW_EFFECT_HIGH 0x11 +#define SNDRV_GF1_VW_EFFECT_LOW 0x12 +#define SNDRV_GF1_VA_EFFECT SNDRV_GF1_VW_EFFECT_HIGH +#define SNDRV_GF1_VW_OFFSET_LEFT 0x13 +#define SNDRV_GF1_VB_ACCUMULATOR 0x14 +#define SNDRV_GF1_VB_MODE 0x15 +#define SNDRV_GF1_VW_EFFECT_VOLUME 0x16 +#define SNDRV_GF1_VB_FREQUENCY_LFO 0x17 +#define SNDRV_GF1_VB_VOLUME_LFO 0x18 +#define SNDRV_GF1_VW_OFFSET_RIGHT_FINAL 0x1b +#define SNDRV_GF1_VW_OFFSET_LEFT_FINAL 0x1c +#define SNDRV_GF1_VW_EFFECT_VOLUME_FINAL 0x1d + +/* ICS registers */ + +#define SNDRV_ICS_MIC_DEV 0 +#define SNDRV_ICS_LINE_DEV 1 +#define SNDRV_ICS_CD_DEV 2 +#define SNDRV_ICS_GF1_DEV 3 +#define SNDRV_ICS_NONE_DEV 4 +#define SNDRV_ICS_MASTER_DEV 5 + +/* LFO */ + +#define SNDRV_LFO_TREMOLO 0 +#define SNDRV_LFO_VIBRATO 1 + +/* misc */ + +#define SNDRV_GF1_DMA_UNSIGNED 0x80 +#define SNDRV_GF1_DMA_16BIT 0x40 +#define SNDRV_GF1_DMA_IRQ 0x20 +#define SNDRV_GF1_DMA_WIDTH16 0x04 +#define SNDRV_GF1_DMA_READ 0x02 /* read from GUS's DRAM */ +#define SNDRV_GF1_DMA_ENABLE 0x01 + +/* ramp ranges */ + +#define SNDRV_GF1_ATTEN(x) (snd_gf1_atten_table[x]) +#define SNDRV_GF1_MIN_VOLUME 1800 +#define SNDRV_GF1_MAX_VOLUME 4095 +#define SNDRV_GF1_MIN_OFFSET (SNDRV_GF1_MIN_VOLUME>>4) +#define SNDRV_GF1_MAX_OFFSET 255 +#define SNDRV_GF1_MAX_TDEPTH 90 + +/* defines for memory manager */ + +#define SNDRV_GF1_MEM_BLOCK_16BIT 0x0001 + +#define SNDRV_GF1_MEM_OWNER_DRIVER 0x0001 +#define SNDRV_GF1_MEM_OWNER_WAVE_SIMPLE 0x0002 +#define SNDRV_GF1_MEM_OWNER_WAVE_GF1 0x0003 +#define SNDRV_GF1_MEM_OWNER_WAVE_IWFFFF 0x0004 + +/* constants for interrupt handlers */ + +#define SNDRV_GF1_HANDLER_MIDI_OUT 0x00010000 +#define SNDRV_GF1_HANDLER_MIDI_IN 0x00020000 +#define SNDRV_GF1_HANDLER_TIMER1 0x00040000 +#define SNDRV_GF1_HANDLER_TIMER2 0x00080000 +#define SNDRV_GF1_HANDLER_VOICE 0x00100000 +#define SNDRV_GF1_HANDLER_DMA_WRITE 0x00200000 +#define SNDRV_GF1_HANDLER_DMA_READ 0x00400000 +#define SNDRV_GF1_HANDLER_ALL (0xffff0000&~SNDRV_GF1_HANDLER_VOICE) + +/* constants for DMA flags */ + +#define SNDRV_GF1_DMA_TRIGGER 1 + +/* --- */ + +struct snd_gus_card; + +/* GF1 specific structure */ + +struct snd_gf1_bank_info { + unsigned int address; + unsigned int size; +}; + +struct snd_gf1_mem_block { + unsigned short flags; /* flags - SNDRV_GF1_MEM_BLOCK_XXXX */ + unsigned short owner; /* owner - SNDRV_GF1_MEM_OWNER_XXXX */ + unsigned int share; /* share count */ + unsigned int share_id[4]; /* share ID */ + unsigned int ptr; + unsigned int size; + char *name; + struct snd_gf1_mem_block *next; + struct snd_gf1_mem_block *prev; +}; + +struct snd_gf1_mem { + struct snd_gf1_bank_info banks_8[4]; + struct snd_gf1_bank_info banks_16[4]; + struct snd_gf1_mem_block *first; + struct snd_gf1_mem_block *last; + struct mutex memory_mutex; +}; + +struct snd_gf1_dma_block { + void *buffer; /* buffer in computer's RAM */ + unsigned long buf_addr; /* buffer address */ + unsigned int addr; /* address in onboard memory */ + unsigned int count; /* count in bytes */ + unsigned int cmd; /* DMA command (format) */ + void (*ack)(struct snd_gus_card * gus, void *private_data); + void *private_data; + struct snd_gf1_dma_block *next; +}; + +struct snd_gus_port { + struct snd_midi_channel_set * chset; + struct snd_gus_card * gus; + int mode; /* operation mode */ + int client; /* sequencer client number */ + int port; /* sequencer port number */ + unsigned int midi_has_voices: 1; +}; + +struct snd_gus_voice; + +#define SNDRV_GF1_VOICE_TYPE_PCM 0 +#define SNDRV_GF1_VOICE_TYPE_SYNTH 1 +#define SNDRV_GF1_VOICE_TYPE_MIDI 2 + +#define SNDRV_GF1_VFLG_RUNNING (1<<0) +#define SNDRV_GF1_VFLG_EFFECT_TIMER1 (1<<1) +#define SNDRV_GF1_VFLG_PAN (1<<2) + +enum snd_gus_volume_state { + VENV_BEFORE, + VENV_ATTACK, + VENV_SUSTAIN, + VENV_RELEASE, + VENV_DONE, + VENV_VOLUME +}; + +struct snd_gus_voice { + int number; + unsigned int use: 1, + pcm: 1, + synth:1, + midi: 1; + unsigned int flags; + unsigned char client; + unsigned char port; + unsigned char index; + unsigned char pad; + +#ifdef CONFIG_SND_DEBUG + unsigned int interrupt_stat_wave; + unsigned int interrupt_stat_volume; +#endif + void (*handler_wave) (struct snd_gus_card * gus, struct snd_gus_voice * voice); + void (*handler_volume) (struct snd_gus_card * gus, struct snd_gus_voice * voice); + void (*handler_effect) (struct snd_gus_card * gus, struct snd_gus_voice * voice); + void (*volume_change) (struct snd_gus_card * gus); + + struct snd_gus_sample_ops *sample_ops; + + /* running status / registers */ + + unsigned short fc_register; + unsigned short fc_lfo; + unsigned short gf1_volume; + unsigned char control; + unsigned char mode; + unsigned char gf1_pan; + unsigned char effect_accumulator; + unsigned char volume_control; + unsigned char venv_value_next; + enum snd_gus_volume_state venv_state; + enum snd_gus_volume_state venv_state_prev; + unsigned short vlo; + unsigned short vro; + unsigned short gf1_effect_volume; + + /* --- */ + + void *private_data; + void (*private_free)(struct snd_gus_voice *voice); +}; + +struct snd_gf1 { + + unsigned int enh_mode:1, /* enhanced mode (GFA1) */ + hw_lfo:1, /* use hardware LFO */ + sw_lfo:1, /* use software LFO */ + effect:1; /* use effect voices */ + + unsigned long port; /* port of GF1 chip */ + struct resource *res_port1; + struct resource *res_port2; + int irq; /* IRQ number */ + int dma1; /* DMA1 number */ + int dma2; /* DMA2 number */ + unsigned int memory; /* GUS's DRAM size in bytes */ + unsigned int rom_memory; /* GUS's ROM size in bytes */ + unsigned int rom_present; /* bitmask */ + unsigned int rom_banks; /* GUS's ROM banks */ + + struct snd_gf1_mem mem_alloc; + + /* registers */ + unsigned short reg_page; + unsigned short reg_regsel; + unsigned short reg_data8; + unsigned short reg_data16; + unsigned short reg_irqstat; + unsigned short reg_dram; + unsigned short reg_timerctrl; + unsigned short reg_timerdata; + unsigned char ics_regs[6][2]; + /* --------- */ + + unsigned char active_voices; /* active voices */ + unsigned char active_voice; /* selected voice (GF1PAGE register) */ + + struct snd_gus_voice voices[32]; /* GF1 voices */ + + unsigned int default_voice_address; + + unsigned short playback_freq; /* GF1 playback (mixing) frequency */ + unsigned short mode; /* see to SNDRV_GF1_MODE_XXXX */ + unsigned char volume_ramp; + unsigned char smooth_pan; + unsigned char full_range_pan; + unsigned char pad0; + + unsigned char *lfos; + + /* interrupt handlers */ + + void (*interrupt_handler_midi_out) (struct snd_gus_card * gus); + void (*interrupt_handler_midi_in) (struct snd_gus_card * gus); + void (*interrupt_handler_timer1) (struct snd_gus_card * gus); + void (*interrupt_handler_timer2) (struct snd_gus_card * gus); + void (*interrupt_handler_dma_write) (struct snd_gus_card * gus); + void (*interrupt_handler_dma_read) (struct snd_gus_card * gus); + +#ifdef CONFIG_SND_DEBUG + unsigned int interrupt_stat_midi_out; + unsigned int interrupt_stat_midi_in; + unsigned int interrupt_stat_timer1; + unsigned int interrupt_stat_timer2; + unsigned int interrupt_stat_dma_write; + unsigned int interrupt_stat_dma_read; + unsigned int interrupt_stat_voice_lost; +#endif + + /* synthesizer */ + + int seq_client; + struct snd_gus_port seq_ports[4]; + + /* timer */ + + unsigned short timer_enabled; + struct snd_timer *timer1; + struct snd_timer *timer2; + + /* midi */ + + unsigned short uart_cmd; + unsigned int uart_framing; + unsigned int uart_overrun; + + /* dma operations */ + + unsigned int dma_flags; + unsigned int dma_shared; + struct snd_gf1_dma_block *dma_data_pcm; + struct snd_gf1_dma_block *dma_data_pcm_last; + struct snd_gf1_dma_block *dma_data_synth; + struct snd_gf1_dma_block *dma_data_synth_last; + void (*dma_ack)(struct snd_gus_card * gus, void *private_data); + void *dma_private_data; + + /* pcm */ + int pcm_channels; + int pcm_alloc_voices; + unsigned short pcm_volume_level_left; + unsigned short pcm_volume_level_right; + unsigned short pcm_volume_level_left1; + unsigned short pcm_volume_level_right1; + + unsigned char pcm_rcntrl_reg; + unsigned char pad_end; +}; + +/* main structure for GUS card */ + +struct snd_gus_card { + struct snd_card *card; + + unsigned int + initialized: 1, /* resources were initialized */ + equal_irq:1, /* GF1 and CODEC shares IRQ (GUS MAX only) */ + equal_dma:1, /* if dma channels are equal (not valid for daughter board) */ + ics_flag:1, /* have we ICS mixer chip */ + ics_flipped:1, /* ICS mixer have flipped some channels? */ + codec_flag:1, /* have we CODEC chip? */ + max_flag:1, /* have we GUS MAX card? */ + max_ctrl_flag:1, /* have we original GUS MAX card? */ + daughter_flag:1, /* have we daughter board? */ + interwave:1, /* hey - we have InterWave card */ + ess_flag:1, /* ESS chip found... GUS Extreme */ + ace_flag:1, /* GUS ACE detected */ + uart_enable:1; /* enable MIDI UART */ + unsigned short revision; /* revision of chip */ + unsigned short max_cntrl_val; /* GUS MAX control value */ + unsigned short mix_cntrl_reg; /* mixer control register */ + unsigned short joystick_dac; /* joystick DAC level */ + int timer_dev; /* timer device */ + + struct snd_gf1 gf1; /* gf1 specific variables */ + struct snd_pcm *pcm; + struct snd_pcm_substream *pcm_cap_substream; + unsigned int c_dma_size; + unsigned int c_period_size; + unsigned int c_pos; + + struct snd_rawmidi *midi_uart; + struct snd_rawmidi_substream *midi_substream_output; + struct snd_rawmidi_substream *midi_substream_input; + + spinlock_t reg_lock; + spinlock_t voice_alloc; + spinlock_t active_voice_lock; + spinlock_t event_lock; + spinlock_t dma_lock; + spinlock_t pcm_volume_level_lock; + spinlock_t uart_cmd_lock; + struct mutex dma_mutex; + struct mutex register_mutex; +}; + +/* I/O functions for GF1/InterWave chip - gus_io.c */ + +static inline void snd_gf1_select_voice(struct snd_gus_card * gus, int voice) +{ + unsigned long flags; + + spin_lock_irqsave(&gus->active_voice_lock, flags); + if (voice != gus->gf1.active_voice) { + gus->gf1.active_voice = voice; + outb(voice, GUSP(gus, GF1PAGE)); + } + spin_unlock_irqrestore(&gus->active_voice_lock, flags); +} + +static inline void snd_gf1_uart_cmd(struct snd_gus_card * gus, unsigned char b) +{ + outb(gus->gf1.uart_cmd = b, GUSP(gus, MIDICTRL)); +} + +static inline unsigned char snd_gf1_uart_stat(struct snd_gus_card * gus) +{ + return inb(GUSP(gus, MIDISTAT)); +} + +static inline void snd_gf1_uart_put(struct snd_gus_card * gus, unsigned char b) +{ + outb(b, GUSP(gus, MIDIDATA)); +} + +static inline unsigned char snd_gf1_uart_get(struct snd_gus_card * gus) +{ + return inb(GUSP(gus, MIDIDATA)); +} + +extern void snd_gf1_delay(struct snd_gus_card * gus); + +extern void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg); + +extern void snd_gf1_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data); +extern unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg); +static inline unsigned char snd_gf1_read8(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_look8(gus, reg | 0x80); +} +extern void snd_gf1_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data); +extern unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg); +static inline unsigned short snd_gf1_read16(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_look16(gus, reg | 0x80); +} +extern void snd_gf1_adlib_write(struct snd_gus_card * gus, unsigned char reg, unsigned char data); +extern void snd_gf1_dram_addr(struct snd_gus_card * gus, unsigned int addr); +extern void snd_gf1_poke(struct snd_gus_card * gus, unsigned int addr, unsigned char data); +extern unsigned char snd_gf1_peek(struct snd_gus_card * gus, unsigned int addr); +extern void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg, unsigned int addr, short w_16bit); +extern unsigned int snd_gf1_read_addr(struct snd_gus_card * gus, unsigned char reg, short w_16bit); +extern void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg); +extern void snd_gf1_i_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data); +extern unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg); +extern void snd_gf1_i_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data); +static inline unsigned char snd_gf1_i_read8(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_i_look8(gus, reg | 0x80); +} +extern unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg); +static inline unsigned short snd_gf1_i_read16(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_i_look16(gus, reg | 0x80); +} + +extern void snd_gf1_select_active_voices(struct snd_gus_card * gus); + +/* gus_lfo.c */ + +struct _SND_IW_LFO_PROGRAM { + unsigned short freq_and_control; + unsigned char depth_final; + unsigned char depth_inc; + unsigned short twave; + unsigned short depth; +}; + +/* gus_mem.c */ + +int snd_gf1_mem_xfree(struct snd_gf1_mem * alloc, struct snd_gf1_mem_block * block); +struct snd_gf1_mem_block *snd_gf1_mem_alloc(struct snd_gf1_mem * alloc, int owner, + char *name, int size, int w_16, + int align, unsigned int *share_id); +int snd_gf1_mem_free(struct snd_gf1_mem * alloc, unsigned int address); +int snd_gf1_mem_free_owner(struct snd_gf1_mem * alloc, int owner); +int snd_gf1_mem_init(struct snd_gus_card * gus); +int snd_gf1_mem_done(struct snd_gus_card * gus); + +/* gus_mem_proc.c */ + +int snd_gf1_mem_proc_init(struct snd_gus_card * gus); + +/* gus_dma.c */ + +int snd_gf1_dma_init(struct snd_gus_card * gus); +int snd_gf1_dma_done(struct snd_gus_card * gus); +int snd_gf1_dma_transfer_block(struct snd_gus_card * gus, + struct snd_gf1_dma_block * block, + int atomic, + int synth); +void snd_gf1_dma_suspend(struct snd_gus_card *gus); + +/* gus_volume.c */ + +unsigned short snd_gf1_lvol_to_gvol_raw(unsigned int vol); +unsigned short snd_gf1_translate_freq(struct snd_gus_card * gus, unsigned int freq2); + +/* gus_reset.c */ + +void snd_gf1_set_default_handlers(struct snd_gus_card * gus, unsigned int what); +void snd_gf1_smart_stop_voice(struct snd_gus_card * gus, unsigned short voice); +void snd_gf1_stop_voice(struct snd_gus_card * gus, unsigned short voice); +void snd_gf1_stop_voices(struct snd_gus_card * gus, unsigned short v_min, unsigned short v_max); +struct snd_gus_voice *snd_gf1_alloc_voice(struct snd_gus_card * gus, int type, int client, int port); +void snd_gf1_free_voice(struct snd_gus_card * gus, struct snd_gus_voice *voice); +int snd_gf1_start(struct snd_gus_card * gus); +int snd_gf1_stop(struct snd_gus_card * gus); +int snd_gf1_suspend(struct snd_gus_card *gus); +int snd_gf1_resume(struct snd_gus_card *gus); + +/* gus_mixer.c */ + +int snd_gf1_new_mixer(struct snd_gus_card * gus); + +/* gus_pcm.c */ + +int snd_gf1_pcm_new(struct snd_gus_card *gus, int pcm_dev, int control_index); + +/* gus.c */ + +int snd_gus_create(struct snd_card *card, + unsigned long port, + int irq, int dma1, int dma2, + int timer_dev, + int voices, + int pcm_channels, + int effect, + struct snd_gus_card ** rgus); +int snd_gus_initialize(struct snd_gus_card * gus); +int snd_gus_suspend(struct snd_gus_card *gus); +int snd_gus_resume(struct snd_gus_card *gus); + +/* gus_irq.c */ + +irqreturn_t snd_gus_interrupt(int irq, void *dev_id); +#ifdef CONFIG_SND_DEBUG +void snd_gus_irq_profile_init(struct snd_gus_card *gus); +#endif + +/* gus_uart.c */ + +int snd_gf1_rawmidi_new(struct snd_gus_card *gus, int device); +void snd_gf1_uart_suspend(struct snd_gus_card *gus); +void snd_gf1_uart_resume(struct snd_gus_card *gus); + +/* gus_dram.c */ +int snd_gus_dram_write(struct snd_gus_card *gus, char __user *ptr, + unsigned int addr, unsigned int size); +int snd_gus_dram_read(struct snd_gus_card *gus, char __user *ptr, + unsigned int addr, unsigned int size, int rom); + +/* gus_timer.c */ +void snd_gf1_timers_init(struct snd_gus_card *gus); +void snd_gf1_timers_done(struct snd_gus_card *gus); +void snd_gf1_timers_resume(struct snd_gus_card *gus); + +#endif /* __SOUND_GUS_H */ diff --git a/include/sound/hda-mlink.h b/include/sound/hda-mlink.h new file mode 100644 index 000000000..ba35f0357 --- /dev/null +++ b/include/sound/hda-mlink.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2022-2023 Intel Corporation + */ + +struct hdac_bus; +struct hdac_ext_link; + +/** + * enum hda_bus_ml_link_type - mlink link type, used by SOF link DMA + * allocator constraints (see struct sof_intel_hda_dev). + * + * @HDA_BUS_ML_LINK_HDA: non-alt link, i.e. HDA codec or iDisp + * @HDA_BUS_ML_LINK_SDW: alt link, SoundWire + * @HDA_BUS_ML_LINK_UAOL: alt link, USB Audio Offload + * @HDA_BUS_ML_LINK_OTHER: alt link, SSP or DMIC + */ +enum hda_bus_ml_link_type { + HDA_BUS_ML_LINK_HDA, + HDA_BUS_ML_LINK_SDW, + HDA_BUS_ML_LINK_UAOL, + HDA_BUS_ML_LINK_OTHER, +}; + +#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_MLINK) + +int hda_bus_ml_init(struct hdac_bus *bus); +void hda_bus_ml_free(struct hdac_bus *bus); + +int hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid); +void hdac_bus_eml_enable_interrupt_unlocked(struct hdac_bus *bus, bool alt, int elid, bool enable); +void hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable); +bool hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid); + +int hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd); +int hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd); + +int hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid); +int hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus); + +void hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink); +void hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink); + +int hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid); +int hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus); + +bool hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid); +bool hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus); + +int hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink); +int hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink); + +int hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink); +int hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink); + +int hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink); +int hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink); + +int hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid); +int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num); + +int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, + int channel_mask, int stream_id, int dir); + +void hda_bus_ml_reset_losidv(struct hdac_bus *bus); +int hda_bus_ml_resume(struct hdac_bus *bus); +int hda_bus_ml_suspend(struct hdac_bus *bus); + +enum hda_bus_ml_link_type hda_bus_ml_link_get_type(struct hdac_ext_link *hlink); + +struct hdac_ext_link *hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus); +struct hdac_ext_link *hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus); +struct hdac_ext_link *hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus); + +struct mutex *hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid); + +void hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable); + +/* microphone privacy specific function supported by ACE3+ architecture */ +void hdac_bus_eml_set_mic_privacy_mask(struct hdac_bus *bus, bool alt, int elid, + unsigned long mask); +bool hdac_bus_eml_is_mic_privacy_changed(struct hdac_bus *bus, bool alt, int elid); +bool hdac_bus_eml_get_mic_privacy_state(struct hdac_bus *bus, bool alt, int elid); + +#else + +static inline int +hda_bus_ml_init(struct hdac_bus *bus) { return 0; } + +static inline void hda_bus_ml_free(struct hdac_bus *bus) { } + +static inline int +hdac_bus_eml_get_count(struct hdac_bus *bus, bool alt, int elid) { return 0; } + +static inline void +hdac_bus_eml_enable_interrupt_unlocked(struct hdac_bus *bus, bool alt, int elid, bool enable) { } + +static inline void +hdac_bus_eml_enable_interrupt(struct hdac_bus *bus, bool alt, int elid, bool enable) { } + +static inline bool +hdac_bus_eml_check_interrupt(struct hdac_bus *bus, bool alt, int elid) { return false; } + +static inline int +hdac_bus_eml_set_syncprd_unlocked(struct hdac_bus *bus, bool alt, int elid, u32 syncprd) +{ + return 0; +} + +static inline int +hdac_bus_eml_sdw_set_syncprd_unlocked(struct hdac_bus *bus, u32 syncprd) +{ + return 0; +} + +static inline int +hdac_bus_eml_wait_syncpu_unlocked(struct hdac_bus *bus, bool alt, int elid) +{ + return 0; +} + +static inline int +hdac_bus_eml_sdw_wait_syncpu_unlocked(struct hdac_bus *bus) { return 0; } + +static inline void +hdac_bus_eml_sync_arm_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) { } + +static inline void +hdac_bus_eml_sdw_sync_arm_unlocked(struct hdac_bus *bus, int sublink) { } + +static inline int +hdac_bus_eml_sync_go_unlocked(struct hdac_bus *bus, bool alt, int elid) { return 0; } + +static inline int +hdac_bus_eml_sdw_sync_go_unlocked(struct hdac_bus *bus) { return 0; } + +static inline bool +hdac_bus_eml_check_cmdsync_unlocked(struct hdac_bus *bus, bool alt, int elid) { return false; } + +static inline bool +hdac_bus_eml_sdw_check_cmdsync_unlocked(struct hdac_bus *bus) { return false; } + +static inline int +hdac_bus_eml_power_up(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_power_up_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_power_down(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, int sublink) +{ + return 0; +} + +static inline int +hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink) { return 0; } + +static inline int +hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink) { return 0; } + +static inline int +hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid) { return 0; } + +static inline int +hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num) { return 0; } + +static inline int +hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, + int channel_mask, int stream_id, int dir) +{ + return 0; +} + +static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { } +static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; } +static inline int hda_bus_ml_suspend(struct hdac_bus *bus) { return 0; } + +static inline enum hda_bus_ml_link_type +hda_bus_ml_link_get_type(struct hdac_ext_link *hlink) { return HDA_BUS_ML_LINK_HDA; } + +static inline struct hdac_ext_link * +hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus) { return NULL; } + +static inline struct hdac_ext_link * +hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus) { return NULL; } + +static inline struct hdac_ext_link * +hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus) { return NULL; } + +static inline struct mutex * +hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid) { return NULL; } + +static inline void +hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable) +{ +} + +static inline void +hdac_bus_eml_set_mic_privacy_mask(struct hdac_bus *bus, bool alt, int elid, + unsigned long mask) +{ +} + +static inline bool +hdac_bus_eml_is_mic_privacy_changed(struct hdac_bus *bus, bool alt, int elid) +{ + return false; +} + +static inline bool +hdac_bus_eml_get_mic_privacy_state(struct hdac_bus *bus, bool alt, int elid) +{ + return false; +} + +#endif /* CONFIG_SND_SOC_SOF_HDA_MLINK */ diff --git a/include/sound/hda-sdw-bpt.h b/include/sound/hda-sdw-bpt.h new file mode 100644 index 000000000..e24a549f7 --- /dev/null +++ b/include/sound/hda-sdw-bpt.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2025 Intel Corporation. + */ + +#ifndef __HDA_SDW_BPT_H +#define __HDA_SDW_BPT_H + +#include + +struct hdac_ext_stream; +struct snd_dma_buffer; + +#if IS_ENABLED(CONFIG_SND_SOF_SOF_HDA_SDW_BPT) +int hda_sdw_bpt_open(struct device *dev, int link_id, struct hdac_ext_stream **bpt_tx_stream, + struct snd_dma_buffer *dmab_tx_bdl, u32 bpt_tx_num_bytes, + u32 tx_dma_bandwidth, struct hdac_ext_stream **bpt_rx_stream, + struct snd_dma_buffer *dmab_rx_bdl, u32 bpt_rx_num_bytes, + u32 rx_dma_bandwidth); + +int hda_sdw_bpt_send_async(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, + struct hdac_ext_stream *bpt_rx_stream); + +int hda_sdw_bpt_wait(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, + struct hdac_ext_stream *bpt_rx_stream); + +int hda_sdw_bpt_close(struct device *dev, int link_id, struct hdac_ext_stream *bpt_tx_stream, + struct snd_dma_buffer *dmab_tx_bdl, struct hdac_ext_stream *bpt_rx_stream, + struct snd_dma_buffer *dmab_rx_bdl); + +unsigned int hda_sdw_bpt_get_buf_size_alignment(unsigned int dma_bandwidth); +#else +static inline int hda_sdw_bpt_open(struct device *dev, int link_id, + struct hdac_ext_stream **bpt_tx_stream, + struct snd_dma_buffer *dmab_tx_bdl, u32 bpt_tx_num_bytes, + u32 tx_dma_bandwidth, struct hdac_ext_stream **bpt_rx_stream, + struct snd_dma_buffer *dmab_rx_bdl, u32 bpt_rx_num_bytes, + u32 rx_dma_bandwidth) +{ + WARN_ONCE(1, "SoundWire BPT is disabled"); + return -EOPNOTSUPP; +} + +static inline int hda_sdw_bpt_send_async(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, + struct hdac_ext_stream *bpt_rx_stream) +{ + WARN_ONCE(1, "SoundWire BPT is disabled"); + return -EOPNOTSUPP; +} + +static inline int hda_sdw_bpt_wait(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, + struct hdac_ext_stream *bpt_rx_stream) +{ + WARN_ONCE(1, "SoundWire BPT is disabled"); + return -EOPNOTSUPP; +} + +static inline int hda_sdw_bpt_close(struct device *dev, int link_id, + struct hdac_ext_stream *bpt_tx_stream, + struct snd_dma_buffer *dmab_tx_bdl, + struct hdac_ext_stream *bpt_rx_stream, + struct snd_dma_buffer *dmab_rx_bdl) +{ + WARN_ONCE(1, "SoundWire BPT is disabled"); + return -EOPNOTSUPP; +} + +static inline unsigned int hda_sdw_bpt_get_buf_size_alignment(unsigned int dma_bandwidth) +{ + return 0; +} +#endif + +#endif /* __HDA_SDW_BPT_H */ diff --git a/include/sound/hda_chmap.h b/include/sound/hda_chmap.h new file mode 100644 index 000000000..e508f3192 --- /dev/null +++ b/include/sound/hda_chmap.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * For multichannel support + */ + +#ifndef __SOUND_HDA_CHMAP_H +#define __SOUND_HDA_CHMAP_H + +#include +#include + + +#define SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE 80 + +struct hdac_cea_channel_speaker_allocation { + int ca_index; + int speakers[8]; + + /* derived values, just for convenience */ + int channels; + int spk_mask; +}; +struct hdac_chmap; + +struct hdac_chmap_ops { + /* + * Helpers for producing the channel map TLVs. These can be overridden + * for devices that have non-standard mapping requirements. + */ + int (*chmap_cea_alloc_validate_get_type)(struct hdac_chmap *chmap, + struct hdac_cea_channel_speaker_allocation *cap, int channels); + void (*cea_alloc_to_tlv_chmap)(struct hdac_chmap *hchmap, + struct hdac_cea_channel_speaker_allocation *cap, + unsigned int *chmap, int channels); + + /* check that the user-given chmap is supported */ + int (*chmap_validate)(struct hdac_chmap *hchmap, int ca, + int channels, unsigned char *chmap); + + int (*get_spk_alloc)(struct hdac_device *hdac, int pcm_idx); + + void (*get_chmap)(struct hdac_device *hdac, int pcm_idx, + unsigned char *chmap); + void (*set_chmap)(struct hdac_device *hdac, int pcm_idx, + unsigned char *chmap, int prepared); + bool (*is_pcm_attached)(struct hdac_device *hdac, int pcm_idx); + + /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */ + int (*pin_get_slot_channel)(struct hdac_device *codec, + hda_nid_t pin_nid, int asp_slot); + int (*pin_set_slot_channel)(struct hdac_device *codec, + hda_nid_t pin_nid, int asp_slot, int channel); + void (*set_channel_count)(struct hdac_device *codec, + hda_nid_t cvt_nid, int chs); +}; + +struct hdac_chmap { + unsigned int channels_max; /* max over all cvts */ + struct hdac_chmap_ops ops; + struct hdac_device *hdac; +}; + +void snd_hdac_register_chmap_ops(struct hdac_device *hdac, + struct hdac_chmap *chmap); +int snd_hdac_channel_allocation(struct hdac_device *hdac, int spk_alloc, + int channels, bool chmap_set, + bool non_pcm, unsigned char *map); +int snd_hdac_get_active_channels(int ca); +void snd_hdac_setup_channel_mapping(struct hdac_chmap *chmap, + hda_nid_t pin_nid, bool non_pcm, int ca, + int channels, unsigned char *map, + bool chmap_set); +void snd_hdac_print_channel_allocation(int spk_alloc, char *buf, int buflen); +struct hdac_cea_channel_speaker_allocation *snd_hdac_get_ch_alloc_from_ca(int ca); +int snd_hdac_chmap_to_spk_mask(unsigned char c); +int snd_hdac_spk_to_chmap(int spk); +int snd_hdac_add_chmap_ctls(struct snd_pcm *pcm, int pcm_idx, + struct hdac_chmap *chmap); +#endif /* __SOUND_HDA_CHMAP_H */ diff --git a/include/sound/hda_codec.h b/include/sound/hda_codec.h new file mode 100644 index 000000000..1d05f991f --- /dev/null +++ b/include/sound/hda_codec.h @@ -0,0 +1,584 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal Interface for Intel High Definition Audio Codec + * + * Copyright (c) 2004 Takashi Iwai + */ + +#ifndef __SOUND_HDA_CODEC_H +#define __SOUND_HDA_CODEC_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Structures + */ + +struct hda_bus; +struct hda_beep; +struct hda_codec; +struct hda_pcm; +struct hda_pcm_stream; +struct hda_codec_ops; + +/* + * codec bus + * + * each controller needs to creata a hda_bus to assign the accessor. + * A hda_bus contains several codecs in the list codec_list. + */ +struct hda_bus { + struct hdac_bus core; + + struct snd_card *card; + + struct pci_dev *pci; + const char *modelname; + + struct mutex prepare_mutex; + + /* assigned PCMs */ + DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES); + + /* misc op flags */ + unsigned int allow_bus_reset:1; /* allow bus reset at fatal error */ + /* status for codec/controller */ + unsigned int shutdown :1; /* being unloaded */ + unsigned int response_reset:1; /* controller was reset */ + unsigned int in_reset:1; /* during reset operation */ + unsigned int no_response_fallback:1; /* don't fallback at RIRB error */ + unsigned int bus_probing :1; /* during probing process */ + unsigned int keep_power:1; /* keep power up for notification */ + unsigned int jackpoll_in_suspend:1; /* keep jack polling during + * runtime suspend + */ + + int primary_dig_out_type; /* primary digital out PCM type */ + unsigned int mixer_assigned; /* codec addr for mixer name */ +}; + +/* from hdac_bus to hda_bus */ +#define to_hda_bus(bus) container_of(bus, struct hda_bus, core) + +/* + * codec preset + */ + +#define HDA_CODEC_ID_SKIP_PROBE 0x00000001 +#define HDA_CODEC_ID_GENERIC_HDMI 0x00000101 +#define HDA_CODEC_ID_GENERIC 0x00000201 + +#define HDA_CODEC_ID_REV_MODEL(_vid, _rev, _name, _model) \ + { .vendor_id = (_vid), .rev_id = (_rev), .name = (_name), \ + .api_version = HDA_DEV_LEGACY, .driver_data = (_model) } +#define HDA_CODEC_ID_MODEL(_vid, _name, _model) \ + HDA_CODEC_ID_REV_MODEL(_vid, 0, _name, _model) +#define HDA_CODEC_ID_REV(_vid, _rev, _name) \ + HDA_CODEC_ID_REV_MODEL(_vid, _rev, _name, 0) +#define HDA_CODEC_ID(_vid, _name) \ + HDA_CODEC_ID_REV(_vid, 0, _name) + +struct hda_codec_driver { + struct hdac_driver core; + const struct hda_device_id *id; + const struct hda_codec_ops *ops; +}; + +#define hda_codec_to_driver(codec) \ + container_of((codec)->core.dev.driver, struct hda_codec_driver, core.driver) + +int __hda_codec_driver_register(struct hda_codec_driver *drv, const char *name, + struct module *owner); +#define hda_codec_driver_register(drv) \ + __hda_codec_driver_register(drv, KBUILD_MODNAME, THIS_MODULE) +void hda_codec_driver_unregister(struct hda_codec_driver *drv); +#define module_hda_codec_driver(drv) \ + module_driver(drv, hda_codec_driver_register, \ + hda_codec_driver_unregister) + +/* ops for hda codec driver */ +struct hda_codec_ops { + int (*probe)(struct hda_codec *codec, const struct hda_device_id *id); + void (*remove)(struct hda_codec *codec); + int (*build_controls)(struct hda_codec *codec); + int (*build_pcms)(struct hda_codec *codec); + int (*init)(struct hda_codec *codec); + void (*unsol_event)(struct hda_codec *codec, unsigned int res); + void (*set_power_state)(struct hda_codec *codec, hda_nid_t fg, + unsigned int power_state); + int (*suspend)(struct hda_codec *codec); + int (*resume)(struct hda_codec *codec); + int (*check_power_status)(struct hda_codec *codec, hda_nid_t nid); + void (*stream_pm)(struct hda_codec *codec, hda_nid_t nid, bool on); +}; + +/* PCM callbacks */ +struct hda_pcm_ops { + int (*open)(struct hda_pcm_stream *info, struct hda_codec *codec, + struct snd_pcm_substream *substream); + int (*close)(struct hda_pcm_stream *info, struct hda_codec *codec, + struct snd_pcm_substream *substream); + int (*prepare)(struct hda_pcm_stream *info, struct hda_codec *codec, + unsigned int stream_tag, unsigned int format, + struct snd_pcm_substream *substream); + int (*cleanup)(struct hda_pcm_stream *info, struct hda_codec *codec, + struct snd_pcm_substream *substream); + unsigned int (*get_delay)(struct hda_pcm_stream *info, + struct hda_codec *codec, + struct snd_pcm_substream *substream); +}; + +/* PCM information for each substream */ +struct hda_pcm_stream { + unsigned int substreams; /* number of substreams, 0 = not exist*/ + unsigned int channels_min; /* min. number of channels */ + unsigned int channels_max; /* max. number of channels */ + hda_nid_t nid; /* default NID to query rates/formats/bps, or set up */ + u32 rates; /* supported rates */ + u64 formats; /* supported formats (SNDRV_PCM_FMTBIT_) */ + u32 subformats; /* for S32_LE format, SNDRV_PCM_SUBFMTBIT_* */ + unsigned int maxbps; /* supported max. bit per sample */ + const struct snd_pcm_chmap_elem *chmap; /* chmap to override */ + struct hda_pcm_ops ops; +}; + +/* PCM types */ +enum { + HDA_PCM_TYPE_AUDIO, + HDA_PCM_TYPE_SPDIF, + HDA_PCM_TYPE_HDMI, + HDA_PCM_TYPE_MODEM, + HDA_PCM_NTYPES +}; + +#define SNDRV_PCM_INVALID_DEVICE (-1) +/* for PCM creation */ +struct hda_pcm { + char *name; + struct hda_pcm_stream stream[2]; + unsigned int pcm_type; /* HDA_PCM_TYPE_XXX */ + int device; /* device number to assign */ + struct snd_pcm *pcm; /* assigned PCM instance */ + bool own_chmap; /* codec driver provides own channel maps */ + /* private: */ + struct hda_codec *codec; + struct list_head list; + unsigned int disconnected:1; +}; + +/* codec information */ +struct hda_codec { + struct hdac_device core; + struct hda_bus *bus; + struct snd_card *card; + unsigned int addr; /* codec addr*/ + u32 probe_id; /* overridden id for probing */ + + /* detected preset */ + const struct hda_device_id *preset; + const char *modelname; /* model name for preset */ + + /* PCM to create, set by hda_codec_ops.build_pcms callback */ + struct list_head pcm_list_head; + struct snd_refcount pcm_ref; + + /* codec specific info */ + void *spec; + + /* beep device */ + struct hda_beep *beep; + unsigned int beep_mode; + bool beep_just_power_on; + + /* widget capabilities cache */ + u32 *wcaps; + + struct snd_array mixers; /* list of assigned mixer elements */ + struct snd_array nids; /* list of mapped mixer elements */ + + struct list_head conn_list; /* linked-list of connection-list */ + + struct mutex spdif_mutex; + struct mutex control_mutex; + struct snd_array spdif_out; + unsigned int spdif_in_enable; /* SPDIF input enable? */ + const hda_nid_t *follower_dig_outs; /* optional digital out follower widgets */ + struct snd_array init_pins; /* initial (BIOS) pin configurations */ + struct snd_array driver_pins; /* pin configs set by codec parser */ + struct snd_array cvt_setups; /* audio convert setups */ + + struct mutex user_mutex; +#ifdef CONFIG_SND_HDA_RECONFIG + struct snd_array init_verbs; /* additional init verbs */ + struct snd_array hints; /* additional hints */ + struct snd_array user_pins; /* default pin configs to override */ +#endif + +#ifdef CONFIG_SND_HDA_HWDEP + struct snd_hwdep *hwdep; /* assigned hwdep device */ +#endif + + /* misc flags */ + unsigned int configured:1; /* codec was configured */ + unsigned int in_freeing:1; /* being released */ + unsigned int display_power_control:1; /* needs display power */ + unsigned int spdif_status_reset :1; /* needs to toggle SPDIF for each + * status change + * (e.g. Realtek codecs) + */ + unsigned int pin_amp_workaround:1; /* pin out-amp takes index + * (e.g. Conexant codecs) + */ + unsigned int single_adc_amp:1; /* adc in-amp takes no index + * (e.g. CX20549 codec) + */ + unsigned int no_sticky_stream:1; /* no sticky-PCM stream assignment */ + unsigned int pins_shutup:1; /* pins are shut up */ + unsigned int no_trigger_sense:1; /* don't trigger at pin-sensing */ + unsigned int no_jack_detect:1; /* Machine has no jack-detection */ + unsigned int inv_eapd:1; /* broken h/w: inverted EAPD control */ + unsigned int inv_jack_detect:1; /* broken h/w: inverted detection bit */ + unsigned int pcm_format_first:1; /* PCM format must be set first */ + unsigned int cached_write:1; /* write only to caches */ + unsigned int dp_mst:1; /* support DP1.2 Multi-stream transport */ + unsigned int dump_coef:1; /* dump processing coefs in codec proc file */ + unsigned int power_save_node:1; /* advanced PM for each widget */ + unsigned int auto_runtime_pm:1; /* enable automatic codec runtime pm */ + unsigned int force_pin_prefix:1; /* Add location prefix */ + unsigned int link_down_at_suspend:1; /* link down at runtime suspend */ + unsigned int relaxed_resume:1; /* don't resume forcibly for jack */ + unsigned int forced_resume:1; /* forced resume for jack */ + unsigned int acomp_requested_resume:1; /* resume requested by acomp */ + unsigned int no_stream_clean_at_suspend:1; /* do not clean streams at suspend */ + unsigned int ctl_dev_id:1; /* old control element id build behaviour */ + unsigned int eld_jack_detect:1; /* Machine jack-detection by ELD */ + + unsigned long power_on_acct; + unsigned long power_off_acct; + unsigned long power_jiffies; + + /* filter the requested power state per nid */ + unsigned int (*power_filter)(struct hda_codec *codec, hda_nid_t nid, + unsigned int power_state); + + /* codec-specific additional proc output */ + void (*proc_widget_hook)(struct snd_info_buffer *buffer, + struct hda_codec *codec, hda_nid_t nid); + + /* jack detection */ + struct snd_array jacktbl; + unsigned long jackpoll_interval; /* In jiffies. Zero means no poll, rely on unsol events */ + struct delayed_work jackpoll_work; + + int depop_delay; /* depop delay in ms, -1 for default delay time */ + + /* fix-up list */ + int fixup_id; + const struct hda_fixup *fixup_list; + const char *fixup_name; + + /* additional init verbs */ + struct snd_array verbs; +}; + +#define dev_to_hda_codec(_dev) container_of(_dev, struct hda_codec, core.dev) +#define hda_codec_dev(_dev) (&(_dev)->core.dev) + +#define hdac_to_hda_codec(_hdac) container_of(_hdac, struct hda_codec, core) + +#define list_for_each_codec(c, bus) \ + list_for_each_entry(c, &(bus)->core.codec_list, core.list) +#define list_for_each_codec_safe(c, n, bus) \ + list_for_each_entry_safe(c, n, &(bus)->core.codec_list, core.list) + +/* snd_hda_codec_read/write optional flags */ +#define HDA_RW_NO_RESPONSE_FALLBACK (1 << 0) + +/* + * constructors + */ +__printf(3, 4) struct hda_codec * +snd_hda_codec_device_init(struct hda_bus *bus, unsigned int codec_addr, + const char *fmt, ...); +int snd_hda_codec_new(struct hda_bus *bus, struct snd_card *card, + unsigned int codec_addr, struct hda_codec **codecp); +int snd_hda_codec_device_new(struct hda_bus *bus, struct snd_card *card, + unsigned int codec_addr, struct hda_codec *codec, + bool snddev_managed); +int snd_hda_codec_configure(struct hda_codec *codec); +int snd_hda_codec_update_widgets(struct hda_codec *codec); +void snd_hda_codec_register(struct hda_codec *codec); +void snd_hda_codec_unregister(struct hda_codec *codec); +void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec); + +/* + * low level functions + */ +static inline unsigned int +snd_hda_codec_read(struct hda_codec *codec, hda_nid_t nid, + int flags, + unsigned int verb, unsigned int parm) +{ + return snd_hdac_codec_read(&codec->core, nid, flags, verb, parm); +} + +static inline int +snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int flags, + unsigned int verb, unsigned int parm) +{ + return snd_hdac_codec_write(&codec->core, nid, flags, verb, parm); +} + +/* sync after write */ +static inline int +snd_hda_codec_write_sync(struct hda_codec *codec, hda_nid_t nid, int flags, + unsigned int verb, unsigned int parm) +{ + /* use snd_hda_codec_read() for writing; + * the returned value is usually discarded + */ + return snd_hdac_codec_read(&codec->core, nid, flags, verb, parm); +} + +#define snd_hda_param_read(codec, nid, param) \ + snd_hdac_read_parm(&(codec)->core, nid, param) +#define snd_hda_get_sub_nodes(codec, nid, start_nid) \ + snd_hdac_get_sub_nodes(&(codec)->core, nid, start_nid) +int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid, + hda_nid_t *conn_list, int max_conns); +static inline int +snd_hda_get_num_conns(struct hda_codec *codec, hda_nid_t nid) +{ + return snd_hda_get_connections(codec, nid, NULL, 0); +} + +#define snd_hda_get_raw_connections(codec, nid, list, max_conns) \ + snd_hdac_get_connections(&(codec)->core, nid, list, max_conns) +#define snd_hda_get_num_raw_conns(codec, nid) \ + snd_hdac_get_connections(&(codec)->core, nid, NULL, 0) + +int snd_hda_get_conn_list(struct hda_codec *codec, hda_nid_t nid, + const hda_nid_t **listp); +int snd_hda_override_conn_list(struct hda_codec *codec, hda_nid_t nid, int nums, + const hda_nid_t *list); +int snd_hda_get_conn_index(struct hda_codec *codec, hda_nid_t mux, + hda_nid_t nid, int recursive); +unsigned int snd_hda_get_num_devices(struct hda_codec *codec, hda_nid_t nid); +unsigned int snd_hda_get_devices(struct hda_codec *codec, hda_nid_t nid, + u8 *dev_list, unsigned int max_devices); +int snd_hda_get_dev_select(struct hda_codec *codec, hda_nid_t nid); +int snd_hda_set_dev_select(struct hda_codec *codec, hda_nid_t nid, int dev_id); + +struct hda_verb { + hda_nid_t nid; + u32 verb; + u32 param; +}; + +void snd_hda_sequence_write(struct hda_codec *codec, + const struct hda_verb *seq); + +/* cached write */ +static inline int +snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid, + int flags, unsigned int verb, unsigned int parm) +{ + return snd_hdac_regmap_write(&codec->core, nid, verb, parm); +} + +/* the struct for codec->pin_configs */ +struct hda_pincfg { + hda_nid_t nid; + unsigned char ctrl; /* original pin control value */ + unsigned char target; /* target pin control value */ + unsigned int cfg; /* default configuration */ +}; + +unsigned int snd_hda_codec_get_pincfg(struct hda_codec *codec, hda_nid_t nid); +int snd_hda_codec_set_pincfg(struct hda_codec *codec, hda_nid_t nid, + unsigned int cfg); +int snd_hda_add_pincfg(struct hda_codec *codec, struct snd_array *list, + hda_nid_t nid, unsigned int cfg); /* for hwdep */ +void snd_hda_shutup_pins(struct hda_codec *codec); + +/* SPDIF controls */ +struct hda_spdif_out { + hda_nid_t nid; /* Converter nid values relate to */ + unsigned int status; /* IEC958 status bits */ + unsigned short ctls; /* SPDIF control bits */ +}; +struct hda_spdif_out *snd_hda_spdif_out_of_nid(struct hda_codec *codec, + hda_nid_t nid); +void snd_hda_spdif_ctls_unassign(struct hda_codec *codec, int idx); +void snd_hda_spdif_ctls_assign(struct hda_codec *codec, int idx, hda_nid_t nid); + +/* + * Mixer + */ +int snd_hda_codec_build_controls(struct hda_codec *codec); + +/* + * PCM + */ +int snd_hda_codec_parse_pcms(struct hda_codec *codec); +int snd_hda_codec_build_pcms(struct hda_codec *codec); + +__printf(2, 3) +struct hda_pcm *snd_hda_codec_pcm_new(struct hda_codec *codec, + const char *fmt, ...); + +void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec); + +static inline void snd_hda_codec_pcm_get(struct hda_pcm *pcm) +{ + snd_refcount_get(&pcm->codec->pcm_ref); +} +static inline void snd_hda_codec_pcm_put(struct hda_pcm *pcm) +{ + snd_refcount_put(&pcm->codec->pcm_ref); +} + +int snd_hda_codec_prepare(struct hda_codec *codec, + struct hda_pcm_stream *hinfo, + unsigned int stream, + unsigned int format, + struct snd_pcm_substream *substream); +void snd_hda_codec_cleanup(struct hda_codec *codec, + struct hda_pcm_stream *hinfo, + struct snd_pcm_substream *substream); + +void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid, + u32 stream_tag, + int channel_id, int format); +void __snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid, + int do_now); +#define snd_hda_codec_cleanup_stream(codec, nid) \ + __snd_hda_codec_cleanup_stream(codec, nid, 0) + +#define snd_hda_query_supported_pcm(codec, nid, ratesp, fmtsp, subfmtp, bpsp) \ + snd_hdac_query_supported_pcm(&(codec)->core, nid, ratesp, fmtsp, subfmtp, bpsp) +#define snd_hda_is_supported_format(codec, nid, fmt) \ + snd_hdac_is_supported_format(&(codec)->core, nid, fmt) + +extern const struct snd_pcm_chmap_elem snd_pcm_2_1_chmaps[]; + +int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, + struct hda_pcm *cpcm); + +/* + * Misc + */ +void snd_hda_get_codec_name(struct hda_codec *codec, char *name, int namelen); +void snd_hda_codec_set_power_to_all(struct hda_codec *codec, hda_nid_t fg, + unsigned int power_state); + +int snd_hda_lock_devices(struct hda_bus *bus); +void snd_hda_unlock_devices(struct hda_bus *bus); +void snd_hda_bus_reset(struct hda_bus *bus); +void snd_hda_bus_reset_codecs(struct hda_bus *bus); + +void snd_hda_codec_set_gpio(struct hda_codec *codec, unsigned int mask, + unsigned int dir, unsigned int data, + unsigned int delay); + +int snd_hda_codec_set_name(struct hda_codec *codec, const char *name); + +/* + * power management + */ +extern const struct dev_pm_ops hda_codec_driver_pm; + +static inline +int hda_call_check_power_status(struct hda_codec *codec, hda_nid_t nid) +{ + struct hda_codec_driver *driver = hda_codec_to_driver(codec); + + if (driver->ops && driver->ops->check_power_status) + return driver->ops->check_power_status(codec, nid); + return 0; +} + +/* + * power saving + */ +#define snd_hda_power_up(codec) snd_hdac_power_up(&(codec)->core) +#define snd_hda_power_up_pm(codec) snd_hdac_power_up_pm(&(codec)->core) +#define snd_hda_power_down(codec) snd_hdac_power_down(&(codec)->core) +#define snd_hda_power_down_pm(codec) snd_hdac_power_down_pm(&(codec)->core) +void snd_hda_codec_set_power_save(struct hda_codec *codec, int delay); +void snd_hda_set_power_save(struct hda_bus *bus, int delay); +void snd_hda_update_power_acct(struct hda_codec *codec); + +static inline bool hda_codec_need_resume(struct hda_codec *codec) +{ + return !codec->relaxed_resume && codec->jacktbl.used; +} + +/* + * PM with auto-cleanup: call like CLASS(snd_hda_power, pm)(codec) + * If the error handling is needed, refer pm.err. + */ +struct __hda_power_obj { + struct hda_codec *codec; + int err; +}; + +static inline struct __hda_power_obj __snd_hda_power_up(struct hda_codec *codec) +{ + struct __hda_power_obj T = { .codec = codec }; + T.err = snd_hda_power_up(codec); + return T; +} + +static inline struct __hda_power_obj __snd_hda_power_up_pm(struct hda_codec *codec) +{ + struct __hda_power_obj T = { .codec = codec }; + T.err = snd_hda_power_up_pm(codec); + return T; +} + +DEFINE_CLASS(snd_hda_power, struct __hda_power_obj, + snd_hda_power_down((_T).codec), __snd_hda_power_up(codec), + struct hda_codec *codec) +DEFINE_CLASS(snd_hda_power_pm, struct __hda_power_obj, + snd_hda_power_down_pm((_T).codec), __snd_hda_power_up_pm(codec), + struct hda_codec *codec) + +#ifdef CONFIG_SND_HDA_PATCH_LOADER +/* + * patch firmware + */ +int snd_hda_load_patch(struct hda_bus *bus, size_t size, const void *buf); +#endif + +#ifdef CONFIG_SND_HDA_DSP_LOADER +int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, + unsigned int size, + struct snd_dma_buffer *bufp); +void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start); +void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, + struct snd_dma_buffer *dmab); +#else +static inline int +snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, + unsigned int size, + struct snd_dma_buffer *bufp) +{ + return -ENOSYS; +} +static inline void +snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) {} +static inline void +snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, + struct snd_dma_buffer *dmab) {} +#endif + +#endif /* __SOUND_HDA_CODEC_H */ diff --git a/include/sound/hda_component.h b/include/sound/hda_component.h new file mode 100644 index 000000000..d4804c72d --- /dev/null +++ b/include/sound/hda_component.h @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +// HD-Audio helpers to sync with DRM driver + +#ifndef __SOUND_HDA_COMPONENT_H +#define __SOUND_HDA_COMPONENT_H + +#include +#include + +/* virtual idx for controller */ +#define HDA_CODEC_IDX_CONTROLLER HDA_MAX_CODECS + +#ifdef CONFIG_SND_HDA_COMPONENT +int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable); +void snd_hdac_display_power(struct hdac_bus *bus, unsigned int idx, + bool enable); +int snd_hdac_sync_audio_rate(struct hdac_device *codec, hda_nid_t nid, + int dev_id, int rate); +int snd_hdac_acomp_get_eld(struct hdac_device *codec, hda_nid_t nid, int dev_id, + bool *audio_enabled, char *buffer, int max_bytes); +int snd_hdac_acomp_init(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *aops, + int (*match_master)(struct device *, int, void *), + size_t extra_size); +int snd_hdac_acomp_exit(struct hdac_bus *bus); +int snd_hdac_acomp_register_notifier(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *ops); +#else +static inline int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable) +{ + return 0; +} +static inline void snd_hdac_display_power(struct hdac_bus *bus, + unsigned int idx, bool enable) +{ +} +static inline int snd_hdac_sync_audio_rate(struct hdac_device *codec, + hda_nid_t nid, int dev_id, int rate) +{ + return 0; +} +static inline int snd_hdac_acomp_get_eld(struct hdac_device *codec, hda_nid_t nid, + int dev_id, bool *audio_enabled, + char *buffer, int max_bytes) +{ + return -ENODEV; +} +static inline int snd_hdac_acomp_init(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *aops, + int (*match_master)(struct device *, + int, void *), + size_t extra_size) +{ + return -ENODEV; +} +static inline int snd_hdac_acomp_exit(struct hdac_bus *bus) +{ + return 0; +} +static inline int snd_hdac_acomp_register_notifier(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *ops) +{ + return -ENODEV; +} +#endif + +#endif /* __SOUND_HDA_COMPONENT_H */ diff --git a/include/sound/hda_hwdep.h b/include/sound/hda_hwdep.h new file mode 100644 index 000000000..f9b5b05ba --- /dev/null +++ b/include/sound/hda_hwdep.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * HWDEP Interface for HD-audio codec + * + * Copyright (c) 2007 Takashi Iwai + */ + +#ifndef __SOUND_HDA_HWDEP_H +#define __SOUND_HDA_HWDEP_H + +#define HDA_HWDEP_VERSION ((1 << 16) | (0 << 8) | (0 << 0)) /* 1.0.0 */ + +/* verb */ +#define HDA_REG_NID_SHIFT 24 +#define HDA_REG_VERB_SHIFT 8 +#define HDA_REG_VAL_SHIFT 0 +#define HDA_VERB(nid,verb,param) ((nid)<<24 | (verb)<<8 | (param)) + +struct hda_verb_ioctl { + u32 verb; /* HDA_VERB() */ + u32 res; /* response */ +}; + +/* + * ioctls + */ +#define HDA_IOCTL_PVERSION _IOR('H', 0x10, int) +#define HDA_IOCTL_VERB_WRITE _IOWR('H', 0x11, struct hda_verb_ioctl) +#define HDA_IOCTL_GET_WCAP _IOWR('H', 0x12, struct hda_verb_ioctl) + +#endif diff --git a/include/sound/hda_i915.h b/include/sound/hda_i915.h new file mode 100644 index 000000000..6b79614a8 --- /dev/null +++ b/include/sound/hda_i915.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-Audio helpers to sync with i915 driver + */ +#ifndef __SOUND_HDA_I915_H +#define __SOUND_HDA_I915_H + +#include "hda_component.h" + +#ifdef CONFIG_SND_HDA_I915 +void snd_hdac_i915_set_bclk(struct hdac_bus *bus); +int snd_hdac_i915_init(struct hdac_bus *bus); +#else +static inline void snd_hdac_i915_set_bclk(struct hdac_bus *bus) +{ +} +static inline int snd_hdac_i915_init(struct hdac_bus *bus) +{ + return -ENODEV; +} +#endif +static inline int snd_hdac_i915_exit(struct hdac_bus *bus) +{ + return snd_hdac_acomp_exit(bus); +} + +#endif /* __SOUND_HDA_I915_H */ diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h new file mode 100644 index 000000000..db1cc0b89 --- /dev/null +++ b/include/sound/hda_register.h @@ -0,0 +1,368 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio controller (Azalia) registers and helpers + * + * For traditional reasons, we still use azx_ prefix here + */ + +#ifndef __SOUND_HDA_REGISTER_H +#define __SOUND_HDA_REGISTER_H + +#include +#include + +#define AZX_REG_GCAP 0x00 +#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */ +#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */ +#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */ +#define AZX_GCAP_ISS (15 << 8) /* # of input streams */ +#define AZX_GCAP_OSS (15 << 12) /* # of output streams */ +#define AZX_REG_VMIN 0x02 +#define AZX_REG_VMAJ 0x03 +#define AZX_REG_OUTPAY 0x04 +#define AZX_REG_INPAY 0x06 +#define AZX_REG_GCTL 0x08 +#define AZX_GCTL_RESET (1 << 0) /* controller reset */ +#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */ +#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ +#define AZX_REG_WAKEEN 0x0c +#define AZX_REG_STATESTS 0x0e +#define AZX_REG_GSTS 0x10 +#define AZX_GSTS_FSTS (1 << 1) /* flush status */ +#define AZX_REG_GCAP2 0x12 +#define AZX_REG_LLCH 0x14 +#define AZX_REG_OUTSTRMPAY 0x18 +#define AZX_REG_INSTRMPAY 0x1A +#define AZX_REG_INTCTL 0x20 +#define AZX_REG_INTSTS 0x24 +#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ +#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ +#define AZX_REG_SSYNC 0x38 +#define AZX_REG_CORBLBASE 0x40 +#define AZX_REG_CORBUBASE 0x44 +#define AZX_REG_CORBWP 0x48 +#define AZX_REG_CORBRP 0x4a +#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */ +#define AZX_REG_CORBCTL 0x4c +#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */ +#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ +#define AZX_REG_CORBSTS 0x4d +#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */ +#define AZX_REG_CORBSIZE 0x4e + +#define AZX_REG_RIRBLBASE 0x50 +#define AZX_REG_RIRBUBASE 0x54 +#define AZX_REG_RIRBWP 0x58 +#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */ +#define AZX_REG_RINTCNT 0x5a +#define AZX_REG_RIRBCTL 0x5c +#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ +#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */ +#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ +#define AZX_REG_RIRBSTS 0x5d +#define AZX_RBSTS_IRQ (1 << 0) /* response irq */ +#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */ +#define AZX_REG_RIRBSIZE 0x5e + +#define AZX_REG_IC 0x60 +#define AZX_REG_IR 0x64 +#define AZX_REG_IRS 0x68 +#define AZX_IRS_VALID (1<<1) +#define AZX_IRS_BUSY (1<<0) + +#define AZX_REG_DPLBASE 0x70 +#define AZX_REG_DPUBASE 0x74 +#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */ + +/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ +enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; + +/* stream register offsets from stream base */ +#define AZX_REG_SD_CTL 0x00 +#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ +#define AZX_REG_SD_STS 0x03 +#define AZX_REG_SD_LPIB 0x04 +#define AZX_REG_SD_CBL 0x08 +#define AZX_REG_SD_LVI 0x0c +#define AZX_REG_SD_FIFOW 0x0e +#define AZX_REG_SD_FIFOSIZE 0x10 +#define AZX_REG_SD_FORMAT 0x12 +#define AZX_REG_SD_FIFOL 0x14 +#define AZX_REG_SD_BDLPL 0x18 +#define AZX_REG_SD_BDLPU 0x1c + +#define AZX_SD_FIFOSIZE_MASK GENMASK(15, 0) + +/* GTS registers */ +#define AZX_REG_LLCH 0x14 + +#define AZX_REG_GTS_BASE 0x520 + +#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00) +#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04) +#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08) +#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C) +#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14) +#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18) +#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C) + +/* Haswell/Broadwell display HD-A controller Extended Mode registers */ +#define AZX_REG_HSW_EM4 0x100c +#define AZX_REG_HSW_EM5 0x1010 + +/* Skylake/Broxton vendor-specific registers */ +#define AZX_REG_VS_EM1 0x1000 +#define AZX_REG_VS_INRC 0x1004 +#define AZX_REG_VS_OUTRC 0x1008 +#define AZX_REG_VS_FIFOTRK 0x100C +#define AZX_REG_VS_FIFOTRK2 0x1010 +#define AZX_REG_VS_EM2 0x1030 +#define AZX_REG_VS_EM3L 0x1038 +#define AZX_REG_VS_EM3U 0x103C +#define AZX_REG_VS_EM4L 0x1040 +#define AZX_REG_VS_EM4U 0x1044 +#define AZX_REG_VS_LTRP 0x1048 +#define AZX_REG_VS_D0I3C 0x104A +#define AZX_REG_VS_PCE 0x104B +#define AZX_REG_VS_L2MAGC 0x1050 +#define AZX_REG_VS_L2LAHPT 0x1054 +#define AZX_REG_VS_SDXDPIB_XBASE 0x1084 +#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 +#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 +#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 + +#define AZX_REG_VS_LTRP_GB_MASK GENMASK(6, 0) + +/* PCI space */ +#define AZX_PCIREG_TCSEL 0x44 + +/* + * other constants + */ + +/* max number of fragments - we may use more if allocating more pages for BDL */ +#define BDL_SIZE 4096 +#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) +#define AZX_MAX_FRAG 32 +/* + * max buffer size - artificial 4MB limit per stream to avoid big allocations + * In theory it can be really big, but as it is per stream on systems with many streams memory could + * be quickly saturated if userspace requests maximum buffer size for each of them. + */ +#define AZX_MAX_BUF_SIZE (4*1024*1024) + +/* RIRB int mask: overrun[2], response[0] */ +#define RIRB_INT_RESPONSE 0x01 +#define RIRB_INT_OVERRUN 0x04 +#define RIRB_INT_MASK 0x05 + +/* STATESTS int mask: S3,SD2,SD1,SD0 */ +#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1) + +/* SD_CTL bits */ +#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ +#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ +#define SD_CTL_STRIPE (3 << 16) /* stripe control */ +#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ +#define SD_CTL_DIR (1 << 19) /* bi-directional stream */ +#define SD_CTL_STREAM_TAG_MASK (0xf << 20) +#define SD_CTL_STREAM_TAG_SHIFT 20 + +/* SD_CTL and SD_STS */ +#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ +#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ +#define SD_INT_COMPLETE 0x04 /* completion interrupt */ +#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ + SD_INT_COMPLETE) +#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */ + +/* SD_STS */ +#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ + +/* INTCTL and INTSTS */ +#define AZX_INT_ALL_STREAM 0x3fffffff /* all stream interrupts */ +#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ +#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ + +/* below are so far hardcoded - should read registers in future */ +#define AZX_MAX_CORB_ENTRIES 256 +#define AZX_MAX_RIRB_ENTRIES 256 + +/* Capability header Structure */ +#define AZX_REG_CAP_HDR 0x0 +#define AZX_CAP_HDR_VER_OFF 28 +#define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF) +#define AZX_CAP_HDR_ID_OFF 16 +#define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF) +#define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF + +/* registers of Software Position Based FIFO Capability Structure */ +#define AZX_SPB_CAP_ID 0x4 +#define AZX_REG_SPB_BASE_ADDR 0x700 +#define AZX_REG_SPB_SPBFCH 0x00 +#define AZX_REG_SPB_SPBFCCTL 0x04 +/* Base used to calculate the iterating register offset */ +#define AZX_SPB_BASE 0x08 +/* Interval used to calculate the iterating register offset */ +#define AZX_SPB_INTERVAL 0x08 +/* SPIB base */ +#define AZX_SPB_SPIB 0x00 +/* SPIB MAXFIFO base*/ +#define AZX_SPB_MAXFIFO 0x04 + +/* registers of Global Time Synchronization Capability Structure */ +#define AZX_GTS_CAP_ID 0x1 +#define AZX_REG_GTS_GTSCH 0x00 +#define AZX_REG_GTS_GTSCD 0x04 +#define AZX_REG_GTS_GTSCTLAC 0x0C +#define AZX_GTS_BASE 0x20 +#define AZX_GTS_INTERVAL 0x20 + +/* registers for Processing Pipe Capability Structure */ +#define AZX_PP_CAP_ID 0x3 +#define AZX_REG_PP_PPCH 0x10 +#define AZX_REG_PP_PPCTL 0x04 +#define AZX_PPCTL_PIE (1<<31) +#define AZX_PPCTL_GPROCEN (1<<30) +/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */ +#define AZX_PPCTL_PROCEN(_X_) (1<<(_X_)) + +#define AZX_REG_PP_PPSTS 0x08 + +#define AZX_PPHC_BASE 0x10 +#define AZX_PPHC_INTERVAL 0x10 + +#define AZX_REG_PPHCLLPL 0x0 +#define AZX_REG_PPHCLLPU 0x4 +#define AZX_REG_PPHCLDPL 0x8 +#define AZX_REG_PPHCLDPU 0xC + +#define AZX_PPLC_BASE 0x10 +#define AZX_PPLC_MULTI 0x10 +#define AZX_PPLC_INTERVAL 0x10 + +#define AZX_REG_PPLCCTL 0x0 +#define AZX_PPLCCTL_STRM_BITS 4 +#define AZX_PPLCCTL_STRM_SHIFT 20 +#define AZX_REG_MASK(bit_num, offset) \ + (((1 << (bit_num)) - 1) << (offset)) +#define AZX_PPLCCTL_STRM_MASK \ + AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT) +#define AZX_PPLCCTL_RUN (1<<1) +#define AZX_PPLCCTL_STRST (1<<0) + +#define AZX_REG_PPLCFMT 0x4 +#define AZX_REG_PPLCLLPL 0x8 +#define AZX_REG_PPLCLLPU 0xC + +/* registers for Multiple Links Capability Structure */ +#define AZX_ML_CAP_ID 0x2 +#define AZX_REG_ML_MLCH 0x00 +#define AZX_REG_ML_MLCD 0x04 +#define AZX_ML_BASE 0x40 +#define AZX_ML_INTERVAL 0x40 + +/* HDaudio registers valid for HDaudio and HDaudio extended links */ +#define AZX_REG_ML_LCAP 0x00 + +#define AZX_ML_HDA_LCAP_ALT BIT(28) +#define AZX_ML_HDA_LCAP_ALT_HDA 0x0 +#define AZX_ML_HDA_LCAP_ALT_HDA_EXT 0x1 + +#define AZX_ML_HDA_LCAP_INTC BIT(27) /* only used if ALT == 1 */ +#define AZX_ML_HDA_LCAP_OFLS BIT(26) /* only used if ALT == 1 */ +#define AZX_ML_HDA_LCAP_LSS BIT(23) /* only used if ALT == 1 */ +#define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */ + +#define AZX_REG_ML_LCTL 0x04 +#define AZX_ML_LCTL_INTSTS BIT(31) /* only used if ALT == 1 */ +#define AZX_ML_LCTL_CPA BIT(23) +#define AZX_ML_LCTL_CPA_SHIFT 23 +#define AZX_ML_LCTL_SPA BIT(16) +#define AZX_ML_LCTL_SPA_SHIFT 16 +#define AZX_ML_LCTL_INTEN BIT(5) /* only used if ALT == 1 */ +#define AZX_ML_LCTL_OFLEN BIT(4) /* only used if ALT == 1 */ +#define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */ + +#define AZX_REG_ML_LOSIDV 0x08 + +/* bit0 is reserved, with BIT(1) mapping to stream1 */ +#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE + +#define AZX_REG_ML_LSDIID 0x0C +#define AZX_REG_ML_LSDIID_OFFSET(x) (0x0C + (x) * 0x02) /* only used if ALT == 1 */ + +/* HDaudio registers only valid if LCAP.ALT == 0 */ +#define AZX_REG_ML_LPSOO 0x10 +#define AZX_REG_ML_LPSIO 0x12 +#define AZX_REG_ML_LWALFC 0x18 +#define AZX_REG_ML_LOUTPAY 0x20 +#define AZX_REG_ML_LINPAY 0x30 + +/* HDaudio Extended link registers only valid if LCAP.ALT == 1 */ +#define AZX_REG_ML_LSYNC 0x1C + +#define AZX_REG_ML_LSYNC_CMDSYNC BIT(24) +#define AZX_REG_ML_LSYNC_CMDSYNC_SHIFT 24 +#define AZX_REG_ML_LSYNC_SYNCGO BIT(23) +#define AZX_REG_ML_LSYNC_SYNCPU BIT(20) +#define AZX_REG_ML_LSYNC_SYNCPRD GENMASK(19, 0) + +#define AZX_REG_ML_LEPTR 0x20 + +#define AZX_REG_ML_LEPTR_ID GENMASK(31, 24) +#define AZX_REG_ML_LEPTR_ID_SHIFT 24 +#define AZX_REG_ML_LEPTR_ID_SDW 0x00 +#define AZX_REG_ML_LEPTR_ID_INTEL_SSP 0xC0 +#define AZX_REG_ML_LEPTR_ID_INTEL_DMIC 0xC1 +#define AZX_REG_ML_LEPTR_ID_INTEL_UAOL 0xC2 +#define AZX_REG_ML_LEPTR_VER GENMASK(23, 20) +#define AZX_REG_ML_LEPTR_PTR GENMASK(19, 0) + +/* registers for DMA Resume Capability Structure */ +#define AZX_DRSM_CAP_ID 0x5 +#define AZX_REG_DRSM_CTL 0x4 +/* Base used to calculate the iterating register offset */ +#define AZX_DRSM_BASE 0x08 +/* Interval used to calculate the iterating register offset */ +#define AZX_DRSM_INTERVAL 0x08 + +/* Global time synchronization registers */ +#define GTSCC_TSCCD_MASK 0x80000000 +#define GTSCC_TSCCD_SHIFT BIT(31) +#define GTSCC_TSCCI_MASK 0x20 +#define GTSCC_CDMAS_DMA_DIR_SHIFT 4 + +#define WALFCC_CIF_MASK 0x1FF +#define WALFCC_FN_SHIFT 9 +#define HDA_CLK_CYCLES_PER_FRAME 512 + +/* + * An error occurs near frame "rollover". The clocks in frame value indicates + * whether this error may have occurred. Here we use the value of 10. Please + * see the errata for the right number [<10] + */ +#define HDA_MAX_CYCLE_VALUE 499 +#define HDA_MAX_CYCLE_OFFSET 10 +#define HDA_MAX_CYCLE_READ_RETRY 10 + +#define TSCCU_CCU_SHIFT 32 +#define LLPC_CCU_SHIFT 32 + + +/* + * helpers to read the stream position + */ +static inline unsigned int +snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream) +{ + return snd_hdac_stream_readl(stream, SD_LPIB); +} + +static inline unsigned int +snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream) +{ + return le32_to_cpu(*stream->posbuf); +} + +#endif /* __SOUND_HDA_REGISTER_H */ diff --git a/include/sound/hda_regmap.h b/include/sound/hda_regmap.h new file mode 100644 index 000000000..e06e4847e --- /dev/null +++ b/include/sound/hda_regmap.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio regmap helpers + */ + +#ifndef __SOUND_HDA_REGMAP_H +#define __SOUND_HDA_REGMAP_H + +#include +#include +#include + +#define AC_AMP_FAKE_MUTE 0x10 /* fake mute bit set to amp verbs */ + +int snd_hdac_regmap_init(struct hdac_device *codec); +void snd_hdac_regmap_exit(struct hdac_device *codec); +int snd_hdac_regmap_add_vendor_verb(struct hdac_device *codec, + unsigned int verb); +int snd_hdac_regmap_read_raw(struct hdac_device *codec, unsigned int reg, + unsigned int *val); +int snd_hdac_regmap_read_raw_uncached(struct hdac_device *codec, + unsigned int reg, unsigned int *val); +int snd_hdac_regmap_write_raw(struct hdac_device *codec, unsigned int reg, + unsigned int val); +int snd_hdac_regmap_update_raw(struct hdac_device *codec, unsigned int reg, + unsigned int mask, unsigned int val); +int snd_hdac_regmap_update_raw_once(struct hdac_device *codec, unsigned int reg, + unsigned int mask, unsigned int val); +void snd_hdac_regmap_sync(struct hdac_device *codec); + +/** + * snd_hdac_regmap_encode_verb - encode the verb to a pseudo register + * @nid: widget NID + * @verb: codec verb + * + * Returns an encoded pseudo register. + */ +#define snd_hdac_regmap_encode_verb(nid, verb) \ + (((verb) << 8) | 0x80000 | ((unsigned int)(nid) << 20)) + +/** + * snd_hdac_regmap_encode_amp - encode the AMP verb to a pseudo register + * @nid: widget NID + * @ch: channel (left = 0, right = 1) + * @dir: direction (#HDA_INPUT, #HDA_OUTPUT) + * @idx: input index value + * + * Returns an encoded pseudo register. + */ +#define snd_hdac_regmap_encode_amp(nid, ch, dir, idx) \ + (snd_hdac_regmap_encode_verb(nid, AC_VERB_GET_AMP_GAIN_MUTE) | \ + ((ch) ? AC_AMP_GET_RIGHT : AC_AMP_GET_LEFT) | \ + ((dir) == HDA_OUTPUT ? AC_AMP_GET_OUTPUT : AC_AMP_GET_INPUT) | \ + (idx)) + +/** + * snd_hdac_regmap_encode_amp_stereo - encode a pseudo register for stereo AMPs + * @nid: widget NID + * @dir: direction (#HDA_INPUT, #HDA_OUTPUT) + * @idx: input index value + * + * Returns an encoded pseudo register. + */ +#define snd_hdac_regmap_encode_amp_stereo(nid, dir, idx) \ + (snd_hdac_regmap_encode_verb(nid, AC_VERB_GET_AMP_GAIN_MUTE) | \ + AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT | /* both bits set! */ \ + ((dir) == HDA_OUTPUT ? AC_AMP_GET_OUTPUT : AC_AMP_GET_INPUT) | \ + (idx)) + +/** + * snd_hdac_regmap_write - Write a verb with caching + * @codec: HD-audio codec base device + * @nid: codec NID + * @verb: verb to write + * @val: value to write + * + * For writing an amp value, use snd_hdac_regmap_update_amp(). + * + * Returns: %0 if successful or a negative error code. + */ +static inline int +snd_hdac_regmap_write(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_verb(nid, verb); + + return snd_hdac_regmap_write_raw(codec, cmd, val); +} + +/** + * snd_hdac_regmap_update - Update a verb value with caching + * @codec: HD-audio codec + * @nid: codec NID + * @verb: verb to update + * @mask: bit mask to update + * @val: value to update + * + * For updating an amp value, use snd_hdac_regmap_update_amp(). + * + * Returns: %0 if successful or a negative error code. + */ +static inline int +snd_hdac_regmap_update(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int mask, + unsigned int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_verb(nid, verb); + + return snd_hdac_regmap_update_raw(codec, cmd, mask, val); +} + +/** + * snd_hdac_regmap_read - Read a verb with caching + * @codec: HD-audio codec + * @nid: codec NID + * @verb: verb to read + * @val: pointer to store the value + * + * For reading an amp value, use snd_hda_regmap_get_amp(). + * + * Returns: %0 if successful or a negative error code. + */ +static inline int +snd_hdac_regmap_read(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int *val) +{ + unsigned int cmd = snd_hdac_regmap_encode_verb(nid, verb); + + return snd_hdac_regmap_read_raw(codec, cmd, val); +} + +/** + * snd_hdac_regmap_get_amp - Read AMP value + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @ch: channel (left=0 or right=1) + * @dir: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) + * + * Read AMP value. The volume is between 0 to 0x7f, 0x80 = mute bit. + * + * Returns: the value or a negative error. + */ +static inline int +snd_hdac_regmap_get_amp(struct hdac_device *codec, hda_nid_t nid, + int ch, int dir, int idx) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp(nid, ch, dir, idx); + int err, val; + + err = snd_hdac_regmap_read_raw(codec, cmd, &val); + return err < 0 ? err : val; +} + +/** + * snd_hdac_regmap_update_amp - update the AMP value + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @ch: channel (left=0 or right=1) + * @dir: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) + * @mask: bit mask to set + * @val: the bits value to set + * + * Update the AMP value with a bit mask. + * + * Returns: 0 if the value is unchanged, 1 if changed, or a negative error. + */ +static inline int +snd_hdac_regmap_update_amp(struct hdac_device *codec, hda_nid_t nid, + int ch, int dir, int idx, int mask, int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp(nid, ch, dir, idx); + + return snd_hdac_regmap_update_raw(codec, cmd, mask, val); +} + +/** + * snd_hdac_regmap_get_amp_stereo - Read stereo AMP values + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @dir: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) + * + * Read stereo AMP values. The lower byte is left, the upper byte is right. + * + * Returns: the value or a negative error. + */ +static inline int +snd_hdac_regmap_get_amp_stereo(struct hdac_device *codec, hda_nid_t nid, + int dir, int idx) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp_stereo(nid, dir, idx); + int err, val; + + err = snd_hdac_regmap_read_raw(codec, cmd, &val); + return err < 0 ? err : val; +} + +/** + * snd_hdac_regmap_update_amp_stereo - update the stereo AMP value + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @dir: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) + * @mask: bit mask to set + * @val: the bits value to set + * + * Update the stereo AMP value with a bit mask. + * The lower byte is left, the upper byte is right. + * + * Returns: 0 if the value is unchanged, 1 if changed, or a negative error. + */ +static inline int +snd_hdac_regmap_update_amp_stereo(struct hdac_device *codec, hda_nid_t nid, + int dir, int idx, int mask, int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp_stereo(nid, dir, idx); + + return snd_hdac_regmap_update_raw(codec, cmd, mask, val); +} + +/** + * snd_hdac_regmap_sync_node - sync the widget node attributes + * @codec: HD-audio codec + * @nid: NID to sync + */ +static inline void +snd_hdac_regmap_sync_node(struct hdac_device *codec, hda_nid_t nid) +{ + regcache_mark_dirty(codec->regmap); + regcache_sync_region(codec->regmap, nid << 20, ((nid + 1) << 20) - 1); +} + +#endif /* __SOUND_HDA_REGMAP_H */ diff --git a/include/sound/hda_verbs.h b/include/sound/hda_verbs.h new file mode 100644 index 000000000..606695440 --- /dev/null +++ b/include/sound/hda_verbs.h @@ -0,0 +1,568 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio codec verbs + */ + +#ifndef __SOUND_HDA_VERBS_H +#define __SOUND_HDA_VERBS_H + +/* + * nodes + */ +#define AC_NODE_ROOT 0x00 + +/* + * function group types + */ +enum { + AC_GRP_AUDIO_FUNCTION = 0x01, + AC_GRP_MODEM_FUNCTION = 0x02, +}; + +/* + * widget types + */ +enum { + AC_WID_AUD_OUT, /* Audio Out */ + AC_WID_AUD_IN, /* Audio In */ + AC_WID_AUD_MIX, /* Audio Mixer */ + AC_WID_AUD_SEL, /* Audio Selector */ + AC_WID_PIN, /* Pin Complex */ + AC_WID_POWER, /* Power */ + AC_WID_VOL_KNB, /* Volume Knob */ + AC_WID_BEEP, /* Beep Generator */ + AC_WID_VENDOR = 0x0f /* Vendor specific */ +}; + +/* + * GET verbs + */ +#define AC_VERB_GET_STREAM_FORMAT 0x0a00 +#define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00 +#define AC_VERB_GET_PROC_COEF 0x0c00 +#define AC_VERB_GET_COEF_INDEX 0x0d00 +#define AC_VERB_PARAMETERS 0x0f00 +#define AC_VERB_GET_CONNECT_SEL 0x0f01 +#define AC_VERB_GET_CONNECT_LIST 0x0f02 +#define AC_VERB_GET_PROC_STATE 0x0f03 +#define AC_VERB_GET_SDI_SELECT 0x0f04 +#define AC_VERB_GET_POWER_STATE 0x0f05 +#define AC_VERB_GET_CONV 0x0f06 +#define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07 +#define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08 +#define AC_VERB_GET_PIN_SENSE 0x0f09 +#define AC_VERB_GET_BEEP_CONTROL 0x0f0a +#define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c +#define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d +#define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */ +#define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f +/* f10-f1a: GPI/GPO/GPIO */ +#define AC_VERB_GET_GPI_DATA 0x0f10 +#define AC_VERB_GET_GPI_WAKE_MASK 0x0f11 +#define AC_VERB_GET_GPI_UNSOLICITED_RSP_MASK 0x0f12 +#define AC_VERB_GET_GPI_STICKY_MASK 0x0f13 +#define AC_VERB_GET_GPO_DATA 0x0f14 +#define AC_VERB_GET_GPIO_DATA 0x0f15 +#define AC_VERB_GET_GPIO_MASK 0x0f16 +#define AC_VERB_GET_GPIO_DIRECTION 0x0f17 +#define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18 +#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19 +#define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a +#define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c +/* f20: AFG/MFG */ +#define AC_VERB_GET_SUBSYSTEM_ID 0x0f20 +#define AC_VERB_GET_STRIPE_CONTROL 0x0f24 +#define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d +#define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e +#define AC_VERB_GET_HDMI_ELDD 0x0f2f +#define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30 +#define AC_VERB_GET_HDMI_DIP_DATA 0x0f31 +#define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32 +#define AC_VERB_GET_HDMI_CP_CTRL 0x0f33 +#define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34 +#define AC_VERB_GET_DEVICE_SEL 0xf35 +#define AC_VERB_GET_DEVICE_LIST 0xf36 + +/* + * SET verbs + */ +#define AC_VERB_SET_STREAM_FORMAT 0x200 +#define AC_VERB_SET_AMP_GAIN_MUTE 0x300 +#define AC_VERB_SET_PROC_COEF 0x400 +#define AC_VERB_SET_COEF_INDEX 0x500 +#define AC_VERB_SET_CONNECT_SEL 0x701 +#define AC_VERB_SET_PROC_STATE 0x703 +#define AC_VERB_SET_SDI_SELECT 0x704 +#define AC_VERB_SET_POWER_STATE 0x705 +#define AC_VERB_SET_CHANNEL_STREAMID 0x706 +#define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707 +#define AC_VERB_SET_UNSOLICITED_ENABLE 0x708 +#define AC_VERB_SET_PIN_SENSE 0x709 +#define AC_VERB_SET_BEEP_CONTROL 0x70a +#define AC_VERB_SET_EAPD_BTLENABLE 0x70c +#define AC_VERB_SET_DIGI_CONVERT_1 0x70d +#define AC_VERB_SET_DIGI_CONVERT_2 0x70e +#define AC_VERB_SET_DIGI_CONVERT_3 0x73e +#define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f +#define AC_VERB_SET_GPI_DATA 0x710 +#define AC_VERB_SET_GPI_WAKE_MASK 0x711 +#define AC_VERB_SET_SPI_UNSOLICITED_RSP_MASK 0x712 +#define AC_VERB_SET_GPI_STICKY_MASK 0x713 +#define AC_VERB_SET_GPO_DATA 0x714 +#define AC_VERB_SET_GPIO_DATA 0x715 +#define AC_VERB_SET_GPIO_MASK 0x716 +#define AC_VERB_SET_GPIO_DIRECTION 0x717 +#define AC_VERB_SET_GPIO_WAKE_MASK 0x718 +#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719 +#define AC_VERB_SET_GPIO_STICKY_MASK 0x71a +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f +#define AC_VERB_SET_EAPD 0x788 +#define AC_VERB_SET_CODEC_RESET 0x7ff +#define AC_VERB_SET_STRIPE_CONTROL 0x724 +#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d +#define AC_VERB_SET_HDMI_DIP_INDEX 0x730 +#define AC_VERB_SET_HDMI_DIP_DATA 0x731 +#define AC_VERB_SET_HDMI_DIP_XMIT 0x732 +#define AC_VERB_SET_HDMI_CP_CTRL 0x733 +#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734 +#define AC_VERB_SET_DEVICE_SEL 0x735 + +/* + * Parameter IDs + */ +#define AC_PAR_VENDOR_ID 0x00 +#define AC_PAR_SUBSYSTEM_ID 0x01 +#define AC_PAR_REV_ID 0x02 +#define AC_PAR_NODE_COUNT 0x04 +#define AC_PAR_FUNCTION_TYPE 0x05 +#define AC_PAR_AUDIO_FG_CAP 0x08 +#define AC_PAR_AUDIO_WIDGET_CAP 0x09 +#define AC_PAR_PCM 0x0a +#define AC_PAR_STREAM 0x0b +#define AC_PAR_PIN_CAP 0x0c +#define AC_PAR_AMP_IN_CAP 0x0d +#define AC_PAR_CONNLIST_LEN 0x0e +#define AC_PAR_POWER_STATE 0x0f +#define AC_PAR_PROC_CAP 0x10 +#define AC_PAR_GPIO_CAP 0x11 +#define AC_PAR_AMP_OUT_CAP 0x12 +#define AC_PAR_VOL_KNB_CAP 0x13 +#define AC_PAR_DEVLIST_LEN 0x15 +#define AC_PAR_HDMI_LPCM_CAP 0x20 + +/* + * AC_VERB_PARAMETERS results (32bit) + */ + +/* Function Group Type */ +#define AC_FGT_TYPE (0xff<<0) +#define AC_FGT_TYPE_SHIFT 0 +#define AC_FGT_UNSOL_CAP (1<<8) + +/* Audio Function Group Capabilities */ +#define AC_AFG_OUT_DELAY (0xf<<0) +#define AC_AFG_IN_DELAY (0xf<<8) +#define AC_AFG_BEEP_GEN (1<<16) + +/* Audio Widget Capabilities */ +#define AC_WCAP_STEREO (1<<0) /* stereo I/O */ +#define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */ +#define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */ +#define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */ +#define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */ +#define AC_WCAP_STRIPE (1<<5) /* stripe */ +#define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */ +#define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */ +#define AC_WCAP_CONN_LIST (1<<8) /* connection list */ +#define AC_WCAP_DIGITAL (1<<9) /* digital I/O */ +#define AC_WCAP_POWER (1<<10) /* power control */ +#define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */ +#define AC_WCAP_CP_CAPS (1<<12) /* content protection */ +#define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */ +#define AC_WCAP_DELAY (0xf<<16) +#define AC_WCAP_DELAY_SHIFT 16 +#define AC_WCAP_TYPE (0xf<<20) +#define AC_WCAP_TYPE_SHIFT 20 + +/* supported PCM rates and bits */ +#define AC_SUPPCM_RATES (0xfff << 0) +#define AC_SUPPCM_BITS_8 (1<<16) +#define AC_SUPPCM_BITS_16 (1<<17) +#define AC_SUPPCM_BITS_20 (1<<18) +#define AC_SUPPCM_BITS_24 (1<<19) +#define AC_SUPPCM_BITS_32 (1<<20) + +/* supported PCM stream format */ +#define AC_SUPFMT_PCM (1<<0) +#define AC_SUPFMT_FLOAT32 (1<<1) +#define AC_SUPFMT_AC3 (1<<2) + +/* GP I/O count */ +#define AC_GPIO_IO_COUNT (0xff<<0) +#define AC_GPIO_O_COUNT (0xff<<8) +#define AC_GPIO_O_COUNT_SHIFT 8 +#define AC_GPIO_I_COUNT (0xff<<16) +#define AC_GPIO_I_COUNT_SHIFT 16 +#define AC_GPIO_UNSOLICITED (1<<30) +#define AC_GPIO_WAKE (1<<31) + +/* Converter stream, channel */ +#define AC_CONV_CHANNEL (0xf<<0) +#define AC_CONV_STREAM (0xf<<4) +#define AC_CONV_STREAM_SHIFT 4 + +/* Input converter SDI select */ +#define AC_SDI_SELECT (0xf<<0) + +/* stream format id */ +#define AC_FMT_CHAN_SHIFT 0 +#define AC_FMT_CHAN_MASK (0x0f << 0) +#define AC_FMT_BITS_SHIFT 4 +#define AC_FMT_BITS_MASK (7 << 4) +#define AC_FMT_BITS_8 (0 << 4) +#define AC_FMT_BITS_16 (1 << 4) +#define AC_FMT_BITS_20 (2 << 4) +#define AC_FMT_BITS_24 (3 << 4) +#define AC_FMT_BITS_32 (4 << 4) +#define AC_FMT_DIV_SHIFT 8 +#define AC_FMT_DIV_MASK (7 << 8) +#define AC_FMT_MULT_SHIFT 11 +#define AC_FMT_MULT_MASK (7 << 11) +#define AC_FMT_BASE_SHIFT 14 +#define AC_FMT_BASE_48K (0 << 14) +#define AC_FMT_BASE_44K (1 << 14) +#define AC_FMT_TYPE_SHIFT 15 +#define AC_FMT_TYPE_PCM (0 << 15) +#define AC_FMT_TYPE_NON_PCM (1 << 15) + +/* Unsolicited response control */ +#define AC_UNSOL_TAG (0x3f<<0) +#define AC_UNSOL_ENABLED (1<<7) +#define AC_USRSP_EN AC_UNSOL_ENABLED + +/* Unsolicited responses */ +#define AC_UNSOL_RES_TAG (0x3f<<26) +#define AC_UNSOL_RES_TAG_SHIFT 26 +#define AC_UNSOL_RES_SUBTAG (0x1f<<21) +#define AC_UNSOL_RES_SUBTAG_SHIFT 21 +#define AC_UNSOL_RES_DE (0x3f<<15) /* Device Entry + * (for DP1.2 MST) + */ +#define AC_UNSOL_RES_DE_SHIFT 15 +#define AC_UNSOL_RES_IA (1<<2) /* Inactive (for DP1.2 MST) */ +#define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */ +#define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */ +#define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */ +#define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */ + +/* Pin widget capabilies */ +#define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */ +#define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */ +#define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */ +#define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */ +#define AC_PINCAP_OUT (1<<4) /* output capable */ +#define AC_PINCAP_IN (1<<5) /* input capable */ +#define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */ +/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification, + * but is marked reserved in the Intel HDA specification. + */ +#define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */ +/* Note: The same bit as LR_SWAP is newly defined as HDMI capability + * in HD-audio specification + */ +#define AC_PINCAP_HDMI (1<<7) /* HDMI pin */ +#define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can + * coexist with AC_PINCAP_HDMI + */ +#define AC_PINCAP_VREF (0x37<<8) +#define AC_PINCAP_VREF_SHIFT 8 +#define AC_PINCAP_EAPD (1<<16) /* EAPD capable */ +#define AC_PINCAP_HBR (1<<27) /* High Bit Rate */ +/* Vref status (used in pin cap) */ +#define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */ +#define AC_PINCAP_VREF_50 (1<<1) /* 50% */ +#define AC_PINCAP_VREF_GRD (1<<2) /* ground */ +#define AC_PINCAP_VREF_80 (1<<4) /* 80% */ +#define AC_PINCAP_VREF_100 (1<<5) /* 100% */ + +/* Amplifier capabilities */ +#define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */ +#define AC_AMPCAP_OFFSET_SHIFT 0 +#define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */ +#define AC_AMPCAP_NUM_STEPS_SHIFT 8 +#define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB + * in 0.25dB + */ +#define AC_AMPCAP_STEP_SIZE_SHIFT 16 +#define AC_AMPCAP_MUTE (1<<31) /* mute capable */ +#define AC_AMPCAP_MUTE_SHIFT 31 + +/* driver-specific amp-caps: using bits 24-30 */ +#define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */ + +/* Connection list */ +#define AC_CLIST_LENGTH (0x7f<<0) +#define AC_CLIST_LONG (1<<7) + +/* Supported power status */ +#define AC_PWRST_D0SUP (1<<0) +#define AC_PWRST_D1SUP (1<<1) +#define AC_PWRST_D2SUP (1<<2) +#define AC_PWRST_D3SUP (1<<3) +#define AC_PWRST_D3COLDSUP (1<<4) +#define AC_PWRST_S3D3COLDSUP (1<<29) +#define AC_PWRST_CLKSTOP (1<<30) +#define AC_PWRST_EPSS (1U<<31) + +/* Power state values */ +#define AC_PWRST_SETTING (0xf<<0) +#define AC_PWRST_ACTUAL (0xf<<4) +#define AC_PWRST_ACTUAL_SHIFT 4 +#define AC_PWRST_D0 0x00 +#define AC_PWRST_D1 0x01 +#define AC_PWRST_D2 0x02 +#define AC_PWRST_D3 0x03 +#define AC_PWRST_ERROR (1<<8) +#define AC_PWRST_CLK_STOP_OK (1<<9) +#define AC_PWRST_SETTING_RESET (1<<10) + +/* Processing capabilies */ +#define AC_PCAP_BENIGN (1<<0) +#define AC_PCAP_NUM_COEF (0xff<<8) +#define AC_PCAP_NUM_COEF_SHIFT 8 + +/* Volume knobs capabilities */ +#define AC_KNBCAP_NUM_STEPS (0x7f<<0) +#define AC_KNBCAP_DELTA (1<<7) + +/* HDMI LPCM capabilities */ +#define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */ +#define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */ +#define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */ +#define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */ +#define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */ +#define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */ +#define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */ +#define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */ +#define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */ +#define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */ +#define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */ +#define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */ +#define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */ +#define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */ + +/* Display pin's device list length */ +#define AC_DEV_LIST_LEN_MASK 0x3f +#define AC_MAX_DEV_LIST_LEN 64 + +/* + * Control Parameters + */ + +/* Amp gain/mute */ +#define AC_AMP_MUTE (1<<7) +#define AC_AMP_GAIN (0x7f) +#define AC_AMP_GET_INDEX (0xf<<0) + +#define AC_AMP_GET_LEFT (1<<13) +#define AC_AMP_GET_RIGHT (0<<13) +#define AC_AMP_GET_OUTPUT (1<<15) +#define AC_AMP_GET_INPUT (0<<15) + +#define AC_AMP_SET_INDEX (0xf<<8) +#define AC_AMP_SET_INDEX_SHIFT 8 +#define AC_AMP_SET_RIGHT (1<<12) +#define AC_AMP_SET_LEFT (1<<13) +#define AC_AMP_SET_INPUT (1<<14) +#define AC_AMP_SET_OUTPUT (1<<15) + +/* DIGITAL1 bits */ +#define AC_DIG1_ENABLE (1<<0) +#define AC_DIG1_V (1<<1) +#define AC_DIG1_VCFG (1<<2) +#define AC_DIG1_EMPHASIS (1<<3) +#define AC_DIG1_COPYRIGHT (1<<4) +#define AC_DIG1_NONAUDIO (1<<5) +#define AC_DIG1_PROFESSIONAL (1<<6) +#define AC_DIG1_LEVEL (1<<7) + +/* DIGITAL2 bits */ +#define AC_DIG2_CC (0x7f<<0) + +/* DIGITAL3 bits */ +#define AC_DIG3_ICT (0xf<<0) +#define AC_DIG3_KAE (1<<7) + +/* Pin widget control - 8bit */ +#define AC_PINCTL_EPT (0x3<<0) +#define AC_PINCTL_EPT_NATIVE 0 +#define AC_PINCTL_EPT_HBR 3 +#define AC_PINCTL_VREFEN (0x7<<0) +#define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */ +#define AC_PINCTL_VREF_50 1 /* 50% */ +#define AC_PINCTL_VREF_GRD 2 /* ground */ +#define AC_PINCTL_VREF_80 4 /* 80% */ +#define AC_PINCTL_VREF_100 5 /* 100% */ +#define AC_PINCTL_IN_EN (1<<5) +#define AC_PINCTL_OUT_EN (1<<6) +#define AC_PINCTL_HP_EN (1<<7) + +/* Pin sense - 32bit */ +#define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff) +#define AC_PINSENSE_PRESENCE (1<<31) +#define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */ + +/* EAPD/BTL enable - 32bit */ +#define AC_EAPDBTL_BALANCED (1<<0) +#define AC_EAPDBTL_EAPD (1<<1) +#define AC_EAPDBTL_LR_SWAP (1<<2) + +/* HDMI ELD data */ +#define AC_ELDD_ELD_VALID (1<<31) +#define AC_ELDD_ELD_DATA 0xff + +/* HDMI DIP size */ +#define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */ +#define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */ + +/* HDMI DIP index */ +#define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */ +#define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */ + +/* HDMI DIP xmit (transmit) control */ +#define AC_DIPXMIT_MASK (0x3<<6) +#define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */ +#define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */ +#define AC_DIPXMIT_BEST (0x3<<6) /* best effort */ + +/* HDMI content protection (CP) control */ +#define AC_CPCTRL_CES (1<<9) /* current encryption state */ +#define AC_CPCTRL_READY (1<<8) /* ready bit */ +#define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */ +#define AC_CPCTRL_STATE (3<<0) /* current CP request state */ + +/* Converter channel <-> HDMI slot mapping */ +#define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */ +#define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */ + +/* configuration default - 32bit */ +#define AC_DEFCFG_SEQUENCE (0xf<<0) +#define AC_DEFCFG_DEF_ASSOC (0xf<<4) +#define AC_DEFCFG_ASSOC_SHIFT 4 +#define AC_DEFCFG_MISC (0xf<<8) +#define AC_DEFCFG_MISC_SHIFT 8 +#define AC_DEFCFG_MISC_NO_PRESENCE (1<<0) +#define AC_DEFCFG_COLOR (0xf<<12) +#define AC_DEFCFG_COLOR_SHIFT 12 +#define AC_DEFCFG_CONN_TYPE (0xf<<16) +#define AC_DEFCFG_CONN_TYPE_SHIFT 16 +#define AC_DEFCFG_DEVICE (0xf<<20) +#define AC_DEFCFG_DEVICE_SHIFT 20 +#define AC_DEFCFG_LOCATION (0x3f<<24) +#define AC_DEFCFG_LOCATION_SHIFT 24 +#define AC_DEFCFG_PORT_CONN (0x3<<30) +#define AC_DEFCFG_PORT_CONN_SHIFT 30 + +/* Display pin's device list entry */ +#define AC_DE_PD (1<<0) +#define AC_DE_ELDV (1<<1) +#define AC_DE_IA (1<<2) + +/* device types (0x0-0xf) */ +enum { + AC_JACK_LINE_OUT, + AC_JACK_SPEAKER, + AC_JACK_HP_OUT, + AC_JACK_CD, + AC_JACK_SPDIF_OUT, + AC_JACK_DIG_OTHER_OUT, + AC_JACK_MODEM_LINE_SIDE, + AC_JACK_MODEM_HAND_SIDE, + AC_JACK_LINE_IN, + AC_JACK_AUX, + AC_JACK_MIC_IN, + AC_JACK_TELEPHONY, + AC_JACK_SPDIF_IN, + AC_JACK_DIG_OTHER_IN, + AC_JACK_OTHER = 0xf, +}; + +/* jack connection types (0x0-0xf) */ +enum { + AC_JACK_CONN_UNKNOWN, + AC_JACK_CONN_1_8, + AC_JACK_CONN_1_4, + AC_JACK_CONN_ATAPI, + AC_JACK_CONN_RCA, + AC_JACK_CONN_OPTICAL, + AC_JACK_CONN_OTHER_DIGITAL, + AC_JACK_CONN_OTHER_ANALOG, + AC_JACK_CONN_DIN, + AC_JACK_CONN_XLR, + AC_JACK_CONN_RJ11, + AC_JACK_CONN_COMB, + AC_JACK_CONN_OTHER = 0xf, +}; + +/* jack colors (0x0-0xf) */ +enum { + AC_JACK_COLOR_UNKNOWN, + AC_JACK_COLOR_BLACK, + AC_JACK_COLOR_GREY, + AC_JACK_COLOR_BLUE, + AC_JACK_COLOR_GREEN, + AC_JACK_COLOR_RED, + AC_JACK_COLOR_ORANGE, + AC_JACK_COLOR_YELLOW, + AC_JACK_COLOR_PURPLE, + AC_JACK_COLOR_PINK, + AC_JACK_COLOR_WHITE = 0xe, + AC_JACK_COLOR_OTHER, +}; + +/* Jack location (0x0-0x3f) */ +/* common case */ +enum { + AC_JACK_LOC_NONE, + AC_JACK_LOC_REAR, + AC_JACK_LOC_FRONT, + AC_JACK_LOC_LEFT, + AC_JACK_LOC_RIGHT, + AC_JACK_LOC_TOP, + AC_JACK_LOC_BOTTOM, +}; +/* bits 4-5 */ +enum { + AC_JACK_LOC_EXTERNAL = 0x00, + AC_JACK_LOC_INTERNAL = 0x10, + AC_JACK_LOC_SEPARATE = 0x20, + AC_JACK_LOC_OTHER = 0x30, +}; +enum { + /* external on primary chasis */ + AC_JACK_LOC_REAR_PANEL = 0x07, + AC_JACK_LOC_DRIVE_BAY, + /* internal */ + AC_JACK_LOC_RISER = 0x17, + AC_JACK_LOC_HDMI, + AC_JACK_LOC_ATAPI, + /* others */ + AC_JACK_LOC_MOBILE_IN = 0x37, + AC_JACK_LOC_MOBILE_OUT, +}; + +/* Port connectivity (0-3) */ +enum { + AC_JACK_PORT_COMPLEX, + AC_JACK_PORT_NONE, + AC_JACK_PORT_FIXED, + AC_JACK_PORT_BOTH, +}; + +/* max. codec address */ +#define HDA_MAX_CODEC_ADDRESS 0x0f + +#endif /* __SOUND_HDA_VERBS_H */ diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h new file mode 100644 index 000000000..aa994d6e6 --- /dev/null +++ b/include/sound/hdaudio.h @@ -0,0 +1,766 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio core stuff + */ + +#ifndef __SOUND_HDAUDIO_H +#define __SOUND_HDAUDIO_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* codec node id */ +typedef u16 hda_nid_t; + +struct hdac_bus; +struct hdac_stream; +struct hdac_device; +struct hdac_driver; +struct hdac_widget_tree; +struct hda_device_id; + +/* + * exported bus type + */ +extern const struct bus_type snd_hda_bus_type; + +/* + * generic arrays + */ +struct snd_array { + unsigned int used; + unsigned int alloced; + unsigned int elem_size; + unsigned int alloc_align; + void *list; +}; + +/* + * HD-audio codec base device + */ +struct hdac_device { + struct device dev; + int type; + struct hdac_bus *bus; + unsigned int addr; /* codec address */ + struct list_head list; /* list point for bus codec_list */ + + hda_nid_t afg; /* AFG node id */ + hda_nid_t mfg; /* MFG node id */ + + /* ids */ + unsigned int vendor_id; + unsigned int subsystem_id; + unsigned int revision_id; + unsigned int afg_function_id; + unsigned int mfg_function_id; + unsigned int afg_unsol:1; + unsigned int mfg_unsol:1; + + unsigned int power_caps; /* FG power caps */ + + const char *vendor_name; /* codec vendor name */ + const char *chip_name; /* codec chip name */ + + /* verb exec op override */ + int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, + unsigned int flags, unsigned int *res); + + /* widgets */ + unsigned int num_nodes; + hda_nid_t start_nid, end_nid; + + /* misc flags */ + atomic_t in_pm; /* suspend/resume being performed */ + + /* sysfs */ + struct mutex widget_lock; + struct hdac_widget_tree *widgets; + + /* regmap */ + struct regmap *regmap; + struct mutex regmap_lock; + struct snd_array vendor_verbs; + bool lazy_cache:1; /* don't wake up for writes */ + bool caps_overwriting:1; /* caps overwrite being in process */ + bool cache_coef:1; /* cache COEF read/write too */ + unsigned int registered:1; /* codec was registered */ +}; + +/* device/driver type used for matching */ +enum { + HDA_DEV_CORE, + HDA_DEV_LEGACY, + HDA_DEV_ASOC, +}; + +enum { + SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ + SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ + SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ +}; + +/* direction */ +enum { + HDA_INPUT, HDA_OUTPUT +}; + +#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) + +int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, + const char *name, unsigned int addr); +void snd_hdac_device_exit(struct hdac_device *dev); +int snd_hdac_device_register(struct hdac_device *codec); +void snd_hdac_device_unregister(struct hdac_device *codec); +int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); +int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size); + +int snd_hdac_refresh_widgets(struct hdac_device *codec); + +int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int parm, unsigned int *res); +int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, + unsigned int *res); +int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, + int parm); +int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, + unsigned int parm, unsigned int val); +int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, + hda_nid_t *conn_list, int max_conns); +int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, + hda_nid_t *start_id); +unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat, + unsigned int maxbits); +unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate); +unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits, + unsigned int rate, unsigned short spdif_ctls); +int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, + u32 *ratesp, u64 *formatsp, u32 *subformatsp, + unsigned int *bpsp); +bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, + unsigned int format); + +int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, + int flags, unsigned int verb, unsigned int parm); +int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, + int flags, unsigned int verb, unsigned int parm); +bool snd_hdac_check_power_state(struct hdac_device *hdac, + hda_nid_t nid, unsigned int target_state); +unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, + hda_nid_t nid, unsigned int target_state); +/** + * snd_hdac_read_parm - read a codec parameter + * @codec: the codec object + * @nid: NID to read a parameter + * @parm: parameter to read + * + * Returns -1 for error. If you need to distinguish the error more + * strictly, use _snd_hdac_read_parm() directly. + */ +static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, + int parm) +{ + unsigned int val; + + return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; +} + +#ifdef CONFIG_PM +int snd_hdac_power_up(struct hdac_device *codec); +int snd_hdac_power_down(struct hdac_device *codec); +int snd_hdac_power_up_pm(struct hdac_device *codec); +int snd_hdac_power_down_pm(struct hdac_device *codec); +int snd_hdac_keep_power_up(struct hdac_device *codec); + +/* call this at entering into suspend/resume callbacks in codec driver */ +static inline void snd_hdac_enter_pm(struct hdac_device *codec) +{ + atomic_inc(&codec->in_pm); +} + +/* call this at leaving from suspend/resume callbacks in codec driver */ +static inline void snd_hdac_leave_pm(struct hdac_device *codec) +{ + atomic_dec(&codec->in_pm); +} + +static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) +{ + return atomic_read(&codec->in_pm); +} + +static inline bool snd_hdac_is_power_on(struct hdac_device *codec) +{ + return !pm_runtime_suspended(&codec->dev); +} +#else +static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } +static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} +static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} +static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; } +static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; } +#endif + +/* + * HD-audio codec base driver + */ +struct hdac_driver { + struct device_driver driver; + int type; + const struct hda_device_id *id_table; + int (*match)(struct hdac_device *dev, const struct hdac_driver *drv); + void (*unsol_event)(struct hdac_device *dev, unsigned int event); + + /* fields used by ext bus APIs */ + int (*probe)(struct hdac_device *dev); + int (*remove)(struct hdac_device *dev); + void (*shutdown)(struct hdac_device *dev); +}; + +#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) + +const struct hda_device_id * +hdac_get_device_id(struct hdac_device *hdev, const struct hdac_driver *drv); + +/* + * Bus verb operators + */ +struct hdac_bus_ops { + /* send a single command */ + int (*command)(struct hdac_bus *bus, unsigned int cmd); + /* get a response from the last command */ + int (*get_response)(struct hdac_bus *bus, unsigned int addr, + unsigned int *res); + /* notify of codec link power-up/down */ + void (*link_power)(struct hdac_device *hdev, bool enable); +}; + +/* + * ops used for ASoC HDA codec drivers + */ +struct hdac_ext_bus_ops { + int (*hdev_attach)(struct hdac_device *hdev); + int (*hdev_detach)(struct hdac_device *hdev); +}; + +#define HDA_UNSOL_QUEUE_SIZE 64 +#define HDA_MAX_CODECS 8 /* limit by controller side */ + +/* + * CORB/RIRB + * + * Each CORB entry is 4byte, RIRB is 8byte + */ +struct hdac_rb { + __le32 *buf; /* virtual address of CORB/RIRB buffer */ + dma_addr_t addr; /* physical address of CORB/RIRB buffer */ + unsigned short rp, wp; /* RIRB read/write pointers */ + int cmds[HDA_MAX_CODECS]; /* number of pending requests */ + u32 res[HDA_MAX_CODECS]; /* last read value */ +}; + +/* + * HD-audio bus base driver + * + * @ppcap: pp capabilities pointer + * @spbcap: SPIB capabilities pointer + * @mlcap: MultiLink capabilities pointer + * @gtscap: gts capabilities pointer + * @drsmcap: dma resume capabilities pointer + * @num_streams: streams supported + * @idx: HDA link index + * @hlink_list: link list of HDA links + * @lock: lock for link and display power mgmt + * @cmd_dma_state: state of cmd DMAs: CORB and RIRB + */ +struct hdac_bus { + struct device *dev; + const struct hdac_bus_ops *ops; + const struct hdac_ext_bus_ops *ext_ops; + + /* h/w resources */ + unsigned long addr; + void __iomem *remap_addr; + int irq; + + void __iomem *ppcap; + void __iomem *spbcap; + void __iomem *mlcap; + void __iomem *gtscap; + void __iomem *drsmcap; + + /* codec linked list */ + struct list_head codec_list; + unsigned int num_codecs; + + /* link caddr -> codec */ + struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; + + /* unsolicited event queue */ + u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ + unsigned int unsol_rp, unsol_wp; + struct work_struct unsol_work; + + /* bit flags of detected codecs */ + unsigned long codec_mask; + + /* bit flags of powered codecs */ + unsigned long codec_powered; + + /* CORB/RIRB */ + struct hdac_rb corb; + struct hdac_rb rirb; + unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ + wait_queue_head_t rirb_wq; + + /* CORB/RIRB and position buffers */ + struct snd_dma_buffer rb; + struct snd_dma_buffer posbuf; + int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ + + /* hdac_stream linked list */ + struct list_head stream_list; + + /* operation state */ + bool chip_init:1; /* h/w initialized */ + + /* behavior flags */ + bool aligned_mmio:1; /* aligned MMIO access */ + bool sync_write:1; /* sync after verb write */ + bool use_posbuf:1; /* use position buffer */ + bool snoop:1; /* enable snooping */ + bool align_bdle_4k:1; /* BDLE align 4K boundary */ + bool reverse_assign:1; /* assign devices in reverse order */ + bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ + bool polling_mode:1; + bool needs_damn_long_delay:1; + bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */ + bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */ + bool use_pio_for_commands:1; /* Use PIO instead of CORB for commands */ + + int poll_count; + + int bdl_pos_adj; /* BDL position adjustment */ + + /* delay time in us for dma stop */ + unsigned int dma_stop_delay; + + /* locks */ + spinlock_t reg_lock; + struct mutex cmd_mutex; + struct mutex lock; + + /* DRM component interface */ + struct drm_audio_component *audio_component; + long display_power_status; + unsigned long display_power_active; + + /* parameters required for enhanced capabilities */ + int num_streams; + int idx; + + /* link management */ + struct list_head hlink_list; + bool cmd_dma_state; + + /* factor used to derive STRIPE control value */ + unsigned int sdo_limit; + + /* address offset between host and hadc */ + dma_addr_t addr_offset; +}; + +int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, + const struct hdac_bus_ops *ops); +void snd_hdac_bus_exit(struct hdac_bus *bus); +int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, + unsigned int cmd, unsigned int *res); + +void snd_hdac_codec_link_up(struct hdac_device *codec); +void snd_hdac_codec_link_down(struct hdac_device *codec); + +int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); +int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, + unsigned int *res); +int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); + +bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); +void snd_hdac_bus_stop_chip(struct hdac_bus *bus); +void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); +void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); +void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); +void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); +int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); +void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable); + +void snd_hdac_bus_update_rirb(struct hdac_bus *bus); +int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, + void (*ack)(struct hdac_bus *, + struct hdac_stream *)); + +int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); +void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); + +#ifdef CONFIG_SND_HDA_ALIGNED_MMIO +unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); +void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, + unsigned int mask); +#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio +#else +#define snd_hdac_aligned_mmio(bus) false +#define snd_hdac_aligned_read(addr, mask) 0 +#define snd_hdac_aligned_write(val, addr, mask) do {} while (0) +#endif + +static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr, + u8 val) +{ + if (snd_hdac_aligned_mmio(bus)) + snd_hdac_aligned_write(val, addr, 0xff); + else + writeb(val, addr); +} + +static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr, + u16 val) +{ + if (snd_hdac_aligned_mmio(bus)) + snd_hdac_aligned_write(val, addr, 0xffff); + else + writew(val, addr); +} + +static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr) +{ + return snd_hdac_aligned_mmio(bus) ? + snd_hdac_aligned_read(addr, 0xff) : readb(addr); +} + +static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr) +{ + return snd_hdac_aligned_mmio(bus) ? + snd_hdac_aligned_read(addr, 0xffff) : readw(addr); +} + +#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) +#define snd_hdac_reg_readl(bus, addr) readl(addr) +#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr) +#define snd_hdac_reg_readq(bus, addr) readq(addr) + +/* + * macros for easy use + */ +#define _snd_hdac_chip_writeb(chip, reg, value) \ + snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) +#define _snd_hdac_chip_readb(chip, reg) \ + snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) +#define _snd_hdac_chip_writew(chip, reg, value) \ + snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) +#define _snd_hdac_chip_readw(chip, reg) \ + snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) +#define _snd_hdac_chip_writel(chip, reg, value) \ + snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) +#define _snd_hdac_chip_readl(chip, reg) \ + snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) + +/* read/write a register, pass without AZX_REG_ prefix */ +#define snd_hdac_chip_writel(chip, reg, value) \ + _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) +#define snd_hdac_chip_writew(chip, reg, value) \ + _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) +#define snd_hdac_chip_writeb(chip, reg, value) \ + _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) +#define snd_hdac_chip_readl(chip, reg) \ + _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) +#define snd_hdac_chip_readw(chip, reg) \ + _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) +#define snd_hdac_chip_readb(chip, reg) \ + _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) + +/* update a register, pass without AZX_REG_ prefix */ +#define snd_hdac_chip_updatel(chip, reg, mask, val) \ + snd_hdac_chip_writel(chip, reg, \ + (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_chip_updatew(chip, reg, mask, val) \ + snd_hdac_chip_writew(chip, reg, \ + (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_chip_updateb(chip, reg, mask, val) \ + snd_hdac_chip_writeb(chip, reg, \ + (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) + +/* update register macro */ +#define snd_hdac_updatel(addr, reg, mask, val) \ + writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg) + +#define snd_hdac_updatew(addr, reg, mask, val) \ + writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg) + +/* + * HD-audio stream + */ +struct hdac_stream { + struct hdac_bus *bus; + struct snd_dma_buffer bdl; /* BDL buffer */ + __le32 *posbuf; /* position buffer pointer */ + int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ + + unsigned int bufsize; /* size of the play buffer in bytes */ + unsigned int period_bytes; /* size of the period in bytes */ + unsigned int frags; /* number for period in the play buffer */ + unsigned int fifo_size; /* FIFO size */ + + void __iomem *sd_addr; /* stream descriptor pointer */ + + void __iomem *spib_addr; /* software position in buffers stream pointer */ + void __iomem *fifo_addr; /* software position Max fifos stream pointer */ + + void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */ + u32 dpib; /* DMA position in buffer */ + u32 lpib; /* Linear position in buffer */ + + u32 sd_int_sta_mask; /* stream int status mask */ + + /* pcm support */ + struct snd_pcm_substream *substream; /* assigned substream, + * set in PCM open + */ + struct snd_compr_stream *cstream; + unsigned int format_val; /* format value to be set in the + * controller and the codec + */ + unsigned char stream_tag; /* assigned stream */ + unsigned char index; /* stream index */ + int assigned_key; /* last device# key assigned to */ + + bool opened:1; + bool running:1; + bool prepared:1; + bool no_period_wakeup:1; + bool locked:1; + bool stripe:1; /* apply stripe control */ + + u64 curr_pos; + /* timestamp */ + unsigned long start_wallclk; /* start + minimum wallclk */ + unsigned long period_wallclk; /* wallclk for period */ + struct timecounter tc; + struct cyclecounter cc; + int delay_negative_threshold; + + struct list_head list; +#ifdef CONFIG_SND_HDA_DSP_LOADER + /* DSP access mutex */ + struct mutex dsp_mutex; +#endif +}; + +void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, + int idx, int direction, int tag); +struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, + struct snd_pcm_substream *substream); +void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev); +void snd_hdac_stream_release(struct hdac_stream *azx_dev); +struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, + int dir, int stream_tag); + +int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading); +void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); +int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); +int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, + unsigned int format_val); +void snd_hdac_stream_start(struct hdac_stream *azx_dev); +void snd_hdac_stream_stop(struct hdac_stream *azx_dev); +void snd_hdac_stop_streams(struct hdac_bus *bus); +void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus); +void snd_hdac_stream_reset(struct hdac_stream *azx_dev); +void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, + unsigned int streams, unsigned int reg); +void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, + unsigned int streams); +void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, + unsigned int streams, bool start); +int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, + struct snd_pcm_substream *substream); + +void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip, + bool enable, int index); +int snd_hdac_stream_set_spib(struct hdac_bus *bus, + struct hdac_stream *azx_dev, u32 value); +void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, + bool enable, int index); +int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev); +int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, + struct hdac_stream *azx_dev, u32 value); +int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value); + +/* + * macros for easy use + */ +/* read/write a register, pass without AZX_REG_ prefix */ +#define snd_hdac_stream_writel(dev, reg, value) \ + snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) +#define snd_hdac_stream_writew(dev, reg, value) \ + snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) +#define snd_hdac_stream_writeb(dev, reg, value) \ + snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) +#define snd_hdac_stream_readl(dev, reg) \ + snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readw(dev, reg) \ + snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readb(dev, reg) \ + snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \ + false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \ + false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \ + false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) + +/* update a register, pass without AZX_REG_ prefix */ +#define snd_hdac_stream_updatel(dev, reg, mask, val) \ + snd_hdac_stream_writel(dev, reg, \ + (snd_hdac_stream_readl(dev, reg) & \ + ~(mask)) | (val)) +#define snd_hdac_stream_updatew(dev, reg, mask, val) \ + snd_hdac_stream_writew(dev, reg, \ + (snd_hdac_stream_readw(dev, reg) & \ + ~(mask)) | (val)) +#define snd_hdac_stream_updateb(dev, reg, mask, val) \ + snd_hdac_stream_writeb(dev, reg, \ + (snd_hdac_stream_readb(dev, reg) & \ + ~(mask)) | (val)) + +#ifdef CONFIG_SND_HDA_DSP_LOADER +/* DSP lock helpers */ +#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) +#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) +#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) +#define snd_hdac_stream_is_locked(dev) ((dev)->locked) +DEFINE_GUARD(snd_hdac_dsp_lock, struct hdac_stream *, snd_hdac_dsp_lock(_T), snd_hdac_dsp_unlock(_T)) +/* DSP loader helpers */ +int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, + unsigned int byte_size, struct snd_dma_buffer *bufp); +void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); +void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, + struct snd_dma_buffer *dmab); +#else /* CONFIG_SND_HDA_DSP_LOADER */ +#define snd_hdac_dsp_lock_init(dev) do {} while (0) +#define snd_hdac_dsp_lock(dev) do {} while (0) +#define snd_hdac_dsp_unlock(dev) do {} while (0) +#define snd_hdac_stream_is_locked(dev) 0 + +static inline int +snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, + unsigned int byte_size, struct snd_dma_buffer *bufp) +{ + return 0; +} + +static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) +{ +} + +static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, + struct snd_dma_buffer *dmab) +{ +} +#endif /* CONFIG_SND_HDA_DSP_LOADER */ + +/* + * Easy macros for widget capabilities + */ +#define snd_hdac_get_wcaps(codec, nid) \ + snd_hdac_read_parm(codec, nid, AC_PAR_AUDIO_WIDGET_CAP) + +/* get the widget type from widget capability bits */ +static inline int snd_hdac_get_wcaps_type(unsigned int wcaps) +{ + if (!wcaps) + return -1; /* invalid type */ + return (wcaps & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT; +} + +/* get the number of supported channels */ +static inline unsigned int snd_hdac_get_wcaps_channels(u32 wcaps) +{ + unsigned int chans; + + chans = (wcaps & AC_WCAP_CHAN_CNT_EXT) >> 13; + chans = (chans + 1) * 2; + + return chans; +} + +/* + * generic array helpers + */ +void *snd_array_new(struct snd_array *array); +void snd_array_free(struct snd_array *array); +static inline void snd_array_init(struct snd_array *array, unsigned int size, + unsigned int align) +{ + array->elem_size = size; + array->alloc_align = align; +} + +static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) +{ + return array->list + idx * array->elem_size; +} + +static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) +{ + return (unsigned long)(ptr - array->list) / array->elem_size; +} + +/* a helper macro to iterate for each snd_array element */ +#define snd_array_for_each(array, idx, ptr) \ + for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ + (ptr) = snd_array_elem(array, ++(idx))) + +/* + * Device matching + */ + +#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \ + { } \ + }, pci)) + +#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \ + { } \ + }, pci)) + +#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \ + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BMG) }, \ + { } \ + }, pci) || HDA_CONTROLLER_IS_HSW(pci)) + +#endif /* __SOUND_HDAUDIO_H */ diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h new file mode 100644 index 000000000..7de390022 --- /dev/null +++ b/include/sound/hdaudio_ext.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_HDAUDIO_EXT_H +#define __SOUND_HDAUDIO_EXT_H + +#include + +int snd_hdac_ext_bus_init(struct hdac_bus *bus, struct device *dev, + const struct hdac_bus_ops *ops, + const struct hdac_ext_bus_ops *ext_ops); + +void snd_hdac_ext_bus_exit(struct hdac_bus *bus); +void snd_hdac_ext_bus_device_remove(struct hdac_bus *bus); + +#define HDA_CODEC_REV_EXT_ENTRY(_vid, _rev, _name, drv_data) \ + { .vendor_id = (_vid), .rev_id = (_rev), .name = (_name), \ + .api_version = HDA_DEV_ASOC, \ + .driver_data = (unsigned long)(drv_data) } +#define HDA_CODEC_EXT_ENTRY(_vid, _revid, _name, _drv_data) \ + HDA_CODEC_REV_EXT_ENTRY(_vid, _revid, _name, _drv_data) + +void snd_hdac_ext_bus_ppcap_enable(struct hdac_bus *chip, bool enable); +void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_bus *chip, bool enable); + +int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus); +struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_id(struct hdac_bus *bus, u32 id); +struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_addr(struct hdac_bus *bus, int addr); +struct hdac_ext_link *snd_hdac_ext_bus_get_hlink_by_name(struct hdac_bus *bus, + const char *codec_name); + +enum hdac_ext_stream_type { + HDAC_EXT_STREAM_TYPE_COUPLED = 0, + HDAC_EXT_STREAM_TYPE_HOST, + HDAC_EXT_STREAM_TYPE_LINK +}; + +/** + * hdac_ext_stream: HDAC extended stream for extended HDA caps + * + * @hstream: hdac_stream + * @pphc_addr: processing pipe host stream pointer + * @pplc_addr: processing pipe link stream pointer + * @decoupled: stream host and link is decoupled + * @link_locked: link is locked + * @link_prepared: link is prepared + * @link_substream: link substream + */ +struct hdac_ext_stream { + struct hdac_stream hstream; + + void __iomem *pphc_addr; + void __iomem *pplc_addr; + + u32 pphcllpl; + u32 pphcllpu; + u32 pphcldpl; + u32 pphcldpu; + + u32 pplcllpl; + u32 pplcllpu; + + bool decoupled:1; + bool link_locked:1; + bool link_prepared; + + int (*host_setup)(struct hdac_stream *, bool); + + struct snd_pcm_substream *link_substream; +}; + +#define hdac_stream(s) (&(s)->hstream) +#define stream_to_hdac_ext_stream(s) \ + container_of(s, struct hdac_ext_stream, hstream) + +int snd_hdac_ext_stream_init_all(struct hdac_bus *bus, int start_idx, + int num_stream, int dir); +void snd_hdac_ext_stream_free_all(struct hdac_bus *bus); +void snd_hdac_ext_link_free_all(struct hdac_bus *bus); +struct hdac_ext_stream *snd_hdac_ext_stream_assign(struct hdac_bus *bus, + struct snd_pcm_substream *substream, + int type); +void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type); +struct hdac_ext_stream *snd_hdac_ext_cstream_assign(struct hdac_bus *bus, + struct snd_compr_stream *cstream); +void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus, + struct hdac_ext_stream *hext_stream, bool decouple); +void snd_hdac_ext_stream_decouple(struct hdac_bus *bus, + struct hdac_ext_stream *azx_dev, bool decouple); + +void snd_hdac_ext_stream_start(struct hdac_ext_stream *hext_stream); +void snd_hdac_ext_stream_clear(struct hdac_ext_stream *hext_stream); +void snd_hdac_ext_stream_reset(struct hdac_ext_stream *hext_stream); +int snd_hdac_ext_stream_setup(struct hdac_ext_stream *hext_stream, int fmt); +int snd_hdac_ext_host_stream_setup(struct hdac_ext_stream *hext_stream, bool code_loading); + +struct hdac_ext_link { + struct hdac_bus *bus; + int index; + void __iomem *ml_addr; /* link output stream reg pointer */ + u32 lcaps; /* link capablities */ + u16 lsdiid; /* link sdi identifier */ + u32 id; + u8 slcount; + + int ref_count; + + struct list_head list; +}; + +#define hdac_ext_link_alt(link) ((link)->lcaps & AZX_ML_HDA_LCAP_ALT) +#define hdac_ext_link_ofls(link) ((link)->lcaps & AZX_ML_HDA_LCAP_OFLS) + +int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *hlink); +int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *hlink); +int snd_hdac_ext_bus_link_power_up_all(struct hdac_bus *bus); +int snd_hdac_ext_bus_link_power_down_all(struct hdac_bus *bus); +void snd_hdac_ext_bus_link_set_stream_id(struct hdac_ext_link *hlink, + int stream); +void snd_hdac_ext_bus_link_clear_stream_id(struct hdac_ext_link *hlink, + int stream); + +int snd_hdac_ext_bus_link_get(struct hdac_bus *bus, struct hdac_ext_link *hlink); +int snd_hdac_ext_bus_link_put(struct hdac_bus *bus, struct hdac_ext_link *hlink); + +void snd_hdac_ext_bus_link_power(struct hdac_device *codec, bool enable); + +struct hdac_ext_device; + +/* ops common to all codec drivers */ +struct hdac_ext_codec_ops { + int (*build_controls)(struct hdac_ext_device *dev); + int (*init)(struct hdac_ext_device *dev); + void (*free)(struct hdac_ext_device *dev); +}; + +struct hda_dai_map { + char *dai_name; + hda_nid_t nid; + u32 maxbps; +}; + +struct hdac_ext_dma_params { + u32 format; + u8 stream_tag; +}; + +int snd_hda_ext_driver_register(struct hdac_driver *drv); +void snd_hda_ext_driver_unregister(struct hdac_driver *drv); + +#endif /* __SOUND_HDAUDIO_EXT_H */ diff --git a/include/sound/hdmi-codec.h b/include/sound/hdmi-codec.h new file mode 100644 index 000000000..273f4c36f --- /dev/null +++ b/include/sound/hdmi-codec.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * hdmi-codec.h - HDMI Codec driver API + * + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com + * + * Author: Jyri Sarha + */ + +#ifndef __HDMI_CODEC_H__ +#define __HDMI_CODEC_H__ + +#include +#include +#include +#include +#include + +/* + * Protocol between ASoC cpu-dai and HDMI-encoder + */ +struct hdmi_codec_daifmt { + enum { + HDMI_I2S, + HDMI_RIGHT_J, + HDMI_LEFT_J, + HDMI_DSP_A, + HDMI_DSP_B, + HDMI_AC97, + HDMI_SPDIF, + } fmt; + unsigned int bit_clk_inv:1; + unsigned int frame_clk_inv:1; + unsigned int bit_clk_provider:1; + unsigned int frame_clk_provider:1; + /* bit_fmt could be standard PCM format or + * IEC958 encoded format. ALSA IEC958 plugin will pass + * IEC958_SUBFRAME format to the underneath driver. + */ + snd_pcm_format_t bit_fmt; +}; + +/* + * HDMI audio parameters + */ +struct hdmi_codec_params { + struct hdmi_audio_infoframe cea; + struct snd_aes_iec958 iec; + int sample_rate; + int sample_width; + int channels; +}; + +typedef void (*hdmi_codec_plugged_cb)(struct device *dev, + bool plugged); + +struct hdmi_codec_pdata; +struct hdmi_codec_ops { + /* + * Called when ASoC starts an audio stream setup. + * Optional + */ + int (*audio_startup)(struct device *dev, void *data); + + /* + * Configures HDMI-encoder for audio stream. + * Having either prepare or hw_params is mandatory. + */ + int (*hw_params)(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms); + + /* + * Configures HDMI-encoder for audio stream. Can be called + * multiple times for each setup. + * + * Having either prepare or hw_params is mandatory. + */ + int (*prepare)(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms); + + /* + * Shuts down the audio stream. + * Mandatory + */ + void (*audio_shutdown)(struct device *dev, void *data); + + /* + * Mute/unmute HDMI audio stream. + * Optional + */ + int (*mute_stream)(struct device *dev, void *data, + bool enable, int direction); + + /* + * Provides EDID-Like-Data from connected HDMI device. + * Optional + */ + int (*get_eld)(struct device *dev, void *data, + uint8_t *buf, size_t len); + + /* + * Getting DAI ID + * Optional + */ + int (*get_dai_id)(struct snd_soc_component *comment, + struct device_node *endpoint, + void *data); + + /* + * Hook callback function to handle connector plug event. + * Optional + */ + int (*hook_plugged_cb)(struct device *dev, void *data, + hdmi_codec_plugged_cb fn, + struct device *codec_dev); +}; + +/* HDMI codec initalization data */ +struct hdmi_codec_pdata { + const struct hdmi_codec_ops *ops; + u64 i2s_formats; + uint i2s:1; + uint no_i2s_playback:1; + uint no_i2s_capture:1; + uint spdif:1; + uint no_spdif_playback:1; + uint no_spdif_capture:1; + uint no_capture_mute:1; + int max_i2s_channels; + void *data; +}; + +struct snd_soc_component; +struct snd_soc_jack; + +#define HDMI_CODEC_DRV_NAME "hdmi-audio-codec" + +#endif /* __HDMI_CODEC_H__ */ diff --git a/include/sound/hwdep.h b/include/sound/hwdep.h new file mode 100644 index 000000000..b0da63318 --- /dev/null +++ b/include/sound/hwdep.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_HWDEP_H +#define __SOUND_HWDEP_H + +/* + * Hardware dependent layer + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include + +struct snd_hwdep; + +/* hwdep file ops; all ops can be NULL */ +struct snd_hwdep_ops { + long long (*llseek)(struct snd_hwdep *hw, struct file *file, + long long offset, int orig); + long (*read)(struct snd_hwdep *hw, char __user *buf, + long count, loff_t *offset); + long (*write)(struct snd_hwdep *hw, const char __user *buf, + long count, loff_t *offset); + int (*open)(struct snd_hwdep *hw, struct file * file); + int (*release)(struct snd_hwdep *hw, struct file * file); + __poll_t (*poll)(struct snd_hwdep *hw, struct file *file, + poll_table *wait); + int (*ioctl)(struct snd_hwdep *hw, struct file *file, + unsigned int cmd, unsigned long arg); + int (*ioctl_compat)(struct snd_hwdep *hw, struct file *file, + unsigned int cmd, unsigned long arg); + int (*mmap)(struct snd_hwdep *hw, struct file *file, + struct vm_area_struct *vma); + int (*dsp_status)(struct snd_hwdep *hw, + struct snd_hwdep_dsp_status *status); + int (*dsp_load)(struct snd_hwdep *hw, + struct snd_hwdep_dsp_image *image); +}; + +struct snd_hwdep { + struct snd_card *card; + struct list_head list; + int device; + char id[32]; + char name[80]; + int iface; + +#ifdef CONFIG_SND_OSSEMUL + int oss_type; + int ossreg; +#endif + + struct snd_hwdep_ops ops; + wait_queue_head_t open_wait; + void *private_data; + void (*private_free) (struct snd_hwdep *hwdep); + struct device *dev; + + struct mutex open_mutex; + int used; /* reference counter */ + unsigned int dsp_loaded; /* bit fields of loaded dsp indices */ + unsigned int exclusive:1; /* exclusive access mode */ +}; + +extern int snd_hwdep_new(struct snd_card *card, char *id, int device, + struct snd_hwdep **rhwdep); + +#endif /* __SOUND_HWDEP_H */ diff --git a/include/sound/i2c.h b/include/sound/i2c.h new file mode 100644 index 000000000..6f0162ae9 --- /dev/null +++ b/include/sound/i2c.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_I2C_H +#define __SOUND_I2C_H + +/* + */ + +#define SND_I2C_DEVICE_ADDRTEN (1<<0) /* 10-bit I2C address */ + +struct snd_i2c_device { + struct list_head list; + struct snd_i2c_bus *bus; /* I2C bus */ + char name[32]; /* some useful device name */ + unsigned short flags; /* device flags */ + unsigned short addr; /* device address (might be 10-bit) */ + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_i2c_device *device); +}; + +#define snd_i2c_device(n) list_entry(n, struct snd_i2c_device, list) + +struct snd_i2c_bit_ops { + void (*start)(struct snd_i2c_bus *bus); /* transfer start */ + void (*stop)(struct snd_i2c_bus *bus); /* transfer stop */ + void (*direction)(struct snd_i2c_bus *bus, int clock, int data); /* set line direction (0 = write, 1 = read) */ + void (*setlines)(struct snd_i2c_bus *bus, int clock, int data); + int (*getclock)(struct snd_i2c_bus *bus); + int (*getdata)(struct snd_i2c_bus *bus, int ack); +}; + +struct snd_i2c_ops { + int (*sendbytes)(struct snd_i2c_device *device, unsigned char *bytes, int count); + int (*readbytes)(struct snd_i2c_device *device, unsigned char *bytes, int count); + int (*probeaddr)(struct snd_i2c_bus *bus, unsigned short addr); +}; + +struct snd_i2c_bus { + struct snd_card *card; /* card which I2C belongs to */ + char name[32]; /* some useful label */ + + struct mutex lock_mutex; + + struct snd_i2c_bus *master; /* master bus when SCK/SCL is shared */ + struct list_head buses; /* master: slave buses sharing SCK/SCL, slave: link list */ + + struct list_head devices; /* attached devices to this bus */ + + union { + struct snd_i2c_bit_ops *bit; + void *ops; + } hw_ops; /* lowlevel operations */ + const struct snd_i2c_ops *ops; /* midlevel operations */ + + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_i2c_bus *bus); +}; + +#define snd_i2c_slave_bus(n) list_entry(n, struct snd_i2c_bus, buses) + +int snd_i2c_bus_create(struct snd_card *card, const char *name, + struct snd_i2c_bus *master, struct snd_i2c_bus **ri2c); +int snd_i2c_device_create(struct snd_i2c_bus *bus, const char *name, + unsigned char addr, struct snd_i2c_device **rdevice); +int snd_i2c_device_free(struct snd_i2c_device *device); + +static inline void snd_i2c_lock(struct snd_i2c_bus *bus) +{ + if (bus->master) + mutex_lock(&bus->master->lock_mutex); + else + mutex_lock(&bus->lock_mutex); +} + +static inline void snd_i2c_unlock(struct snd_i2c_bus *bus) +{ + if (bus->master) + mutex_unlock(&bus->master->lock_mutex); + else + mutex_unlock(&bus->lock_mutex); +} + +int snd_i2c_sendbytes(struct snd_i2c_device *device, unsigned char *bytes, int count); +int snd_i2c_readbytes(struct snd_i2c_device *device, unsigned char *bytes, int count); +int snd_i2c_probeaddr(struct snd_i2c_bus *bus, unsigned short addr); + +#endif /* __SOUND_I2C_H */ diff --git a/include/sound/info.h b/include/sound/info.h new file mode 100644 index 000000000..adbc50686 --- /dev/null +++ b/include/sound/info.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_INFO_H +#define __SOUND_INFO_H + +/* + * Header file for info interface + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include +#include + +/* buffer for information */ +struct snd_info_buffer { + char *buffer; /* pointer to begin of buffer */ + unsigned int curr; /* current position in buffer */ + unsigned int size; /* current size */ + unsigned int len; /* total length of buffer */ + int stop; /* stop flag */ + int error; /* error code */ +}; + +#define SNDRV_INFO_CONTENT_TEXT 0 +#define SNDRV_INFO_CONTENT_DATA 1 + +struct snd_info_entry; + +struct snd_info_entry_text { + void (*read)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); + void (*write)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); +}; + +struct snd_info_entry_ops { + int (*open)(struct snd_info_entry *entry, + unsigned short mode, void **file_private_data); + int (*release)(struct snd_info_entry *entry, + unsigned short mode, void *file_private_data); + ssize_t (*read)(struct snd_info_entry *entry, void *file_private_data, + struct file *file, char __user *buf, + size_t count, loff_t pos); + ssize_t (*write)(struct snd_info_entry *entry, void *file_private_data, + struct file *file, const char __user *buf, + size_t count, loff_t pos); + loff_t (*llseek)(struct snd_info_entry *entry, + void *file_private_data, struct file *file, + loff_t offset, int orig); + __poll_t (*poll)(struct snd_info_entry *entry, + void *file_private_data, struct file *file, + poll_table *wait); + int (*ioctl)(struct snd_info_entry *entry, void *file_private_data, + struct file *file, unsigned int cmd, unsigned long arg); + int (*mmap)(struct snd_info_entry *entry, void *file_private_data, + struct inode *inode, struct file *file, + struct vm_area_struct *vma); +}; + +struct snd_info_entry { + const char *name; + umode_t mode; + long size; + unsigned short content; + union { + struct snd_info_entry_text text; + const struct snd_info_entry_ops *ops; + } c; + struct snd_info_entry *parent; + struct module *module; + void *private_data; + void (*private_free)(struct snd_info_entry *entry); + struct proc_dir_entry *p; + struct mutex access; + struct list_head children; + struct list_head list; +}; + +#if defined(CONFIG_SND_OSSEMUL) && defined(CONFIG_SND_PROC_FS) +int snd_info_minor_register(void); +#else +#define snd_info_minor_register() 0 +#endif + + +#ifdef CONFIG_SND_PROC_FS + +extern struct snd_info_entry *snd_seq_root; +#ifdef CONFIG_SND_OSSEMUL +extern struct snd_info_entry *snd_oss_root; +void snd_card_info_read_oss(struct snd_info_buffer *buffer); +#else +#define snd_oss_root NULL +static inline void snd_card_info_read_oss(struct snd_info_buffer *buffer) {} +#endif + +/** + * snd_iprintf - printf on the procfs buffer + * @buf: the procfs buffer + * @fmt: the printf format + * + * Outputs the string on the procfs buffer just like printf(). + * + * Return: zero for success, or a negative error code. + */ +#define snd_iprintf(buf, fmt, args...) \ + seq_printf((struct seq_file *)(buf)->buffer, fmt, ##args) + +int snd_info_init(void); +int snd_info_done(void); + +int snd_info_get_line(struct snd_info_buffer *buffer, char *line, int len); +const char *snd_info_get_str(char *dest, const char *src, int len); +struct snd_info_entry *snd_info_create_module_entry(struct module *module, + const char *name, + struct snd_info_entry *parent); +struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, + const char *name, + struct snd_info_entry *parent); +void snd_info_free_entry(struct snd_info_entry *entry); + +int snd_info_card_create(struct snd_card *card); +int snd_info_card_register(struct snd_card *card); +int snd_info_card_free(struct snd_card *card); +void snd_info_card_disconnect(struct snd_card *card); +void snd_info_card_id_change(struct snd_card *card); +int snd_info_register(struct snd_info_entry *entry); + +/* for card drivers */ +static inline int snd_card_proc_new(struct snd_card *card, const char *name, + struct snd_info_entry **entryp) +{ + *entryp = snd_info_create_card_entry(card, name, card->proc_root); + return *entryp ? 0 : -ENOMEM; +} + +static inline void snd_info_set_text_ops(struct snd_info_entry *entry, + void *private_data, + void (*read)(struct snd_info_entry *, struct snd_info_buffer *)) +{ + entry->private_data = private_data; + entry->c.text.read = read; +} + +int snd_card_rw_proc_new(struct snd_card *card, const char *name, + void *private_data, + void (*read)(struct snd_info_entry *, + struct snd_info_buffer *), + void (*write)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer)); + +int snd_info_check_reserved_words(const char *str); + +#else + +#define snd_seq_root NULL +#define snd_oss_root NULL + +static inline int snd_iprintf(struct snd_info_buffer *buffer, char *fmt, ...) { return 0; } +static inline int snd_info_init(void) { return 0; } +static inline int snd_info_done(void) { return 0; } + +static inline int snd_info_get_line(struct snd_info_buffer *buffer, char *line, int len) { return 0; } +static inline char *snd_info_get_str(char *dest, char *src, int len) { return NULL; } +static inline struct snd_info_entry *snd_info_create_module_entry(struct module *module, const char *name, struct snd_info_entry *parent) { return NULL; } +static inline struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, const char *name, struct snd_info_entry *parent) { return NULL; } +static inline void snd_info_free_entry(struct snd_info_entry *entry) { ; } + +static inline int snd_info_card_create(struct snd_card *card) { return 0; } +static inline int snd_info_card_register(struct snd_card *card) { return 0; } +static inline int snd_info_card_free(struct snd_card *card) { return 0; } +static inline void snd_info_card_disconnect(struct snd_card *card) { } +static inline void snd_info_card_id_change(struct snd_card *card) { } +static inline int snd_info_register(struct snd_info_entry *entry) { return 0; } + +static inline int snd_card_proc_new(struct snd_card *card, const char *name, + struct snd_info_entry **entryp) { return -EINVAL; } +static inline void snd_info_set_text_ops(struct snd_info_entry *entry __attribute__((unused)), + void *private_data, + void (*read)(struct snd_info_entry *, struct snd_info_buffer *)) {} +static inline int snd_card_rw_proc_new(struct snd_card *card, const char *name, + void *private_data, + void (*read)(struct snd_info_entry *, + struct snd_info_buffer *), + void (*write)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer)) +{ + return 0; +} +static inline int snd_info_check_reserved_words(const char *str) { return 1; } + +#endif + +/** + * snd_card_ro_proc_new - Create a read-only text proc file entry for the card + * @card: the card instance + * @name: the file name + * @private_data: the arbitrary private data + * @read: the read callback + * + * This proc file entry will be registered via snd_card_register() call, and + * it will be removed automatically at the card removal, too. + */ +static inline int +snd_card_ro_proc_new(struct snd_card *card, const char *name, + void *private_data, + void (*read)(struct snd_info_entry *, + struct snd_info_buffer *)) +{ + return snd_card_rw_proc_new(card, name, private_data, read, NULL); +} + +/* + * OSS info part + */ + +#if defined(CONFIG_SND_OSSEMUL) && defined(CONFIG_SND_PROC_FS) + +#define SNDRV_OSS_INFO_DEV_AUDIO 0 +#define SNDRV_OSS_INFO_DEV_SYNTH 1 +#define SNDRV_OSS_INFO_DEV_MIDI 2 +#define SNDRV_OSS_INFO_DEV_TIMERS 4 +#define SNDRV_OSS_INFO_DEV_MIXERS 5 + +#define SNDRV_OSS_INFO_DEV_COUNT 6 + +int snd_oss_info_register(int dev, int num, char *string); +#define snd_oss_info_unregister(dev, num) snd_oss_info_register(dev, num, NULL) + +#endif /* CONFIG_SND_OSSEMUL && CONFIG_SND_PROC_FS */ + +#endif /* __SOUND_INFO_H */ diff --git a/include/sound/initval.h b/include/sound/initval.h new file mode 100644 index 000000000..a1ff3b486 --- /dev/null +++ b/include/sound/initval.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_INITVAL_H +#define __SOUND_INITVAL_H + +/* + * Init values for soundcard modules + * Copyright (c) by Jaroslav Kysela + */ + +#define SNDRV_AUTO_PORT 1 +#define SNDRV_AUTO_IRQ 0xffff +#define SNDRV_AUTO_DMA 0xffff +#define SNDRV_AUTO_DMA_SIZE (0x7fffffff) + +#define SNDRV_DEFAULT_IDX1 (-1) +#define SNDRV_DEFAULT_STR1 NULL +#define SNDRV_DEFAULT_ENABLE1 1 +#define SNDRV_DEFAULT_PORT1 SNDRV_AUTO_PORT +#define SNDRV_DEFAULT_IRQ1 SNDRV_AUTO_IRQ +#define SNDRV_DEFAULT_DMA1 SNDRV_AUTO_DMA +#define SNDRV_DEFAULT_DMA_SIZE1 SNDRV_AUTO_DMA_SIZE +#define SNDRV_DEFAULT_PTR1 SNDRV_DEFAULT_STR1 + +#define SNDRV_DEFAULT_IDX { [0 ... (SNDRV_CARDS-1)] = -1 } +#define SNDRV_DEFAULT_STR { [0 ... (SNDRV_CARDS-1)] = NULL } +#define SNDRV_DEFAULT_ENABLE { 1, [1 ... (SNDRV_CARDS-1)] = 0 } +#define SNDRV_DEFAULT_ENABLE_PNP { [0 ... (SNDRV_CARDS-1)] = 1 } +#ifdef CONFIG_PNP +#define SNDRV_DEFAULT_ENABLE_ISAPNP SNDRV_DEFAULT_ENABLE_PNP +#else +#define SNDRV_DEFAULT_ENABLE_ISAPNP SNDRV_DEFAULT_ENABLE +#endif +#define SNDRV_DEFAULT_PORT { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_PORT } +#define SNDRV_DEFAULT_IRQ { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_IRQ } +#define SNDRV_DEFAULT_DMA { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA } +#define SNDRV_DEFAULT_DMA_SIZE { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA_SIZE } +#define SNDRV_DEFAULT_PTR SNDRV_DEFAULT_STR + +#ifdef SNDRV_LEGACY_FIND_FREE_IOPORT +static long snd_legacy_find_free_ioport(const long *port_table, long size) +{ + while (*port_table != -1) { + if (request_region(*port_table, size, "ALSA test")) { + release_region(*port_table, size); + return *port_table; + } + port_table++; + } + return -1; +} +#endif + +#ifdef SNDRV_LEGACY_FIND_FREE_IRQ +#include + +static irqreturn_t snd_legacy_empty_irq_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static int snd_legacy_find_free_irq(const int *irq_table) +{ + while (*irq_table != -1) { + if (!request_irq(*irq_table, snd_legacy_empty_irq_handler, + IRQF_PROBE_SHARED, "ALSA Test IRQ", + (void *) irq_table)) { + free_irq(*irq_table, (void *) irq_table); + return *irq_table; + } + irq_table++; + } + return -1; +} +#endif + +#ifdef SNDRV_LEGACY_FIND_FREE_DMA +static int snd_legacy_find_free_dma(const int *dma_table) +{ + while (*dma_table != -1) { + if (!request_dma(*dma_table, "ALSA Test DMA")) { + free_dma(*dma_table); + return *dma_table; + } + dma_table++; + } + return -1; +} +#endif + +#endif /* __SOUND_INITVAL_H */ diff --git a/include/sound/intel-dsp-config.h b/include/sound/intel-dsp-config.h new file mode 100644 index 000000000..34c975910 --- /dev/null +++ b/include/sound/intel-dsp-config.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * intel-dsp-config.h - Intel DSP config + * + * Copyright (c) 2019 Jaroslav Kysela + */ + +#ifndef __INTEL_DSP_CONFIG_H__ +#define __INTEL_DSP_CONFIG_H__ + +struct pci_dev; + +enum { + SND_INTEL_DSP_DRIVER_ANY = 0, + SND_INTEL_DSP_DRIVER_LEGACY, + SND_INTEL_DSP_DRIVER_SST, + SND_INTEL_DSP_DRIVER_SOF, + SND_INTEL_DSP_DRIVER_AVS, + SND_INTEL_DSP_DRIVER_LAST = SND_INTEL_DSP_DRIVER_AVS +}; + +#if IS_ENABLED(CONFIG_SND_INTEL_DSP_CONFIG) + +int snd_intel_dsp_driver_probe(struct pci_dev *pci); +int snd_intel_acpi_dsp_driver_probe(struct device *dev, const u8 acpi_hid[ACPI_ID_LEN]); + +#else + +static inline int snd_intel_dsp_driver_probe(struct pci_dev *pci) +{ + return SND_INTEL_DSP_DRIVER_ANY; +} + +static inline +int snd_intel_acpi_dsp_driver_probe(struct device *dev, const u8 acpi_hid[ACPI_ID_LEN]) +{ + return SND_INTEL_DSP_DRIVER_ANY; +} + +#endif + +#endif diff --git a/include/sound/intel-nhlt.h b/include/sound/intel-nhlt.h new file mode 100644 index 000000000..24dbe1668 --- /dev/null +++ b/include/sound/intel-nhlt.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * intel-nhlt.h - Intel HDA Platform NHLT header + * + * Copyright (c) 2015-2019 Intel Corporation + */ + +#ifndef __INTEL_NHLT_H__ +#define __INTEL_NHLT_H__ + +#include + +enum nhlt_link_type { + NHLT_LINK_HDA = 0, + NHLT_LINK_DSP = 1, + NHLT_LINK_DMIC = 2, + NHLT_LINK_SSP = 3, + NHLT_LINK_INVALID +}; + +enum nhlt_device_type { + NHLT_DEVICE_BT = 0, + NHLT_DEVICE_DMIC = 1, + NHLT_DEVICE_I2S = 4, + NHLT_DEVICE_INVALID +}; + +struct wav_fmt { + u16 fmt_tag; + u16 channels; + u32 samples_per_sec; + u32 avg_bytes_per_sec; + u16 block_align; + u16 bits_per_sample; + u16 cb_size; +} __packed; + +struct wav_fmt_ext { + struct wav_fmt fmt; + union samples { + u16 valid_bits_per_sample; + u16 samples_per_block; + u16 reserved; + } sample; + u32 channel_mask; + u8 sub_fmt[16]; +} __packed; + +struct nhlt_specific_cfg { + u32 size; + u8 caps[]; +} __packed; + +struct nhlt_fmt_cfg { + struct wav_fmt_ext fmt_ext; + struct nhlt_specific_cfg config; +} __packed; + +struct nhlt_fmt { + u8 fmt_count; + struct nhlt_fmt_cfg fmt_config[]; +} __packed; + +struct nhlt_endpoint { + u32 length; + u8 linktype; + u8 instance_id; + u16 vendor_id; + u16 device_id; + u16 revision_id; + u32 subsystem_id; + u8 device_type; + u8 direction; + u8 virtual_bus_id; + struct nhlt_specific_cfg config; +} __packed; + +struct nhlt_acpi_table { + struct acpi_table_header header; + u8 endpoint_count; + struct nhlt_endpoint desc[]; +} __packed; + +struct nhlt_resource_desc { + u32 extra; + u16 flags; + u64 addr_spc_gra; + u64 min_addr; + u64 max_addr; + u64 addr_trans_offset; + u64 length; +} __packed; + +#define MIC_ARRAY_2CH 2 +#define MIC_ARRAY_4CH 4 + +struct nhlt_device_specific_config { + u8 virtual_slot; + u8 config_type; +} __packed; + +struct nhlt_dmic_array_config { + struct nhlt_device_specific_config device_config; + u8 array_type; +} __packed; + +struct nhlt_vendor_dmic_array_config { + struct nhlt_dmic_array_config dmic_config; + u8 nb_mics; + /* TODO add vendor mic config */ +} __packed; + +enum { + NHLT_CONFIG_TYPE_GENERIC = 0, + NHLT_CONFIG_TYPE_MIC_ARRAY = 1 +}; + +enum { + NHLT_MIC_ARRAY_2CH_SMALL = 0xa, + NHLT_MIC_ARRAY_2CH_BIG = 0xb, + NHLT_MIC_ARRAY_4CH_1ST_GEOM = 0xc, + NHLT_MIC_ARRAY_4CH_L_SHAPED = 0xd, + NHLT_MIC_ARRAY_4CH_2ND_GEOM = 0xe, + NHLT_MIC_ARRAY_VENDOR_DEFINED = 0xf, +}; + +#if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SND_INTEL_NHLT) + +struct nhlt_acpi_table *intel_nhlt_init(struct device *dev); + +void intel_nhlt_free(struct nhlt_acpi_table *addr); + +int intel_nhlt_get_dmic_geo(struct device *dev, struct nhlt_acpi_table *nhlt); + +bool intel_nhlt_has_endpoint_type(struct nhlt_acpi_table *nhlt, u8 link_type); + +int intel_nhlt_ssp_endpoint_mask(struct nhlt_acpi_table *nhlt, u8 device_type); + +int intel_nhlt_ssp_mclk_mask(struct nhlt_acpi_table *nhlt, int ssp_num); + +struct nhlt_specific_cfg * +intel_nhlt_get_endpoint_blob(struct device *dev, struct nhlt_acpi_table *nhlt, + u32 bus_id, u8 link_type, u8 vbps, u8 bps, + u8 num_ch, u32 rate, u8 dir, u8 dev_type); + +int intel_nhlt_ssp_device_type(struct device *dev, struct nhlt_acpi_table *nhlt, + u8 virtual_bus_id); + +#else + +static inline struct nhlt_acpi_table *intel_nhlt_init(struct device *dev) +{ + return NULL; +} + +static inline void intel_nhlt_free(struct nhlt_acpi_table *addr) +{ +} + +static inline int intel_nhlt_get_dmic_geo(struct device *dev, + struct nhlt_acpi_table *nhlt) +{ + return 0; +} + +static inline bool intel_nhlt_has_endpoint_type(struct nhlt_acpi_table *nhlt, + u8 link_type) +{ + return false; +} + +static inline int intel_nhlt_ssp_endpoint_mask(struct nhlt_acpi_table *nhlt, u8 device_type) +{ + return 0; +} + +static inline int intel_nhlt_ssp_mclk_mask(struct nhlt_acpi_table *nhlt, int ssp_num) +{ + return 0; +} + +static inline struct nhlt_specific_cfg * +intel_nhlt_get_endpoint_blob(struct device *dev, struct nhlt_acpi_table *nhlt, + u32 bus_id, u8 link_type, u8 vbps, u8 bps, + u8 num_ch, u32 rate, u8 dir, u8 dev_type) +{ + return NULL; +} + +static inline int intel_nhlt_ssp_device_type(struct device *dev, + struct nhlt_acpi_table *nhlt, + u8 virtual_bus_id) +{ + return -EINVAL; +} + +#endif + +#endif diff --git a/include/sound/jack.h b/include/sound/jack.h new file mode 100644 index 000000000..715b95983 --- /dev/null +++ b/include/sound/jack.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_JACK_H +#define __SOUND_JACK_H + +/* + * Jack abstraction layer + * + * Copyright 2008 Wolfson Microelectronics plc + */ + +#include + +struct input_dev; + +/** + * enum snd_jack_types - Jack types which can be reported + * @SND_JACK_HEADPHONE: Headphone + * @SND_JACK_MICROPHONE: Microphone + * @SND_JACK_HEADSET: Headset + * @SND_JACK_LINEOUT: Line out + * @SND_JACK_MECHANICAL: Mechanical switch + * @SND_JACK_VIDEOOUT: Video out + * @SND_JACK_AVOUT: AV (Audio Video) out + * @SND_JACK_LINEIN: Line in + * @SND_JACK_USB: USB audio device + * @SND_JACK_BTN_0: Button 0 + * @SND_JACK_BTN_1: Button 1 + * @SND_JACK_BTN_2: Button 2 + * @SND_JACK_BTN_3: Button 3 + * @SND_JACK_BTN_4: Button 4 + * @SND_JACK_BTN_5: Button 5 + * + * These values are used as a bitmask. + * + * Note that this must be kept in sync with the lookup table in + * sound/core/jack.c. + */ +enum snd_jack_types { + SND_JACK_HEADPHONE = 0x0001, + SND_JACK_MICROPHONE = 0x0002, + SND_JACK_HEADSET = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE, + SND_JACK_LINEOUT = 0x0004, + SND_JACK_MECHANICAL = 0x0008, /* If detected separately */ + SND_JACK_VIDEOOUT = 0x0010, + SND_JACK_AVOUT = SND_JACK_LINEOUT | SND_JACK_VIDEOOUT, + SND_JACK_LINEIN = 0x0020, + SND_JACK_USB = 0x0040, + + /* Kept separate from switches to facilitate implementation */ + SND_JACK_BTN_0 = 0x4000, + SND_JACK_BTN_1 = 0x2000, + SND_JACK_BTN_2 = 0x1000, + SND_JACK_BTN_3 = 0x0800, + SND_JACK_BTN_4 = 0x0400, + SND_JACK_BTN_5 = 0x0200, +}; + +/* Keep in sync with definitions above */ +#define SND_JACK_SWITCH_TYPES 7 + +struct snd_jack { + struct list_head kctl_list; + struct snd_card *card; + const char *id; +#ifdef CONFIG_SND_JACK_INPUT_DEV + struct input_dev *input_dev; + struct mutex input_dev_lock; + int registered; + int type; + char name[100]; + unsigned int key[6]; /* Keep in sync with definitions above */ +#endif /* CONFIG_SND_JACK_INPUT_DEV */ + int hw_status_cache; + void *private_data; + void (*private_free)(struct snd_jack *); +}; + +#ifdef CONFIG_SND_JACK + +int snd_jack_new(struct snd_card *card, const char *id, int type, + struct snd_jack **jack, bool initial_kctl, bool phantom_jack); +int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask); +#ifdef CONFIG_SND_JACK_INPUT_DEV +int snd_jack_set_key(struct snd_jack *jack, enum snd_jack_types type, + int keytype); +#endif +void snd_jack_report(struct snd_jack *jack, int status); + +#else +static inline int snd_jack_new(struct snd_card *card, const char *id, int type, + struct snd_jack **jack, bool initial_kctl, bool phantom_jack) +{ + return 0; +} + +static inline int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask) +{ + return 0; +} + +static inline void snd_jack_report(struct snd_jack *jack, int status) +{ +} + +#endif + +#if !defined(CONFIG_SND_JACK) || !defined(CONFIG_SND_JACK_INPUT_DEV) +static inline int snd_jack_set_key(struct snd_jack *jack, + enum snd_jack_types type, + int keytype) +{ + return 0; +} +#endif /* !CONFIG_SND_JACK || !CONFIG_SND_JACK_INPUT_DEV */ + +#endif diff --git a/include/sound/madera-pdata.h b/include/sound/madera-pdata.h new file mode 100644 index 000000000..58398d80c --- /dev/null +++ b/include/sound/madera-pdata.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Platform data for Madera codec driver + * + * Copyright (C) 2016-2019 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef MADERA_CODEC_PDATA_H +#define MADERA_CODEC_PDATA_H + +#include + +#define MADERA_MAX_INPUT 6 +#define MADERA_MAX_MUXED_CHANNELS 4 +#define MADERA_MAX_OUTPUT 6 +#define MADERA_MAX_AIF 4 +#define MADERA_MAX_PDM_SPK 2 +#define MADERA_MAX_DSP 7 + +/** + * struct madera_codec_pdata + * + * @max_channels_clocked: Maximum number of channels that I2S clocks will be + * generated for. Useful when clock master for systems + * where the I2S bus has multiple data lines. + * @dmic_ref: Indicates how the MICBIAS pins have been externally + * connected to DMICs on each input. A value of 0 + * indicates MICVDD and is the default. Other values are: + * For CS47L35 one of the CS47L35_DMIC_REF_xxx values + * For all other codecs one of the MADERA_DMIC_REF_xxx + * Also see the datasheet for a description of the + * INn_DMIC_SUP field. + * @inmode: Mode for the ADC inputs. One of the MADERA_INMODE_xxx + * values. Two-dimensional array + * [input_number][channel number], with four slots per + * input in the order + * [n][0]=INnAL [n][1]=INnAR [n][2]=INnBL [n][3]=INnBR + * @out_mono: For each output set the value to TRUE to indicate that + * the output is mono. [0]=OUT1, [1]=OUT2, ... + * @pdm_fmt: PDM speaker data format. See the PDM_SPKn_FMT field in + * the datasheet for a description of this value. + * @pdm_mute: PDM mute format. See the PDM_SPKn_CTRL_1 register + * in the datasheet for a description of this value. + */ +struct madera_codec_pdata { + u32 max_channels_clocked[MADERA_MAX_AIF]; + + u32 dmic_ref[MADERA_MAX_INPUT]; + + u32 inmode[MADERA_MAX_INPUT][MADERA_MAX_MUXED_CHANNELS]; + + bool out_mono[MADERA_MAX_OUTPUT]; + + u32 pdm_fmt[MADERA_MAX_PDM_SPK]; + u32 pdm_mute[MADERA_MAX_PDM_SPK]; +}; + +#endif diff --git a/include/sound/max9768.h b/include/sound/max9768.h new file mode 100644 index 000000000..8509ba007 --- /dev/null +++ b/include/sound/max9768.h @@ -0,0 +1,20 @@ +/* + * Platform data for MAX9768 + * Copyright (C) 2011, 2012 by Wolfram Sang, Pengutronix e.K. + * same licence as the driver + */ + +#ifndef __SOUND_MAX9768_PDATA_H__ +#define __SOUND_MAX9768_PDATA_H__ + +/** + * struct max9768_pdata - optional platform specific MAX9768 configuration + * @flags: configuration flags, e.g. set classic PWM mode (check datasheet + * regarding "filterless modulation" which is default). + */ +struct max9768_pdata { + unsigned flags; +#define MAX9768_FLAG_CLASSIC_PWM (1 << 0) +}; + +#endif /* __SOUND_MAX9768_PDATA_H__*/ diff --git a/include/sound/max98088.h b/include/sound/max98088.h new file mode 100644 index 000000000..76b376919 --- /dev/null +++ b/include/sound/max98088.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for MAX98088 + * + * Copyright 2010 Maxim Integrated Products + */ + +#ifndef __SOUND_MAX98088_PDATA_H__ +#define __SOUND_MAX98088_PDATA_H__ + +/* Equalizer filter response configuration */ +struct max98088_eq_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; + u16 band3[5]; + u16 band4[5]; + u16 band5[5]; +}; + +/* codec platform data */ +struct max98088_pdata { + + /* Equalizers for DAI1 and DAI2 */ + struct max98088_eq_cfg *eq_cfg; + unsigned int eq_cfgcnt; + + /* Receiver output can be configured as power amplifier or LINE out */ + /* Set receiver_mode to: + * 0 = amplifier output, or + * 1 = LINE level output + */ + unsigned int receiver_mode:1; + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microphone input + */ + unsigned int digmic_left_mode:1; + unsigned int digmic_right_mode:1; + +}; + +#endif diff --git a/include/sound/max98090.h b/include/sound/max98090.h new file mode 100644 index 000000000..6bc1b014f --- /dev/null +++ b/include/sound/max98090.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for MAX98090 + * + * Copyright 2011-2012 Maxim Integrated Products + */ + +#ifndef __SOUND_MAX98090_PDATA_H__ +#define __SOUND_MAX98090_PDATA_H__ + +/* codec platform data */ +struct max98090_pdata { + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microphone input + */ + unsigned int digmic_left_mode:1; + unsigned int digmic_right_mode:1; + unsigned int digmic_3_mode:1; + unsigned int digmic_4_mode:1; +}; + +#endif diff --git a/include/sound/max98095.h b/include/sound/max98095.h new file mode 100644 index 000000000..731c88551 --- /dev/null +++ b/include/sound/max98095.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for MAX98095 + * + * Copyright 2011 Maxim Integrated Products + */ + +#ifndef __SOUND_MAX98095_PDATA_H__ +#define __SOUND_MAX98095_PDATA_H__ + +/* Equalizer filter response configuration */ +struct max98095_eq_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; + u16 band3[5]; + u16 band4[5]; + u16 band5[5]; +}; + +/* Biquad filter response configuration */ +struct max98095_biquad_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; +}; + +/* codec platform data */ +struct max98095_pdata { + + /* Equalizers for DAI1 and DAI2 */ + struct max98095_eq_cfg *eq_cfg; + unsigned int eq_cfgcnt; + + /* Biquad filter for DAI1 and DAI2 */ + struct max98095_biquad_cfg *bq_cfg; + unsigned int bq_cfgcnt; + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microphone input + */ + unsigned int digmic_left_mode:1; + unsigned int digmic_right_mode:1; + + /* Pin5 is the mechanical method of sensing jack insertion + * but it is something that might not be supported. + * 0 = PIN5 not supported + * 1 = PIN5 supported + */ + unsigned int jack_detect_pin5en:1; + + /* Slew amount for jack detection. Calculated as 4 * (delay + 1). + * Default delay is 24 to get a time of 100ms. + */ + unsigned int jack_detect_delay; +}; + +#endif diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h new file mode 100644 index 000000000..9dd475cf4 --- /dev/null +++ b/include/sound/memalloc.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) by Jaroslav Kysela + * Takashi Iwai + * + * Generic memory allocators + */ + +#ifndef __SOUND_MEMALLOC_H +#define __SOUND_MEMALLOC_H + +#include +#include + +struct device; +struct vm_area_struct; +struct sg_table; + +/* + * buffer device info + */ +struct snd_dma_device { + int type; /* SNDRV_DMA_TYPE_XXX */ + enum dma_data_direction dir; /* DMA direction */ + bool need_sync; /* explicit sync needed? */ + struct device *dev; /* generic device */ +}; + +/* + * buffer types + */ +#define SNDRV_DMA_TYPE_UNKNOWN 0 /* not defined */ +#define SNDRV_DMA_TYPE_CONTINUOUS 1 /* continuous no-DMA memory */ +#define SNDRV_DMA_TYPE_DEV 2 /* generic device continuous */ +#define SNDRV_DMA_TYPE_DEV_WC 5 /* continuous write-combined */ +#ifdef CONFIG_GENERIC_ALLOCATOR +#define SNDRV_DMA_TYPE_DEV_IRAM 4 /* generic device iram-buffer */ +#else +#define SNDRV_DMA_TYPE_DEV_IRAM SNDRV_DMA_TYPE_DEV +#endif +#define SNDRV_DMA_TYPE_VMALLOC 7 /* vmalloc'ed buffer */ +#define SNDRV_DMA_TYPE_NONCONTIG 8 /* non-coherent SG buffer */ +#define SNDRV_DMA_TYPE_NONCOHERENT 9 /* non-coherent buffer */ +#ifdef CONFIG_SND_DMA_SGBUF +#define SNDRV_DMA_TYPE_DEV_SG 3 /* S/G pages */ +#define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */ +#else +#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */ +#define SNDRV_DMA_TYPE_DEV_WC_SG SNDRV_DMA_TYPE_DEV_WC +#endif + +/* + * info for buffer allocation + */ +struct snd_dma_buffer { + struct snd_dma_device dev; /* device type */ + unsigned char *area; /* virtual pointer */ + dma_addr_t addr; /* physical address */ + size_t bytes; /* buffer size in bytes */ + void *private_data; /* private for allocator; don't touch */ +}; + +/* + * return the pages matching with the given byte size + */ +static inline unsigned int snd_sgbuf_aligned_pages(size_t size) +{ + return (size + PAGE_SIZE - 1) >> PAGE_SHIFT; +} + +/* allocate/release a buffer */ +int snd_dma_alloc_dir_pages(int type, struct device *dev, + enum dma_data_direction dir, size_t size, + struct snd_dma_buffer *dmab); + +static inline int snd_dma_alloc_pages(int type, struct device *dev, + size_t size, struct snd_dma_buffer *dmab) +{ + return snd_dma_alloc_dir_pages(type, dev, DMA_BIDIRECTIONAL, size, dmab); +} + +int snd_dma_alloc_pages_fallback(int type, struct device *dev, size_t size, + struct snd_dma_buffer *dmab); +void snd_dma_free_pages(struct snd_dma_buffer *dmab); +int snd_dma_buffer_mmap(struct snd_dma_buffer *dmab, + struct vm_area_struct *area); + +enum snd_dma_sync_mode { SNDRV_DMA_SYNC_CPU, SNDRV_DMA_SYNC_DEVICE }; +#ifdef CONFIG_HAS_DMA +void snd_dma_buffer_sync(struct snd_dma_buffer *dmab, + enum snd_dma_sync_mode mode); +#else +static inline void snd_dma_buffer_sync(struct snd_dma_buffer *dmab, + enum snd_dma_sync_mode mode) {} +#endif + +dma_addr_t snd_sgbuf_get_addr(struct snd_dma_buffer *dmab, size_t offset); +struct page *snd_sgbuf_get_page(struct snd_dma_buffer *dmab, size_t offset); +unsigned int snd_sgbuf_get_chunk_size(struct snd_dma_buffer *dmab, + unsigned int ofs, unsigned int size); + +/* device-managed memory allocator */ +struct snd_dma_buffer *snd_devm_alloc_dir_pages(struct device *dev, int type, + enum dma_data_direction dir, + size_t size); + +static inline struct snd_dma_buffer * +snd_devm_alloc_pages(struct device *dev, int type, size_t size) +{ + return snd_devm_alloc_dir_pages(dev, type, DMA_BIDIRECTIONAL, size); +} + +static inline struct sg_table * +snd_dma_noncontig_sg_table(struct snd_dma_buffer *dmab) +{ + return dmab->private_data; +} + +#endif /* __SOUND_MEMALLOC_H */ + diff --git a/include/sound/minors.h b/include/sound/minors.h new file mode 100644 index 000000000..2b0395693 --- /dev/null +++ b/include/sound/minors.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_MINORS_H +#define __SOUND_MINORS_H + +/* + * MINOR numbers + */ + +#define SNDRV_OS_MINORS 256 + +#define SNDRV_MINOR_DEVICES 32 +#define SNDRV_MINOR_CARD(minor) ((minor) >> 5) +#define SNDRV_MINOR_DEVICE(minor) ((minor) & 0x001f) +#define SNDRV_MINOR(card, dev) (((card) << 5) | (dev)) + +/* these minors can still be used for autoloading devices (/dev/aload*) */ +#define SNDRV_MINOR_CONTROL 0 /* 0 */ +#define SNDRV_MINOR_GLOBAL 1 /* 1 */ +#define SNDRV_MINOR_SEQUENCER 1 /* SNDRV_MINOR_GLOBAL + 0 * 32 */ +#define SNDRV_MINOR_TIMER 33 /* SNDRV_MINOR_GLOBAL + 1 * 32 */ + +#ifndef CONFIG_SND_DYNAMIC_MINORS +#define SNDRV_MINOR_COMPRESS 2 /* 2 - 3 */ +#define SNDRV_MINOR_HWDEP 4 /* 4 - 7 */ +#define SNDRV_MINOR_RAWMIDI 8 /* 8 - 15 */ +#define SNDRV_MINOR_PCM_PLAYBACK 16 /* 16 - 23 */ +#define SNDRV_MINOR_PCM_CAPTURE 24 /* 24 - 31 */ + +/* same as first respective minor number to make minor allocation easier */ +#define SNDRV_DEVICE_TYPE_CONTROL SNDRV_MINOR_CONTROL +#define SNDRV_DEVICE_TYPE_HWDEP SNDRV_MINOR_HWDEP +#define SNDRV_DEVICE_TYPE_RAWMIDI SNDRV_MINOR_RAWMIDI +#define SNDRV_DEVICE_TYPE_PCM_PLAYBACK SNDRV_MINOR_PCM_PLAYBACK +#define SNDRV_DEVICE_TYPE_PCM_CAPTURE SNDRV_MINOR_PCM_CAPTURE +#define SNDRV_DEVICE_TYPE_SEQUENCER SNDRV_MINOR_SEQUENCER +#define SNDRV_DEVICE_TYPE_TIMER SNDRV_MINOR_TIMER +#define SNDRV_DEVICE_TYPE_COMPRESS SNDRV_MINOR_COMPRESS + +#else /* CONFIG_SND_DYNAMIC_MINORS */ + +enum { + SNDRV_DEVICE_TYPE_CONTROL, + SNDRV_DEVICE_TYPE_SEQUENCER, + SNDRV_DEVICE_TYPE_TIMER, + SNDRV_DEVICE_TYPE_HWDEP, + SNDRV_DEVICE_TYPE_RAWMIDI, + SNDRV_DEVICE_TYPE_PCM_PLAYBACK, + SNDRV_DEVICE_TYPE_PCM_CAPTURE, + SNDRV_DEVICE_TYPE_COMPRESS, +}; + +#endif /* CONFIG_SND_DYNAMIC_MINORS */ + +#define SNDRV_MINOR_HWDEPS 4 +#define SNDRV_MINOR_RAWMIDIS 8 +#define SNDRV_MINOR_PCMS 8 + + +#ifdef CONFIG_SND_OSSEMUL + +#define SNDRV_MINOR_OSS_DEVICES 16 +#define SNDRV_MINOR_OSS_CARD(minor) ((minor) >> 4) +#define SNDRV_MINOR_OSS_DEVICE(minor) ((minor) & 0x000f) +#define SNDRV_MINOR_OSS(card, dev) (((card) << 4) | (dev)) + +#define SNDRV_MINOR_OSS_MIXER 0 /* /dev/mixer - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_SEQUENCER 1 /* /dev/sequencer - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_MIDI 2 /* /dev/midi - native midi interface - OSS 3.XX compatible - UART */ +#define SNDRV_MINOR_OSS_PCM 3 /* alias */ +#define SNDRV_MINOR_OSS_PCM_8 3 /* /dev/dsp - 8bit PCM - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_AUDIO 4 /* /dev/audio - SunSparc compatible */ +#define SNDRV_MINOR_OSS_PCM_16 5 /* /dev/dsp16 - 16bit PCM - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_SNDSTAT 6 /* /dev/sndstat - for compatibility with OSS */ +#define SNDRV_MINOR_OSS_RESERVED7 7 /* reserved for future use */ +#define SNDRV_MINOR_OSS_MUSIC 8 /* /dev/music - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_DMMIDI 9 /* /dev/dmmidi0 - this device can have another minor # with OSS */ +#define SNDRV_MINOR_OSS_DMFM 10 /* /dev/dmfm0 - this device can have another minor # with OSS */ +#define SNDRV_MINOR_OSS_MIXER1 11 /* alternate mixer */ +#define SNDRV_MINOR_OSS_PCM1 12 /* alternate PCM (GF-A-1) */ +#define SNDRV_MINOR_OSS_MIDI1 13 /* alternate midi - SYNTH */ +#define SNDRV_MINOR_OSS_DMMIDI1 14 /* alternate dmmidi - SYNTH */ +#define SNDRV_MINOR_OSS_RESERVED15 15 /* reserved for future use */ + +#define SNDRV_OSS_DEVICE_TYPE_MIXER 0 +#define SNDRV_OSS_DEVICE_TYPE_SEQUENCER 1 +#define SNDRV_OSS_DEVICE_TYPE_PCM 2 +#define SNDRV_OSS_DEVICE_TYPE_MIDI 3 +#define SNDRV_OSS_DEVICE_TYPE_DMFM 4 +#define SNDRV_OSS_DEVICE_TYPE_SNDSTAT 5 +#define SNDRV_OSS_DEVICE_TYPE_MUSIC 6 + +#define MODULE_ALIAS_SNDRV_MINOR(type) \ + MODULE_ALIAS("sound-service-?-" __stringify(type)) + +#endif + +#endif /* __SOUND_MINORS_H */ diff --git a/include/sound/mixer_oss.h b/include/sound/mixer_oss.h new file mode 100644 index 000000000..9a212c0ce --- /dev/null +++ b/include/sound/mixer_oss.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_MIXER_OSS_H +#define __SOUND_MIXER_OSS_H + +/* + * OSS MIXER API + * Copyright (c) by Jaroslav Kysela + */ + +#if IS_ENABLED(CONFIG_SND_MIXER_OSS) + +#define SNDRV_OSS_MAX_MIXERS 32 + +struct snd_mixer_oss_file; + +struct snd_mixer_oss_slot { + int number; + unsigned int stereo: 1; + int (*get_volume)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int *left, int *right); + int (*put_volume)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int left, int right); + int (*get_recsrc)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int *active); + int (*put_recsrc)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int active); + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_mixer_oss_slot *slot); + int volume[2]; +}; + +struct snd_mixer_oss { + struct snd_card *card; + char id[16]; + char name[32]; + struct snd_mixer_oss_slot slots[SNDRV_OSS_MAX_MIXERS]; /* OSS mixer slots */ + unsigned int mask_recsrc; /* exclusive recsrc mask */ + int (*get_recsrc)(struct snd_mixer_oss_file *fmixer, + unsigned int *active_index); + int (*put_recsrc)(struct snd_mixer_oss_file *fmixer, + unsigned int active_index); + void *private_data_recsrc; + void (*private_free_recsrc)(struct snd_mixer_oss *mixer); + struct mutex reg_mutex; + struct snd_info_entry *proc_entry; + int oss_dev_alloc; + /* --- */ + int oss_recsrc; +}; + +struct snd_mixer_oss_file { + struct snd_card *card; + struct snd_mixer_oss *mixer; +}; + +int snd_mixer_oss_ioctl_card(struct snd_card *card, + unsigned int cmd, unsigned long arg); + +#endif /* CONFIG_SND_MIXER_OSS */ + +#endif /* __SOUND_MIXER_OSS_H */ diff --git a/include/sound/mpu401.h b/include/sound/mpu401.h new file mode 100644 index 000000000..d4c915a37 --- /dev/null +++ b/include/sound/mpu401.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_MPU401_H +#define __SOUND_MPU401_H + +/* + * Header file for MPU-401 and compatible cards + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include + +#define MPU401_HW_MPU401 1 /* native MPU401 */ +#define MPU401_HW_SB 2 /* SoundBlaster MPU-401 UART */ +#define MPU401_HW_ES1688 3 /* AudioDrive ES1688 MPU-401 UART */ +#define MPU401_HW_OPL3SA2 4 /* Yamaha OPL3-SA2 */ +#define MPU401_HW_SONICVIBES 5 /* S3 SonicVibes */ +#define MPU401_HW_CS4232 6 /* CS4232 */ +#define MPU401_HW_ES18XX 7 /* AudioDrive ES18XX MPU-401 UART */ +#define MPU401_HW_FM801 8 /* ForteMedia FM801 */ +#define MPU401_HW_TRID4DWAVE 9 /* Trident 4DWave */ +#define MPU401_HW_AZT2320 10 /* Aztech AZT2320 */ +#define MPU401_HW_ALS100 11 /* Avance Logic ALS100 */ +#define MPU401_HW_ICE1712 12 /* Envy24 */ +#define MPU401_HW_VIA686A 13 /* VIA 82C686A */ +#define MPU401_HW_YMFPCI 14 /* YMF DS-XG PCI */ +#define MPU401_HW_CMIPCI 15 /* CMIPCI MPU-401 UART */ +#define MPU401_HW_ALS4000 16 /* Avance Logic ALS4000 */ +#define MPU401_HW_INTEL8X0 17 /* Intel8x0 driver */ +#define MPU401_HW_PC98II 18 /* Roland PC98II */ +#define MPU401_HW_AUREAL 19 /* Aureal Vortex */ + +#define MPU401_INFO_INPUT (1 << 0) /* input stream */ +#define MPU401_INFO_OUTPUT (1 << 1) /* output stream */ +#define MPU401_INFO_INTEGRATED (1 << 2) /* integrated h/w port */ +#define MPU401_INFO_MMIO (1 << 3) /* MMIO access */ +#define MPU401_INFO_TX_IRQ (1 << 4) /* independent TX irq */ +#define MPU401_INFO_IRQ_HOOK (1 << 5) /* mpu401 irq handler is called + from driver irq handler */ +#define MPU401_INFO_NO_ACK (1 << 6) /* No ACK cmd needed */ +#define MPU401_INFO_USE_TIMER (1 << 15) /* internal */ + +#define MPU401_MODE_BIT_INPUT 0 +#define MPU401_MODE_BIT_OUTPUT 1 +#define MPU401_MODE_BIT_INPUT_TRIGGER 2 +#define MPU401_MODE_BIT_OUTPUT_TRIGGER 3 + +#define MPU401_MODE_INPUT (1<cport +#define MPU401D(mpu) (mpu)->port + +/* + * control register bits + */ +/* read MPU401C() */ +#define MPU401_RX_EMPTY 0x80 +#define MPU401_TX_FULL 0x40 + +/* write MPU401C() */ +#define MPU401_RESET 0xff +#define MPU401_ENTER_UART 0x3f + +/* read MPU401D() */ +#define MPU401_ACK 0xfe + + +/* + + */ + +irqreturn_t snd_mpu401_uart_interrupt(int irq, void *dev_id); +irqreturn_t snd_mpu401_uart_interrupt_tx(int irq, void *dev_id); + +int snd_mpu401_uart_new(struct snd_card *card, + int device, + unsigned short hardware, + unsigned long port, + unsigned int info_flags, + int irq, + struct snd_rawmidi ** rrawmidi); + +#endif /* __SOUND_MPU401_H */ diff --git a/include/sound/omap-hdmi-audio.h b/include/sound/omap-hdmi-audio.h new file mode 100644 index 000000000..e5f82044a --- /dev/null +++ b/include/sound/omap-hdmi-audio.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * hdmi-audio.c -- OMAP4+ DSS HDMI audio support library + * + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com + * + * Author: Jyri Sarha + */ + +#ifndef __OMAP_HDMI_AUDIO_H__ +#define __OMAP_HDMI_AUDIO_H__ + +#include + +struct omap_dss_audio { + struct snd_aes_iec958 *iec; + struct snd_cea_861_aud_if *cea; +}; + +struct omap_hdmi_audio_ops { + int (*audio_startup)(struct device *dev, + void (*abort_cb)(struct device *dev)); + int (*audio_shutdown)(struct device *dev); + int (*audio_start)(struct device *dev); + void (*audio_stop)(struct device *dev); + int (*audio_config)(struct device *dev, + struct omap_dss_audio *dss_audio); +}; + +/* HDMI audio initalization data */ +struct omap_hdmi_audio_pdata { + struct device *dev; + unsigned int version; + phys_addr_t audio_dma_addr; + + const struct omap_hdmi_audio_ops *ops; +}; + +#endif /* __OMAP_HDMI_AUDIO_H__ */ diff --git a/include/sound/opl3.h b/include/sound/opl3.h new file mode 100644 index 000000000..052395a2f --- /dev/null +++ b/include/sound/opl3.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_OPL3_H +#define __SOUND_OPL3_H + +/* + * Definitions of the OPL-3 registers. + * + * Copyright (c) by Jaroslav Kysela , + * Hannu Savolainen 1993-1996 + * + * The OPL-3 mode is switched on by writing 0x01, to the offset 5 + * of the right side. + * + * Another special register at the right side is at offset 4. It contains + * a bit mask defining which voices are used as 4 OP voices. + * + * The percussive mode is implemented in the left side only. + * + * With the above exceptions the both sides can be operated independently. + * + * A 4 OP voice can be created by setting the corresponding + * bit at offset 4 of the right side. + * + * For example setting the rightmost bit (0x01) changes the + * first voice on the right side to the 4 OP mode. The fourth + * voice is made inaccessible. + * + * If a voice is set to the 2 OP mode, it works like 2 OP modes + * of the original YM3812 (AdLib). In addition the voice can + * be connected the left, right or both stereo channels. It can + * even be left unconnected. This works with 4 OP voices also. + * + * The stereo connection bits are located in the FEEDBACK_CONNECTION + * register of the voice (0xC0-0xC8). In 4 OP voices these bits are + * in the second half of the voice. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Register numbers for the global registers + */ + +#define OPL3_REG_TEST 0x01 +#define OPL3_ENABLE_WAVE_SELECT 0x20 + +#define OPL3_REG_TIMER1 0x02 +#define OPL3_REG_TIMER2 0x03 +#define OPL3_REG_TIMER_CONTROL 0x04 /* Left side */ +#define OPL3_IRQ_RESET 0x80 +#define OPL3_TIMER1_MASK 0x40 +#define OPL3_TIMER2_MASK 0x20 +#define OPL3_TIMER1_START 0x01 +#define OPL3_TIMER2_START 0x02 + +#define OPL3_REG_CONNECTION_SELECT 0x04 /* Right side */ +#define OPL3_LEFT_4OP_0 0x01 +#define OPL3_LEFT_4OP_1 0x02 +#define OPL3_LEFT_4OP_2 0x04 +#define OPL3_RIGHT_4OP_0 0x08 +#define OPL3_RIGHT_4OP_1 0x10 +#define OPL3_RIGHT_4OP_2 0x20 + +#define OPL3_REG_MODE 0x05 /* Right side */ +#define OPL3_OPL3_ENABLE 0x01 /* OPL3 mode */ +#define OPL3_OPL4_ENABLE 0x02 /* OPL4 mode */ + +#define OPL3_REG_KBD_SPLIT 0x08 /* Left side */ +#define OPL3_COMPOSITE_SINE_WAVE_MODE 0x80 /* Don't use with OPL-3? */ +#define OPL3_KEYBOARD_SPLIT 0x40 + +#define OPL3_REG_PERCUSSION 0xbd /* Left side only */ +#define OPL3_TREMOLO_DEPTH 0x80 +#define OPL3_VIBRATO_DEPTH 0x40 +#define OPL3_PERCUSSION_ENABLE 0x20 +#define OPL3_BASSDRUM_ON 0x10 +#define OPL3_SNAREDRUM_ON 0x08 +#define OPL3_TOMTOM_ON 0x04 +#define OPL3_CYMBAL_ON 0x02 +#define OPL3_HIHAT_ON 0x01 + +/* + * Offsets to the register banks for operators. To get the + * register number just add the operator offset to the bank offset + * + * AM/VIB/EG/KSR/Multiple (0x20 to 0x35) + */ +#define OPL3_REG_AM_VIB 0x20 +#define OPL3_TREMOLO_ON 0x80 +#define OPL3_VIBRATO_ON 0x40 +#define OPL3_SUSTAIN_ON 0x20 +#define OPL3_KSR 0x10 /* Key scaling rate */ +#define OPL3_MULTIPLE_MASK 0x0f /* Frequency multiplier */ + + /* + * KSL/Total level (0x40 to 0x55) + */ +#define OPL3_REG_KSL_LEVEL 0x40 +#define OPL3_KSL_MASK 0xc0 /* Envelope scaling bits */ +#define OPL3_TOTAL_LEVEL_MASK 0x3f /* Strength (volume) of OP */ + +/* + * Attack / Decay rate (0x60 to 0x75) + */ +#define OPL3_REG_ATTACK_DECAY 0x60 +#define OPL3_ATTACK_MASK 0xf0 +#define OPL3_DECAY_MASK 0x0f + +/* + * Sustain level / Release rate (0x80 to 0x95) + */ +#define OPL3_REG_SUSTAIN_RELEASE 0x80 +#define OPL3_SUSTAIN_MASK 0xf0 +#define OPL3_RELEASE_MASK 0x0f + +/* + * Wave select (0xE0 to 0xF5) + */ +#define OPL3_REG_WAVE_SELECT 0xe0 +#define OPL3_WAVE_SELECT_MASK 0x07 + +/* + * Offsets to the register banks for voices. Just add to the + * voice number to get the register number. + * + * F-Number low bits (0xA0 to 0xA8). + */ +#define OPL3_REG_FNUM_LOW 0xa0 + +/* + * F-number high bits / Key on / Block (octave) (0xB0 to 0xB8) + */ +#define OPL3_REG_KEYON_BLOCK 0xb0 +#define OPL3_KEYON_BIT 0x20 +#define OPL3_BLOCKNUM_MASK 0x1c +#define OPL3_FNUM_HIGH_MASK 0x03 + +/* + * Feedback / Connection (0xc0 to 0xc8) + * + * These registers have two new bits when the OPL-3 mode + * is selected. These bits controls connecting the voice + * to the stereo channels. For 4 OP voices this bit is + * defined in the second half of the voice (add 3 to the + * register offset). + * + * For 4 OP voices the connection bit is used in the + * both halves (gives 4 ways to connect the operators). + */ +#define OPL3_REG_FEEDBACK_CONNECTION 0xc0 +#define OPL3_FEEDBACK_MASK 0x0e /* Valid just for 1st OP of a voice */ +#define OPL3_CONNECTION_BIT 0x01 +/* + * In the 4 OP mode there is four possible configurations how the + * operators can be connected together (in 2 OP modes there is just + * AM or FM). The 4 OP connection mode is defined by the rightmost + * bit of the FEEDBACK_CONNECTION (0xC0-0xC8) on the both halves. + * + * First half Second half Mode + * + * +---+ + * v | + * 0 0 >+-1-+--2--3--4--> + * + * + * + * +---+ + * | | + * 0 1 >+-1-+--2-+ + * |-> + * >--3----4-+ + * + * +---+ + * | | + * 1 0 >+-1-+-----+ + * |-> + * >--2--3--4-+ + * + * +---+ + * | | + * 1 1 >+-1-+--+ + * | + * >--2--3-+-> + * | + * >--4----+ + */ +#define OPL3_STEREO_BITS 0x30 /* OPL-3 only */ +#define OPL3_VOICE_TO_LEFT 0x10 +#define OPL3_VOICE_TO_RIGHT 0x20 + +/* + + */ + +#define OPL3_LEFT 0x0000 +#define OPL3_RIGHT 0x0100 + +#define OPL3_HW_AUTO 0x0000 +#define OPL3_HW_OPL2 0x0200 +#define OPL3_HW_OPL3 0x0300 +#define OPL3_HW_OPL3_SV 0x0301 /* S3 SonicVibes */ +#define OPL3_HW_OPL3_CS 0x0302 /* CS4232/CS4236+ */ +#define OPL3_HW_OPL3_FM801 0x0303 /* FM801 */ +#define OPL3_HW_OPL3_CS4281 0x0304 /* CS4281 */ +#define OPL3_HW_OPL4 0x0400 /* YMF278B/YMF295 */ +#define OPL3_HW_OPL4_ML 0x0401 /* YMF704/YMF721 */ +#define OPL3_HW_MASK 0xff00 + +#define MAX_OPL2_VOICES 9 +#define MAX_OPL3_VOICES 18 + +struct snd_opl3; + +/* + * Instrument record, aka "Patch" + */ + +/* FM operator */ +struct fm_operator { + unsigned char am_vib; + unsigned char ksl_level; + unsigned char attack_decay; + unsigned char sustain_release; + unsigned char wave_select; +} __packed; + +/* Instrument data */ +struct fm_instrument { + struct fm_operator op[4]; + unsigned char feedback_connection[2]; + unsigned char echo_delay; + unsigned char echo_atten; + unsigned char chorus_spread; + unsigned char trnsps; + unsigned char fix_dur; + unsigned char modes; + unsigned char fix_key; +}; + +/* type */ +#define FM_PATCH_OPL2 0x01 /* OPL2 2 operators FM instrument */ +#define FM_PATCH_OPL3 0x02 /* OPL3 4 operators FM instrument */ + +/* Instrument record */ +struct fm_patch { + unsigned char prog; + unsigned char bank; + unsigned char type; + struct fm_instrument inst; + char name[24]; + struct fm_patch *next; +}; + + +/* + * A structure to keep track of each hardware voice + */ +struct snd_opl3_voice { + int state; /* status */ +#define SNDRV_OPL3_ST_OFF 0 /* Not playing */ +#define SNDRV_OPL3_ST_ON_2OP 1 /* 2op voice is allocated */ +#define SNDRV_OPL3_ST_ON_4OP 2 /* 4op voice is allocated */ +#define SNDRV_OPL3_ST_NOT_AVAIL -1 /* voice is not available */ + + unsigned int time; /* An allocation time */ + unsigned char note; /* Note currently assigned to this voice */ + + unsigned long note_off; /* note-off time */ + int note_off_check; /* check note-off time */ + + unsigned char keyon_reg; /* KON register shadow */ + + struct snd_midi_channel *chan; /* Midi channel for this note */ +}; + +struct snd_opl3 { + unsigned long l_port; + unsigned long r_port; + struct resource *res_l_port; + struct resource *res_r_port; + unsigned short hardware; + /* hardware access */ + void (*command) (struct snd_opl3 * opl3, unsigned short cmd, unsigned char val); + unsigned short timer_enable; + int seq_dev_num; /* sequencer device number */ + struct snd_timer *timer1; + struct snd_timer *timer2; + spinlock_t timer_lock; + + void *private_data; + void (*private_free)(struct snd_opl3 *); + + struct snd_hwdep *hwdep; + spinlock_t reg_lock; + struct snd_card *card; /* The card that this belongs to */ + unsigned char fm_mode; /* OPL mode, see SNDRV_DM_FM_MODE_XXX */ + unsigned char rhythm; /* percussion mode flag */ + unsigned char max_voices; /* max number of voices */ +#if IS_ENABLED(CONFIG_SND_SEQUENCER) +#define SNDRV_OPL3_MODE_SYNTH 0 /* OSS - voices allocated by application */ +#define SNDRV_OPL3_MODE_SEQ 1 /* ALSA - driver handles voice allocation */ + int synth_mode; /* synth mode */ + int seq_client; + + struct snd_seq_device *seq_dev; /* sequencer device */ + struct snd_midi_channel_set * chset; + +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + struct snd_seq_device *oss_seq_dev; /* OSS sequencer device */ + struct snd_midi_channel_set * oss_chset; +#endif + +#define OPL3_PATCH_HASH_SIZE 32 + struct fm_patch *patch_table[OPL3_PATCH_HASH_SIZE]; + + struct snd_opl3_voice voices[MAX_OPL3_VOICES]; /* Voices (OPL3 'channel') */ + int use_time; /* allocation counter */ + + unsigned short connection_reg; /* connection reg shadow */ + unsigned char drum_reg; /* percussion reg shadow */ + + spinlock_t voice_lock; /* Lock for voice access */ + + struct timer_list tlist; /* timer for note-offs and effects */ + int sys_timer_status; /* system timer run status */ + spinlock_t sys_timer_lock; /* Lock for system timer access */ +#endif +}; + +/* opl3.c */ +void snd_opl3_interrupt(struct snd_hwdep * hw); +int snd_opl3_new(struct snd_card *card, unsigned short hardware, + struct snd_opl3 **ropl3); +int snd_opl3_init(struct snd_opl3 *opl3); +int snd_opl3_create(struct snd_card *card, + unsigned long l_port, unsigned long r_port, + unsigned short hardware, + int integrated, + struct snd_opl3 ** opl3); +int snd_opl3_timer_new(struct snd_opl3 * opl3, int timer1_dev, int timer2_dev); +int snd_opl3_hwdep_new(struct snd_opl3 * opl3, int device, int seq_device, + struct snd_hwdep ** rhwdep); + +/* opl3_synth */ +int snd_opl3_open(struct snd_hwdep * hw, struct file *file); +int snd_opl3_ioctl(struct snd_hwdep * hw, struct file *file, + unsigned int cmd, unsigned long arg); +int snd_opl3_release(struct snd_hwdep * hw, struct file *file); + +void snd_opl3_reset(struct snd_opl3 * opl3); + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) +long snd_opl3_write(struct snd_hwdep *hw, const char __user *buf, long count, + loff_t *offset); +int snd_opl3_load_patch(struct snd_opl3 *opl3, + int prog, int bank, int type, + const char *name, + const unsigned char *ext, + const unsigned char *data); +struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank, + int create_patch); +void snd_opl3_clear_patches(struct snd_opl3 *opl3); +#else +#define snd_opl3_write NULL +static inline void snd_opl3_clear_patches(struct snd_opl3 *opl3) {} +#endif + +#endif /* __SOUND_OPL3_H */ diff --git a/include/sound/opl4.h b/include/sound/opl4.h new file mode 100644 index 000000000..9f337148c --- /dev/null +++ b/include/sound/opl4.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_OPL4_H +#define __SOUND_OPL4_H + +/* + * Global definitions for the OPL4 driver + * Copyright (c) 2003 by Clemens Ladisch + */ + +#include + +struct snd_opl4; + +extern int snd_opl4_create(struct snd_card *card, + unsigned long fm_port, unsigned long pcm_port, + int seq_device, + struct snd_opl3 **opl3, struct snd_opl4 **opl4); + +#endif /* __SOUND_OPL4_H */ diff --git a/include/sound/pcm-indirect.h b/include/sound/pcm-indirect.h new file mode 100644 index 000000000..98e06ea73 --- /dev/null +++ b/include/sound/pcm-indirect.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper functions for indirect PCM data transfer + * + * Copyright (c) by Takashi Iwai + * Jaroslav Kysela + */ + +#ifndef __SOUND_PCM_INDIRECT_H +#define __SOUND_PCM_INDIRECT_H + +#include + +struct snd_pcm_indirect { + unsigned int hw_buffer_size; /* Byte size of hardware buffer */ + unsigned int hw_queue_size; /* Max queue size of hw buffer (0 = buffer size) */ + unsigned int hw_data; /* Offset to next dst (or src) in hw ring buffer */ + unsigned int hw_io; /* Ring buffer hw pointer */ + int hw_ready; /* Bytes ready for play (or captured) in hw ring buffer */ + unsigned int sw_buffer_size; /* Byte size of software buffer */ + unsigned int sw_data; /* Offset to next dst (or src) in sw ring buffer */ + unsigned int sw_io; /* Current software pointer in bytes */ + int sw_ready; /* Bytes ready to be transferred to/from hw */ + snd_pcm_uframes_t appl_ptr; /* Last seen appl_ptr */ +}; + +typedef void (*snd_pcm_indirect_copy_t)(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, size_t bytes); + +/* + * helper function for playback ack callback + */ +static inline int +snd_pcm_indirect_playback_transfer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, + snd_pcm_indirect_copy_t copy) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr; + snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr; + int qsize; + + if (diff) { + if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2)) + diff += runtime->boundary; + if (diff < 0) + return -EPIPE; + rec->sw_ready += (int)frames_to_bytes(runtime, diff); + rec->appl_ptr = appl_ptr; + } + qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size; + while (rec->hw_ready < qsize && rec->sw_ready > 0) { + unsigned int hw_to_end = rec->hw_buffer_size - rec->hw_data; + unsigned int sw_to_end = rec->sw_buffer_size - rec->sw_data; + unsigned int bytes = qsize - rec->hw_ready; + if (rec->sw_ready < (int)bytes) + bytes = rec->sw_ready; + if (hw_to_end < bytes) + bytes = hw_to_end; + if (sw_to_end < bytes) + bytes = sw_to_end; + if (! bytes) + break; + copy(substream, rec, bytes); + rec->hw_data += bytes; + if (rec->hw_data == rec->hw_buffer_size) + rec->hw_data = 0; + rec->sw_data += bytes; + if (rec->sw_data == rec->sw_buffer_size) + rec->sw_data = 0; + rec->hw_ready += bytes; + rec->sw_ready -= bytes; + } + return 0; +} + +/* + * helper function for playback pointer callback + * ptr = current byte pointer + */ +static inline snd_pcm_uframes_t +snd_pcm_indirect_playback_pointer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, unsigned int ptr) +{ + int bytes = ptr - rec->hw_io; + int err; + + if (bytes < 0) + bytes += rec->hw_buffer_size; + rec->hw_io = ptr; + rec->hw_ready -= bytes; + rec->sw_io += bytes; + if (rec->sw_io >= rec->sw_buffer_size) + rec->sw_io -= rec->sw_buffer_size; + if (substream->ops->ack) { + err = substream->ops->ack(substream); + if (err == -EPIPE) + return SNDRV_PCM_POS_XRUN; + } + return bytes_to_frames(substream->runtime, rec->sw_io); +} + + +/* + * helper function for capture ack callback + */ +static inline int +snd_pcm_indirect_capture_transfer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, + snd_pcm_indirect_copy_t copy) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr; + snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr; + + if (diff) { + if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2)) + diff += runtime->boundary; + if (diff < 0) + return -EPIPE; + rec->sw_ready -= frames_to_bytes(runtime, diff); + rec->appl_ptr = appl_ptr; + } + while (rec->hw_ready > 0 && + rec->sw_ready < (int)rec->sw_buffer_size) { + size_t hw_to_end = rec->hw_buffer_size - rec->hw_data; + size_t sw_to_end = rec->sw_buffer_size - rec->sw_data; + size_t bytes = rec->sw_buffer_size - rec->sw_ready; + if (rec->hw_ready < (int)bytes) + bytes = rec->hw_ready; + if (hw_to_end < bytes) + bytes = hw_to_end; + if (sw_to_end < bytes) + bytes = sw_to_end; + if (! bytes) + break; + copy(substream, rec, bytes); + rec->hw_data += bytes; + if ((int)rec->hw_data == rec->hw_buffer_size) + rec->hw_data = 0; + rec->sw_data += bytes; + if (rec->sw_data == rec->sw_buffer_size) + rec->sw_data = 0; + rec->hw_ready -= bytes; + rec->sw_ready += bytes; + } + return 0; +} + +/* + * helper function for capture pointer callback, + * ptr = current byte pointer + */ +static inline snd_pcm_uframes_t +snd_pcm_indirect_capture_pointer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, unsigned int ptr) +{ + int qsize; + int bytes = ptr - rec->hw_io; + int err; + + if (bytes < 0) + bytes += rec->hw_buffer_size; + rec->hw_io = ptr; + rec->hw_ready += bytes; + qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size; + if (rec->hw_ready > qsize) + return SNDRV_PCM_POS_XRUN; + rec->sw_io += bytes; + if (rec->sw_io >= rec->sw_buffer_size) + rec->sw_io -= rec->sw_buffer_size; + if (substream->ops->ack) { + err = substream->ops->ack(substream); + if (err == -EPIPE) + return SNDRV_PCM_POS_XRUN; + } + return bytes_to_frames(substream->runtime, rec->sw_io); +} + +#endif /* __SOUND_PCM_INDIRECT_H */ diff --git a/include/sound/pcm.h b/include/sound/pcm.h new file mode 100644 index 000000000..02d868935 --- /dev/null +++ b/include/sound/pcm.h @@ -0,0 +1,1591 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_PCM_H +#define __SOUND_PCM_H + +/* + * Digital Audio (PCM) abstract layer + * Copyright (c) by Jaroslav Kysela + * Abramo Bagnara + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define snd_pcm_substream_chip(substream) ((substream)->private_data) +#define snd_pcm_chip(pcm) ((pcm)->private_data) + +#if IS_ENABLED(CONFIG_SND_PCM_OSS) +#include +#endif + +/* + * Hardware (lowlevel) section + */ + +struct snd_pcm_hardware { + unsigned int info; /* SNDRV_PCM_INFO_* */ + u64 formats; /* SNDRV_PCM_FMTBIT_* */ + u32 subformats; /* for S32_LE, SNDRV_PCM_SUBFMTBIT_* */ + unsigned int rates; /* SNDRV_PCM_RATE_* */ + unsigned int rate_min; /* min rate */ + unsigned int rate_max; /* max rate */ + unsigned int channels_min; /* min channels */ + unsigned int channels_max; /* max channels */ + size_t buffer_bytes_max; /* max buffer size */ + size_t period_bytes_min; /* min period size */ + size_t period_bytes_max; /* max period size */ + unsigned int periods_min; /* min # of periods */ + unsigned int periods_max; /* max # of periods */ + size_t fifo_size; /* fifo size in bytes */ +}; + +struct snd_pcm_status64; +struct snd_pcm_substream; + +struct snd_pcm_audio_tstamp_config; /* definitions further down */ +struct snd_pcm_audio_tstamp_report; + +struct snd_pcm_ops { + int (*open)(struct snd_pcm_substream *substream); + int (*close)(struct snd_pcm_substream *substream); + int (*ioctl)(struct snd_pcm_substream * substream, + unsigned int cmd, void *arg); + int (*hw_params)(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); + int (*hw_free)(struct snd_pcm_substream *substream); + int (*prepare)(struct snd_pcm_substream *substream); + int (*trigger)(struct snd_pcm_substream *substream, int cmd); + int (*sync_stop)(struct snd_pcm_substream *substream); + snd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *substream); + int (*get_time_info)(struct snd_pcm_substream *substream, + struct timespec64 *system_ts, struct timespec64 *audio_ts, + struct snd_pcm_audio_tstamp_config *audio_tstamp_config, + struct snd_pcm_audio_tstamp_report *audio_tstamp_report); + int (*fill_silence)(struct snd_pcm_substream *substream, int channel, + unsigned long pos, unsigned long bytes); + int (*copy)(struct snd_pcm_substream *substream, int channel, + unsigned long pos, struct iov_iter *iter, unsigned long bytes); + struct page *(*page)(struct snd_pcm_substream *substream, + unsigned long offset); + int (*mmap)(struct snd_pcm_substream *substream, struct vm_area_struct *vma); + int (*ack)(struct snd_pcm_substream *substream); +}; + +/* + * + */ + +#if defined(CONFIG_SND_DYNAMIC_MINORS) +#define SNDRV_PCM_DEVICES (SNDRV_OS_MINORS-2) +#else +#define SNDRV_PCM_DEVICES 8 +#endif + +#define SNDRV_PCM_IOCTL1_RESET 0 +/* 1 is absent slot. */ +#define SNDRV_PCM_IOCTL1_CHANNEL_INFO 2 +/* 3 is absent slot. */ +#define SNDRV_PCM_IOCTL1_FIFO_SIZE 4 +#define SNDRV_PCM_IOCTL1_SYNC_ID 5 + +#define SNDRV_PCM_TRIGGER_STOP 0 +#define SNDRV_PCM_TRIGGER_START 1 +#define SNDRV_PCM_TRIGGER_PAUSE_PUSH 2 +#define SNDRV_PCM_TRIGGER_PAUSE_RELEASE 3 +#define SNDRV_PCM_TRIGGER_SUSPEND 4 +#define SNDRV_PCM_TRIGGER_RESUME 5 +#define SNDRV_PCM_TRIGGER_DRAIN 6 + +#define SNDRV_PCM_POS_XRUN ((snd_pcm_uframes_t)-1) + +/* If you change this don't forget to change rates[] table in pcm_native.c */ +#define SNDRV_PCM_RATE_5512 (1U<<0) /* 5512Hz */ +#define SNDRV_PCM_RATE_8000 (1U<<1) /* 8000Hz */ +#define SNDRV_PCM_RATE_11025 (1U<<2) /* 11025Hz */ +#define SNDRV_PCM_RATE_16000 (1U<<3) /* 16000Hz */ +#define SNDRV_PCM_RATE_22050 (1U<<4) /* 22050Hz */ +#define SNDRV_PCM_RATE_32000 (1U<<5) /* 32000Hz */ +#define SNDRV_PCM_RATE_44100 (1U<<6) /* 44100Hz */ +#define SNDRV_PCM_RATE_48000 (1U<<7) /* 48000Hz */ +#define SNDRV_PCM_RATE_64000 (1U<<8) /* 64000Hz */ +#define SNDRV_PCM_RATE_88200 (1U<<9) /* 88200Hz */ +#define SNDRV_PCM_RATE_96000 (1U<<10) /* 96000Hz */ +#define SNDRV_PCM_RATE_176400 (1U<<11) /* 176400Hz */ +#define SNDRV_PCM_RATE_192000 (1U<<12) /* 192000Hz */ +#define SNDRV_PCM_RATE_352800 (1U<<13) /* 352800Hz */ +#define SNDRV_PCM_RATE_384000 (1U<<14) /* 384000Hz */ +#define SNDRV_PCM_RATE_705600 (1U<<15) /* 705600Hz */ +#define SNDRV_PCM_RATE_768000 (1U<<16) /* 768000Hz */ +/* extended rates since 6.12 */ +#define SNDRV_PCM_RATE_12000 (1U<<17) /* 12000Hz */ +#define SNDRV_PCM_RATE_24000 (1U<<18) /* 24000Hz */ +#define SNDRV_PCM_RATE_128000 (1U<<19) /* 128000Hz */ + +#define SNDRV_PCM_RATE_CONTINUOUS (1U<<30) /* continuous range */ +#define SNDRV_PCM_RATE_KNOT (1U<<31) /* supports more non-continuous rates */ + +#define SNDRV_PCM_RATE_8000_44100 (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\ + SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|\ + SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100) +#define SNDRV_PCM_RATE_8000_48000 (SNDRV_PCM_RATE_8000_44100|SNDRV_PCM_RATE_48000) +#define SNDRV_PCM_RATE_8000_96000 (SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_64000|\ + SNDRV_PCM_RATE_88200|SNDRV_PCM_RATE_96000) +#define SNDRV_PCM_RATE_8000_192000 (SNDRV_PCM_RATE_8000_96000|SNDRV_PCM_RATE_176400|\ + SNDRV_PCM_RATE_192000) +#define SNDRV_PCM_RATE_8000_384000 (SNDRV_PCM_RATE_8000_192000|\ + SNDRV_PCM_RATE_352800|\ + SNDRV_PCM_RATE_384000) +#define SNDRV_PCM_RATE_8000_768000 (SNDRV_PCM_RATE_8000_384000|\ + SNDRV_PCM_RATE_705600|\ + SNDRV_PCM_RATE_768000) +#define SNDRV_PCM_FMTBIT_S8 (1ULL << SNDRV_PCM_FORMAT_S8) +#define SNDRV_PCM_FMTBIT_U8 (1ULL << SNDRV_PCM_FORMAT_U8) +#define SNDRV_PCM_FMTBIT_S16_LE (1ULL << SNDRV_PCM_FORMAT_S16_LE) +#define SNDRV_PCM_FMTBIT_S16_BE (1ULL << SNDRV_PCM_FORMAT_S16_BE) +#define SNDRV_PCM_FMTBIT_U16_LE (1ULL << SNDRV_PCM_FORMAT_U16_LE) +#define SNDRV_PCM_FMTBIT_U16_BE (1ULL << SNDRV_PCM_FORMAT_U16_BE) +#define SNDRV_PCM_FMTBIT_S24_LE (1ULL << SNDRV_PCM_FORMAT_S24_LE) +#define SNDRV_PCM_FMTBIT_S24_BE (1ULL << SNDRV_PCM_FORMAT_S24_BE) +#define SNDRV_PCM_FMTBIT_U24_LE (1ULL << SNDRV_PCM_FORMAT_U24_LE) +#define SNDRV_PCM_FMTBIT_U24_BE (1ULL << SNDRV_PCM_FORMAT_U24_BE) +// For S32/U32 formats, 'msbits' hardware parameter is often used to deliver information about the +// available bit count in most significant bit. It's for the case of so-called 'left-justified' or +// `right-padding` sample which has less width than 32 bit. +#define SNDRV_PCM_FMTBIT_S32_LE (1ULL << SNDRV_PCM_FORMAT_S32_LE) +#define SNDRV_PCM_FMTBIT_S32_BE (1ULL << SNDRV_PCM_FORMAT_S32_BE) +#define SNDRV_PCM_FMTBIT_U32_LE (1ULL << SNDRV_PCM_FORMAT_U32_LE) +#define SNDRV_PCM_FMTBIT_U32_BE (1ULL << SNDRV_PCM_FORMAT_U32_BE) +#define SNDRV_PCM_FMTBIT_FLOAT_LE (1ULL << SNDRV_PCM_FORMAT_FLOAT_LE) +#define SNDRV_PCM_FMTBIT_FLOAT_BE (1ULL << SNDRV_PCM_FORMAT_FLOAT_BE) +#define SNDRV_PCM_FMTBIT_FLOAT64_LE (1ULL << SNDRV_PCM_FORMAT_FLOAT64_LE) +#define SNDRV_PCM_FMTBIT_FLOAT64_BE (1ULL << SNDRV_PCM_FORMAT_FLOAT64_BE) +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE (1ULL << SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE (1ULL << SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE) +#define SNDRV_PCM_FMTBIT_MU_LAW (1ULL << SNDRV_PCM_FORMAT_MU_LAW) +#define SNDRV_PCM_FMTBIT_A_LAW (1ULL << SNDRV_PCM_FORMAT_A_LAW) +#define SNDRV_PCM_FMTBIT_IMA_ADPCM (1ULL << SNDRV_PCM_FORMAT_IMA_ADPCM) +#define SNDRV_PCM_FMTBIT_MPEG (1ULL << SNDRV_PCM_FORMAT_MPEG) +#define SNDRV_PCM_FMTBIT_GSM (1ULL << SNDRV_PCM_FORMAT_GSM) +#define SNDRV_PCM_FMTBIT_S20_LE (1ULL << SNDRV_PCM_FORMAT_S20_LE) +#define SNDRV_PCM_FMTBIT_U20_LE (1ULL << SNDRV_PCM_FORMAT_U20_LE) +#define SNDRV_PCM_FMTBIT_S20_BE (1ULL << SNDRV_PCM_FORMAT_S20_BE) +#define SNDRV_PCM_FMTBIT_U20_BE (1ULL << SNDRV_PCM_FORMAT_U20_BE) +#define SNDRV_PCM_FMTBIT_SPECIAL (1ULL << SNDRV_PCM_FORMAT_SPECIAL) +#define SNDRV_PCM_FMTBIT_S24_3LE (1ULL << SNDRV_PCM_FORMAT_S24_3LE) +#define SNDRV_PCM_FMTBIT_U24_3LE (1ULL << SNDRV_PCM_FORMAT_U24_3LE) +#define SNDRV_PCM_FMTBIT_S24_3BE (1ULL << SNDRV_PCM_FORMAT_S24_3BE) +#define SNDRV_PCM_FMTBIT_U24_3BE (1ULL << SNDRV_PCM_FORMAT_U24_3BE) +#define SNDRV_PCM_FMTBIT_S20_3LE (1ULL << SNDRV_PCM_FORMAT_S20_3LE) +#define SNDRV_PCM_FMTBIT_U20_3LE (1ULL << SNDRV_PCM_FORMAT_U20_3LE) +#define SNDRV_PCM_FMTBIT_S20_3BE (1ULL << SNDRV_PCM_FORMAT_S20_3BE) +#define SNDRV_PCM_FMTBIT_U20_3BE (1ULL << SNDRV_PCM_FORMAT_U20_3BE) +#define SNDRV_PCM_FMTBIT_S18_3LE (1ULL << SNDRV_PCM_FORMAT_S18_3LE) +#define SNDRV_PCM_FMTBIT_U18_3LE (1ULL << SNDRV_PCM_FORMAT_U18_3LE) +#define SNDRV_PCM_FMTBIT_S18_3BE (1ULL << SNDRV_PCM_FORMAT_S18_3BE) +#define SNDRV_PCM_FMTBIT_U18_3BE (1ULL << SNDRV_PCM_FORMAT_U18_3BE) +#define SNDRV_PCM_FMTBIT_G723_24 (1ULL << SNDRV_PCM_FORMAT_G723_24) +#define SNDRV_PCM_FMTBIT_G723_24_1B (1ULL << SNDRV_PCM_FORMAT_G723_24_1B) +#define SNDRV_PCM_FMTBIT_G723_40 (1ULL << SNDRV_PCM_FORMAT_G723_40) +#define SNDRV_PCM_FMTBIT_G723_40_1B (1ULL << SNDRV_PCM_FORMAT_G723_40_1B) +#define SNDRV_PCM_FMTBIT_DSD_U8 (1ULL << SNDRV_PCM_FORMAT_DSD_U8) +#define SNDRV_PCM_FMTBIT_DSD_U16_LE (1ULL << SNDRV_PCM_FORMAT_DSD_U16_LE) +#define SNDRV_PCM_FMTBIT_DSD_U32_LE (1ULL << SNDRV_PCM_FORMAT_DSD_U32_LE) +#define SNDRV_PCM_FMTBIT_DSD_U16_BE (1ULL << SNDRV_PCM_FORMAT_DSD_U16_BE) +#define SNDRV_PCM_FMTBIT_DSD_U32_BE (1ULL << SNDRV_PCM_FORMAT_DSD_U32_BE) + +#ifdef SNDRV_LITTLE_ENDIAN +#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_LE +#define SNDRV_PCM_FMTBIT_U16 SNDRV_PCM_FMTBIT_U16_LE +#define SNDRV_PCM_FMTBIT_S24 SNDRV_PCM_FMTBIT_S24_LE +#define SNDRV_PCM_FMTBIT_U24 SNDRV_PCM_FMTBIT_U24_LE +#define SNDRV_PCM_FMTBIT_S32 SNDRV_PCM_FMTBIT_S32_LE +#define SNDRV_PCM_FMTBIT_U32 SNDRV_PCM_FMTBIT_U32_LE +#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_LE +#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_LE +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE +#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_LE +#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_LE +#endif +#ifdef SNDRV_BIG_ENDIAN +#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_BE +#define SNDRV_PCM_FMTBIT_U16 SNDRV_PCM_FMTBIT_U16_BE +#define SNDRV_PCM_FMTBIT_S24 SNDRV_PCM_FMTBIT_S24_BE +#define SNDRV_PCM_FMTBIT_U24 SNDRV_PCM_FMTBIT_U24_BE +#define SNDRV_PCM_FMTBIT_S32 SNDRV_PCM_FMTBIT_S32_BE +#define SNDRV_PCM_FMTBIT_U32 SNDRV_PCM_FMTBIT_U32_BE +#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_BE +#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_BE +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE +#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_BE +#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_BE +#endif + +#define SNDRV_PCM_SUBFMTBIT_STD (1U << SNDRV_PCM_SUBFORMAT_STD) +#define SNDRV_PCM_SUBFMTBIT_MSBITS_MAX (1U << SNDRV_PCM_SUBFORMAT_MSBITS_MAX) +#define SNDRV_PCM_SUBFMTBIT_MSBITS_20 (1U << SNDRV_PCM_SUBFORMAT_MSBITS_20) +#define SNDRV_PCM_SUBFMTBIT_MSBITS_24 (1U << SNDRV_PCM_SUBFORMAT_MSBITS_24) + +struct snd_pcm_file { + struct snd_pcm_substream *substream; + int no_compat_mmap; + unsigned int user_pversion; /* supported protocol version */ +}; + +struct snd_pcm_hw_rule; +typedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule); + +struct snd_pcm_hw_rule { + unsigned int cond; + int var; + int deps[5]; + + snd_pcm_hw_rule_func_t func; + void *private; +}; + +struct snd_pcm_hw_constraints { + struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - + SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; + struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - + SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; + unsigned int rules_num; + unsigned int rules_all; + struct snd_pcm_hw_rule *rules; +}; + +static inline struct snd_mask *constrs_mask(struct snd_pcm_hw_constraints *constrs, + snd_pcm_hw_param_t var) +{ + return &constrs->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; +} + +static inline struct snd_interval *constrs_interval(struct snd_pcm_hw_constraints *constrs, + snd_pcm_hw_param_t var) +{ + return &constrs->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL]; +} + +struct snd_ratnum { + unsigned int num; + unsigned int den_min, den_max, den_step; +}; + +struct snd_ratden { + unsigned int num_min, num_max, num_step; + unsigned int den; +}; + +struct snd_pcm_hw_constraint_ratnums { + int nrats; + const struct snd_ratnum *rats; +}; + +struct snd_pcm_hw_constraint_ratdens { + int nrats; + const struct snd_ratden *rats; +}; + +struct snd_pcm_hw_constraint_list { + const unsigned int *list; + unsigned int count; + unsigned int mask; +}; + +struct snd_pcm_hw_constraint_ranges { + unsigned int count; + const struct snd_interval *ranges; + unsigned int mask; +}; + +/* + * userspace-provided audio timestamp config to kernel, + * structure is for internal use only and filled with dedicated unpack routine + */ +struct snd_pcm_audio_tstamp_config { + /* 5 of max 16 bits used */ + u32 type_requested:4; + u32 report_delay:1; /* add total delay to A/D or D/A */ +}; + +static inline void snd_pcm_unpack_audio_tstamp_config(__u32 data, + struct snd_pcm_audio_tstamp_config *config) +{ + config->type_requested = data & 0xF; + config->report_delay = (data >> 4) & 1; +} + +/* + * kernel-provided audio timestamp report to user-space + * structure is for internal use only and read by dedicated pack routine + */ +struct snd_pcm_audio_tstamp_report { + /* 6 of max 16 bits used for bit-fields */ + + /* for backwards compatibility */ + u32 valid:1; + + /* actual type if hardware could not support requested timestamp */ + u32 actual_type:4; + + /* accuracy represented in ns units */ + u32 accuracy_report:1; /* 0 if accuracy unknown, 1 if accuracy field is valid */ + u32 accuracy; /* up to 4.29s, will be packed in separate field */ +}; + +static inline void snd_pcm_pack_audio_tstamp_report(__u32 *data, __u32 *accuracy, + const struct snd_pcm_audio_tstamp_report *report) +{ + u32 tmp; + + tmp = report->accuracy_report; + tmp <<= 4; + tmp |= report->actual_type; + tmp <<= 1; + tmp |= report->valid; + + *data &= 0xffff; /* zero-clear MSBs */ + *data |= (tmp << 16); + *accuracy = report->accuracy; +} + + +struct snd_pcm_runtime { + /* -- Status -- */ + snd_pcm_state_t state; /* stream state */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + struct snd_pcm_substream *trigger_master; + struct timespec64 trigger_tstamp; /* trigger timestamp */ + bool trigger_tstamp_latched; /* trigger timestamp latched in low-level driver/hardware */ + int overrange; + snd_pcm_uframes_t avail_max; + snd_pcm_uframes_t hw_ptr_base; /* Position at buffer restart */ + snd_pcm_uframes_t hw_ptr_interrupt; /* Position at interrupt time */ + unsigned long hw_ptr_jiffies; /* Time when hw_ptr is updated */ + unsigned long hw_ptr_buffer_jiffies; /* buffer time in jiffies */ + snd_pcm_sframes_t delay; /* extra delay; typically FIFO size */ + u64 hw_ptr_wrap; /* offset for hw_ptr due to boundary wrap-around */ + + /* -- HW params -- */ + snd_pcm_access_t access; /* access mode */ + snd_pcm_format_t format; /* SNDRV_PCM_FORMAT_* */ + snd_pcm_subformat_t subformat; /* subformat */ + unsigned int rate; /* rate in Hz */ + unsigned int channels; /* channels */ + snd_pcm_uframes_t period_size; /* period size */ + unsigned int periods; /* periods */ + snd_pcm_uframes_t buffer_size; /* buffer size */ + snd_pcm_uframes_t min_align; /* Min alignment for the format */ + size_t byte_align; + unsigned int frame_bits; + unsigned int sample_bits; + unsigned int info; + unsigned int rate_num; + unsigned int rate_den; + unsigned int no_period_wakeup: 1; + + /* -- SW params; see struct snd_pcm_sw_params for comments -- */ + int tstamp_mode; + unsigned int period_step; + snd_pcm_uframes_t start_threshold; + snd_pcm_uframes_t stop_threshold; + snd_pcm_uframes_t silence_threshold; + snd_pcm_uframes_t silence_size; + snd_pcm_uframes_t boundary; + + /* internal data of auto-silencer */ + snd_pcm_uframes_t silence_start; /* starting pointer to silence area */ + snd_pcm_uframes_t silence_filled; /* already filled part of silence area */ + + bool std_sync_id; /* hardware synchronization - standard per card ID */ + + /* -- mmap -- */ + struct snd_pcm_mmap_status *status; + struct snd_pcm_mmap_control *control; + + /* -- locking / scheduling -- */ + snd_pcm_uframes_t twake; /* do transfer (!poll) wakeup if non-zero */ + wait_queue_head_t sleep; /* poll sleep */ + wait_queue_head_t tsleep; /* transfer sleep */ + struct snd_fasync *fasync; + bool stop_operating; /* sync_stop will be called */ + struct mutex buffer_mutex; /* protect for buffer changes */ + atomic_t buffer_accessing; /* >0: in r/w operation, <0: blocked */ + + /* -- private section -- */ + void *private_data; + void (*private_free)(struct snd_pcm_runtime *runtime); + + /* -- hardware description -- */ + struct snd_pcm_hardware hw; + struct snd_pcm_hw_constraints hw_constraints; + + /* -- timer -- */ + unsigned int timer_resolution; /* timer resolution */ + int tstamp_type; /* timestamp type */ + + /* -- DMA -- */ + unsigned char *dma_area; /* DMA area */ + dma_addr_t dma_addr; /* physical bus address (not accessible from main CPU) */ + size_t dma_bytes; /* size of DMA area */ + + struct snd_dma_buffer *dma_buffer_p; /* allocated buffer */ + unsigned int buffer_changed:1; /* buffer allocation changed; set only in managed mode */ + + /* -- audio timestamp config -- */ + struct snd_pcm_audio_tstamp_config audio_tstamp_config; + struct snd_pcm_audio_tstamp_report audio_tstamp_report; + struct timespec64 driver_tstamp; + +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + /* -- OSS things -- */ + struct snd_pcm_oss_runtime oss; +#endif +}; + +struct snd_pcm_group { /* keep linked substreams */ + spinlock_t lock; + struct mutex mutex; + struct list_head substreams; + refcount_t refs; +}; + +struct pid; + +struct snd_pcm_substream { + struct snd_pcm *pcm; + struct snd_pcm_str *pstr; + void *private_data; /* copied from pcm->private_data */ + int number; + char name[32]; /* substream name */ + int stream; /* stream (direction) */ + struct pm_qos_request latency_pm_qos_req; /* pm_qos request */ + size_t buffer_bytes_max; /* limit ring buffer size */ + struct snd_dma_buffer dma_buffer; + size_t dma_max; + /* -- hardware operations -- */ + const struct snd_pcm_ops *ops; + /* -- runtime information -- */ + struct snd_pcm_runtime *runtime; + /* -- timer section -- */ + struct snd_timer *timer; /* timer */ + unsigned timer_running: 1; /* time is running */ + long wait_time; /* time in ms for R/W to wait for avail */ + /* -- next substream -- */ + struct snd_pcm_substream *next; + /* -- linked substreams -- */ + struct list_head link_list; /* linked list member */ + struct snd_pcm_group self_group; /* fake group for non linked substream (with substream lock inside) */ + struct snd_pcm_group *group; /* pointer to current group */ + /* -- assigned files -- */ + int ref_count; + atomic_t mmap_count; + unsigned int f_flags; + void (*pcm_release)(struct snd_pcm_substream *); + struct pid *pid; +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + /* -- OSS things -- */ + struct snd_pcm_oss_substream oss; +#endif +#ifdef CONFIG_SND_VERBOSE_PROCFS + struct snd_info_entry *proc_root; +#endif /* CONFIG_SND_VERBOSE_PROCFS */ + /* misc flags */ + unsigned int hw_opened: 1; + unsigned int managed_buffer_alloc:1; +#ifdef CONFIG_SND_PCM_XRUN_DEBUG + unsigned int xrun_counter; /* number of times xrun happens */ +#endif /* CONFIG_SND_PCM_XRUN_DEBUG */ +}; + +#define SUBSTREAM_BUSY(substream) ((substream)->ref_count > 0) + + +struct snd_pcm_str { + int stream; /* stream (direction) */ + struct snd_pcm *pcm; + /* -- substreams -- */ + unsigned int substream_count; + unsigned int substream_opened; + struct snd_pcm_substream *substream; +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + /* -- OSS things -- */ + struct snd_pcm_oss_stream oss; +#endif +#ifdef CONFIG_SND_VERBOSE_PROCFS + struct snd_info_entry *proc_root; +#ifdef CONFIG_SND_PCM_XRUN_DEBUG + unsigned int xrun_debug; /* 0 = disabled, 1 = verbose, 2 = stacktrace */ +#endif +#endif + struct snd_kcontrol *chmap_kctl; /* channel-mapping controls */ + struct device *dev; +}; + +struct snd_pcm { + struct snd_card *card; + struct list_head list; + int device; /* device number */ + unsigned int info_flags; + unsigned short dev_class; + unsigned short dev_subclass; + char id[64]; + char name[80]; + struct snd_pcm_str streams[2]; + struct mutex open_mutex; + wait_queue_head_t open_wait; + void *private_data; + void (*private_free) (struct snd_pcm *pcm); + bool internal; /* pcm is for internal use only */ + bool nonatomic; /* whole PCM operations are in non-atomic context */ + bool no_device_suspend; /* don't invoke device PM suspend */ +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + struct snd_pcm_oss oss; +#endif +}; + +/* + * Registering + */ + +extern const struct file_operations snd_pcm_f_ops[2]; + +int snd_pcm_new(struct snd_card *card, const char *id, int device, + int playback_count, int capture_count, + struct snd_pcm **rpcm); +int snd_pcm_new_internal(struct snd_card *card, const char *id, int device, + int playback_count, int capture_count, + struct snd_pcm **rpcm); +int snd_pcm_new_stream(struct snd_pcm *pcm, int stream, int substream_count); + +#if IS_ENABLED(CONFIG_SND_PCM_OSS) +struct snd_pcm_notify { + int (*n_register) (struct snd_pcm * pcm); + int (*n_disconnect) (struct snd_pcm * pcm); + int (*n_unregister) (struct snd_pcm * pcm); + struct list_head list; +}; +int snd_pcm_notify(struct snd_pcm_notify *notify, int nfree); +#endif + +/* + * Native I/O + */ + +int snd_pcm_info(struct snd_pcm_substream *substream, struct snd_pcm_info *info); +int snd_pcm_info_user(struct snd_pcm_substream *substream, + struct snd_pcm_info __user *info); +int snd_pcm_status64(struct snd_pcm_substream *substream, + struct snd_pcm_status64 *status); +int snd_pcm_start(struct snd_pcm_substream *substream); +int snd_pcm_stop(struct snd_pcm_substream *substream, snd_pcm_state_t status); +int snd_pcm_drain_done(struct snd_pcm_substream *substream); +int snd_pcm_stop_xrun(struct snd_pcm_substream *substream); +#ifdef CONFIG_PM +int snd_pcm_suspend_all(struct snd_pcm *pcm); +#else +static inline int snd_pcm_suspend_all(struct snd_pcm *pcm) +{ + return 0; +} +#endif +int snd_pcm_kernel_ioctl(struct snd_pcm_substream *substream, unsigned int cmd, void *arg); +int snd_pcm_open_substream(struct snd_pcm *pcm, int stream, struct file *file, + struct snd_pcm_substream **rsubstream); +void snd_pcm_release_substream(struct snd_pcm_substream *substream); +int snd_pcm_attach_substream(struct snd_pcm *pcm, int stream, struct file *file, + struct snd_pcm_substream **rsubstream); +void snd_pcm_detach_substream(struct snd_pcm_substream *substream); +int snd_pcm_mmap_data(struct snd_pcm_substream *substream, struct file *file, struct vm_area_struct *area); + + +#ifdef CONFIG_SND_DEBUG +void snd_pcm_debug_name(struct snd_pcm_substream *substream, + char *name, size_t len); +#else +static inline void +snd_pcm_debug_name(struct snd_pcm_substream *substream, char *buf, size_t size) +{ + *buf = 0; +} +#endif + +/* + * PCM library + */ + +/** + * snd_pcm_stream_linked - Check whether the substream is linked with others + * @substream: substream to check + * + * Return: true if the given substream is being linked with others + */ +static inline int snd_pcm_stream_linked(struct snd_pcm_substream *substream) +{ + return substream->group != &substream->self_group; +} + +void snd_pcm_stream_lock(struct snd_pcm_substream *substream); +void snd_pcm_stream_unlock(struct snd_pcm_substream *substream); +void snd_pcm_stream_lock_irq(struct snd_pcm_substream *substream); +void snd_pcm_stream_unlock_irq(struct snd_pcm_substream *substream); +unsigned long _snd_pcm_stream_lock_irqsave(struct snd_pcm_substream *substream); +unsigned long _snd_pcm_stream_lock_irqsave_nested(struct snd_pcm_substream *substream); + +/** + * snd_pcm_stream_lock_irqsave - Lock the PCM stream + * @substream: PCM substream + * @flags: irq flags + * + * This locks the PCM stream like snd_pcm_stream_lock() but with the local + * IRQ (only when nonatomic is false). In nonatomic case, this is identical + * as snd_pcm_stream_lock(). + */ +#define snd_pcm_stream_lock_irqsave(substream, flags) \ + do { \ + typecheck(unsigned long, flags); \ + flags = _snd_pcm_stream_lock_irqsave(substream); \ + } while (0) +void snd_pcm_stream_unlock_irqrestore(struct snd_pcm_substream *substream, + unsigned long flags); + +/** + * snd_pcm_stream_lock_irqsave_nested - Single-nested PCM stream locking + * @substream: PCM substream + * @flags: irq flags + * + * This locks the PCM stream like snd_pcm_stream_lock_irqsave() but with + * the single-depth lockdep subclass. + */ +#define snd_pcm_stream_lock_irqsave_nested(substream, flags) \ + do { \ + typecheck(unsigned long, flags); \ + flags = _snd_pcm_stream_lock_irqsave_nested(substream); \ + } while (0) + +/* definitions for guard(); use like guard(pcm_stream_lock) */ +DEFINE_LOCK_GUARD_1(pcm_stream_lock, struct snd_pcm_substream, + snd_pcm_stream_lock(_T->lock), + snd_pcm_stream_unlock(_T->lock)) +DEFINE_LOCK_GUARD_1(pcm_stream_lock_irq, struct snd_pcm_substream, + snd_pcm_stream_lock_irq(_T->lock), + snd_pcm_stream_unlock_irq(_T->lock)) +DEFINE_LOCK_GUARD_1(pcm_stream_lock_irqsave, struct snd_pcm_substream, + snd_pcm_stream_lock_irqsave(_T->lock, _T->flags), + snd_pcm_stream_unlock_irqrestore(_T->lock, _T->flags), + unsigned long flags) + +/** + * snd_pcm_group_for_each_entry - iterate over the linked substreams + * @s: the iterator + * @substream: the substream + * + * Iterate over the all linked substreams to the given @substream. + * When @substream isn't linked with any others, this gives returns @substream + * itself once. + */ +#define snd_pcm_group_for_each_entry(s, substream) \ + list_for_each_entry(s, &substream->group->substreams, link_list) + +#define for_each_pcm_streams(stream) \ + for (stream = SNDRV_PCM_STREAM_PLAYBACK; \ + stream <= SNDRV_PCM_STREAM_LAST; \ + stream++) + +/** + * snd_pcm_running - Check whether the substream is in a running state + * @substream: substream to check + * + * Return: true if the given substream is in the state RUNNING, or in the + * state DRAINING for playback. + */ +static inline int snd_pcm_running(struct snd_pcm_substream *substream) +{ + return (substream->runtime->state == SNDRV_PCM_STATE_RUNNING || + (substream->runtime->state == SNDRV_PCM_STATE_DRAINING && + substream->stream == SNDRV_PCM_STREAM_PLAYBACK)); +} + +/** + * __snd_pcm_set_state - Change the current PCM state + * @runtime: PCM runtime to set + * @state: the current state to set + * + * Call within the stream lock + */ +static inline void __snd_pcm_set_state(struct snd_pcm_runtime *runtime, + snd_pcm_state_t state) +{ + runtime->state = state; + runtime->status->state = state; /* copy for mmap */ +} + +void snd_pcm_set_state(struct snd_pcm_substream *substream, + snd_pcm_state_t state); +snd_pcm_state_t snd_pcm_get_state(struct snd_pcm_substream *substream); + +/** + * bytes_to_samples - Unit conversion of the size from bytes to samples + * @runtime: PCM runtime instance + * @size: size in bytes + * + * Return: the size in samples + */ +static inline ssize_t bytes_to_samples(struct snd_pcm_runtime *runtime, ssize_t size) +{ + return size * 8 / runtime->sample_bits; +} + +/** + * bytes_to_frames - Unit conversion of the size from bytes to frames + * @runtime: PCM runtime instance + * @size: size in bytes + * + * Return: the size in frames + */ +static inline snd_pcm_sframes_t bytes_to_frames(struct snd_pcm_runtime *runtime, ssize_t size) +{ + return size * 8 / runtime->frame_bits; +} + +/** + * samples_to_bytes - Unit conversion of the size from samples to bytes + * @runtime: PCM runtime instance + * @size: size in samples + * + * Return: the byte size + */ +static inline ssize_t samples_to_bytes(struct snd_pcm_runtime *runtime, ssize_t size) +{ + return size * runtime->sample_bits / 8; +} + +/** + * frames_to_bytes - Unit conversion of the size from frames to bytes + * @runtime: PCM runtime instance + * @size: size in frames + * + * Return: the byte size + */ +static inline ssize_t frames_to_bytes(struct snd_pcm_runtime *runtime, snd_pcm_sframes_t size) +{ + return size * runtime->frame_bits / 8; +} + +/** + * frame_aligned - Check whether the byte size is aligned to frames + * @runtime: PCM runtime instance + * @bytes: size in bytes + * + * Return: true if aligned, or false if not + */ +static inline int frame_aligned(struct snd_pcm_runtime *runtime, ssize_t bytes) +{ + return bytes % runtime->byte_align == 0; +} + +/** + * snd_pcm_lib_buffer_bytes - Get the buffer size of the current PCM in bytes + * @substream: PCM substream + * + * Return: buffer byte size + */ +static inline size_t snd_pcm_lib_buffer_bytes(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return frames_to_bytes(runtime, runtime->buffer_size); +} + +/** + * snd_pcm_lib_period_bytes - Get the period size of the current PCM in bytes + * @substream: PCM substream + * + * Return: period byte size + */ +static inline size_t snd_pcm_lib_period_bytes(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return frames_to_bytes(runtime, runtime->period_size); +} + +/** + * snd_pcm_playback_avail - Get the available (writable) space for playback + * @runtime: PCM runtime instance + * + * Result is between 0 ... (boundary - 1) + * + * Return: available frame size + */ +static inline snd_pcm_uframes_t snd_pcm_playback_avail(struct snd_pcm_runtime *runtime) +{ + snd_pcm_sframes_t avail = runtime->status->hw_ptr + runtime->buffer_size - runtime->control->appl_ptr; + if (avail < 0) + avail += runtime->boundary; + else if ((snd_pcm_uframes_t) avail >= runtime->boundary) + avail -= runtime->boundary; + return avail; +} + +/** + * snd_pcm_capture_avail - Get the available (readable) space for capture + * @runtime: PCM runtime instance + * + * Result is between 0 ... (boundary - 1) + * + * Return: available frame size + */ +static inline snd_pcm_uframes_t snd_pcm_capture_avail(struct snd_pcm_runtime *runtime) +{ + snd_pcm_sframes_t avail = runtime->status->hw_ptr - runtime->control->appl_ptr; + if (avail < 0) + avail += runtime->boundary; + return avail; +} + +/** + * snd_pcm_playback_hw_avail - Get the queued space for playback + * @runtime: PCM runtime instance + * + * Return: available frame size + */ +static inline snd_pcm_sframes_t snd_pcm_playback_hw_avail(struct snd_pcm_runtime *runtime) +{ + return runtime->buffer_size - snd_pcm_playback_avail(runtime); +} + +/** + * snd_pcm_capture_hw_avail - Get the free space for capture + * @runtime: PCM runtime instance + * + * Return: available frame size + */ +static inline snd_pcm_sframes_t snd_pcm_capture_hw_avail(struct snd_pcm_runtime *runtime) +{ + return runtime->buffer_size - snd_pcm_capture_avail(runtime); +} + +/** + * snd_pcm_playback_ready - check whether the playback buffer is available + * @substream: the pcm substream instance + * + * Checks whether enough free space is available on the playback buffer. + * + * Return: Non-zero if available, or zero if not. + */ +static inline int snd_pcm_playback_ready(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_playback_avail(runtime) >= runtime->control->avail_min; +} + +/** + * snd_pcm_capture_ready - check whether the capture buffer is available + * @substream: the pcm substream instance + * + * Checks whether enough capture data is available on the capture buffer. + * + * Return: Non-zero if available, or zero if not. + */ +static inline int snd_pcm_capture_ready(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_capture_avail(runtime) >= runtime->control->avail_min; +} + +/** + * snd_pcm_playback_data - check whether any data exists on the playback buffer + * @substream: the pcm substream instance + * + * Checks whether any data exists on the playback buffer. + * + * Return: Non-zero if any data exists, or zero if not. If stop_threshold + * is bigger or equal to boundary, then this function returns always non-zero. + */ +static inline int snd_pcm_playback_data(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + if (runtime->stop_threshold >= runtime->boundary) + return 1; + return snd_pcm_playback_avail(runtime) < runtime->buffer_size; +} + +/** + * snd_pcm_playback_empty - check whether the playback buffer is empty + * @substream: the pcm substream instance + * + * Checks whether the playback buffer is empty. + * + * Return: Non-zero if empty, or zero if not. + */ +static inline int snd_pcm_playback_empty(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_playback_avail(runtime) >= runtime->buffer_size; +} + +/** + * snd_pcm_capture_empty - check whether the capture buffer is empty + * @substream: the pcm substream instance + * + * Checks whether the capture buffer is empty. + * + * Return: Non-zero if empty, or zero if not. + */ +static inline int snd_pcm_capture_empty(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_capture_avail(runtime) == 0; +} + +/** + * snd_pcm_trigger_done - Mark the master substream + * @substream: the pcm substream instance + * @master: the linked master substream + * + * When multiple substreams of the same card are linked and the hardware + * supports the single-shot operation, the driver calls this in the loop + * in snd_pcm_group_for_each_entry() for marking the substream as "done". + * Then most of trigger operations are performed only to the given master + * substream. + * + * The trigger_master mark is cleared at timestamp updates at the end + * of trigger operations. + */ +static inline void snd_pcm_trigger_done(struct snd_pcm_substream *substream, + struct snd_pcm_substream *master) +{ + substream->runtime->trigger_master = master; +} + +static inline int hw_is_mask(int var) +{ + return var >= SNDRV_PCM_HW_PARAM_FIRST_MASK && + var <= SNDRV_PCM_HW_PARAM_LAST_MASK; +} + +static inline int hw_is_interval(int var) +{ + return var >= SNDRV_PCM_HW_PARAM_FIRST_INTERVAL && + var <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; +} + +static inline struct snd_mask *hw_param_mask(struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; +} + +static inline struct snd_interval *hw_param_interval(struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL]; +} + +static inline const struct snd_mask *hw_param_mask_c(const struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; +} + +static inline const struct snd_interval *hw_param_interval_c(const struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL]; +} + +/** + * params_channels - Get the number of channels from the hw params + * @p: hw params + * + * Return: the number of channels + */ +static inline unsigned int params_channels(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_CHANNELS)->min; +} + +/** + * params_rate - Get the sample rate from the hw params + * @p: hw params + * + * Return: the sample rate + */ +static inline unsigned int params_rate(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_RATE)->min; +} + +/** + * params_period_size - Get the period size (in frames) from the hw params + * @p: hw params + * + * Return: the period size in frames + */ +static inline unsigned int params_period_size(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_PERIOD_SIZE)->min; +} + +/** + * params_periods - Get the number of periods from the hw params + * @p: hw params + * + * Return: the number of periods + */ +static inline unsigned int params_periods(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_PERIODS)->min; +} + +/** + * params_buffer_size - Get the buffer size (in frames) from the hw params + * @p: hw params + * + * Return: the buffer size in frames + */ +static inline unsigned int params_buffer_size(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_BUFFER_SIZE)->min; +} + +/** + * params_buffer_bytes - Get the buffer size (in bytes) from the hw params + * @p: hw params + * + * Return: the buffer size in bytes + */ +static inline unsigned int params_buffer_bytes(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_BUFFER_BYTES)->min; +} + +int snd_interval_refine(struct snd_interval *i, const struct snd_interval *v); +int snd_interval_list(struct snd_interval *i, unsigned int count, + const unsigned int *list, unsigned int mask); +int snd_interval_ranges(struct snd_interval *i, unsigned int count, + const struct snd_interval *list, unsigned int mask); +int snd_interval_ratnum(struct snd_interval *i, + unsigned int rats_count, const struct snd_ratnum *rats, + unsigned int *nump, unsigned int *denp); + +void _snd_pcm_hw_params_any(struct snd_pcm_hw_params *params); +void _snd_pcm_hw_param_setempty(struct snd_pcm_hw_params *params, snd_pcm_hw_param_t var); + +int snd_pcm_hw_refine(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params); + +int snd_pcm_hw_constraint_mask64(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, + u_int64_t mask); +int snd_pcm_hw_constraint_minmax(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, + unsigned int min, unsigned int max); +int snd_pcm_hw_constraint_integer(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var); +int snd_pcm_hw_constraint_list(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_list *l); +int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_ranges *r); +int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_ratnums *r); +int snd_pcm_hw_constraint_ratdens(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_ratdens *r); +int snd_pcm_hw_constraint_msbits(struct snd_pcm_runtime *runtime, + unsigned int cond, + unsigned int width, + unsigned int msbits); +int snd_pcm_hw_constraint_step(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + unsigned long step); +int snd_pcm_hw_constraint_pow2(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var); +int snd_pcm_hw_rule_noresample(struct snd_pcm_runtime *runtime, + unsigned int base_rate); +int snd_pcm_hw_rule_add(struct snd_pcm_runtime *runtime, + unsigned int cond, + int var, + snd_pcm_hw_rule_func_t func, void *private, + int dep, ...); + +/** + * snd_pcm_hw_constraint_single() - Constrain parameter to a single value + * @runtime: PCM runtime instance + * @var: The hw_params variable to constrain + * @val: The value to constrain to + * + * Return: Positive if the value is changed, zero if it's not changed, or a + * negative error code. + */ +static inline int snd_pcm_hw_constraint_single( + struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, + unsigned int val) +{ + return snd_pcm_hw_constraint_minmax(runtime, var, val, val); +} + +int snd_pcm_format_signed(snd_pcm_format_t format); +int snd_pcm_format_unsigned(snd_pcm_format_t format); +int snd_pcm_format_linear(snd_pcm_format_t format); +int snd_pcm_format_little_endian(snd_pcm_format_t format); +int snd_pcm_format_big_endian(snd_pcm_format_t format); +#if 0 /* just for kernel-doc */ +/** + * snd_pcm_format_cpu_endian - Check the PCM format is CPU-endian + * @format: the format to check + * + * Return: 1 if the given PCM format is CPU-endian, 0 if + * opposite, or a negative error code if endian not specified. + */ +int snd_pcm_format_cpu_endian(snd_pcm_format_t format); +#endif /* DocBook */ +#ifdef SNDRV_LITTLE_ENDIAN +#define snd_pcm_format_cpu_endian(format) snd_pcm_format_little_endian(format) +#else +#define snd_pcm_format_cpu_endian(format) snd_pcm_format_big_endian(format) +#endif +int snd_pcm_format_width(snd_pcm_format_t format); /* in bits */ +int snd_pcm_format_physical_width(snd_pcm_format_t format); /* in bits */ +ssize_t snd_pcm_format_size(snd_pcm_format_t format, size_t samples); +const unsigned char *snd_pcm_format_silence_64(snd_pcm_format_t format); +int snd_pcm_format_set_silence(snd_pcm_format_t format, void *buf, unsigned int frames); + +void snd_pcm_set_ops(struct snd_pcm * pcm, int direction, + const struct snd_pcm_ops *ops); +void snd_pcm_set_sync_per_card(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, + const unsigned char *id, unsigned int len); +/** + * snd_pcm_set_sync - set the PCM sync id + * @substream: the pcm substream + * + * Use the default PCM sync identifier for the specific card. + */ +static inline void snd_pcm_set_sync(struct snd_pcm_substream *substream) +{ + substream->runtime->std_sync_id = true; +} +int snd_pcm_lib_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); +void snd_pcm_period_elapsed_under_stream_lock(struct snd_pcm_substream *substream); +void snd_pcm_period_elapsed(struct snd_pcm_substream *substream); +snd_pcm_sframes_t __snd_pcm_lib_xfer(struct snd_pcm_substream *substream, + void *buf, bool interleaved, + snd_pcm_uframes_t frames, bool in_kernel); + +static inline snd_pcm_sframes_t +snd_pcm_lib_write(struct snd_pcm_substream *substream, + const void __user *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void __force *)buf, true, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_lib_read(struct snd_pcm_substream *substream, + void __user *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void __force *)buf, true, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_lib_writev(struct snd_pcm_substream *substream, + void __user **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void *)bufs, false, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_lib_readv(struct snd_pcm_substream *substream, + void __user **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void *)bufs, false, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_write(struct snd_pcm_substream *substream, + const void *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void *)buf, true, frames, true); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_read(struct snd_pcm_substream *substream, + void *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, buf, true, frames, true); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_writev(struct snd_pcm_substream *substream, + void **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, bufs, false, frames, true); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_readv(struct snd_pcm_substream *substream, + void **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, bufs, false, frames, true); +} + +int snd_pcm_hw_limit_rates(struct snd_pcm_hardware *hw); + +static inline int +snd_pcm_limit_hw_rates(struct snd_pcm_runtime *runtime) +{ + return snd_pcm_hw_limit_rates(&runtime->hw); +} + +unsigned int snd_pcm_rate_to_rate_bit(unsigned int rate); +unsigned int snd_pcm_rate_bit_to_rate(unsigned int rate_bit); +unsigned int snd_pcm_rate_mask_intersect(unsigned int rates_a, + unsigned int rates_b); + +/** + * snd_pcm_set_runtime_buffer - Set the PCM runtime buffer + * @substream: PCM substream to set + * @bufp: the buffer information, NULL to clear + * + * Copy the buffer information to runtime->dma_buffer when @bufp is non-NULL. + * Otherwise it clears the current buffer information. + */ +static inline void snd_pcm_set_runtime_buffer(struct snd_pcm_substream *substream, + struct snd_dma_buffer *bufp) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + if (bufp) { + runtime->dma_buffer_p = bufp; + runtime->dma_area = bufp->area; + runtime->dma_addr = bufp->addr; + runtime->dma_bytes = bufp->bytes; + } else { + runtime->dma_buffer_p = NULL; + runtime->dma_area = NULL; + runtime->dma_addr = 0; + runtime->dma_bytes = 0; + } +} + +/** + * snd_pcm_gettime - Fill the timespec64 depending on the timestamp mode + * @runtime: PCM runtime instance + * @tv: timespec64 to fill + */ +static inline void snd_pcm_gettime(struct snd_pcm_runtime *runtime, + struct timespec64 *tv) +{ + switch (runtime->tstamp_type) { + case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC: + ktime_get_ts64(tv); + break; + case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW: + ktime_get_raw_ts64(tv); + break; + default: + ktime_get_real_ts64(tv); + break; + } +} + +/* + * Memory + */ + +void snd_pcm_lib_preallocate_free(struct snd_pcm_substream *substream); +void snd_pcm_lib_preallocate_free_for_all(struct snd_pcm *pcm); +void snd_pcm_lib_preallocate_pages(struct snd_pcm_substream *substream, + int type, struct device *data, + size_t size, size_t max); +void snd_pcm_lib_preallocate_pages_for_all(struct snd_pcm *pcm, + int type, void *data, + size_t size, size_t max); +int snd_pcm_lib_malloc_pages(struct snd_pcm_substream *substream, size_t size); +int snd_pcm_lib_free_pages(struct snd_pcm_substream *substream); + +int snd_pcm_set_managed_buffer(struct snd_pcm_substream *substream, int type, + struct device *data, size_t size, size_t max); +int snd_pcm_set_managed_buffer_all(struct snd_pcm *pcm, int type, + struct device *data, + size_t size, size_t max); + +/** + * snd_pcm_set_fixed_buffer - Preallocate and set up the fixed size PCM buffer + * @substream: the pcm substream instance + * @type: DMA type (SNDRV_DMA_TYPE_*) + * @data: DMA type dependent data + * @size: the requested pre-allocation size in bytes + * + * This is a variant of snd_pcm_set_managed_buffer(), but this pre-allocates + * only the given sized buffer and doesn't allow re-allocation nor dynamic + * allocation of a larger buffer unlike the standard one. + * The function may return -ENOMEM error, hence the caller must check it. + * + * Return: zero if successful, or a negative error code + */ +static inline int __must_check +snd_pcm_set_fixed_buffer(struct snd_pcm_substream *substream, int type, + struct device *data, size_t size) +{ + return snd_pcm_set_managed_buffer(substream, type, data, size, 0); +} + +/** + * snd_pcm_set_fixed_buffer_all - Preallocate and set up the fixed size PCM buffer + * @pcm: the pcm instance + * @type: DMA type (SNDRV_DMA_TYPE_*) + * @data: DMA type dependent data + * @size: the requested pre-allocation size in bytes + * + * Apply the set up of the fixed buffer via snd_pcm_set_fixed_buffer() for + * all substream. If any of allocation fails, it returns -ENOMEM, hence the + * caller must check the return value. + * + * Return: zero if successful, or a negative error code + */ +static inline int __must_check +snd_pcm_set_fixed_buffer_all(struct snd_pcm *pcm, int type, + struct device *data, size_t size) +{ + return snd_pcm_set_managed_buffer_all(pcm, type, data, size, 0); +} + +#define snd_pcm_get_dma_buf(substream) ((substream)->runtime->dma_buffer_p) + +/** + * snd_pcm_sgbuf_get_addr - Get the DMA address at the corresponding offset + * @substream: PCM substream + * @ofs: byte offset + * + * Return: DMA address + */ +static inline dma_addr_t +snd_pcm_sgbuf_get_addr(struct snd_pcm_substream *substream, unsigned int ofs) +{ + return snd_sgbuf_get_addr(snd_pcm_get_dma_buf(substream), ofs); +} + +/** + * snd_pcm_sgbuf_get_chunk_size - Compute the max size that fits within the + * contig. page from the given size + * @substream: PCM substream + * @ofs: byte offset + * @size: byte size to examine + * + * Return: chunk size + */ +static inline unsigned int +snd_pcm_sgbuf_get_chunk_size(struct snd_pcm_substream *substream, + unsigned int ofs, unsigned int size) +{ + return snd_sgbuf_get_chunk_size(snd_pcm_get_dma_buf(substream), ofs, size); +} + +int snd_pcm_lib_default_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *area); +/* mmap for io-memory area */ +#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA) +#define SNDRV_PCM_INFO_MMAP_IOMEM SNDRV_PCM_INFO_MMAP +int snd_pcm_lib_mmap_iomem(struct snd_pcm_substream *substream, struct vm_area_struct *area); +#else +#define SNDRV_PCM_INFO_MMAP_IOMEM 0 +#define snd_pcm_lib_mmap_iomem NULL +#endif + +int snd_pcm_runtime_buffer_set_silence(struct snd_pcm_runtime *runtime); + +/** + * snd_pcm_limit_isa_dma_size - Get the max size fitting with ISA DMA transfer + * @dma: DMA number + * @max: pointer to store the max size + */ +static inline void snd_pcm_limit_isa_dma_size(int dma, size_t *max) +{ + *max = dma < 4 ? 64 * 1024 : 128 * 1024; +} + +/* + * Misc + */ + +#define SNDRV_PCM_DEFAULT_CON_SPDIF (IEC958_AES0_CON_EMPHASIS_NONE|\ + (IEC958_AES1_CON_ORIGINAL<<8)|\ + (IEC958_AES1_CON_PCM_CODER<<8)|\ + (IEC958_AES3_CON_FS_48000<<24)) + +const char *snd_pcm_format_name(snd_pcm_format_t format); + +/** + * snd_pcm_direction_name - Get a string naming the direction of a stream + * @direction: Stream's direction, one of SNDRV_PCM_STREAM_XXX + * + * Returns a string naming the direction of the stream. + */ +static inline const char *snd_pcm_direction_name(int direction) +{ + if (direction == SNDRV_PCM_STREAM_PLAYBACK) + return "Playback"; + else + return "Capture"; +} + +/** + * snd_pcm_stream_str - Get a string naming the direction of a stream + * @substream: the pcm substream instance + * + * Return: A string naming the direction of the stream. + */ +static inline const char *snd_pcm_stream_str(struct snd_pcm_substream *substream) +{ + return snd_pcm_direction_name(substream->stream); +} + +/* + * PCM channel-mapping control API + */ +/* array element of channel maps */ +struct snd_pcm_chmap_elem { + unsigned char channels; + unsigned char map[15]; +}; + +/* channel map information; retrieved via snd_kcontrol_chip() */ +struct snd_pcm_chmap { + struct snd_pcm *pcm; /* assigned PCM instance */ + int stream; /* PLAYBACK or CAPTURE */ + struct snd_kcontrol *kctl; + const struct snd_pcm_chmap_elem *chmap; + unsigned int max_channels; + unsigned int channel_mask; /* optional: active channels bitmask */ + void *private_data; /* optional: private data pointer */ +}; + +/** + * snd_pcm_chmap_substream - get the PCM substream assigned to the given chmap info + * @info: chmap information + * @idx: the substream number index + * + * Return: the matched PCM substream, or NULL if not found + */ +static inline struct snd_pcm_substream * +snd_pcm_chmap_substream(struct snd_pcm_chmap *info, unsigned int idx) +{ + struct snd_pcm_substream *s; + for (s = info->pcm->streams[info->stream].substream; s; s = s->next) + if (s->number == idx) + return s; + return NULL; +} + +/* ALSA-standard channel maps (RL/RR prior to C/LFE) */ +extern const struct snd_pcm_chmap_elem snd_pcm_std_chmaps[]; +/* Other world's standard channel maps (C/LFE prior to RL/RR) */ +extern const struct snd_pcm_chmap_elem snd_pcm_alt_chmaps[]; + +/* bit masks to be passed to snd_pcm_chmap.channel_mask field */ +#define SND_PCM_CHMAP_MASK_24 ((1U << 2) | (1U << 4)) +#define SND_PCM_CHMAP_MASK_246 (SND_PCM_CHMAP_MASK_24 | (1U << 6)) +#define SND_PCM_CHMAP_MASK_2468 (SND_PCM_CHMAP_MASK_246 | (1U << 8)) + +int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_chmap_elem *chmap, + int max_channels, + unsigned long private_value, + struct snd_pcm_chmap **info_ret); + +/** + * pcm_format_to_bits - Strong-typed conversion of pcm_format to bitwise + * @pcm_format: PCM format + * + * Return: 64bit mask corresponding to the given PCM format + */ +static inline u64 pcm_format_to_bits(snd_pcm_format_t pcm_format) +{ + return 1ULL << pcm_format; +} + +/** + * pcm_for_each_format - helper to iterate for each format type + * @f: the iterator variable in snd_pcm_format_t type + */ +#define pcm_for_each_format(f) \ + for ((f) = SNDRV_PCM_FORMAT_FIRST; (f) <= SNDRV_PCM_FORMAT_LAST; (f)++) + +/* printk helpers */ +#define pcm_err(pcm, fmt, args...) \ + dev_err((pcm)->card->dev, fmt, ##args) +#define pcm_warn(pcm, fmt, args...) \ + dev_warn((pcm)->card->dev, fmt, ##args) +#define pcm_dbg(pcm, fmt, args...) \ + dev_dbg((pcm)->card->dev, fmt, ##args) + +/* helpers for copying between iov_iter and iomem */ +size_t copy_to_iter_fromio(const void __iomem *src, size_t bytes, + struct iov_iter *iter) __must_check; +size_t copy_from_iter_toio(void __iomem *dst, size_t bytes, + struct iov_iter *iter) __must_check; + +struct snd_pcm_status64 { + snd_pcm_state_t state; /* stream state */ + u8 rsvd[4]; + s64 trigger_tstamp_sec; /* time when stream was started/stopped/paused */ + s64 trigger_tstamp_nsec; + s64 tstamp_sec; /* reference timestamp */ + s64 tstamp_nsec; + snd_pcm_uframes_t appl_ptr; /* appl ptr */ + snd_pcm_uframes_t hw_ptr; /* hw ptr */ + snd_pcm_sframes_t delay; /* current delay in frames */ + snd_pcm_uframes_t avail; /* number of frames available */ + snd_pcm_uframes_t avail_max; /* max frames available on hw since last status */ + snd_pcm_uframes_t overrange; /* count of ADC (capture) overrange detections from last status */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + __u32 audio_tstamp_data; /* needed for 64-bit alignment, used for configs/report to/from userspace */ + s64 audio_tstamp_sec; /* sample counter, wall clock, PHC or on-demand sync'ed */ + s64 audio_tstamp_nsec; + s64 driver_tstamp_sec; /* useful in case reference system tstamp is reported with delay */ + s64 driver_tstamp_nsec; + __u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ + unsigned char reserved[52-4*sizeof(s64)]; /* must be filled with zero */ +}; + +#define SNDRV_PCM_IOCTL_STATUS64 _IOR('A', 0x20, struct snd_pcm_status64) +#define SNDRV_PCM_IOCTL_STATUS_EXT64 _IOWR('A', 0x24, struct snd_pcm_status64) + +struct snd_pcm_status32 { + snd_pcm_state_t state; /* stream state */ + s32 trigger_tstamp_sec; /* time when stream was started/stopped/paused */ + s32 trigger_tstamp_nsec; + s32 tstamp_sec; /* reference timestamp */ + s32 tstamp_nsec; + u32 appl_ptr; /* appl ptr */ + u32 hw_ptr; /* hw ptr */ + s32 delay; /* current delay in frames */ + u32 avail; /* number of frames available */ + u32 avail_max; /* max frames available on hw since last status */ + u32 overrange; /* count of ADC (capture) overrange detections from last status */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + u32 audio_tstamp_data; /* needed for 64-bit alignment, used for configs/report to/from userspace */ + s32 audio_tstamp_sec; /* sample counter, wall clock, PHC or on-demand sync'ed */ + s32 audio_tstamp_nsec; + s32 driver_tstamp_sec; /* useful in case reference system tstamp is reported with delay */ + s32 driver_tstamp_nsec; + u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ + unsigned char reserved[52-4*sizeof(s32)]; /* must be filled with zero */ +}; + +#define SNDRV_PCM_IOCTL_STATUS32 _IOR('A', 0x20, struct snd_pcm_status32) +#define SNDRV_PCM_IOCTL_STATUS_EXT32 _IOWR('A', 0x24, struct snd_pcm_status32) + +#endif /* __SOUND_PCM_H */ diff --git a/include/sound/pcm_drm_eld.h b/include/sound/pcm_drm_eld.h new file mode 100644 index 000000000..5a38413ad --- /dev/null +++ b/include/sound/pcm_drm_eld.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_PCM_DRM_ELD_H +#define __SOUND_PCM_DRM_ELD_H + +enum eld_versions { + ELD_VER_CEA_861D = 2, + ELD_VER_PARTIAL = 31, +}; + +enum cea_audio_coding_types { + AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0, + AUDIO_CODING_TYPE_LPCM = 1, + AUDIO_CODING_TYPE_AC3 = 2, + AUDIO_CODING_TYPE_MPEG1 = 3, + AUDIO_CODING_TYPE_MP3 = 4, + AUDIO_CODING_TYPE_MPEG2 = 5, + AUDIO_CODING_TYPE_AACLC = 6, + AUDIO_CODING_TYPE_DTS = 7, + AUDIO_CODING_TYPE_ATRAC = 8, + AUDIO_CODING_TYPE_SACD = 9, + AUDIO_CODING_TYPE_EAC3 = 10, + AUDIO_CODING_TYPE_DTS_HD = 11, + AUDIO_CODING_TYPE_MLP = 12, + AUDIO_CODING_TYPE_DST = 13, + AUDIO_CODING_TYPE_WMAPRO = 14, + AUDIO_CODING_TYPE_REF_CXT = 15, + /* also include valid xtypes below */ + AUDIO_CODING_TYPE_HE_AAC = 15, + AUDIO_CODING_TYPE_HE_AAC2 = 16, + AUDIO_CODING_TYPE_MPEG_SURROUND = 17, +}; + +enum cea_audio_coding_xtypes { + AUDIO_CODING_XTYPE_HE_REF_CT = 0, + AUDIO_CODING_XTYPE_HE_AAC = 1, + AUDIO_CODING_XTYPE_HE_AAC2 = 2, + AUDIO_CODING_XTYPE_MPEG_SURROUND = 3, + AUDIO_CODING_XTYPE_FIRST_RESERVED = 4, +}; + +/* + * CEA Short Audio Descriptor data + */ +struct snd_cea_sad { + int channels; + int format; /* (format == 0) indicates invalid SAD */ + int rates; + int sample_bits; /* for LPCM */ + int max_bitrate; /* for AC3...ATRAC */ + int profile; /* for WMAPRO */ +}; + +#define ELD_FIXED_BYTES 20 +#define ELD_MAX_SIZE 256 +#define ELD_MAX_MNL 16 +#define ELD_MAX_SAD 16 + +#define ELD_PCM_BITS_8 BIT(0) +#define ELD_PCM_BITS_16 BIT(1) +#define ELD_PCM_BITS_20 BIT(2) +#define ELD_PCM_BITS_24 BIT(3) +#define ELD_PCM_BITS_32 BIT(4) + +/* + * ELD: EDID Like Data + */ +struct snd_parsed_hdmi_eld { + /* + * all fields will be cleared before updating ELD + */ + int baseline_len; + int eld_ver; + int cea_edid_ver; + char monitor_name[ELD_MAX_MNL + 1]; + int manufacture_id; + int product_id; + u64 port_id; + int support_hdcp; + int support_ai; + int conn_type; + int aud_synch_delay; + int spk_alloc; + int sad_count; + struct snd_cea_sad sad[ELD_MAX_SAD]; +}; + +int snd_pcm_hw_constraint_eld(struct snd_pcm_runtime *runtime, void *eld); + +int snd_parse_eld(struct device *dev, struct snd_parsed_hdmi_eld *e, + const unsigned char *buf, int size); +void snd_show_eld(struct device *dev, struct snd_parsed_hdmi_eld *e); + +#ifdef CONFIG_SND_PROC_FS +void snd_print_eld_info(struct snd_parsed_hdmi_eld *eld, + struct snd_info_buffer *buffer); +#endif + +#endif diff --git a/include/sound/pcm_iec958.h b/include/sound/pcm_iec958.h new file mode 100644 index 000000000..64e84441c --- /dev/null +++ b/include/sound/pcm_iec958.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_PCM_IEC958_H +#define __SOUND_PCM_IEC958_H + +#include + +int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len); + +int snd_pcm_fill_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, + size_t len); + +int snd_pcm_fill_iec958_consumer_hw_params(struct snd_pcm_hw_params *params, + u8 *cs, size_t len); + +int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, + size_t len); + +int snd_pcm_create_iec958_consumer_hw_params(struct snd_pcm_hw_params *params, + u8 *cs, size_t len); +#endif diff --git a/include/sound/pcm_oss.h b/include/sound/pcm_oss.h new file mode 100644 index 000000000..c96f23c77 --- /dev/null +++ b/include/sound/pcm_oss.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_PCM_OSS_H +#define __SOUND_PCM_OSS_H + +/* + * Digital Audio (PCM) - OSS compatibility abstract layer + * Copyright (c) by Jaroslav Kysela + */ + +struct snd_pcm_oss_setup { + char *task_name; + unsigned int disable:1, + direct:1, + block:1, + nonblock:1, + partialfrag:1, + nosilence:1, + buggyptr:1; + unsigned int periods; + unsigned int period_size; + struct snd_pcm_oss_setup *next; +}; + +struct snd_pcm_oss_runtime { + unsigned params: 1, /* format/parameter change */ + prepare: 1, /* need to prepare the operation */ + trigger: 1, /* trigger flag */ + sync_trigger: 1; /* sync trigger flag */ + int rate; /* requested rate */ + int format; /* requested OSS format */ + unsigned int channels; /* requested channels */ + unsigned int fragshift; + unsigned int maxfrags; + unsigned int subdivision; /* requested subdivision */ + size_t period_bytes; /* requested period size */ + size_t period_frames; /* period frames for poll */ + size_t period_ptr; /* actual write pointer to period */ + unsigned int periods; + size_t buffer_bytes; /* requested buffer size */ + size_t bytes; /* total # bytes processed */ + size_t mmap_bytes; + char *buffer; /* vmallocated period */ + size_t buffer_used; /* used length from period buffer */ + struct mutex params_lock; + atomic_t rw_ref; /* concurrent read/write accesses */ +#ifdef CONFIG_SND_PCM_OSS_PLUGINS + struct snd_pcm_plugin *plugin_first; + struct snd_pcm_plugin *plugin_last; +#endif + unsigned int prev_hw_ptr_period; +}; + +struct snd_pcm_oss_file { + struct snd_pcm_substream *streams[2]; +}; + +struct snd_pcm_oss_substream { + unsigned oss: 1; /* oss mode */ + struct snd_pcm_oss_setup setup; /* active setup */ +}; + +struct snd_pcm_oss_stream { + struct snd_pcm_oss_setup *setup_list; /* setup list */ + struct mutex setup_mutex; +#ifdef CONFIG_SND_VERBOSE_PROCFS + struct snd_info_entry *proc_entry; +#endif +}; + +struct snd_pcm_oss { + int reg; + unsigned int reg_mask; +}; + +#endif /* __SOUND_PCM_OSS_H */ diff --git a/include/sound/pcm_params.h b/include/sound/pcm_params.h new file mode 100644 index 000000000..bc43955fc --- /dev/null +++ b/include/sound/pcm_params.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_PCM_PARAMS_H +#define __SOUND_PCM_PARAMS_H + +/* + * PCM params helpers + * Copyright (c) by Abramo Bagnara + */ + +#include + +int snd_pcm_hw_param_first(struct snd_pcm_substream *pcm, + struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var, int *dir); +int snd_pcm_hw_param_last(struct snd_pcm_substream *pcm, + struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var, int *dir); +int snd_pcm_hw_param_value(const struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var, int *dir); + +#define SNDRV_MASK_BITS 64 /* we use so far 64bits only */ +#define SNDRV_MASK_SIZE (SNDRV_MASK_BITS / 32) +#define MASK_OFS(i) ((i) >> 5) +#define MASK_BIT(i) (1U << ((i) & 31)) + +static inline void snd_mask_none(struct snd_mask *mask) +{ + memset(mask, 0, sizeof(*mask)); +} + +static inline void snd_mask_any(struct snd_mask *mask) +{ + memset(mask, 0xff, SNDRV_MASK_SIZE * sizeof(u_int32_t)); +} + +static inline int snd_mask_empty(const struct snd_mask *mask) +{ + int i; + for (i = 0; i < SNDRV_MASK_SIZE; i++) + if (mask->bits[i]) + return 0; + return 1; +} + +static inline unsigned int snd_mask_min(const struct snd_mask *mask) +{ + int i; + for (i = 0; i < SNDRV_MASK_SIZE; i++) { + if (mask->bits[i]) + return __ffs(mask->bits[i]) + (i << 5); + } + return 0; +} + +static inline unsigned int snd_mask_max(const struct snd_mask *mask) +{ + int i; + for (i = SNDRV_MASK_SIZE - 1; i >= 0; i--) { + if (mask->bits[i]) + return __fls(mask->bits[i]) + (i << 5); + } + return 0; +} + +static inline void snd_mask_set(struct snd_mask *mask, unsigned int val) +{ + mask->bits[MASK_OFS(val)] |= MASK_BIT(val); +} + +/* Most of drivers need only this one */ +static inline void snd_mask_set_format(struct snd_mask *mask, + snd_pcm_format_t format) +{ + snd_mask_set(mask, format); +} + +static inline void snd_mask_reset(struct snd_mask *mask, unsigned int val) +{ + mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val); +} + +static inline void snd_mask_set_range(struct snd_mask *mask, + unsigned int from, unsigned int to) +{ + unsigned int i; + for (i = from; i <= to; i++) + mask->bits[MASK_OFS(i)] |= MASK_BIT(i); +} + +static inline void snd_mask_reset_range(struct snd_mask *mask, + unsigned int from, unsigned int to) +{ + unsigned int i; + for (i = from; i <= to; i++) + mask->bits[MASK_OFS(i)] &= ~MASK_BIT(i); +} + +static inline void snd_mask_leave(struct snd_mask *mask, unsigned int val) +{ + unsigned int v; + v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); + snd_mask_none(mask); + mask->bits[MASK_OFS(val)] = v; +} + +static inline void snd_mask_intersect(struct snd_mask *mask, + const struct snd_mask *v) +{ + int i; + for (i = 0; i < SNDRV_MASK_SIZE; i++) + mask->bits[i] &= v->bits[i]; +} + +static inline int snd_mask_eq(const struct snd_mask *mask, + const struct snd_mask *v) +{ + return ! memcmp(mask, v, SNDRV_MASK_SIZE * sizeof(u_int32_t)); +} + +static inline void snd_mask_copy(struct snd_mask *mask, + const struct snd_mask *v) +{ + *mask = *v; +} + +static inline int snd_mask_test(const struct snd_mask *mask, unsigned int val) +{ + return mask->bits[MASK_OFS(val)] & MASK_BIT(val); +} + +/* Most of drivers need only this one */ +static inline int snd_mask_test_format(const struct snd_mask *mask, + snd_pcm_format_t format) +{ + return snd_mask_test(mask, format); +} + +static inline int snd_mask_single(const struct snd_mask *mask) +{ + int i, c = 0; + for (i = 0; i < SNDRV_MASK_SIZE; i++) { + if (! mask->bits[i]) + continue; + if (mask->bits[i] & (mask->bits[i] - 1)) + return 0; + if (c) + return 0; + c++; + } + return 1; +} + +static inline int snd_mask_refine(struct snd_mask *mask, + const struct snd_mask *v) +{ + struct snd_mask old; + snd_mask_copy(&old, mask); + snd_mask_intersect(mask, v); + if (snd_mask_empty(mask)) + return -EINVAL; + return !snd_mask_eq(mask, &old); +} + +static inline int snd_mask_refine_first(struct snd_mask *mask) +{ + if (snd_mask_single(mask)) + return 0; + snd_mask_leave(mask, snd_mask_min(mask)); + return 1; +} + +static inline int snd_mask_refine_last(struct snd_mask *mask) +{ + if (snd_mask_single(mask)) + return 0; + snd_mask_leave(mask, snd_mask_max(mask)); + return 1; +} + +static inline int snd_mask_refine_min(struct snd_mask *mask, unsigned int val) +{ + if (snd_mask_min(mask) >= val) + return 0; + snd_mask_reset_range(mask, 0, val - 1); + if (snd_mask_empty(mask)) + return -EINVAL; + return 1; +} + +static inline int snd_mask_refine_max(struct snd_mask *mask, unsigned int val) +{ + if (snd_mask_max(mask) <= val) + return 0; + snd_mask_reset_range(mask, val + 1, SNDRV_MASK_BITS); + if (snd_mask_empty(mask)) + return -EINVAL; + return 1; +} + +static inline int snd_mask_refine_set(struct snd_mask *mask, unsigned int val) +{ + int changed; + changed = !snd_mask_single(mask); + snd_mask_leave(mask, val); + if (snd_mask_empty(mask)) + return -EINVAL; + return changed; +} + +static inline int snd_mask_value(const struct snd_mask *mask) +{ + return snd_mask_min(mask); +} + +static inline void snd_interval_any(struct snd_interval *i) +{ + i->min = 0; + i->openmin = 0; + i->max = UINT_MAX; + i->openmax = 0; + i->integer = 0; + i->empty = 0; +} + +static inline void snd_interval_none(struct snd_interval *i) +{ + i->empty = 1; +} + +static inline int snd_interval_checkempty(const struct snd_interval *i) +{ + return (i->min > i->max || + (i->min == i->max && (i->openmin || i->openmax))); +} + +static inline int snd_interval_empty(const struct snd_interval *i) +{ + return i->empty; +} + +static inline int snd_interval_single(const struct snd_interval *i) +{ + return (i->min == i->max || + (i->min + 1 == i->max && (i->openmin || i->openmax))); +} + +static inline int snd_interval_value(const struct snd_interval *i) +{ + if (i->openmin && !i->openmax) + return i->max; + return i->min; +} + +static inline int snd_interval_min(const struct snd_interval *i) +{ + return i->min; +} + +static inline int snd_interval_max(const struct snd_interval *i) +{ + unsigned int v; + v = i->max; + if (i->openmax) + v--; + return v; +} + +static inline int snd_interval_test(const struct snd_interval *i, unsigned int val) +{ + return !((i->min > val || (i->min == val && i->openmin) || + i->max < val || (i->max == val && i->openmax))); +} + +static inline void snd_interval_copy(struct snd_interval *d, const struct snd_interval *s) +{ + *d = *s; +} + +static inline int snd_interval_setinteger(struct snd_interval *i) +{ + if (i->integer) + return 0; + if (i->openmin && i->openmax && i->min == i->max) + return -EINVAL; + i->integer = 1; + return 1; +} + +static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) +{ + if (i1->empty) + return i2->empty; + if (i2->empty) + return i1->empty; + return i1->min == i2->min && i1->openmin == i2->openmin && + i1->max == i2->max && i1->openmax == i2->openmax; +} + +/** + * params_access - get the access type from the hw params + * @p: hw params + */ +static inline snd_pcm_access_t params_access(const struct snd_pcm_hw_params *p) +{ + return snd_mask_min(hw_param_mask_c(p, SNDRV_PCM_HW_PARAM_ACCESS)); +} + +/** + * params_format - get the sample format from the hw params + * @p: hw params + */ +static inline snd_pcm_format_t params_format(const struct snd_pcm_hw_params *p) +{ + return snd_mask_min(hw_param_mask_c(p, SNDRV_PCM_HW_PARAM_FORMAT)); +} + +/** + * params_subformat - get the sample subformat from the hw params + * @p: hw params + */ +static inline snd_pcm_subformat_t +params_subformat(const struct snd_pcm_hw_params *p) +{ + return snd_mask_min(hw_param_mask_c(p, SNDRV_PCM_HW_PARAM_SUBFORMAT)); +} + +/** + * params_period_bytes - get the period size (in bytes) from the hw params + * @p: hw params + */ +static inline unsigned int +params_period_bytes(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_PERIOD_BYTES)->min; +} + +/** + * params_width - get the number of bits of the sample format from the hw params + * @p: hw params + * + * This function returns the number of bits per sample that the selected sample + * format of the hw params has. + */ +static inline int params_width(const struct snd_pcm_hw_params *p) +{ + return snd_pcm_format_width(params_format(p)); +} + +/* + * params_physical_width - get the storage size of the sample format from the hw params + * @p: hw params + * + * This functions returns the number of bits per sample that the selected sample + * format of the hw params takes up in memory. This will be equal or larger than + * params_width(). + */ +static inline int params_physical_width(const struct snd_pcm_hw_params *p) +{ + return snd_pcm_format_physical_width(params_format(p)); +} + +int snd_pcm_hw_params_bits(const struct snd_pcm_hw_params *p); + +static inline void +params_set_format(struct snd_pcm_hw_params *p, snd_pcm_format_t fmt) +{ + snd_mask_set_format(hw_param_mask(p, SNDRV_PCM_HW_PARAM_FORMAT), fmt); +} + +#endif /* __SOUND_PCM_PARAMS_H */ diff --git a/include/sound/pt2258.h b/include/sound/pt2258.h new file mode 100644 index 000000000..8c32e71cd --- /dev/null +++ b/include/sound/pt2258.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ALSA Driver for the PT2258 volume controller. + * + * Copyright (c) 2006 Jochen Voss + */ + +#ifndef __SOUND_PT2258_H +#define __SOUND_PT2258_H + +struct snd_pt2258 { + struct snd_card *card; + struct snd_i2c_bus *i2c_bus; + struct snd_i2c_device *i2c_dev; + + unsigned char volume[6]; + int mute; +}; + +extern int snd_pt2258_reset(struct snd_pt2258 *pt); +extern int snd_pt2258_build_controls(struct snd_pt2258 *pt); + +#endif /* __SOUND_PT2258_H */ diff --git a/include/sound/pxa2xx-lib.h b/include/sound/pxa2xx-lib.h new file mode 100644 index 000000000..2d86f62f9 --- /dev/null +++ b/include/sound/pxa2xx-lib.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef PXA2XX_LIB_H +#define PXA2XX_LIB_H + +#include + +/* modem registers, used by touchscreen driver */ +u32 pxa2xx_ac97_read_modr(void); +u32 pxa2xx_ac97_read_misr(void); + +#endif diff --git a/include/sound/q6usboffload.h b/include/sound/q6usboffload.h new file mode 100644 index 000000000..f7e2449fe --- /dev/null +++ b/include/sound/q6usboffload.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * sound/q6usboffload.h -- QDSP6 USB offload + * + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/** + * struct q6usb_offload - USB backend DAI link offload parameters + * @dev: dev handle to usb be + * @domain: allocated iommu domain + * @intr_num: usb interrupter number + * @sid: streamID for iommu + **/ +struct q6usb_offload { + struct device *dev; + struct iommu_domain *domain; + u16 intr_num; + u8 sid; +}; diff --git a/include/sound/rawmidi.h b/include/sound/rawmidi.h new file mode 100644 index 000000000..4154035af --- /dev/null +++ b/include/sound/rawmidi.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_RAWMIDI_H +#define __SOUND_RAWMIDI_H + +/* + * Abstract layer for MIDI v1.0 stream + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) +#include +#endif +#include + +/* + * Raw MIDI interface + */ + +#define SNDRV_RAWMIDI_DEVICES 8 + +#define SNDRV_RAWMIDI_LFLG_OUTPUT (1<<0) +#define SNDRV_RAWMIDI_LFLG_INPUT (1<<1) +#define SNDRV_RAWMIDI_LFLG_OPEN (3<<0) +#define SNDRV_RAWMIDI_LFLG_APPEND (1<<2) + +struct snd_rawmidi; +struct snd_rawmidi_substream; +struct snd_seq_port_info; +struct pid; + +struct snd_rawmidi_ops { + int (*open) (struct snd_rawmidi_substream * substream); + int (*close) (struct snd_rawmidi_substream * substream); + void (*trigger) (struct snd_rawmidi_substream * substream, int up); + void (*drain) (struct snd_rawmidi_substream * substream); +}; + +struct snd_rawmidi_global_ops { + int (*dev_register) (struct snd_rawmidi * rmidi); + int (*dev_unregister) (struct snd_rawmidi * rmidi); + void (*get_port_info)(struct snd_rawmidi *rmidi, int number, + struct snd_seq_port_info *info); + long (*ioctl)(struct snd_rawmidi *rmidi, unsigned int cmd, + void __user *argp); + void (*proc_read)(struct snd_info_entry *entry, + struct snd_info_buffer *buf); +}; + +struct snd_rawmidi_runtime { + struct snd_rawmidi_substream *substream; + unsigned int drain: 1, /* drain stage */ + oss: 1; /* OSS compatible mode */ + /* midi stream buffer */ + unsigned char *buffer; /* buffer for MIDI data */ + size_t buffer_size; /* size of buffer */ + size_t appl_ptr; /* application pointer */ + size_t hw_ptr; /* hardware pointer */ + size_t avail_min; /* min avail for wakeup */ + size_t avail; /* max used buffer for wakeup */ + size_t xruns; /* over/underruns counter */ + size_t align; /* alignment (0 = byte stream, 3 = UMP) */ + int buffer_ref; /* buffer reference count */ + /* misc */ + wait_queue_head_t sleep; + /* event handler (new bytes, input only) */ + void (*event)(struct snd_rawmidi_substream *substream); + /* defers calls to event [input] or ops->trigger [output] */ + struct work_struct event_work; + /* private data */ + void *private_data; + void (*private_free)(struct snd_rawmidi_substream *substream); +}; + +struct snd_rawmidi_substream { + struct list_head list; /* list of all substream for given stream */ + int stream; /* direction */ + int number; /* substream number */ + bool opened; /* open flag */ + bool append; /* append flag (merge more streams) */ + bool active_sensing; /* send active sensing when close */ + unsigned int framing; /* whether to frame input data */ + unsigned int clock_type; /* clock source to use for input framing */ + int use_count; /* use counter (for output) */ + bool inactive; /* inactive substream (for UMP legacy) */ + size_t bytes; + spinlock_t lock; + struct snd_rawmidi *rmidi; + struct snd_rawmidi_str *pstr; + char name[32]; + struct snd_rawmidi_runtime *runtime; + struct pid *pid; + /* hardware layer */ + const struct snd_rawmidi_ops *ops; +}; + +struct snd_rawmidi_file { + struct snd_rawmidi *rmidi; + struct snd_rawmidi_substream *input; + struct snd_rawmidi_substream *output; + unsigned int user_pversion; /* supported protocol version */ +}; + +struct snd_rawmidi_str { + unsigned int substream_count; + unsigned int substream_opened; + struct list_head substreams; +}; + +struct snd_rawmidi { + struct snd_card *card; + struct list_head list; + unsigned int device; /* device number */ + unsigned int info_flags; /* SNDRV_RAWMIDI_INFO_XXXX */ + unsigned int tied_device; + char id[64]; + char name[80]; + +#ifdef CONFIG_SND_OSSEMUL + int ossreg; +#endif + + const struct snd_rawmidi_global_ops *ops; + + struct snd_rawmidi_str streams[2]; + + void *private_data; + void (*private_free) (struct snd_rawmidi *rmidi); + + struct mutex open_mutex; + wait_queue_head_t open_wait; + + struct device *dev; + + struct snd_info_entry *proc_entry; + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) + struct snd_seq_device *seq_dev; +#endif +}; + +/* main rawmidi functions */ + +int snd_rawmidi_new(struct snd_card *card, char *id, int device, + int output_count, int input_count, + struct snd_rawmidi **rmidi); +void snd_rawmidi_set_ops(struct snd_rawmidi *rmidi, int stream, + const struct snd_rawmidi_ops *ops); + +/* internal */ +int snd_rawmidi_init(struct snd_rawmidi *rmidi, + struct snd_card *card, char *id, int device, + int output_count, int input_count, + unsigned int info_flags); +int snd_rawmidi_free(struct snd_rawmidi *rmidi); + +/* callbacks */ + +int snd_rawmidi_receive(struct snd_rawmidi_substream *substream, + const unsigned char *buffer, int count); +int snd_rawmidi_transmit_empty(struct snd_rawmidi_substream *substream); +int snd_rawmidi_transmit_peek(struct snd_rawmidi_substream *substream, + unsigned char *buffer, int count); +int snd_rawmidi_transmit_ack(struct snd_rawmidi_substream *substream, int count); +int snd_rawmidi_transmit(struct snd_rawmidi_substream *substream, + unsigned char *buffer, int count); +int snd_rawmidi_proceed(struct snd_rawmidi_substream *substream); + +/* main midi functions */ + +int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info); +int snd_rawmidi_kernel_open_nested(struct snd_rawmidi *rmidi, int subdevice, + int mode, struct snd_rawmidi_file *rfile, + int depth); +int snd_rawmidi_kernel_release_nested(struct snd_rawmidi_file *rfile, + int depth); +int snd_rawmidi_output_params(struct snd_rawmidi_substream *substream, + struct snd_rawmidi_params *params); +int snd_rawmidi_input_params(struct snd_rawmidi_substream *substream, + struct snd_rawmidi_params *params); +int snd_rawmidi_drop_output(struct snd_rawmidi_substream *substream); +int snd_rawmidi_drain_output(struct snd_rawmidi_substream *substream); +int snd_rawmidi_drain_input(struct snd_rawmidi_substream *substream); +long snd_rawmidi_kernel_read(struct snd_rawmidi_substream *substream, + unsigned char *buf, long count); +long snd_rawmidi_kernel_write(struct snd_rawmidi_substream *substream, + const unsigned char *buf, long count); + +/* non-nested version */ +static inline int snd_rawmidi_kernel_open(struct snd_rawmidi *rmidi, + int subdevice, + int mode, + struct snd_rawmidi_file *rfile) +{ + return snd_rawmidi_kernel_open_nested(rmidi, subdevice, mode, rfile, 0); +} + +static inline int snd_rawmidi_kernel_release(struct snd_rawmidi_file *rfile) +{ + return snd_rawmidi_kernel_release_nested(rfile, 0); +} + +/* set up the tied devices */ +static inline void snd_rawmidi_tie_devices(struct snd_rawmidi *r1, + struct snd_rawmidi *r2) +{ + /* tied_device field keeps the device+1 (so that 0 being unknown) */ + r1->tied_device = r2->device + 1; + r2->tied_device = r1->device + 1; +} + +#endif /* __SOUND_RAWMIDI_H */ diff --git a/include/sound/rt1015.h b/include/sound/rt1015.h new file mode 100644 index 000000000..70a7538d4 --- /dev/null +++ b/include/sound/rt1015.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt1015.h -- Platform data for RT1015 + * + * Copyright 2020 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT1015_H +#define __LINUX_SND_RT1015_H + +struct rt1015_platform_data { + unsigned int power_up_delay_ms; +}; + +#endif diff --git a/include/sound/rt1318.h b/include/sound/rt1318.h new file mode 100644 index 000000000..fe6bff060 --- /dev/null +++ b/include/sound/rt1318.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt1318.h -- Platform data for RT1318 + * + * Copyright 2024 Realtek Semiconductor Corp. + */ + +#ifndef __LINUX_SND_RT1318_H +#define __LINUX_SND_RT1318_H + +struct rt1318_platform_data { + unsigned int init_r0_l; + unsigned int init_r0_r; +}; + +#endif diff --git a/include/sound/rt286.h b/include/sound/rt286.h new file mode 100644 index 000000000..df1269a39 --- /dev/null +++ b/include/sound/rt286.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt286.h -- Platform data for RT286 + * + * Copyright 2013 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT286_H +#define __LINUX_SND_RT286_H + +struct rt286_platform_data { + bool cbj_en; /*combo jack enable*/ + bool gpio2_en; /*GPIO2 enable*/ +}; + +#endif diff --git a/include/sound/rt298.h b/include/sound/rt298.h new file mode 100644 index 000000000..cc8053878 --- /dev/null +++ b/include/sound/rt298.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt286.h -- Platform data for RT286 + * + * Copyright 2013 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT298_H +#define __LINUX_SND_RT298_H + +struct rt298_platform_data { + bool cbj_en; /*combo jack enable*/ + bool gpio2_en; /*GPIO2 enable*/ + bool suspend_power_off; /* power is off during suspend */ +}; + +#endif diff --git a/include/sound/rt5514.h b/include/sound/rt5514.h new file mode 100644 index 000000000..3e155e7d8 --- /dev/null +++ b/include/sound/rt5514.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5514.h -- Platform data for RT5514 + * + * Copyright 2016 Realtek Semiconductor Corp. + * Author: Oder Chiou + */ + +#ifndef __LINUX_SND_RT5514_H +#define __LINUX_SND_RT5514_H + +struct rt5514_platform_data { + unsigned int dmic_init_delay; + const char *dsp_calib_clk_name; + unsigned int dsp_calib_clk_rate; +}; + +#endif + diff --git a/include/sound/rt5659.h b/include/sound/rt5659.h new file mode 100644 index 000000000..d495311df --- /dev/null +++ b/include/sound/rt5659.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5659.h -- Platform data for RT5659 + * + * Copyright 2013 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5659_H +#define __LINUX_SND_RT5659_H + +enum rt5659_dmic1_data_pin { + RT5659_DMIC1_NULL, + RT5659_DMIC1_DATA_IN2N, + RT5659_DMIC1_DATA_GPIO5, + RT5659_DMIC1_DATA_GPIO9, + RT5659_DMIC1_DATA_GPIO11, +}; + +enum rt5659_dmic2_data_pin { + RT5659_DMIC2_NULL, + RT5659_DMIC2_DATA_IN2P, + RT5659_DMIC2_DATA_GPIO6, + RT5659_DMIC2_DATA_GPIO10, + RT5659_DMIC2_DATA_GPIO12, +}; + +enum rt5659_jd_src { + RT5659_JD_NULL, + RT5659_JD3, + RT5659_JD_HDA_HEADER, +}; + +struct rt5659_platform_data { + bool in1_diff; + bool in3_diff; + bool in4_diff; + + int ldo1_en; /* GPIO for LDO1_EN */ + int reset; /* GPIO for RESET */ + + enum rt5659_dmic1_data_pin dmic1_data_pin; + enum rt5659_dmic2_data_pin dmic2_data_pin; + enum rt5659_jd_src jd_src; +}; + +#endif + diff --git a/include/sound/rt5660.h b/include/sound/rt5660.h new file mode 100644 index 000000000..7e8656cec --- /dev/null +++ b/include/sound/rt5660.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5660.h -- Platform data for RT5660 + * + * Copyright 2016 Realtek Semiconductor Corp. + * Author: Oder Chiou + */ + +#ifndef __LINUX_SND_RT5660_H +#define __LINUX_SND_RT5660_H + +enum rt5660_dmic1_data_pin { + RT5660_DMIC1_NULL, + RT5660_DMIC1_DATA_GPIO2, + RT5660_DMIC1_DATA_IN1P, +}; + +struct rt5660_platform_data { + /* IN1 & IN3 can optionally be differential */ + bool in1_diff; + bool in3_diff; + bool use_ldo2; + bool poweroff_codec_in_suspend; + + enum rt5660_dmic1_data_pin dmic1_data_pin; +}; + +#endif diff --git a/include/sound/rt5663.h b/include/sound/rt5663.h new file mode 100644 index 000000000..a864cb5c2 --- /dev/null +++ b/include/sound/rt5663.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5663.h -- Platform data for RT5663 + * + * Copyright 2017 Realtek Semiconductor Corp. + */ + +#ifndef __LINUX_SND_RT5663_H +#define __LINUX_SND_RT5663_H + +struct rt5663_platform_data { + unsigned int dc_offset_l_manual; + unsigned int dc_offset_r_manual; + unsigned int dc_offset_l_manual_mic; + unsigned int dc_offset_r_manual_mic; + + unsigned int impedance_sensing_num; + unsigned int *impedance_sensing_table; +}; + +#endif + diff --git a/include/sound/rt5665.h b/include/sound/rt5665.h new file mode 100644 index 000000000..e865f0419 --- /dev/null +++ b/include/sound/rt5665.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5665.h -- Platform data for RT5665 + * + * Copyright 2016 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5665_H +#define __LINUX_SND_RT5665_H + +enum rt5665_dmic1_data_pin { + RT5665_DMIC1_NULL, + RT5665_DMIC1_DATA_GPIO4, + RT5665_DMIC1_DATA_IN2N, +}; + +enum rt5665_dmic2_data_pin { + RT5665_DMIC2_NULL, + RT5665_DMIC2_DATA_GPIO5, + RT5665_DMIC2_DATA_IN2P, +}; + +enum rt5665_jd_src { + RT5665_JD_NULL, + RT5665_JD1, +}; + +struct rt5665_platform_data { + bool in1_diff; + bool in2_diff; + bool in3_diff; + bool in4_diff; + + enum rt5665_dmic1_data_pin dmic1_data_pin; + enum rt5665_dmic2_data_pin dmic2_data_pin; + enum rt5665_jd_src jd_src; + + unsigned int sar_hs_type; +}; + +#endif + diff --git a/include/sound/rt5668.h b/include/sound/rt5668.h new file mode 100644 index 000000000..b682418c6 --- /dev/null +++ b/include/sound/rt5668.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5668.h -- Platform data for RT5668 + * + * Copyright 2018 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5668_H +#define __LINUX_SND_RT5668_H + +enum rt5668_dmic1_data_pin { + RT5668_DMIC1_NULL, + RT5668_DMIC1_DATA_GPIO2, + RT5668_DMIC1_DATA_GPIO5, +}; + +enum rt5668_dmic1_clk_pin { + RT5668_DMIC1_CLK_GPIO1, + RT5668_DMIC1_CLK_GPIO3, +}; + +enum rt5668_jd_src { + RT5668_JD_NULL, + RT5668_JD1, +}; + +struct rt5668_platform_data { + enum rt5668_dmic1_data_pin dmic1_data_pin; + enum rt5668_dmic1_clk_pin dmic1_clk_pin; + enum rt5668_jd_src jd_src; +}; + +#endif + diff --git a/include/sound/rt5682.h b/include/sound/rt5682.h new file mode 100644 index 000000000..4256df721 --- /dev/null +++ b/include/sound/rt5682.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5682.h -- Platform data for RT5682 + * + * Copyright 2018 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5682_H +#define __LINUX_SND_RT5682_H + +enum rt5682_dmic1_data_pin { + RT5682_DMIC1_NULL, + RT5682_DMIC1_DATA_GPIO2, + RT5682_DMIC1_DATA_GPIO5, +}; + +enum rt5682_dmic1_clk_pin { + RT5682_DMIC1_CLK_GPIO1, + RT5682_DMIC1_CLK_GPIO3, +}; + +enum rt5682_jd_src { + RT5682_JD_NULL, + RT5682_JD1, +}; + +enum rt5682_dai_clks { + RT5682_DAI_WCLK_IDX, + RT5682_DAI_BCLK_IDX, + RT5682_DAI_NUM_CLKS, +}; + +struct rt5682_platform_data { + enum rt5682_dmic1_data_pin dmic1_data_pin; + enum rt5682_dmic1_clk_pin dmic1_clk_pin; + enum rt5682_jd_src jd_src; + unsigned int btndet_delay; + unsigned int dmic_clk_rate; + unsigned int dmic_delay; + bool dmic_clk_driving_high; + + const char *dai_clk_names[RT5682_DAI_NUM_CLKS]; +}; + +#endif + diff --git a/include/sound/rt5682s.h b/include/sound/rt5682s.h new file mode 100644 index 000000000..006e6003d --- /dev/null +++ b/include/sound/rt5682s.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5682s.h -- Platform data for RT5682I-VS + * + * Copyright 2021 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5682S_H +#define __LINUX_SND_RT5682S_H + +enum rt5682s_dmic1_data_pin { + RT5682S_DMIC1_DATA_NULL, + RT5682S_DMIC1_DATA_GPIO2, + RT5682S_DMIC1_DATA_GPIO5, +}; + +enum rt5682s_dmic1_clk_pin { + RT5682S_DMIC1_CLK_NULL, + RT5682S_DMIC1_CLK_GPIO1, + RT5682S_DMIC1_CLK_GPIO3, +}; + +enum rt5682s_jd_src { + RT5682S_JD_NULL, + RT5682S_JD1, +}; + +enum rt5682s_dai_clks { + RT5682S_DAI_WCLK_IDX, + RT5682S_DAI_BCLK_IDX, + RT5682S_DAI_NUM_CLKS, +}; + +enum { + RT5682S_LDO_1_607V, + RT5682S_LDO_1_5V, + RT5682S_LDO_1_406V, + RT5682S_LDO_1_731V, +}; + +struct rt5682s_platform_data { + enum rt5682s_dmic1_data_pin dmic1_data_pin; + enum rt5682s_dmic1_clk_pin dmic1_clk_pin; + enum rt5682s_jd_src jd_src; + unsigned int dmic_clk_rate; + unsigned int dmic_delay; + unsigned int amic_delay; + unsigned int ldo_dacref; + bool dmic_clk_driving_high; + + const char *dai_clk_names[RT5682S_DAI_NUM_CLKS]; +}; + +#endif diff --git a/include/sound/sb.h b/include/sound/sb.h new file mode 100644 index 000000000..24970f36c --- /dev/null +++ b/include/sound/sb.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SB_H +#define __SOUND_SB_H + +/* + * Header file for SoundBlaster cards + * Copyright (c) by Jaroslav Kysela + */ + +#include +#include +#include +#include + +enum sb_hw_type { + SB_HW_AUTO, + SB_HW_10, + SB_HW_20, + SB_HW_201, + SB_HW_PRO, + SB_HW_JAZZ16, /* Media Vision Jazz16 */ + SB_HW_16, + SB_HW_16CSP, /* SB16 with CSP chip */ + SB_HW_ALS100, /* Avance Logic ALS100 chip */ + SB_HW_ALS4000, /* Avance Logic ALS4000 chip */ + SB_HW_DT019X, /* Diamond Tech. DT-019X / Avance Logic ALS-007 */ + SB_HW_CS5530, /* Cyrix/NatSemi 5530 VSA1 */ +}; + +#define SB_OPEN_PCM 0x01 +#define SB_OPEN_MIDI_INPUT 0x02 +#define SB_OPEN_MIDI_OUTPUT 0x04 +#define SB_OPEN_MIDI_INPUT_TRIGGER 0x08 +#define SB_OPEN_MIDI_OUTPUT_TRIGGER 0x10 + +#define SB_MODE_HALT 0x00 +#define SB_MODE_PLAYBACK_8 0x01 +#define SB_MODE_PLAYBACK_16 0x02 +#define SB_MODE_PLAYBACK (SB_MODE_PLAYBACK_8 | SB_MODE_PLAYBACK_16) +#define SB_MODE_CAPTURE_8 0x04 +#define SB_MODE_CAPTURE_16 0x08 +#define SB_MODE_CAPTURE (SB_MODE_CAPTURE_8 | SB_MODE_CAPTURE_16) + +#define SB_RATE_LOCK_PLAYBACK 0x10 +#define SB_RATE_LOCK_CAPTURE 0x20 +#define SB_RATE_LOCK (SB_RATE_LOCK_PLAYBACK | SB_RATE_LOCK_CAPTURE) + +#define SB_MPU_INPUT 1 + +struct snd_sb { + unsigned long port; /* base port of DSP chip */ + struct resource *res_port; + unsigned long mpu_port; /* MPU port for SB DSP 4.0+ */ + int irq; /* IRQ number of DSP chip */ + int dma8; /* 8-bit DMA */ + int dma16; /* 16-bit DMA */ + unsigned short version; /* version of DSP chip */ + enum sb_hw_type hardware; /* see to SB_HW_XXXX */ + + unsigned long alt_port; /* alternate port (ALS4000) */ + struct pci_dev *pci; /* ALS4000 */ + + unsigned int open; /* see to SB_OPEN_XXXX for sb8 */ + /* also SNDRV_SB_CSP_MODE_XXX for sb16_csp */ + unsigned int mode; /* current mode of stream */ + unsigned int force_mode16; /* force 16-bit mode of streams */ + unsigned int locked_rate; /* sb16 duplex */ + unsigned int playback_format; + unsigned int capture_format; + struct timer_list midi_timer; + unsigned int p_dma_size; + unsigned int p_period_size; + unsigned int c_dma_size; + unsigned int c_period_size; + + spinlock_t mixer_lock; + + char name[32]; + + void *csp; /* used only when CONFIG_SND_SB16_CSP is set */ + + struct snd_card *card; + struct snd_pcm *pcm; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + + struct snd_rawmidi *rmidi; + struct snd_rawmidi_substream *midi_substream_input; + struct snd_rawmidi_substream *midi_substream_output; + irq_handler_t rmidi_callback; + + spinlock_t reg_lock; + spinlock_t open_lock; + spinlock_t midi_input_lock; + + struct snd_info_entry *proc_entry; + +#ifdef CONFIG_PM + unsigned char saved_regs[0x20]; +#endif +}; + +/* I/O ports */ + +#define SBP(chip, x) ((chip)->port + s_b_SB_##x) +#define SBP1(port, x) ((port) + s_b_SB_##x) + +#define s_b_SB_RESET 0x6 +#define s_b_SB_READ 0xa +#define s_b_SB_WRITE 0xc +#define s_b_SB_COMMAND 0xc +#define s_b_SB_STATUS 0xc +#define s_b_SB_DATA_AVAIL 0xe +#define s_b_SB_DATA_AVAIL_16 0xf +#define s_b_SB_MIXER_ADDR 0x4 +#define s_b_SB_MIXER_DATA 0x5 +#define s_b_SB_OPL3_LEFT 0x0 +#define s_b_SB_OPL3_RIGHT 0x2 +#define s_b_SB_OPL3_BOTH 0x8 + +#define SB_DSP_OUTPUT 0x14 +#define SB_DSP_INPUT 0x24 +#define SB_DSP_BLOCK_SIZE 0x48 +#define SB_DSP_HI_OUTPUT 0x91 +#define SB_DSP_HI_INPUT 0x99 +#define SB_DSP_LO_OUTPUT_AUTO 0x1c +#define SB_DSP_LO_INPUT_AUTO 0x2c +#define SB_DSP_HI_OUTPUT_AUTO 0x90 +#define SB_DSP_HI_INPUT_AUTO 0x98 +#define SB_DSP_IMMED_INT 0xf2 +#define SB_DSP_GET_VERSION 0xe1 +#define SB_DSP_SPEAKER_ON 0xd1 +#define SB_DSP_SPEAKER_OFF 0xd3 +#define SB_DSP_DMA8_OFF 0xd0 +#define SB_DSP_DMA8_ON 0xd4 +#define SB_DSP_DMA8_EXIT 0xda +#define SB_DSP_DMA16_OFF 0xd5 +#define SB_DSP_DMA16_ON 0xd6 +#define SB_DSP_DMA16_EXIT 0xd9 +#define SB_DSP_SAMPLE_RATE 0x40 +#define SB_DSP_SAMPLE_RATE_OUT 0x41 +#define SB_DSP_SAMPLE_RATE_IN 0x42 +#define SB_DSP_MONO_8BIT 0xa0 +#define SB_DSP_MONO_16BIT 0xa4 +#define SB_DSP_STEREO_8BIT 0xa8 +#define SB_DSP_STEREO_16BIT 0xac + +#define SB_DSP_MIDI_INPUT_IRQ 0x31 +#define SB_DSP_MIDI_UART_IRQ 0x35 +#define SB_DSP_MIDI_OUTPUT 0x38 + +#define SB_DSP4_OUT8_AI 0xc6 +#define SB_DSP4_IN8_AI 0xce +#define SB_DSP4_OUT16_AI 0xb6 +#define SB_DSP4_IN16_AI 0xbe +#define SB_DSP4_MODE_UNS_MONO 0x00 +#define SB_DSP4_MODE_SIGN_MONO 0x10 +#define SB_DSP4_MODE_UNS_STEREO 0x20 +#define SB_DSP4_MODE_SIGN_STEREO 0x30 + +#define SB_DSP4_OUTPUT 0x3c +#define SB_DSP4_INPUT_LEFT 0x3d +#define SB_DSP4_INPUT_RIGHT 0x3e + +/* registers for SB 2.0 mixer */ +#define SB_DSP20_MASTER_DEV 0x02 +#define SB_DSP20_PCM_DEV 0x0A +#define SB_DSP20_CD_DEV 0x08 +#define SB_DSP20_FM_DEV 0x06 + +/* registers for SB PRO mixer */ +#define SB_DSP_MASTER_DEV 0x22 +#define SB_DSP_PCM_DEV 0x04 +#define SB_DSP_LINE_DEV 0x2e +#define SB_DSP_CD_DEV 0x28 +#define SB_DSP_FM_DEV 0x26 +#define SB_DSP_MIC_DEV 0x0a +#define SB_DSP_CAPTURE_SOURCE 0x0c +#define SB_DSP_CAPTURE_FILT 0x0c +#define SB_DSP_PLAYBACK_FILT 0x0e +#define SB_DSP_STEREO_SW 0x0e + +#define SB_DSP_MIXS_MIC0 0x00 /* same as MIC */ +#define SB_DSP_MIXS_CD 0x01 +#define SB_DSP_MIXS_MIC 0x02 +#define SB_DSP_MIXS_LINE 0x03 + +/* registers (only for left channel) for SB 16 mixer */ +#define SB_DSP4_MASTER_DEV 0x30 +#define SB_DSP4_BASS_DEV 0x46 +#define SB_DSP4_TREBLE_DEV 0x44 +#define SB_DSP4_SYNTH_DEV 0x34 +#define SB_DSP4_PCM_DEV 0x32 +#define SB_DSP4_SPEAKER_DEV 0x3b +#define SB_DSP4_LINE_DEV 0x38 +#define SB_DSP4_MIC_DEV 0x3a +#define SB_DSP4_OUTPUT_SW 0x3c +#define SB_DSP4_CD_DEV 0x36 +#define SB_DSP4_IGAIN_DEV 0x3f +#define SB_DSP4_OGAIN_DEV 0x41 +#define SB_DSP4_MIC_AGC 0x43 + +/* additional registers for SB 16 mixer */ +#define SB_DSP4_IRQSETUP 0x80 +#define SB_DSP4_DMASETUP 0x81 +#define SB_DSP4_IRQSTATUS 0x82 +#define SB_DSP4_MPUSETUP 0x84 + +#define SB_DSP4_3DSE 0x90 + +/* Registers for DT-019x / ALS-007 mixer */ +#define SB_DT019X_MASTER_DEV 0x62 +#define SB_DT019X_PCM_DEV 0x64 +#define SB_DT019X_SYNTH_DEV 0x66 +#define SB_DT019X_CD_DEV 0x68 +#define SB_DT019X_MIC_DEV 0x6a +#define SB_DT019X_SPKR_DEV 0x6a +#define SB_DT019X_LINE_DEV 0x6e +#define SB_DT019X_OUTPUT_SW2 0x4c +#define SB_DT019X_CAPTURE_SW 0x6c + +#define SB_DT019X_CAP_CD 0x02 +#define SB_DT019X_CAP_MIC 0x04 +#define SB_DT019X_CAP_LINE 0x06 +#define SB_DT019X_CAP_SYNTH 0x07 +#define SB_DT019X_CAP_MAIN 0x07 + +#define SB_ALS4000_MONO_IO_CTRL 0x4b +#define SB_ALS4000_OUT_MIXER_CTRL_2 0x4c +#define SB_ALS4000_MIC_IN_GAIN 0x4d +#define SB_ALS4000_ANALOG_REFRNC_VOLT_CTRL 0x4e +#define SB_ALS4000_FMDAC 0x4f +#define SB_ALS4000_3D_SND_FX 0x50 +#define SB_ALS4000_3D_TIME_DELAY 0x51 +#define SB_ALS4000_3D_AUTO_MUTE 0x52 +#define SB_ALS4000_ANALOG_BLOCK_CTRL 0x53 +#define SB_ALS4000_3D_DELAYLINE_PATTERN 0x54 +#define SB_ALS4000_CR3_CONFIGURATION 0xc3 /* bit 7 is Digital Loop Enable */ +#define SB_ALS4000_QSOUND 0xdb + +/* IRQ setting bitmap */ +#define SB_IRQSETUP_IRQ9 0x01 +#define SB_IRQSETUP_IRQ5 0x02 +#define SB_IRQSETUP_IRQ7 0x04 +#define SB_IRQSETUP_IRQ10 0x08 + +/* IRQ types */ +#define SB_IRQTYPE_8BIT 0x01 +#define SB_IRQTYPE_16BIT 0x02 +#define SB_IRQTYPE_MPUIN 0x04 +#define ALS4K_IRQTYPE_CR1E_DMA 0x20 + +/* DMA setting bitmap */ +#define SB_DMASETUP_DMA0 0x01 +#define SB_DMASETUP_DMA1 0x02 +#define SB_DMASETUP_DMA3 0x08 +#define SB_DMASETUP_DMA5 0x20 +#define SB_DMASETUP_DMA6 0x40 +#define SB_DMASETUP_DMA7 0x80 + +/* + * + */ + +static inline void snd_sb_ack_8bit(struct snd_sb *chip) +{ + inb(SBP(chip, DATA_AVAIL)); +} + +static inline void snd_sb_ack_16bit(struct snd_sb *chip) +{ + inb(SBP(chip, DATA_AVAIL_16)); +} + +/* sb_common.c */ +int snd_sbdsp_command(struct snd_sb *chip, unsigned char val); +int snd_sbdsp_get_byte(struct snd_sb *chip); +int snd_sbdsp_reset(struct snd_sb *chip); +int snd_sbdsp_create(struct snd_card *card, + unsigned long port, + int irq, + irq_handler_t irq_handler, + int dma8, int dma16, + unsigned short hardware, + struct snd_sb **r_chip); +/* sb_mixer.c */ +void snd_sbmixer_write(struct snd_sb *chip, unsigned char reg, unsigned char data); +unsigned char snd_sbmixer_read(struct snd_sb *chip, unsigned char reg); +int snd_sbmixer_new(struct snd_sb *chip); +#ifdef CONFIG_PM +void snd_sbmixer_suspend(struct snd_sb *chip); +void snd_sbmixer_resume(struct snd_sb *chip); +#else +static inline void snd_sbmixer_suspend(struct snd_sb *chip) {} +static inline void snd_sbmixer_resume(struct snd_sb *chip) {} +#endif + +/* sb8_init.c */ +int snd_sb8dsp_pcm(struct snd_sb *chip, int device); +/* sb8.c */ +irqreturn_t snd_sb8dsp_interrupt(struct snd_sb *chip); +int snd_sb8_playback_open(struct snd_pcm_substream *substream); +int snd_sb8_capture_open(struct snd_pcm_substream *substream); +int snd_sb8_playback_close(struct snd_pcm_substream *substream); +int snd_sb8_capture_close(struct snd_pcm_substream *substream); +/* midi8.c */ +irqreturn_t snd_sb8dsp_midi_interrupt(struct snd_sb *chip); +int snd_sb8dsp_midi(struct snd_sb *chip, int device); + +/* sb16_init.c */ +int snd_sb16dsp_pcm(struct snd_sb *chip, int device); +const struct snd_pcm_ops *snd_sb16dsp_get_pcm_ops(int direction); +int snd_sb16dsp_configure(struct snd_sb *chip); +/* sb16.c */ +irqreturn_t snd_sb16dsp_interrupt(int irq, void *dev_id); + +/* exported mixer stuffs */ +enum { + SB_MIX_SINGLE, + SB_MIX_DOUBLE, + SB_MIX_INPUT_SW, + SB_MIX_CAPTURE_PRO, + SB_MIX_CAPTURE_DT019X, + SB_MIX_MONO_CAPTURE_ALS4K +}; + +#define SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) \ + ((left_reg) | ((right_reg) << 8) | ((left_shift) << 16) | ((right_shift) << 19) | ((mask) << 24)) +#define SB_MIXVAL_SINGLE(reg, shift, mask) \ + ((reg) | ((shift) << 16) | ((mask) << 24)) +#define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \ + ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24)) + +int snd_sbmixer_add_ctl(struct snd_sb *chip, const char *name, int index, int type, unsigned long value); + +/* for ease of use */ +struct sbmix_elem { + const char *name; + int type; + unsigned long private_value; +}; + +#define SB_SINGLE(xname, reg, shift, mask) \ +{ .name = xname, \ + .type = SB_MIX_SINGLE, \ + .private_value = SB_MIXVAL_SINGLE(reg, shift, mask) } + +#define SB_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask) \ +{ .name = xname, \ + .type = SB_MIX_DOUBLE, \ + .private_value = SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) } + +#define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \ +{ .name = xname, \ + .type = SB_MIX_INPUT_SW, \ + .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) } + +static inline int snd_sbmixer_add_ctl_elem(struct snd_sb *chip, const struct sbmix_elem *c) +{ + return snd_sbmixer_add_ctl(chip, c->name, 0, c->type, c->private_value); +} + +#endif /* __SOUND_SB_H */ diff --git a/include/sound/sb16_csp.h b/include/sound/sb16_csp.h new file mode 100644 index 000000000..cafd415e2 --- /dev/null +++ b/include/sound/sb16_csp.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 1999 by Uros Bizjak + * Takashi Iwai + * + * SB16ASP/AWE32 CSP control + */ +#ifndef __SOUND_SB16_CSP_H +#define __SOUND_SB16_CSP_H + +#include +#include +#include +#include + +struct snd_sb_csp; + +/* indices for the known CSP programs */ +enum { + CSP_PROGRAM_MULAW, + CSP_PROGRAM_ALAW, + CSP_PROGRAM_ADPCM_INIT, + CSP_PROGRAM_ADPCM_PLAYBACK, + CSP_PROGRAM_ADPCM_CAPTURE, + + CSP_PROGRAM_COUNT +}; + +/* + * CSP operators + */ +struct snd_sb_csp_ops { + int (*csp_use) (struct snd_sb_csp * p); + int (*csp_unuse) (struct snd_sb_csp * p); + int (*csp_autoload) (struct snd_sb_csp * p, snd_pcm_format_t pcm_sfmt, int play_rec_mode); + int (*csp_start) (struct snd_sb_csp * p, int sample_width, int channels); + int (*csp_stop) (struct snd_sb_csp * p); + int (*csp_qsound_transfer) (struct snd_sb_csp * p); +}; + +/* + * CSP private data + */ +struct snd_sb_csp { + struct snd_sb *chip; /* SB16 DSP */ + int used; /* usage flag - exclusive */ + char codec_name[16]; /* name of codec */ + unsigned short func_nr; /* function number */ + unsigned int acc_format; /* accepted PCM formats */ + int acc_channels; /* accepted channels */ + int acc_width; /* accepted sample width */ + int acc_rates; /* accepted sample rates */ + int mode; /* MODE */ + int run_channels; /* current CSP channels */ + int run_width; /* current sample width */ + int version; /* CSP version (0x10 - 0x1f) */ + int running; /* running state */ + + struct snd_sb_csp_ops ops; /* operators */ + + spinlock_t q_lock; /* locking */ + int q_enabled; /* enabled flag */ + int qpos_left; /* left position */ + int qpos_right; /* right position */ + int qpos_changed; /* position changed flag */ + + struct snd_kcontrol *qsound_switch; + struct snd_kcontrol *qsound_space; + + struct mutex access_mutex; /* locking */ + + const struct firmware *csp_programs[CSP_PROGRAM_COUNT]; +}; + +int snd_sb_csp_new(struct snd_sb *chip, int device, struct snd_hwdep ** rhwdep); +#endif /* __SOUND_SB16_CSP */ diff --git a/include/sound/sdca.h b/include/sound/sdca.h new file mode 100644 index 000000000..2bdf4e333 --- /dev/null +++ b/include/sound/sdca.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright(c) 2024 Intel Corporation + */ + +#ifndef __SDCA_H__ +#define __SDCA_H__ + +#include +#include + +struct acpi_table_swft; +struct fwnode_handle; +struct sdw_slave; +struct sdca_dev; + +#define SDCA_MAX_FUNCTION_COUNT 8 + +/** + * struct sdca_function_desc - short descriptor for an SDCA Function + * @node: firmware node for the Function. + * @func_dev: pointer to SDCA function device. + * @name: Human-readable string. + * @type: Function topology type. + * @adr: ACPI address (used for SDCA register access). + * @duplicate: Internal flag to indicate if other functions of the same type + * exist. + */ +struct sdca_function_desc { + struct fwnode_handle *node; + struct sdca_dev *func_dev; + const char *name; + u32 type; + u8 adr; + + bool duplicate; +}; + +/** + * struct sdca_device_data - structure containing all SDCA related information + * @interface_revision: Value read from _DSD property, mainly to check + * for changes between silicon versions. + * @num_functions: Total number of supported SDCA functions. Invalid/unsupported + * functions will be skipped. + * @function: Array of function descriptors. + * @swft: Pointer to the SWFT table, if available. + */ +struct sdca_device_data { + u32 interface_revision; + int num_functions; + struct sdca_function_desc function[SDCA_MAX_FUNCTION_COUNT]; + struct acpi_table_swft *swft; +}; + +enum sdca_quirk { + SDCA_QUIRKS_RT712_VB, + SDCA_QUIRKS_SKIP_FUNC_TYPE_PATCHING, +}; + +#if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SND_SOC_SDCA) + +void sdca_lookup_functions(struct sdw_slave *slave); +void sdca_lookup_swft(struct sdw_slave *slave); +void sdca_lookup_interface_revision(struct sdw_slave *slave); +bool sdca_device_quirk_match(struct sdw_slave *slave, enum sdca_quirk quirk); +int sdca_dev_register_functions(struct sdw_slave *slave); +void sdca_dev_unregister_functions(struct sdw_slave *slave); + +#else + +static inline void sdca_lookup_functions(struct sdw_slave *slave) {} +static inline void sdca_lookup_swft(struct sdw_slave *slave) {} +static inline void sdca_lookup_interface_revision(struct sdw_slave *slave) {} +static inline bool sdca_device_quirk_match(struct sdw_slave *slave, enum sdca_quirk quirk) +{ + return false; +} + +static inline int sdca_dev_register_functions(struct sdw_slave *slave) +{ + return 0; +} + +static inline void sdca_dev_unregister_functions(struct sdw_slave *slave) {} + +#endif + +#endif diff --git a/include/sound/sdca_asoc.h b/include/sound/sdca_asoc.h new file mode 100644 index 000000000..599a72f33 --- /dev/null +++ b/include/sound/sdca_asoc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright (C) 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __SDCA_ASOC_H__ +#define __SDCA_ASOC_H__ + +struct device; +struct regmap; +struct sdca_function_data; +struct sdca_pde_delay; +struct snd_ctl_elem_value; +struct snd_kcontrol; +struct snd_kcontrol_new; +struct snd_pcm_hw_params; +struct snd_pcm_substream; +struct snd_soc_component_driver; +struct snd_soc_dai; +struct snd_soc_dai_driver; +struct snd_soc_dai_ops; +struct snd_soc_dapm_route; +struct snd_soc_dapm_widget; +struct snd_soc_pcm_stream; +struct sdca_entity; + +/* convenient macro to handle the mono volume in 7.8 fixed format representation */ +#define SDCA_SINGLE_Q78_TLV(xname, xreg, xmin, xmax, xstep, tlv_array) \ +{ \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = sdca_asoc_q78_get_volsw, \ + .put = sdca_asoc_q78_put_volsw, \ + .private_value = (unsigned long)&(struct soc_mixer_control) { \ + .reg = (xreg), .rreg = (xreg), \ + .min = (xmin), .max = (xmax), \ + .shift = (xstep), .rshift = (xstep), \ + .sign_bit = 15 \ + } \ +} + +/* convenient macro for stereo volume in 7.8 fixed format with separate registers for L/R */ +#define SDCA_DOUBLE_Q78_TLV(xname, xreg_l, xreg_r, xmin, xmax, xstep, tlv_array) \ +{ \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = sdca_asoc_q78_get_volsw, \ + .put = sdca_asoc_q78_put_volsw, \ + .private_value = (unsigned long)&(struct soc_mixer_control) { \ + .reg = (xreg_l), .rreg = (xreg_r), \ + .min = (xmin), .max = (xmax), \ + .shift = (xstep), .rshift = (xstep), \ + .sign_bit = 15 \ + } \ +} + +int sdca_asoc_count_component(struct device *dev, struct sdca_function_data *function, + int *num_widgets, int *num_routes, int *num_controls, + int *num_dais); + +int sdca_asoc_populate_dapm(struct device *dev, struct sdca_function_data *function, + struct snd_soc_dapm_widget *widgets, + struct snd_soc_dapm_route *routes); +int sdca_asoc_populate_controls(struct device *dev, + struct sdca_function_data *function, + struct snd_kcontrol_new *kctl); +int sdca_asoc_populate_dais(struct device *dev, struct sdca_function_data *function, + struct snd_soc_dai_driver *dais, + const struct snd_soc_dai_ops *ops); + +int sdca_asoc_populate_component(struct device *dev, + struct sdca_function_data *function, + struct snd_soc_component_driver *component_drv, + struct snd_soc_dai_driver **dai_drv, int *num_dai_drv, + const struct snd_soc_dai_ops *ops); + +int sdca_asoc_populate_rate_format(struct device *dev, + struct sdca_function_data *function, + struct sdca_entity *entity, + struct snd_soc_pcm_stream *stream); + +int sdca_asoc_set_constraints(struct device *dev, struct regmap *regmap, + struct sdca_function_data *function, + struct snd_pcm_substream *substream, + struct snd_soc_dai *dai); +void sdca_asoc_free_constraints(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai); +int sdca_asoc_get_port(struct device *dev, struct regmap *regmap, + struct sdca_function_data *function, + struct snd_soc_dai *dai); +int sdca_asoc_hw_params(struct device *dev, struct regmap *regmap, + struct sdca_function_data *function, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai); +int sdca_asoc_q78_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int sdca_asoc_q78_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int sdca_asoc_pde_poll_actual_ps(struct regmap *regmap, + int function_id, int entity_id, + int from_ps, int to_ps, + const struct sdca_pde_delay *pde_delays, + int num_delays); +#endif // __SDCA_ASOC_H__ diff --git a/include/sound/sdca_fdl.h b/include/sound/sdca_fdl.h new file mode 100644 index 000000000..bc3600cdd --- /dev/null +++ b/include/sound/sdca_fdl.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright (C) 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __SDCA_FDL_H__ +#define __SDCA_FDL_H__ + +#include +#include + +struct device; +struct regmap; +struct sdca_fdl_set; +struct sdca_function_data; +struct sdca_interrupt; +struct sdca_interrupt_info; + +/** + * struct fdl_state - FDL state structure to keep data between interrupts + * @begin: Completion indicating the start of an FDL download cycle. + * @done: Completion indicating the end of an FDL download cycle. + * @timeout: Delayed work used for timing out UMP transactions. + * @lock: Mutex to protect between the timeout work and IRQ handlers. + * @interrupt: Pointer to the interrupt struct to which this FDL is attached. + * @set: Pointer to the FDL set currently being downloaded. + * @file_index: Index of the current file being processed. + */ +struct fdl_state { + struct completion begin; + struct completion done; + struct delayed_work timeout; + struct mutex lock; + + struct sdca_interrupt *interrupt; + struct sdca_fdl_set *set; + int file_index; +}; + +#define SDCA_CTL_XU_FDLH_COMPLETE 0 +#define SDCA_CTL_XU_FDLH_MORE_FILES SDCA_CTL_XU_FDLH_SET_IN_PROGRESS +#define SDCA_CTL_XU_FDLH_FILE_AVAILABLE (SDCA_CTL_XU_FDLH_TRANSFERRED_FILE | \ + SDCA_CTL_XU_FDLH_SET_IN_PROGRESS) +#define SDCA_CTL_XU_FDLH_MASK (SDCA_CTL_XU_FDLH_TRANSFERRED_CHUNK | \ + SDCA_CTL_XU_FDLH_TRANSFERRED_FILE | \ + SDCA_CTL_XU_FDLH_SET_IN_PROGRESS | \ + SDCA_CTL_XU_FDLH_RESET_ACK | \ + SDCA_CTL_XU_FDLH_REQ_ABORT) + +#define SDCA_CTL_XU_FDLD_COMPLETE 0 +#define SDCA_CTL_XU_FDLD_FILE_OK (SDCA_CTL_XU_FDLH_TRANSFERRED_FILE | \ + SDCA_CTL_XU_FDLH_SET_IN_PROGRESS | \ + SDCA_CTL_XU_FDLD_ACK_TRANSFER | \ + SDCA_CTL_XU_FDLD_NEEDS_SET) +#define SDCA_CTL_XU_FDLD_MORE_FILES_OK (SDCA_CTL_XU_FDLH_SET_IN_PROGRESS | \ + SDCA_CTL_XU_FDLD_ACK_TRANSFER | \ + SDCA_CTL_XU_FDLD_NEEDS_SET) +#define SDCA_CTL_XU_FDLD_MASK (SDCA_CTL_XU_FDLD_REQ_RESET | \ + SDCA_CTL_XU_FDLD_REQ_ABORT | \ + SDCA_CTL_XU_FDLD_ACK_TRANSFER | \ + SDCA_CTL_XU_FDLD_NEEDS_SET) + +#if IS_ENABLED(CONFIG_SND_SOC_SDCA_FDL) + +int sdca_fdl_alloc_state(struct sdca_interrupt *interrupt); +void sdca_fdl_free_state(struct sdca_interrupt *interrupt); + +int sdca_fdl_process(struct sdca_interrupt *interrupt); +int sdca_fdl_sync(struct device *dev, struct sdca_function_data *function, + struct sdca_interrupt_info *info); + +int sdca_reset_function(struct device *dev, struct sdca_function_data *function, + struct regmap *regmap); + +#else + +static inline int sdca_fdl_alloc_state(struct sdca_interrupt *interrupt) +{ + return 0; +} + +static inline void sdca_fdl_free_state(struct sdca_interrupt *interrupt) +{ +} + +static inline int sdca_fdl_process(struct sdca_interrupt *interrupt) +{ + return 0; +} + +static inline int sdca_fdl_sync(struct device *dev, + struct sdca_function_data *function, + struct sdca_interrupt_info *info) +{ + return 0; +} + +static inline int sdca_reset_function(struct device *dev, + struct sdca_function_data *function, + struct regmap *regmap) +{ + return 0; +} + +#endif // CONFIG_SND_SOC_SDCA_FDL + +#endif // __SDCA_FDL_H__ diff --git a/include/sound/sdca_function.h b/include/sound/sdca_function.h new file mode 100644 index 000000000..e580201d6 --- /dev/null +++ b/include/sound/sdca_function.h @@ -0,0 +1,1485 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright(c) 2024 Intel Corporation + */ + +#ifndef __SDCA_FUNCTION_H__ +#define __SDCA_FUNCTION_H__ + +#include +#include +#include + +struct acpi_table_swft; +struct device; +struct sdca_entity; +struct sdca_function_desc; + +#define SDCA_NO_INTERRUPT -1 + +/* + * The addressing space for SDCA relies on 7 bits for Entities, so a + * maximum of 128 Entities per function can be represented. + */ +#define SDCA_MAX_ENTITY_COUNT 128 + +/* + * The Cluster IDs are 16-bit, so a maximum of 65535 Clusters per + * function can be represented, however limit this to a slightly + * more reasonable value. Can be expanded if needed. + */ +#define SDCA_MAX_CLUSTER_COUNT 256 + +/* + * Sanity check on number of channels per Cluster, can be expanded if needed. + */ +#define SDCA_MAX_CHANNEL_COUNT 32 + +/* + * Sanity check on number of PDE delays, can be expanded if needed. + */ +#define SDCA_MAX_DELAY_COUNT 256 + +/* + * Sanity check on size of affected controls data, can be expanded if needed. + */ +#define SDCA_MAX_AFFECTED_COUNT 2048 + +/** + * enum sdca_function_type - SDCA Function Type codes + * @SDCA_FUNCTION_TYPE_SMART_AMP: Amplifier with protection features. + * @SDCA_FUNCTION_TYPE_SIMPLE_AMP: Subset of SmartAmp. + * @SDCA_FUNCTION_TYPE_SMART_MIC: Smart microphone with acoustic triggers. + * @SDCA_FUNCTION_TYPE_SIMPLE_MIC: Subset of SmartMic. + * @SDCA_FUNCTION_TYPE_SPEAKER_MIC: Combination of SmartMic and SmartAmp. + * @SDCA_FUNCTION_TYPE_UAJ: 3.5mm Universal Audio jack. + * @SDCA_FUNCTION_TYPE_RJ: Retaskable jack. + * @SDCA_FUNCTION_TYPE_SIMPLE_JACK: Subset of UAJ. + * @SDCA_FUNCTION_TYPE_HID: Human Interface Device, for e.g. buttons. + * @SDCA_FUNCTION_TYPE_COMPANION_AMP: Sources audio from another amp. + * @SDCA_FUNCTION_TYPE_IMP_DEF: Implementation-defined function. + * + * SDCA Function Types from SDCA specification v1.0a Section 5.1.2 + * all Function types not described are reserved. + * + * Note that SIMPLE_AMP, SIMPLE_MIC and SIMPLE_JACK Function Types + * are NOT defined in SDCA 1.0a, but they were defined in earlier + * drafts and are planned for 1.1. + */ +enum sdca_function_type { + SDCA_FUNCTION_TYPE_SMART_AMP = 0x01, + SDCA_FUNCTION_TYPE_SIMPLE_AMP = 0x02, + SDCA_FUNCTION_TYPE_SMART_MIC = 0x03, + SDCA_FUNCTION_TYPE_SIMPLE_MIC = 0x04, + SDCA_FUNCTION_TYPE_SPEAKER_MIC = 0x05, + SDCA_FUNCTION_TYPE_UAJ = 0x06, + SDCA_FUNCTION_TYPE_RJ = 0x07, + SDCA_FUNCTION_TYPE_SIMPLE_JACK = 0x08, + SDCA_FUNCTION_TYPE_HID = 0x0A, + SDCA_FUNCTION_TYPE_COMPANION_AMP = 0x0B, + SDCA_FUNCTION_TYPE_IMP_DEF = 0x1F, +}; + +/* Human-readable names used for kernel logs and Function device registration/bind */ +#define SDCA_FUNCTION_TYPE_SMART_AMP_NAME "SmartAmp" +#define SDCA_FUNCTION_TYPE_SIMPLE_AMP_NAME "SimpleAmp" +#define SDCA_FUNCTION_TYPE_SMART_MIC_NAME "SmartMic" +#define SDCA_FUNCTION_TYPE_SIMPLE_MIC_NAME "SimpleMic" +#define SDCA_FUNCTION_TYPE_SPEAKER_MIC_NAME "SpeakerMic" +#define SDCA_FUNCTION_TYPE_UAJ_NAME "UAJ" +#define SDCA_FUNCTION_TYPE_RJ_NAME "RJ" +#define SDCA_FUNCTION_TYPE_SIMPLE_NAME "SimpleJack" +#define SDCA_FUNCTION_TYPE_HID_NAME "HID" +#define SDCA_FUNCTION_TYPE_COMPANION_AMP_NAME "CompanionAmp" +#define SDCA_FUNCTION_TYPE_IMP_DEF_NAME "ImplementationDefined" + +/** + * struct sdca_init_write - a single initialization write + * @addr: Register address to be written + * @val: Single byte value to be written + */ +struct sdca_init_write { + u32 addr; + u8 val; +}; + +/** + * define SDCA_CTL_TYPE - create a unique identifier for an SDCA Control + * @ent: Entity Type code. + * @sel: Control Selector code. + * + * Sometimes there is a need to identify a type of Control, for example to + * determine what name the control should have. SDCA Selectors are reused + * across Entity types, as such it is necessary to combine both the Entity + * Type and the Control Selector to obtain a unique identifier. + */ +#define SDCA_CTL_TYPE(ent, sel) ((ent) << 8 | (sel)) + +/** + * define SDCA_CTL_TYPE_S - static version of SDCA_CTL_TYPE + * @ent: Entity name, for example IT, MFPU, etc. this string can be read + * from the last characters of the SDCA_ENTITY_TYPE_* macros. + * @sel: Control Selector name, for example MIC_BIAS, MUTE, etc. this + * string can be read from the last characters of the SDCA_CTL_*_* + * macros. + * + * Short hand to specific a Control type statically for example: + * SDCA_CTL_TYPE_S(IT, MIC_BIAS). + */ +#define SDCA_CTL_TYPE_S(ent, sel) SDCA_CTL_TYPE(SDCA_ENTITY_TYPE_##ent, \ + SDCA_CTL_##ent##_##sel) + +/** + * enum sdca_messageoffset_range - Column definitions UMP MessageOffset + */ +enum sdca_messageoffset_range { + SDCA_MESSAGEOFFSET_BUFFER_START_ADDRESS = 0, + SDCA_MESSAGEOFFSET_BUFFER_LENGTH = 1, + SDCA_MESSAGEOFFSET_UMP_MODE = 2, + SDCA_MESSAGEOFFSET_NCOLS = 3, +}; + +/** + * enum sdca_ump_mode - SDCA UMP Mode + */ +enum sdca_ump_mode { + SDCA_UMP_MODE_DIRECT = 0x00, + SDCA_UMP_MODE_INDIRECT = 0x01, +}; + +/** + * enum sdca_ump_owner - SDCA UMP Owner + */ +enum sdca_ump_owner { + SDCA_UMP_OWNER_HOST = 0x00, + SDCA_UMP_OWNER_DEVICE = 0x01, +}; + +/** + * enum sdca_it_controls - SDCA Controls for Input Terminal + * + * Control Selectors for Input Terminal from SDCA specification v1.0 + * section 6.2.1.3. + */ +enum sdca_it_controls { + SDCA_CTL_IT_MIC_BIAS = 0x03, + SDCA_CTL_IT_USAGE = 0x04, + SDCA_CTL_IT_LATENCY = 0x08, + SDCA_CTL_IT_CLUSTERINDEX = 0x10, + SDCA_CTL_IT_DATAPORT_SELECTOR = 0x11, + SDCA_CTL_IT_MATCHING_GUID = 0x12, + SDCA_CTL_IT_KEEP_ALIVE = 0x13, + SDCA_CTL_IT_NDAI_STREAM = 0x14, + SDCA_CTL_IT_NDAI_CATEGORY = 0x15, + SDCA_CTL_IT_NDAI_CODINGTYPE = 0x16, + SDCA_CTL_IT_NDAI_PACKETTYPE = 0x17, +}; + +/** + * enum sdca_ot_controls - SDCA Controls for Output Terminal + * + * Control Selectors for Output Terminal from SDCA specification v1.0 + * section 6.2.2.3. + */ +enum sdca_ot_controls { + SDCA_CTL_OT_USAGE = 0x04, + SDCA_CTL_OT_LATENCY = 0x08, + SDCA_CTL_OT_DATAPORT_SELECTOR = 0x11, + SDCA_CTL_OT_MATCHING_GUID = 0x12, + SDCA_CTL_OT_KEEP_ALIVE = 0x13, + SDCA_CTL_OT_NDAI_STREAM = 0x14, + SDCA_CTL_OT_NDAI_CATEGORY = 0x15, + SDCA_CTL_OT_NDAI_CODINGTYPE = 0x16, + SDCA_CTL_OT_NDAI_PACKETTYPE = 0x17, +}; + +/** + * enum sdca_usage_range - Column definitions for Usage + */ +enum sdca_usage_range { + SDCA_USAGE_NUMBER = 0, + SDCA_USAGE_CBN = 1, + SDCA_USAGE_SAMPLE_RATE = 2, + SDCA_USAGE_SAMPLE_WIDTH = 3, + SDCA_USAGE_FULL_SCALE = 4, + SDCA_USAGE_NOISE_FLOOR = 5, + SDCA_USAGE_TAG = 6, + SDCA_USAGE_NCOLS = 7, +}; + +/** + * enum sdca_dataport_selector_range - Column definitions for DataPort_Selector + */ +enum sdca_dataport_selector_range { + SDCA_DATAPORT_SELECTOR_NCOLS = 16, + SDCA_DATAPORT_SELECTOR_NROWS = 4, +}; + +/** + * enum sdca_mu_controls - SDCA Controls for Mixer Unit + * + * Control Selectors for Mixer Unit from SDCA specification v1.0 + * section 6.3.4.2. + */ +enum sdca_mu_controls { + SDCA_CTL_MU_MIXER = 0x01, + SDCA_CTL_MU_LATENCY = 0x06, +}; + +/** + * enum sdca_su_controls - SDCA Controls for Selector Unit + * + * Control Selectors for Selector Unit from SDCA specification v1.0 + * section 6.3.8.3. + */ +enum sdca_su_controls { + SDCA_CTL_SU_SELECTOR = 0x01, + SDCA_CTL_SU_LATENCY = 0x02, +}; + +/** + * enum sdca_fu_controls - SDCA Controls for Feature Unit + * + * Control Selectors for Feature Unit from SDCA specification v1.0 + * section 6.3.2.3. + */ +enum sdca_fu_controls { + SDCA_CTL_FU_MUTE = 0x01, + SDCA_CTL_FU_CHANNEL_VOLUME = 0x02, + SDCA_CTL_FU_AGC = 0x07, + SDCA_CTL_FU_BASS_BOOST = 0x09, + SDCA_CTL_FU_LOUDNESS = 0x0A, + SDCA_CTL_FU_GAIN = 0x0B, + SDCA_CTL_FU_LATENCY = 0x10, +}; + +/** + * enum sdca_volume_range - Column definitions for Q7.8dB volumes/gains + */ +enum sdca_volume_range { + SDCA_VOLUME_LINEAR_MIN = 0, + SDCA_VOLUME_LINEAR_MAX = 1, + SDCA_VOLUME_LINEAR_STEP = 2, + SDCA_VOLUME_LINEAR_NCOLS = 3, +}; + +/** + * enum sdca_xu_controls - SDCA Controls for Extension Unit + * + * Control Selectors for Extension Unit from SDCA specification v1.0 + * section 6.3.10.3. + */ +enum sdca_xu_controls { + SDCA_CTL_XU_BYPASS = 0x01, + SDCA_CTL_XU_LATENCY = 0x06, + SDCA_CTL_XU_XU_ID = 0x07, + SDCA_CTL_XU_XU_VERSION = 0x08, + SDCA_CTL_XU_FDL_CURRENTOWNER = 0x10, + SDCA_CTL_XU_FDL_MESSAGEOFFSET = 0x12, + SDCA_CTL_XU_FDL_MESSAGELENGTH = 0x13, + SDCA_CTL_XU_FDL_STATUS = 0x14, + SDCA_CTL_XU_FDL_SET_INDEX = 0x15, + SDCA_CTL_XU_FDL_HOST_REQUEST = 0x16, + + /* FDL Status Host->Device bit definitions */ + SDCA_CTL_XU_FDLH_TRANSFERRED_CHUNK = BIT(0), + SDCA_CTL_XU_FDLH_TRANSFERRED_FILE = BIT(1), + SDCA_CTL_XU_FDLH_SET_IN_PROGRESS = BIT(2), + SDCA_CTL_XU_FDLH_RESET_ACK = BIT(4), + SDCA_CTL_XU_FDLH_REQ_ABORT = BIT(5), + /* FDL Status Device->Host bit definitions */ + SDCA_CTL_XU_FDLD_REQ_RESET = BIT(4), + SDCA_CTL_XU_FDLD_REQ_ABORT = BIT(5), + SDCA_CTL_XU_FDLD_ACK_TRANSFER = BIT(6), + SDCA_CTL_XU_FDLD_NEEDS_SET = BIT(7), +}; + +/** + * enum sdca_fdl_set_index_range - Column definitions UMP SetIndex + */ +enum sdca_fdl_set_index_range { + SDCA_FDL_SET_INDEX_SET_NUMBER = 0, + SDCA_FDL_SET_INDEX_FILE_SET_ID = 1, + SDCA_FDL_SET_INDEX_NCOLS = 2, +}; + +/** + * enum sdca_cs_controls - SDCA Controls for Clock Source + * + * Control Selectors for Clock Source from SDCA specification v1.0 + * section 6.4.1.3. + */ +enum sdca_cs_controls { + SDCA_CTL_CS_CLOCK_VALID = 0x02, + SDCA_CTL_CS_SAMPLERATEINDEX = 0x10, +}; + +/** + * enum sdca_samplerateindex_range - Column definitions for SampleRateIndex + */ +enum sdca_samplerateindex_range { + SDCA_SAMPLERATEINDEX_INDEX = 0, + SDCA_SAMPLERATEINDEX_RATE = 1, + SDCA_SAMPLERATEINDEX_NCOLS = 2, +}; + +/** + * enum sdca_cx_controls - SDCA Controls for Clock Selector + * + * Control Selectors for Clock Selector from SDCA specification v1.0 + * section 6.4.2.3. + */ +enum sdca_cx_controls { + SDCA_CTL_CX_CLOCK_SELECT = 0x01, +}; + +/** + * enum sdca_pde_controls - SDCA Controls for Power Domain Entity + * + * Control Selectors for Power Domain Entity from SDCA specification + * v1.0 section 6.5.2.2. + */ +enum sdca_pde_controls { + SDCA_CTL_PDE_REQUESTED_PS = 0x01, + SDCA_CTL_PDE_ACTUAL_PS = 0x10, +}; + +/** + * enum sdca_requested_ps_range - Column definitions for Requested PS + */ +enum sdca_requested_ps_range { + SDCA_REQUESTED_PS_STATE = 0, + SDCA_REQUESTED_PS_NCOLS = 1, +}; + +/** + * enum sdca_ge_controls - SDCA Controls for Group Unit + * + * Control Selectors for Group Unit from SDCA specification v1.0 + * section 6.5.1.4. + */ +enum sdca_ge_controls { + SDCA_CTL_GE_SELECTED_MODE = 0x01, + SDCA_CTL_GE_DETECTED_MODE = 0x02, +}; + +/** + * enum sdca_selected_mode_range - Column definitions for Selected Mode + */ +enum sdca_selected_mode_range { + SDCA_SELECTED_MODE_INDEX = 0, + SDCA_SELECTED_MODE_TERM_TYPE = 1, + SDCA_SELECTED_MODE_NCOLS = 2, +}; + +/** + * enum sdca_detected_mode_values - Predefined GE Detected Mode values + */ +enum sdca_detected_mode_values { + SDCA_DETECTED_MODE_JACK_UNPLUGGED = 0, + SDCA_DETECTED_MODE_JACK_UNKNOWN = 1, + SDCA_DETECTED_MODE_DETECTION_IN_PROGRESS = 2, +}; + +/** + * enum sdca_spe_controls - SDCA Controls for Security & Privacy Unit + * + * Control Selectors for Security & Privacy Unit from SDCA + * specification v1.0 Section 6.5.3.2. + */ +enum sdca_spe_controls { + SDCA_CTL_SPE_PRIVATE = 0x01, + SDCA_CTL_SPE_PRIVACY_POLICY = 0x02, + SDCA_CTL_SPE_PRIVACY_LOCKSTATE = 0x03, + SDCA_CTL_SPE_PRIVACY_OWNER = 0x04, + SDCA_CTL_SPE_AUTHTX_CURRENTOWNER = 0x10, + SDCA_CTL_SPE_AUTHTX_MESSAGEOFFSET = 0x12, + SDCA_CTL_SPE_AUTHTX_MESSAGELENGTH = 0x13, + SDCA_CTL_SPE_AUTHRX_CURRENTOWNER = 0x14, + SDCA_CTL_SPE_AUTHRX_MESSAGEOFFSET = 0x16, + SDCA_CTL_SPE_AUTHRX_MESSAGELENGTH = 0x17, +}; + +/** + * enum sdca_cru_controls - SDCA Controls for Channel Remapping Unit + * + * Control Selectors for Channel Remapping Unit from SDCA + * specification v1.0 Section 6.3.1.3. + */ +enum sdca_cru_controls { + SDCA_CTL_CRU_LATENCY = 0x06, + SDCA_CTL_CRU_CLUSTERINDEX = 0x10, +}; + +/** + * enum sdca_udmpu_controls - SDCA Controls for Up-Down Mixer Processing Unit + * + * Control Selectors for Up-Down Mixer Processing Unit from SDCA + * specification v1.0 Section 6.3.9.3. + */ +enum sdca_udmpu_controls { + SDCA_CTL_UDMPU_LATENCY = 0x06, + SDCA_CTL_UDMPU_CLUSTERINDEX = 0x10, + SDCA_CTL_UDMPU_ACOUSTIC_ENERGY_LEVEL_MONITOR = 0x11, + SDCA_CTL_UDMPU_ULTRASOUND_LOOP_GAIN = 0x12, + SDCA_CTL_UDMPU_OPAQUESET_0 = 0x18, + SDCA_CTL_UDMPU_OPAQUESET_1 = 0x19, + SDCA_CTL_UDMPU_OPAQUESET_2 = 0x1A, + SDCA_CTL_UDMPU_OPAQUESET_3 = 0x1B, + SDCA_CTL_UDMPU_OPAQUESET_4 = 0x1C, + SDCA_CTL_UDMPU_OPAQUESET_5 = 0x1D, + SDCA_CTL_UDMPU_OPAQUESET_6 = 0x1E, + SDCA_CTL_UDMPU_OPAQUESET_7 = 0x1F, + SDCA_CTL_UDMPU_OPAQUESET_8 = 0x20, + SDCA_CTL_UDMPU_OPAQUESET_9 = 0x21, + SDCA_CTL_UDMPU_OPAQUESET_10 = 0x22, + SDCA_CTL_UDMPU_OPAQUESET_11 = 0x23, + SDCA_CTL_UDMPU_OPAQUESET_12 = 0x24, + SDCA_CTL_UDMPU_OPAQUESET_13 = 0x25, + SDCA_CTL_UDMPU_OPAQUESET_14 = 0x26, + SDCA_CTL_UDMPU_OPAQUESET_15 = 0x27, + SDCA_CTL_UDMPU_OPAQUESET_16 = 0x28, + SDCA_CTL_UDMPU_OPAQUESET_17 = 0x29, + SDCA_CTL_UDMPU_OPAQUESET_18 = 0x2A, + SDCA_CTL_UDMPU_OPAQUESET_19 = 0x2B, + SDCA_CTL_UDMPU_OPAQUESET_20 = 0x2C, + SDCA_CTL_UDMPU_OPAQUESET_21 = 0x2D, + SDCA_CTL_UDMPU_OPAQUESET_22 = 0x2E, + SDCA_CTL_UDMPU_OPAQUESET_23 = 0x2F, +}; + +/** + * enum sdca_mfpu_controls - SDCA Controls for Multi-Function Processing Unit + * + * Control Selectors for Multi-Function Processing Unit from SDCA + * specification v1.0 Section 6.3.3.4. + */ +enum sdca_mfpu_controls { + SDCA_CTL_MFPU_BYPASS = 0x01, + SDCA_CTL_MFPU_ALGORITHM_READY = 0x04, + SDCA_CTL_MFPU_ALGORITHM_ENABLE = 0x05, + SDCA_CTL_MFPU_LATENCY = 0x08, + SDCA_CTL_MFPU_ALGORITHM_PREPARE = 0x09, + SDCA_CTL_MFPU_CLUSTERINDEX = 0x10, + SDCA_CTL_MFPU_CENTER_FREQUENCY_INDEX = 0x11, + SDCA_CTL_MFPU_ULTRASOUND_LEVEL = 0x12, + SDCA_CTL_MFPU_AE_NUMBER = 0x13, + SDCA_CTL_MFPU_AE_CURRENTOWNER = 0x14, + SDCA_CTL_MFPU_AE_MESSAGEOFFSET = 0x16, + SDCA_CTL_MFPU_AE_MESSAGELENGTH = 0x17, +}; + +/** + * enum sdca_smpu_controls - SDCA Controls for Smart Mic Processing Unit + * + * Control Selectors for Smart Mic Processing Unit from SDCA + * specification v1.0 Section 6.3.7.3. + */ +enum sdca_smpu_controls { + SDCA_CTL_SMPU_LATENCY = 0x06, + SDCA_CTL_SMPU_TRIGGER_ENABLE = 0x10, + SDCA_CTL_SMPU_TRIGGER_STATUS = 0x11, + SDCA_CTL_SMPU_HIST_BUFFER_MODE = 0x12, + SDCA_CTL_SMPU_HIST_BUFFER_PREAMBLE = 0x13, + SDCA_CTL_SMPU_HIST_ERROR = 0x14, + SDCA_CTL_SMPU_TRIGGER_EXTENSION = 0x15, + SDCA_CTL_SMPU_TRIGGER_READY = 0x16, + SDCA_CTL_SMPU_HIST_CURRENTOWNER = 0x18, + SDCA_CTL_SMPU_HIST_MESSAGEOFFSET = 0x1A, + SDCA_CTL_SMPU_HIST_MESSAGELENGTH = 0x1B, + SDCA_CTL_SMPU_DTODTX_CURRENTOWNER = 0x1C, + SDCA_CTL_SMPU_DTODTX_MESSAGEOFFSET = 0x1E, + SDCA_CTL_SMPU_DTODTX_MESSAGELENGTH = 0x1F, + SDCA_CTL_SMPU_DTODRX_CURRENTOWNER = 0x20, + SDCA_CTL_SMPU_DTODRX_MESSAGEOFFSET = 0x22, + SDCA_CTL_SMPU_DTODRX_MESSAGELENGTH = 0x23, +}; + +/** + * enum sdca_sapu_controls - SDCA Controls for Smart Amp Processing Unit + * + * Control Selectors for Smart Amp Processing Unit from SDCA + * specification v1.0 Section 6.3.6.3. + */ +enum sdca_sapu_controls { + SDCA_CTL_SAPU_LATENCY = 0x05, + SDCA_CTL_SAPU_PROTECTION_MODE = 0x10, + SDCA_CTL_SAPU_PROTECTION_STATUS = 0x11, + SDCA_CTL_SAPU_OPAQUESETREQ_INDEX = 0x12, + SDCA_CTL_SAPU_DTODTX_CURRENTOWNER = 0x14, + SDCA_CTL_SAPU_DTODTX_MESSAGEOFFSET = 0x16, + SDCA_CTL_SAPU_DTODTX_MESSAGELENGTH = 0x17, + SDCA_CTL_SAPU_DTODRX_CURRENTOWNER = 0x18, + SDCA_CTL_SAPU_DTODRX_MESSAGEOFFSET = 0x1A, + SDCA_CTL_SAPU_DTODRX_MESSAGELENGTH = 0x1B, +}; + +/** + * enum sdca_ppu_controls - SDCA Controls for Post Processing Unit + * + * Control Selectors for Post Processing Unit from SDCA specification + * v1.0 Section 6.3.5.3. + */ +enum sdca_ppu_controls { + SDCA_CTL_PPU_LATENCY = 0x06, + SDCA_CTL_PPU_POSTURENUMBER = 0x10, + SDCA_CTL_PPU_POSTUREEXTENSION = 0x11, + SDCA_CTL_PPU_HORIZONTALBALANCE = 0x12, + SDCA_CTL_PPU_VERTICALBALANCE = 0x13, +}; + +/** + * enum sdca_tg_controls - SDCA Controls for Tone Generator Entity + * + * Control Selectors for Tone Generator from SDCA specification v1.0 + * Section 6.5.4.4. + */ +enum sdca_tg_controls { + SDCA_CTL_TG_TONE_DIVIDER = 0x10, +}; + +/** + * enum sdca_hide_controls - SDCA Controls for HIDE Entity + * + * Control Selectors for HIDE from SDCA specification v1.0 Section + * 6.6.1.2. + */ +enum sdca_hide_controls { + SDCA_CTL_HIDE_HIDTX_CURRENTOWNER = 0x10, + SDCA_CTL_HIDE_HIDTX_MESSAGEOFFSET = 0x12, + SDCA_CTL_HIDE_HIDTX_MESSAGELENGTH = 0x13, + SDCA_CTL_HIDE_HIDRX_CURRENTOWNER = 0x14, + SDCA_CTL_HIDE_HIDRX_MESSAGEOFFSET = 0x16, + SDCA_CTL_HIDE_HIDRX_MESSAGELENGTH = 0x17, +}; + +/** + * enum sdca_entity0_controls - SDCA Controls for Entity 0 + * + * Control Selectors for Entity 0 from SDCA specification v1.0 Section + * 6.7.1.1. + */ +enum sdca_entity0_controls { + SDCA_CTL_ENTITY_0_COMMIT_GROUP_MASK = 0x01, + SDCA_CTL_ENTITY_0_FUNCTION_SDCA_VERSION = 0x04, + SDCA_CTL_ENTITY_0_FUNCTION_TYPE = 0x05, + SDCA_CTL_ENTITY_0_FUNCTION_MANUFACTURER_ID = 0x06, + SDCA_CTL_ENTITY_0_FUNCTION_ID = 0x07, + SDCA_CTL_ENTITY_0_FUNCTION_VERSION = 0x08, + SDCA_CTL_ENTITY_0_FUNCTION_EXTENSION_ID = 0x09, + SDCA_CTL_ENTITY_0_FUNCTION_EXTENSION_VERSION = 0x0A, + SDCA_CTL_ENTITY_0_FUNCTION_STATUS = 0x10, + SDCA_CTL_ENTITY_0_FUNCTION_ACTION = 0x11, + SDCA_CTL_ENTITY_0_MATCHING_GUID = 0x12, + SDCA_CTL_ENTITY_0_DEVICE_MANUFACTURER_ID = 0x2C, + SDCA_CTL_ENTITY_0_DEVICE_PART_ID = 0x2D, + SDCA_CTL_ENTITY_0_DEVICE_VERSION = 0x2E, + SDCA_CTL_ENTITY_0_DEVICE_SDCA_VERSION = 0x2F, + + /* Function Status Bits */ + SDCA_CTL_ENTITY_0_DEVICE_NEWLY_ATTACHED = BIT(0), + SDCA_CTL_ENTITY_0_INTS_DISABLED_ABNORMALLY = BIT(1), + SDCA_CTL_ENTITY_0_STREAMING_STOPPED_ABNORMALLY = BIT(2), + SDCA_CTL_ENTITY_0_FUNCTION_FAULT = BIT(3), + SDCA_CTL_ENTITY_0_UMP_SEQUENCE_FAULT = BIT(4), + SDCA_CTL_ENTITY_0_FUNCTION_NEEDS_INITIALIZATION = BIT(5), + SDCA_CTL_ENTITY_0_FUNCTION_HAS_BEEN_RESET = BIT(6), + SDCA_CTL_ENTITY_0_FUNCTION_BUSY = BIT(7), + + /* Function Action Bits */ + SDCA_CTL_ENTITY_0_RESET_FUNCTION_NOW = BIT(0), +}; + +#define SDCA_CTL_MIC_BIAS_NAME "Mic Bias" +#define SDCA_CTL_USAGE_NAME "Usage" +#define SDCA_CTL_LATENCY_NAME "Latency" +#define SDCA_CTL_CLUSTERINDEX_NAME "Cluster Index" +#define SDCA_CTL_DATAPORT_SELECTOR_NAME "Dataport Selector" +#define SDCA_CTL_MATCHING_GUID_NAME "Matching GUID" +#define SDCA_CTL_KEEP_ALIVE_NAME "Keep Alive" +#define SDCA_CTL_NDAI_STREAM_NAME "NDAI Stream" +#define SDCA_CTL_NDAI_CATEGORY_NAME "NDAI Category" +#define SDCA_CTL_NDAI_CODINGTYPE_NAME "NDAI Coding Type" +#define SDCA_CTL_NDAI_PACKETTYPE_NAME "NDAI Packet Type" +#define SDCA_CTL_MIXER_NAME "Mixer" +#define SDCA_CTL_SELECTOR_NAME "Selector" +#define SDCA_CTL_MUTE_NAME "Channel" +#define SDCA_CTL_CHANNEL_VOLUME_NAME "Channel Volume" +#define SDCA_CTL_AGC_NAME "AGC" +#define SDCA_CTL_BASS_BOOST_NAME "Bass Boost" +#define SDCA_CTL_LOUDNESS_NAME "Loudness" +#define SDCA_CTL_GAIN_NAME "Gain" +#define SDCA_CTL_BYPASS_NAME "Bypass" +#define SDCA_CTL_XU_ID_NAME "XU ID" +#define SDCA_CTL_XU_VERSION_NAME "XU Version" +#define SDCA_CTL_FDL_CURRENTOWNER_NAME "FDL Current Owner" +#define SDCA_CTL_FDL_MESSAGEOFFSET_NAME "FDL Message Offset" +#define SDCA_CTL_FDL_MESSAGELENGTH_NAME "FDL Message Length" +#define SDCA_CTL_FDL_STATUS_NAME "FDL Status" +#define SDCA_CTL_FDL_SET_INDEX_NAME "FDL Set Index" +#define SDCA_CTL_FDL_HOST_REQUEST_NAME "FDL Host Request" +#define SDCA_CTL_CLOCK_VALID_NAME "Clock Valid" +#define SDCA_CTL_SAMPLERATEINDEX_NAME "Sample Rate Index" +#define SDCA_CTL_CLOCK_SELECT_NAME "Clock Select" +#define SDCA_CTL_REQUESTED_PS_NAME "Requested PS" +#define SDCA_CTL_ACTUAL_PS_NAME "Actual PS" +#define SDCA_CTL_SELECTED_MODE_NAME "Selected Mode" +#define SDCA_CTL_DETECTED_MODE_NAME "Detected Mode" +#define SDCA_CTL_PRIVATE_NAME "Private" +#define SDCA_CTL_PRIVACY_POLICY_NAME "Privacy Policy" +#define SDCA_CTL_PRIVACY_LOCKSTATE_NAME "Privacy Lockstate" +#define SDCA_CTL_PRIVACY_OWNER_NAME "Privacy Owner" +#define SDCA_CTL_AUTHTX_CURRENTOWNER_NAME "AuthTX Current Owner" +#define SDCA_CTL_AUTHTX_MESSAGEOFFSET_NAME "AuthTX Message Offset" +#define SDCA_CTL_AUTHTX_MESSAGELENGTH_NAME "AuthTX Message Length" +#define SDCA_CTL_AUTHRX_CURRENTOWNER_NAME "AuthRX Current Owner" +#define SDCA_CTL_AUTHRX_MESSAGEOFFSET_NAME "AuthRX Message Offset" +#define SDCA_CTL_AUTHRX_MESSAGELENGTH_NAME "AuthRX Message Length" +#define SDCA_CTL_ACOUSTIC_ENERGY_LEVEL_MONITOR_NAME "Acoustic Energy Level Monitor" +#define SDCA_CTL_ULTRASOUND_LOOP_GAIN_NAME "Ultrasound Loop Gain" +#define SDCA_CTL_OPAQUESET_0_NAME "Opaqueset 0" +#define SDCA_CTL_OPAQUESET_1_NAME "Opaqueset 1" +#define SDCA_CTL_OPAQUESET_2_NAME "Opaqueset 2" +#define SDCA_CTL_OPAQUESET_3_NAME "Opaqueset 3" +#define SDCA_CTL_OPAQUESET_4_NAME "Opaqueset 4" +#define SDCA_CTL_OPAQUESET_5_NAME "Opaqueset 5" +#define SDCA_CTL_OPAQUESET_6_NAME "Opaqueset 6" +#define SDCA_CTL_OPAQUESET_7_NAME "Opaqueset 7" +#define SDCA_CTL_OPAQUESET_8_NAME "Opaqueset 8" +#define SDCA_CTL_OPAQUESET_9_NAME "Opaqueset 9" +#define SDCA_CTL_OPAQUESET_10_NAME "Opaqueset 10" +#define SDCA_CTL_OPAQUESET_11_NAME "Opaqueset 11" +#define SDCA_CTL_OPAQUESET_12_NAME "Opaqueset 12" +#define SDCA_CTL_OPAQUESET_13_NAME "Opaqueset 13" +#define SDCA_CTL_OPAQUESET_14_NAME "Opaqueset 14" +#define SDCA_CTL_OPAQUESET_15_NAME "Opaqueset 15" +#define SDCA_CTL_OPAQUESET_16_NAME "Opaqueset 16" +#define SDCA_CTL_OPAQUESET_17_NAME "Opaqueset 17" +#define SDCA_CTL_OPAQUESET_18_NAME "Opaqueset 18" +#define SDCA_CTL_OPAQUESET_19_NAME "Opaqueset 19" +#define SDCA_CTL_OPAQUESET_20_NAME "Opaqueset 20" +#define SDCA_CTL_OPAQUESET_21_NAME "Opaqueset 21" +#define SDCA_CTL_OPAQUESET_22_NAME "Opaqueset 22" +#define SDCA_CTL_OPAQUESET_23_NAME "Opaqueset 23" +#define SDCA_CTL_ALGORITHM_READY_NAME "Algorithm Ready" +#define SDCA_CTL_ALGORITHM_ENABLE_NAME "Algorithm Enable" +#define SDCA_CTL_ALGORITHM_PREPARE_NAME "Algorithm Prepare" +#define SDCA_CTL_CENTER_FREQUENCY_INDEX_NAME "Center Frequency Index" +#define SDCA_CTL_ULTRASOUND_LEVEL_NAME "Ultrasound Level" +#define SDCA_CTL_AE_NUMBER_NAME "AE Number" +#define SDCA_CTL_AE_CURRENTOWNER_NAME "AE Current Owner" +#define SDCA_CTL_AE_MESSAGEOFFSET_NAME "AE Message Offset" +#define SDCA_CTL_AE_MESSAGELENGTH_NAME "AE Message Length" +#define SDCA_CTL_TRIGGER_ENABLE_NAME "Trigger Enable" +#define SDCA_CTL_TRIGGER_STATUS_NAME "Trigger Status" +#define SDCA_CTL_HIST_BUFFER_MODE_NAME "Hist Buffer Mode" +#define SDCA_CTL_HIST_BUFFER_PREAMBLE_NAME "Hist Buffer Preamble" +#define SDCA_CTL_HIST_ERROR_NAME "Hist Error" +#define SDCA_CTL_TRIGGER_EXTENSION_NAME "Trigger Extension" +#define SDCA_CTL_TRIGGER_READY_NAME "Trigger Ready" +#define SDCA_CTL_HIST_CURRENTOWNER_NAME "Hist Current Owner" +#define SDCA_CTL_HIST_MESSAGEOFFSET_NAME "Hist Message Offset" +#define SDCA_CTL_HIST_MESSAGELENGTH_NAME "Hist Message Length" +#define SDCA_CTL_DTODTX_CURRENTOWNER_NAME "DTODTX Current Owner" +#define SDCA_CTL_DTODTX_MESSAGEOFFSET_NAME "DTODTX Message Offset" +#define SDCA_CTL_DTODTX_MESSAGELENGTH_NAME "DTODTX Message Length" +#define SDCA_CTL_DTODRX_CURRENTOWNER_NAME "DTODRX Current Owner" +#define SDCA_CTL_DTODRX_MESSAGEOFFSET_NAME "DTODRX Message Offset" +#define SDCA_CTL_DTODRX_MESSAGELENGTH_NAME "DTODRX Message Length" +#define SDCA_CTL_PROTECTION_MODE_NAME "Protection Mode" +#define SDCA_CTL_PROTECTION_STATUS_NAME "Protection Status" +#define SDCA_CTL_OPAQUESETREQ_INDEX_NAME "Opaqueset Req Index" +#define SDCA_CTL_DTODTX_CURRENTOWNER_NAME "DTODTX Current Owner" +#define SDCA_CTL_DTODTX_MESSAGEOFFSET_NAME "DTODTX Message Offset" +#define SDCA_CTL_DTODTX_MESSAGELENGTH_NAME "DTODTX Message Length" +#define SDCA_CTL_DTODRX_CURRENTOWNER_NAME "DTODRX Current Owner" +#define SDCA_CTL_DTODRX_MESSAGEOFFSET_NAME "DTODRX Message Offset" +#define SDCA_CTL_DTODRX_MESSAGELENGTH_NAME "DTODRX Message Length" +#define SDCA_CTL_POSTURENUMBER_NAME "Posture Number" +#define SDCA_CTL_POSTUREEXTENSION_NAME "Posture Extension" +#define SDCA_CTL_HORIZONTALBALANCE_NAME "Horizontal Balance" +#define SDCA_CTL_VERTICALBALANCE_NAME "Vertical Balance" +#define SDCA_CTL_TONE_DIVIDER_NAME "Tone Divider" +#define SDCA_CTL_HIDTX_CURRENTOWNER_NAME "HIDTX Current Owner" +#define SDCA_CTL_HIDTX_MESSAGEOFFSET_NAME "HIDTX Message Offset" +#define SDCA_CTL_HIDTX_MESSAGELENGTH_NAME "HIDTX Message Length" +#define SDCA_CTL_HIDRX_CURRENTOWNER_NAME "HIDRX Current Owner" +#define SDCA_CTL_HIDRX_MESSAGEOFFSET_NAME "HIDRX Message Offset" +#define SDCA_CTL_HIDRX_MESSAGELENGTH_NAME "HIDRX Message Length" +#define SDCA_CTL_COMMIT_GROUP_MASK_NAME "Commit Group Mask" +#define SDCA_CTL_FUNCTION_SDCA_VERSION_NAME "Function SDCA Version" +#define SDCA_CTL_FUNCTION_TYPE_NAME "Function Type" +#define SDCA_CTL_FUNCTION_MANUFACTURER_ID_NAME "Function Manufacturer ID" +#define SDCA_CTL_FUNCTION_ID_NAME "Function ID" +#define SDCA_CTL_FUNCTION_VERSION_NAME "Function Version" +#define SDCA_CTL_FUNCTION_EXTENSION_ID_NAME "Function Extension ID" +#define SDCA_CTL_FUNCTION_EXTENSION_VERSION_NAME "Function Extension Version" +#define SDCA_CTL_FUNCTION_STATUS_NAME "Function Status" +#define SDCA_CTL_FUNCTION_ACTION_NAME "Function Action" +#define SDCA_CTL_DEVICE_MANUFACTURER_ID_NAME "Device Manufacturer ID" +#define SDCA_CTL_DEVICE_PART_ID_NAME "Device Part ID" +#define SDCA_CTL_DEVICE_VERSION_NAME "Device Version" +#define SDCA_CTL_DEVICE_SDCA_VERSION_NAME "Device SDCA Version" + +/** + * enum sdca_control_datatype - SDCA Control Data Types + * + * Data Types as described in the SDCA specification v1.0 section + * 7.3. + */ +enum sdca_control_datatype { + SDCA_CTL_DATATYPE_ONEBIT, + SDCA_CTL_DATATYPE_INTEGER, + SDCA_CTL_DATATYPE_SPEC_ENCODED_VALUE, + SDCA_CTL_DATATYPE_BCD, + SDCA_CTL_DATATYPE_Q7P8DB, + SDCA_CTL_DATATYPE_BYTEINDEX, + SDCA_CTL_DATATYPE_POSTURENUMBER, + SDCA_CTL_DATATYPE_DP_INDEX, + SDCA_CTL_DATATYPE_BITINDEX, + SDCA_CTL_DATATYPE_BITMAP, + SDCA_CTL_DATATYPE_GUID, + SDCA_CTL_DATATYPE_IMPDEF, +}; + +/** + * enum sdca_access_mode - SDCA Control access mode + * + * Access modes as described in the SDCA specification v1.0 section + * 7.1.8.2. + */ +enum sdca_access_mode { + SDCA_ACCESS_MODE_RW = 0x0, + SDCA_ACCESS_MODE_DUAL = 0x1, + SDCA_ACCESS_MODE_RW1C = 0x2, + SDCA_ACCESS_MODE_RO = 0x3, + SDCA_ACCESS_MODE_RW1S = 0x4, + SDCA_ACCESS_MODE_DC = 0x5, +}; + +/** + * enum sdca_access_layer - SDCA Control access layer + * + * Access layers as described in the SDCA specification v1.0 section + * 7.1.9. + */ +enum sdca_access_layer { + SDCA_ACCESS_LAYER_USER = 1 << 0, + SDCA_ACCESS_LAYER_APPLICATION = 1 << 1, + SDCA_ACCESS_LAYER_CLASS = 1 << 2, + SDCA_ACCESS_LAYER_PLATFORM = 1 << 3, + SDCA_ACCESS_LAYER_DEVICE = 1 << 4, + SDCA_ACCESS_LAYER_EXTENSION = 1 << 5, +}; + +/** + * struct sdca_control_range - SDCA Control range table + * @cols: Number of columns in the range table. + * @rows: Number of rows in the range table. + * @data: Array of values contained in the range table. + */ +struct sdca_control_range { + unsigned int cols; + unsigned int rows; + u32 *data; +}; + +/** + * struct sdca_control - information for one SDCA Control + * @label: Name for the Control, from SDCA Specification v1.0, section 7.1.7. + * @sel: Identifier used for addressing. + * @nbits: Number of bits used in the Control. + * @values: Holds the Control value for constants and defaults. + * @reset: Defined reset value for the Control. + * @cn_list: A bitmask showing the valid Control Numbers within this Control, + * Control Numbers typically represent channels. + * @interrupt_position: SCDA interrupt line that will alert to changes on this + * Control. + * @type: Format of the data in the Control. + * @range: Buffer describing valid range of values for the Control. + * @mode: Access mode of the Control. + * @layers: Bitmask of access layers of the Control. + * @deferrable: Indicates if the access to the Control can be deferred. + * @is_volatile: Indicates the Control registers are forced to be treated + * as volatile. + * @has_default: Indicates the Control has a default value to be written. + * @has_reset: Indicates the Control has a defined reset value. + * @has_fixed: Indicates the Control only supports a single value. + */ +struct sdca_control { + const char *label; + int sel; + + int nbits; + int *values; + int reset; + u64 cn_list; + int interrupt_position; + + enum sdca_control_datatype type; + struct sdca_control_range range; + enum sdca_access_mode mode; + u8 layers; + + bool deferrable; + bool is_volatile; + bool has_default; + bool has_reset; + bool has_fixed; +}; + +/** + * enum sdca_terminal_type - SDCA Terminal Types + * + * Indicate what a Terminal Entity is used for, see in section 6.2.3 + * of the SDCA v1.0 specification. + */ +enum sdca_terminal_type { + /* Table 77 - Data Port*/ + SDCA_TERM_TYPE_GENERIC = 0x101, + SDCA_TERM_TYPE_ULTRASOUND = 0x180, + SDCA_TERM_TYPE_CAPTURE_DIRECT_PCM_MIC = 0x181, + SDCA_TERM_TYPE_RAW_PDM_MIC = 0x182, + SDCA_TERM_TYPE_SPEECH = 0x183, + SDCA_TERM_TYPE_VOICE = 0x184, + SDCA_TERM_TYPE_SECONDARY_PCM_MIC = 0x185, + SDCA_TERM_TYPE_ACOUSTIC_CONTEXT_AWARENESS = 0x186, + SDCA_TERM_TYPE_DTOD_STREAM = 0x187, + SDCA_TERM_TYPE_REFERENCE_STREAM = 0x188, + SDCA_TERM_TYPE_SENSE_CAPTURE = 0x189, + SDCA_TERM_TYPE_STREAMING_MIC = 0x18A, + SDCA_TERM_TYPE_OPTIMIZATION_STREAM = 0x190, + SDCA_TERM_TYPE_PDM_RENDER_STREAM = 0x191, + SDCA_TERM_TYPE_COMPANION_DATA = 0x192, + /* Table 78 - Transducer */ + SDCA_TERM_TYPE_MICROPHONE_TRANSDUCER = 0x201, + SDCA_TERM_TYPE_MICROPHONE_ARRAY_TRANSDUCER = 0x205, + SDCA_TERM_TYPE_PRIMARY_FULL_RANGE_SPEAKER = 0x380, + SDCA_TERM_TYPE_PRIMARY_LFE_SPEAKER = 0x381, + SDCA_TERM_TYPE_PRIMARY_TWEETER_SPEAKER = 0x382, + SDCA_TERM_TYPE_PRIMARY_ULTRASOUND_SPEAKER = 0x383, + SDCA_TERM_TYPE_SECONDARY_FULL_RANGE_SPEAKER = 0x390, + SDCA_TERM_TYPE_SECONDARY_LFE_SPEAKER = 0x391, + SDCA_TERM_TYPE_SECONDARY_TWEETER_SPEAKER = 0x392, + SDCA_TERM_TYPE_SECONDARY_ULTRASOUND_SPEAKER = 0x393, + SDCA_TERM_TYPE_TERTIARY_FULL_RANGE_SPEAKER = 0x3A0, + SDCA_TERM_TYPE_TERTIARY_LFE_SPEAKER = 0x3A1, + SDCA_TERM_TYPE_TERTIARY_TWEETER_SPEAKER = 0x3A2, + SDCA_TERM_TYPE_TERTIARY_ULTRASOUND_SPEAKER = 0x3A3, + SDCA_TERM_TYPE_SPDIF = 0x605, + SDCA_TERM_TYPE_NDAI_DISPLAY_AUDIO = 0x610, + SDCA_TERM_TYPE_NDAI_USB = 0x612, + SDCA_TERM_TYPE_NDAI_BLUETOOTH_MAIN = 0x614, + SDCA_TERM_TYPE_NDAI_BLUETOOTH_ALTERNATE = 0x615, + SDCA_TERM_TYPE_NDAI_BLUETOOTH_BOTH = 0x616, + SDCA_TERM_TYPE_LINEIN_STEREO = 0x680, + SDCA_TERM_TYPE_LINEIN_FRONT_LR = 0x681, + SDCA_TERM_TYPE_LINEIN_CENTER_LFE = 0x682, + SDCA_TERM_TYPE_LINEIN_SURROUND_LR = 0x683, + SDCA_TERM_TYPE_LINEIN_REAR_LR = 0x684, + SDCA_TERM_TYPE_LINEOUT_STEREO = 0x690, + SDCA_TERM_TYPE_LINEOUT_FRONT_LR = 0x691, + SDCA_TERM_TYPE_LINEOUT_CENTER_LFE = 0x692, + SDCA_TERM_TYPE_LINEOUT_SURROUND_LR = 0x693, + SDCA_TERM_TYPE_LINEOUT_REAR_LR = 0x694, + SDCA_TERM_TYPE_MIC_JACK = 0x6A0, + SDCA_TERM_TYPE_STEREO_JACK = 0x6B0, + SDCA_TERM_TYPE_FRONT_LR_JACK = 0x6B1, + SDCA_TERM_TYPE_CENTER_LFE_JACK = 0x6B2, + SDCA_TERM_TYPE_SURROUND_LR_JACK = 0x6B3, + SDCA_TERM_TYPE_REAR_LR_JACK = 0x6B4, + SDCA_TERM_TYPE_HEADPHONE_JACK = 0x6C0, + SDCA_TERM_TYPE_HEADSET_JACK = 0x6D0, + /* Table 79 - System */ + SDCA_TERM_TYPE_SENSE_DATA = 0x280, + SDCA_TERM_TYPE_PRIVACY_SIGNALING = 0x741, + SDCA_TERM_TYPE_PRIVACY_INDICATORS = 0x747, +}; + +#define SDCA_TERM_TYPE_LINEIN_STEREO_NAME "LineIn Stereo" +#define SDCA_TERM_TYPE_LINEIN_FRONT_LR_NAME "LineIn Front-LR" +#define SDCA_TERM_TYPE_LINEIN_CENTER_LFE_NAME "LineIn Center-LFE" +#define SDCA_TERM_TYPE_LINEIN_SURROUND_LR_NAME "LineIn Surround-LR" +#define SDCA_TERM_TYPE_LINEIN_REAR_LR_NAME "LineIn Rear-LR" +#define SDCA_TERM_TYPE_LINEOUT_STEREO_NAME "LineOut Stereo" +#define SDCA_TERM_TYPE_LINEOUT_FRONT_LR_NAME "LineOut Front-LR" +#define SDCA_TERM_TYPE_LINEOUT_CENTER_LFE_NAME "LineOut Center-LFE" +#define SDCA_TERM_TYPE_LINEOUT_SURROUND_LR_NAME "LineOut Surround-LR" +#define SDCA_TERM_TYPE_LINEOUT_REAR_LR_NAME "LineOut Rear-LR" +#define SDCA_TERM_TYPE_MIC_JACK_NAME "Microphone" +#define SDCA_TERM_TYPE_STEREO_JACK_NAME "Speaker Stereo" +#define SDCA_TERM_TYPE_FRONT_LR_JACK_NAME "Speaker Front-LR" +#define SDCA_TERM_TYPE_CENTER_LFE_JACK_NAME "Speaker Center-LFE" +#define SDCA_TERM_TYPE_SURROUND_LR_JACK_NAME "Speaker Surround-LR" +#define SDCA_TERM_TYPE_REAR_LR_JACK_NAME "Speaker Rear-LR" +#define SDCA_TERM_TYPE_HEADPHONE_JACK_NAME "Headphone" +#define SDCA_TERM_TYPE_HEADSET_JACK_NAME "Headset" + +/** + * enum sdca_connector_type - SDCA Connector Types + * + * Indicate the type of Connector that a Terminal Entity represents, + * see section 6.2.4 of the SDCA v1.0 specification. + */ +enum sdca_connector_type { + SDCA_CONN_TYPE_UNKNOWN = 0x00, + SDCA_CONN_TYPE_2P5MM_JACK = 0x01, + SDCA_CONN_TYPE_3P5MM_JACK = 0x02, + SDCA_CONN_TYPE_QUARTER_INCH_JACK = 0x03, + SDCA_CONN_TYPE_XLR = 0x05, + SDCA_CONN_TYPE_SPDIF_OPTICAL = 0x06, + SDCA_CONN_TYPE_RCA = 0x07, + SDCA_CONN_TYPE_DIN = 0x0E, + SDCA_CONN_TYPE_MINI_DIN = 0x0F, + SDCA_CONN_TYPE_EIAJ_OPTICAL = 0x13, + SDCA_CONN_TYPE_HDMI = 0x14, + SDCA_CONN_TYPE_DISPLAYPORT = 0x17, + SDCA_CONN_TYPE_LIGHTNING = 0x1B, + SDCA_CONN_TYPE_USB_C = 0x1E, + SDCA_CONN_TYPE_OTHER = 0xFF, +}; + +/** + * struct sdca_entity_iot - information specific to Input/Output Entities + * @clock: Pointer to the Entity providing this Terminal's clock. + * @type: Usage of the Terminal Entity. + * @connector: Physical Connector of the Terminal Entity. + * @reference: Physical Jack number of the Terminal Entity. + * @num_transducer: Number of transducers attached to the Terminal Entity. + * @is_dataport: Boolean indicating if this Terminal represents a Dataport. + */ +struct sdca_entity_iot { + struct sdca_entity *clock; + + enum sdca_terminal_type type; + enum sdca_connector_type connector; + int reference; + int num_transducer; + + bool is_dataport; +}; + +/** + * enum sdca_clock_type - SDCA Clock Types + * + * Indicate the synchronicity of an Clock Entity, see section 6.4.1.3 + * of the SDCA v1.0 specification. + */ +enum sdca_clock_type { + SDCA_CLOCK_TYPE_EXTERNAL = 0x00, + SDCA_CLOCK_TYPE_INTERNAL_ASYNC = 0x01, + SDCA_CLOCK_TYPE_INTERNAL_SYNC = 0x02, + SDCA_CLOCK_TYPE_INTERNAL_SOURCE_SYNC = 0x03, +}; + +/** + * struct sdca_entity_cs - information specific to Clock Source Entities + * @type: Synchronicity of the Clock Source. + * @max_delay: The maximum delay in microseconds before the clock is stable. + */ +struct sdca_entity_cs { + enum sdca_clock_type type; + unsigned int max_delay; +}; + +/** + * enum sdca_pde_power_state - SDCA Power States + * + * SDCA Power State values from SDCA specification v1.0 Section 7.12.4. + */ +enum sdca_pde_power_state { + SDCA_PDE_PS0 = 0x0, + SDCA_PDE_PS1 = 0x1, + SDCA_PDE_PS2 = 0x2, + SDCA_PDE_PS3 = 0x3, + SDCA_PDE_PS4 = 0x4, +}; + +/** + * struct sdca_pde_delay - describes the delay changing between 2 power states + * @from_ps: The power state being exited. + * @to_ps: The power state being entered. + * @us: The delay in microseconds switching between the two states. + */ +struct sdca_pde_delay { + int from_ps; + int to_ps; + unsigned int us; +}; + +/** + * struct sdca_entity_pde - information specific to Power Domain Entities + * @managed: Dynamically allocated array pointing to each Entity + * controlled by this PDE. + * @max_delay: Dynamically allocated array of delays for switching + * between power states. + * @num_managed: Number of Entities controlled by this PDE. + * @num_max_delay: Number of delays specified for state changes. + */ +struct sdca_entity_pde { + struct sdca_entity **managed; + struct sdca_pde_delay *max_delay; + int num_managed; + int num_max_delay; +}; + +/** + * enum sdca_entity_type - SDCA Entity Type codes + * @SDCA_ENTITY_TYPE_ENTITY_0: Entity 0, not actually from the + * specification but useful internally as an Entity structure + * is allocated for Entity 0, to hold Entity 0 controls. + * @SDCA_ENTITY_TYPE_IT: Input Terminal. + * @SDCA_ENTITY_TYPE_OT: Output Terminal. + * @SDCA_ENTITY_TYPE_MU: Mixer Unit. + * @SDCA_ENTITY_TYPE_SU: Selector Unit. + * @SDCA_ENTITY_TYPE_FU: Feature Unit. + * @SDCA_ENTITY_TYPE_XU: Extension Unit. + * @SDCA_ENTITY_TYPE_CS: Clock Source. + * @SDCA_ENTITY_TYPE_CX: Clock selector. + * @SDCA_ENTITY_TYPE_PDE: Power-Domain Entity. + * @SDCA_ENTITY_TYPE_GE: Group Entity. + * @SDCA_ENTITY_TYPE_SPE: Security & Privacy Entity. + * @SDCA_ENTITY_TYPE_CRU: Channel Remapping Unit. + * @SDCA_ENTITY_TYPE_UDMPU: Up-Down Mixer Processing Unit. + * @SDCA_ENTITY_TYPE_MFPU: Multi-Function Processing Unit. + * @SDCA_ENTITY_TYPE_SMPU: Smart Microphone Processing Unit. + * @SDCA_ENTITY_TYPE_SAPU: Smart Amp Processing Unit. + * @SDCA_ENTITY_TYPE_PPU: Posture Processing Unit. + * @SDCA_ENTITY_TYPE_TG: Tone Generator. + * @SDCA_ENTITY_TYPE_HIDE: Human Interface Device Entity. + * + * SDCA Entity Types from SDCA specification v1.0 Section 6.1.2 + * all Entity Types not described are reserved. + */ +enum sdca_entity_type { + SDCA_ENTITY_TYPE_ENTITY_0 = 0x00, + SDCA_ENTITY_TYPE_IT = 0x02, + SDCA_ENTITY_TYPE_OT = 0x03, + SDCA_ENTITY_TYPE_MU = 0x05, + SDCA_ENTITY_TYPE_SU = 0x06, + SDCA_ENTITY_TYPE_FU = 0x07, + SDCA_ENTITY_TYPE_XU = 0x0A, + SDCA_ENTITY_TYPE_CS = 0x0B, + SDCA_ENTITY_TYPE_CX = 0x0C, + SDCA_ENTITY_TYPE_PDE = 0x11, + SDCA_ENTITY_TYPE_GE = 0x12, + SDCA_ENTITY_TYPE_SPE = 0x13, + SDCA_ENTITY_TYPE_CRU = 0x20, + SDCA_ENTITY_TYPE_UDMPU = 0x21, + SDCA_ENTITY_TYPE_MFPU = 0x22, + SDCA_ENTITY_TYPE_SMPU = 0x23, + SDCA_ENTITY_TYPE_SAPU = 0x24, + SDCA_ENTITY_TYPE_PPU = 0x25, + SDCA_ENTITY_TYPE_TG = 0x30, + SDCA_ENTITY_TYPE_HIDE = 0x31, +}; + +/** + * struct sdca_ge_control - control entry in the affected controls list + * @id: Entity ID of the Control affected. + * @sel: Control Selector of the Control affected. + * @cn: Control Number of the Control affected. + * @val: Value written to Control for this Mode. + */ +struct sdca_ge_control { + int id; + int sel; + int cn; + int val; +}; + +/** + * struct sdca_ge_mode - mode entry in the affected controls list + * @controls: Dynamically allocated array of controls written for this Mode. + * @num_controls: Number of controls written in this Mode. + * @val: GE Selector Mode value. + */ +struct sdca_ge_mode { + struct sdca_ge_control *controls; + int num_controls; + int val; +}; + +/** + * struct sdca_entity_ge - information specific to Group Entities + * @kctl: ALSA control pointer that can be used by linked Entities. + * @modes: Dynamically allocated array of Modes and the Controls written + * in each mode. + * @num_modes: Number of Modes. + */ +struct sdca_entity_ge { + struct snd_kcontrol_new *kctl; + struct sdca_ge_mode *modes; + int num_modes; +}; + +/** + * struct sdca_entity_hide - information specific to HIDE Entities + * @num_hidtx_ids: number of HIDTx Report ID + * @num_hidrx_ids: number of HIDRx Report ID + * @hidtx_ids: HIDTx Report ID + * @hidrx_ids: HIDRx Report ID + * @af_number_list: which Audio Function Numbers within this Device are + * sending/receiving the messages in this HIDE + * @hide_reside_function_num: indicating which Audio Function Numbers + * within this Device + * @max_delay: the maximum time in microseconds allowed for the Device + * to change the ownership from Device to Host + */ +struct sdca_entity_hide { + unsigned int *hidtx_ids; + unsigned int *hidrx_ids; + int num_hidtx_ids; + int num_hidrx_ids; + unsigned int af_number_list[SDCA_MAX_FUNCTION_COUNT]; + unsigned int hide_reside_function_num; + unsigned int max_delay; +}; + +/** + * enum sdca_xu_reset_mechanism - SDCA FDL Resets + */ +enum sdca_xu_reset_mechanism { + SDCA_XU_RESET_FUNCTION = 0x0, + SDCA_XU_RESET_DEVICE = 0x1, + SDCA_XU_RESET_BUS = 0x2, +}; + +/** + * struct sdca_entity_xu - information specific to XU Entities + * @max_delay: the maximum time in microseconds allowed for the Device + * to change the ownership from Device to Host + * @reset_mechanism: indicates the type of reset that can be requested + * the end of an FDL. + */ +struct sdca_entity_xu { + unsigned int max_delay; + enum sdca_xu_reset_mechanism reset_mechanism; +}; + +/** + * struct sdca_entity - information for one SDCA Entity + * @label: String such as "OT 12". + * @id: Identifier used for addressing. + * @type: Type code for the Entity. + * @group: Pointer to Group Entity controlling this one, NULL if N/A. + * @sources: Dynamically allocated array pointing to each input Entity + * connected to this Entity. + * @controls: Dynamically allocated array of Controls. + * @num_sources: Number of sources for the Entity. + * @num_controls: Number of Controls for the Entity. + * @iot: Input/Output Terminal specific Entity properties. + * @cs: Clock Source specific Entity properties. + * @pde: Power Domain Entity specific Entity properties. + * @ge: Group Entity specific Entity properties. + * @hide: HIDE Entity specific Entity properties. + * @xu: XU Entity specific Entity properties. + */ +struct sdca_entity { + const char *label; + int id; + enum sdca_entity_type type; + + struct sdca_entity *group; + struct sdca_entity **sources; + struct sdca_control *controls; + int num_sources; + int num_controls; + union { + struct sdca_entity_iot iot; + struct sdca_entity_cs cs; + struct sdca_entity_pde pde; + struct sdca_entity_ge ge; + struct sdca_entity_hide hide; + struct sdca_entity_xu xu; + }; +}; + +/** + * enum sdca_channel_purpose - SDCA Channel Purpose code + * + * Channel Purpose codes as described in the SDCA specification v1.0 + * section 11.4.3. + */ +enum sdca_channel_purpose { + /* Table 210 - Purpose */ + SDCA_CHAN_PURPOSE_GENERIC_AUDIO = 0x01, + SDCA_CHAN_PURPOSE_VOICE = 0x02, + SDCA_CHAN_PURPOSE_SPEECH = 0x03, + SDCA_CHAN_PURPOSE_AMBIENT = 0x04, + SDCA_CHAN_PURPOSE_REFERENCE = 0x05, + SDCA_CHAN_PURPOSE_ULTRASOUND = 0x06, + SDCA_CHAN_PURPOSE_SENSE = 0x08, + SDCA_CHAN_PURPOSE_SILENCE = 0xFE, + SDCA_CHAN_PURPOSE_NON_AUDIO = 0xFF, + /* Table 211 - Amp Sense */ + SDCA_CHAN_PURPOSE_SENSE_V1 = 0x09, + SDCA_CHAN_PURPOSE_SENSE_V2 = 0x0A, + SDCA_CHAN_PURPOSE_SENSE_V12_INTERLEAVED = 0x10, + SDCA_CHAN_PURPOSE_SENSE_V21_INTERLEAVED = 0x11, + SDCA_CHAN_PURPOSE_SENSE_V12_PACKED = 0x12, + SDCA_CHAN_PURPOSE_SENSE_V21_PACKED = 0x13, + SDCA_CHAN_PURPOSE_SENSE_V1212_INTERLEAVED = 0x14, + SDCA_CHAN_PURPOSE_SENSE_V2121_INTERLEAVED = 0x15, + SDCA_CHAN_PURPOSE_SENSE_V1122_INTERLEAVED = 0x16, + SDCA_CHAN_PURPOSE_SENSE_V2211_INTERLEAVED = 0x17, + SDCA_CHAN_PURPOSE_SENSE_V1212_PACKED = 0x18, + SDCA_CHAN_PURPOSE_SENSE_V2121_PACKED = 0x19, + SDCA_CHAN_PURPOSE_SENSE_V1122_PACKED = 0x1A, + SDCA_CHAN_PURPOSE_SENSE_V2211_PACKED = 0x1B, +}; + +/** + * enum sdca_channel_relationship - SDCA Channel Relationship code + * + * Channel Relationship codes as described in the SDCA specification + * v1.0 section 11.4.2. + */ +enum sdca_channel_relationship { + /* Table 206 - Streaming */ + SDCA_CHAN_REL_UNDEFINED = 0x00, + SDCA_CHAN_REL_GENERIC_MONO = 0x01, + SDCA_CHAN_REL_GENERIC_LEFT = 0x02, + SDCA_CHAN_REL_GENERIC_RIGHT = 0x03, + SDCA_CHAN_REL_GENERIC_TOP = 0x48, + SDCA_CHAN_REL_GENERIC_BOTTOM = 0x49, + SDCA_CHAN_REL_CAPTURE_DIRECT = 0x4E, + SDCA_CHAN_REL_RENDER_DIRECT = 0x4F, + SDCA_CHAN_REL_FRONT_LEFT = 0x0B, + SDCA_CHAN_REL_FRONT_RIGHT = 0x0C, + SDCA_CHAN_REL_FRONT_CENTER = 0x0D, + SDCA_CHAN_REL_SIDE_LEFT = 0x12, + SDCA_CHAN_REL_SIDE_RIGHT = 0x13, + SDCA_CHAN_REL_BACK_LEFT = 0x16, + SDCA_CHAN_REL_BACK_RIGHT = 0x17, + SDCA_CHAN_REL_LOW_FREQUENCY_EFFECTS = 0x43, + SDCA_CHAN_REL_SOUNDWIRE_MIC = 0x55, + SDCA_CHAN_REL_SENSE_TRANSDUCER_1 = 0x58, + SDCA_CHAN_REL_SENSE_TRANSDUCER_2 = 0x59, + SDCA_CHAN_REL_SENSE_TRANSDUCER_12 = 0x5A, + SDCA_CHAN_REL_SENSE_TRANSDUCER_21 = 0x5B, + SDCA_CHAN_REL_ECHOREF_NONE = 0x70, + SDCA_CHAN_REL_ECHOREF_1 = 0x71, + SDCA_CHAN_REL_ECHOREF_2 = 0x72, + SDCA_CHAN_REL_ECHOREF_3 = 0x73, + SDCA_CHAN_REL_ECHOREF_4 = 0x74, + SDCA_CHAN_REL_ECHOREF_ALL = 0x75, + SDCA_CHAN_REL_ECHOREF_LFE_ALL = 0x76, + /* Table 207 - Speaker */ + SDCA_CHAN_REL_PRIMARY_TRANSDUCER = 0x50, + SDCA_CHAN_REL_SECONDARY_TRANSDUCER = 0x51, + SDCA_CHAN_REL_TERTIARY_TRANSDUCER = 0x52, + SDCA_CHAN_REL_LOWER_LEFT_ALLTRANSDUCER = 0x60, + SDCA_CHAN_REL_LOWER_RIGHT_ALLTRANSDUCER = 0x61, + SDCA_CHAN_REL_UPPER_LEFT_ALLTRANSDUCER = 0x62, + SDCA_CHAN_REL_UPPER_RIGHT_ALLTRANSDUCER = 0x63, + SDCA_CHAN_REL_LOWER_LEFT_PRIMARY = 0x64, + SDCA_CHAN_REL_LOWER_RIGHT_PRIMARY = 0x65, + SDCA_CHAN_REL_UPPER_LEFT_PRIMARY = 0x66, + SDCA_CHAN_REL_UPPER_RIGHT_PRIMARY = 0x67, + SDCA_CHAN_REL_LOWER_LEFT_SECONDARY = 0x68, + SDCA_CHAN_REL_LOWER_RIGHT_SECONDARY = 0x69, + SDCA_CHAN_REL_UPPER_LEFT_SECONDARY = 0x6A, + SDCA_CHAN_REL_UPPER_RIGHT_SECONDARY = 0x6B, + SDCA_CHAN_REL_LOWER_LEFT_TERTIARY = 0x6C, + SDCA_CHAN_REL_LOWER_RIGHT_TERTIARY = 0x6D, + SDCA_CHAN_REL_UPPER_LEFT_TERTIARY = 0x6E, + SDCA_CHAN_REL_UPPER_RIGHT_TERTIARY = 0x6F, + SDCA_CHAN_REL_DERIVED_LOWER_LEFT_PRIMARY = 0x94, + SDCA_CHAN_REL_DERIVED_LOWER_RIGHT_PRIMARY = 0x95, + SDCA_CHAN_REL_DERIVED_UPPER_LEFT_PRIMARY = 0x96, + SDCA_CHAN_REL_DERIVED_UPPER_RIGHT_PRIMARY = 0x97, + SDCA_CHAN_REL_DERIVED_LOWER_LEFT_SECONDARY = 0x98, + SDCA_CHAN_REL_DERIVED_LOWER_RIGHT_SECONDARY = 0x99, + SDCA_CHAN_REL_DERIVED_UPPER_LEFT_SECONDARY = 0x9A, + SDCA_CHAN_REL_DERIVED_UPPER_RIGHT_SECONDARY = 0x9B, + SDCA_CHAN_REL_DERIVED_LOWER_LEFT_TERTIARY = 0x9C, + SDCA_CHAN_REL_DERIVED_LOWER_RIGHT_TERTIARY = 0x9D, + SDCA_CHAN_REL_DERIVED_UPPER_LEFT_TERTIARY = 0x9E, + SDCA_CHAN_REL_DERIVED_UPPER_RIGHT_TERTIARY = 0x9F, + SDCA_CHAN_REL_DERIVED_MONO_PRIMARY = 0xA0, + SDCA_CHAN_REL_DERIVED_MONO_SECONDARY = 0xAB, + SDCA_CHAN_REL_DERIVED_MONO_TERTIARY = 0xAC, + /* Table 208 - Equipment */ + SDCA_CHAN_REL_EQUIPMENT_LEFT = 0x02, + SDCA_CHAN_REL_EQUIPMENT_RIGHT = 0x03, + SDCA_CHAN_REL_EQUIPMENT_COMBINED = 0x47, + SDCA_CHAN_REL_EQUIPMENT_TOP = 0x48, + SDCA_CHAN_REL_EQUIPMENT_BOTTOM = 0x49, + SDCA_CHAN_REL_EQUIPMENT_TOP_LEFT = 0x4A, + SDCA_CHAN_REL_EQUIPMENT_BOTTOM_LEFT = 0x4B, + SDCA_CHAN_REL_EQUIPMENT_TOP_RIGHT = 0x4C, + SDCA_CHAN_REL_EQUIPMENT_BOTTOM_RIGHT = 0x4D, + SDCA_CHAN_REL_EQUIPMENT_SILENCED_OUTPUT = 0x57, + /* Table 209 - Other */ + SDCA_CHAN_REL_ARRAY = 0x04, + SDCA_CHAN_REL_MIC = 0x53, + SDCA_CHAN_REL_RAW = 0x54, + SDCA_CHAN_REL_SILENCED_MIC = 0x56, + SDCA_CHAN_REL_MULTI_SOURCE_1 = 0x78, + SDCA_CHAN_REL_MULTI_SOURCE_2 = 0x79, + SDCA_CHAN_REL_MULTI_SOURCE_3 = 0x7A, + SDCA_CHAN_REL_MULTI_SOURCE_4 = 0x7B, +}; + +/** + * struct sdca_channel - a single Channel with a Cluster + * @id: Identifier used for addressing. + * @purpose: Indicates the purpose of the Channel, usually to give + * semantic meaning to the audio, eg. voice, ultrasound. + * @relationship: Indicates the relationship of this Channel to others + * in the Cluster, often used to identify the physical position of the + * Channel eg. left. + */ +struct sdca_channel { + int id; + enum sdca_channel_purpose purpose; + enum sdca_channel_relationship relationship; +}; + +/** + * struct sdca_cluster - information about an SDCA Channel Cluster + * @id: Identifier used for addressing. + * @num_channels: Number of Channels within this Cluster. + * @channels: Dynamically allocated array of Channels. + */ +struct sdca_cluster { + int id; + int num_channels; + struct sdca_channel *channels; +}; + +/** + * enum sdca_cluster_range - SDCA Range column definitions for ClusterIndex + */ +enum sdca_cluster_range { + SDCA_CLUSTER_BYTEINDEX = 0, + SDCA_CLUSTER_CLUSTERID = 1, + SDCA_CLUSTER_NCOLS = 2, +}; + +/** + * struct sdca_fdl_file - information about a file from a fileset used in FDL + * @vendor_id: Vendor ID of the file. + * @file_id: File ID of the file. + * @fdl_offset: Offset information for FDL. + */ +struct sdca_fdl_file { + u16 vendor_id; + u32 file_id; + u32 fdl_offset; +}; + +/** + * struct sdca_fdl_set - information about a set of files used in FDL + * @files: Array of files in this FDL set. + * @num_files: Number of files in this FDL set. + * @id: ID of the FDL set. + */ +struct sdca_fdl_set { + struct sdca_fdl_file *files; + int num_files; + u32 id; +}; + +/** + * struct sdca_fdl_data - information about a function's FDL data + * @swft: Pointer to the SoundWire File Table. + * @sets: Array of FDL sets used by this function. + * @num_sets: Number of FDL sets used by this function. + */ +struct sdca_fdl_data { + struct acpi_table_swft *swft; + struct sdca_fdl_set *sets; + int num_sets; +}; + +/** + * struct sdca_function_hid - information about a function's HID descriptors + * @report_desc: HID Report Descriptor for the HID Function + * @desc: HID descriptor for the HID Function + */ +struct sdca_function_hid { + unsigned char *report_desc; + struct hid_descriptor desc; +}; + +/** + * struct sdca_function_data - top-level information for one SDCA function + * @desc: Pointer to short descriptor from initial parsing. + * @init_table: Pointer to a table of initialization writes. + * @entities: Dynamically allocated array of Entities. + * @clusters: Dynamically allocated array of Channel Clusters. + * @num_init_table: Number of initialization writes. + * @num_entities: Number of Entities reported in this Function. + * @num_clusters: Number of Channel Clusters reported in this Function. + * @busy_max_delay: Maximum Function busy delay in microseconds, before an + * error should be reported. + * @reset_max_delay: Maximum Function reset delay in microseconds, before an + * error should be reported. + * @fdl_data: FDL data for this Function, if available. + * @hid: HID data for this Function, if available. + */ +struct sdca_function_data { + struct sdca_function_desc *desc; + + struct sdca_init_write *init_table; + struct sdca_entity *entities; + struct sdca_cluster *clusters; + int num_init_table; + int num_entities; + int num_clusters; + + unsigned int busy_max_delay; + unsigned int reset_max_delay; + + struct sdca_fdl_data fdl_data; + + union { + struct sdca_function_hid hid; + }; +}; + +static inline u32 sdca_range(struct sdca_control_range *range, + unsigned int col, unsigned int row) +{ + return range->data[(row * range->cols) + col]; +} + +static inline u32 sdca_range_search(struct sdca_control_range *range, + int search_col, int value, int result_col) +{ + int i; + + for (i = 0; i < range->rows; i++) { + if (sdca_range(range, search_col, i) == value) + return sdca_range(range, result_col, i); + } + + return 0; +} + +int sdca_parse_function(struct device *dev, struct sdca_function_data *function); + +const char *sdca_find_terminal_name(enum sdca_terminal_type type); + +struct sdca_control *sdca_selector_find_control(struct device *dev, + struct sdca_entity *entity, + const int sel); +struct sdca_control_range *sdca_control_find_range(struct device *dev, + struct sdca_entity *entity, + struct sdca_control *control, + int cols, int rows); +struct sdca_control_range *sdca_selector_find_range(struct device *dev, + struct sdca_entity *entity, + int sel, int cols, int rows); +struct sdca_cluster *sdca_id_find_cluster(struct device *dev, + struct sdca_function_data *function, + const int id); +struct sdca_entity *sdca_find_entity_by_label(struct sdca_function_data *function, + const char *entity_label); + +#endif diff --git a/include/sound/sdca_hid.h b/include/sound/sdca_hid.h new file mode 100644 index 000000000..848081df3 --- /dev/null +++ b/include/sound/sdca_hid.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + */ + +#ifndef __SDCA_HID_H__ +#define __SDCA_HID_H__ + +struct device; +struct sdw_slave; + +struct sdca_entity; +struct sdca_interrupt; + +#if IS_ENABLED(CONFIG_SND_SOC_SDCA_HID) + +int sdca_add_hid_device(struct sdca_interrupt *interrupt); +void sdca_destroy_hid_device(struct sdca_interrupt *interrupt); +int sdca_hid_process_report(struct sdca_interrupt *interrupt); + +#else + +static inline int sdca_add_hid_device(struct sdca_interrupt *interrupt) +{ + return 0; +} + +static inline void sdca_destroy_hid_device(struct sdca_interrupt *interrupt) +{ +} + +static inline int sdca_hid_process_report(struct sdca_interrupt *interrupt) +{ + return 0; +} + +#endif + +#endif /* __SDCA_HID_H__ */ diff --git a/include/sound/sdca_interrupts.h b/include/sound/sdca_interrupts.h new file mode 100644 index 000000000..3b30146e2 --- /dev/null +++ b/include/sound/sdca_interrupts.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright (C) 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __SDCA_INTERRUPTS_H__ +#define __SDCA_INTERRUPTS_H__ + +#include +#include +#include + +struct device; +struct snd_soc_component; +struct sdca_function_data; + +#define SDCA_MAX_INTERRUPTS 31 /* the last bit is reserved for future extensions */ + +/** + * struct sdca_interrupt - contains information about a single SDCA interrupt + * @name: The name of the interrupt. + * @dev: Pointer to the Function device. + * @device_regmap: Pointer to the IRQ regmap. + * @function_regmap: Pointer to the SDCA Function regmap. + * @component: Pointer to the ASoC component owns the interrupt. + * @function: Pointer to the Function that the interrupt is associated with. + * @entity: Pointer to the Entity that the interrupt is associated with. + * @control: Pointer to the Control that the interrupt is associated with. + * @handler: Handler function to be called for the IRQ. + * @priv: Pointer to private data for use by the handler. + * @free_priv: Pointer to a function that can be used to free the priv data. + * @irq: IRQ number allocated to this interrupt, also used internally to track + * the IRQ being assigned. + * @early_request: Flag to indicate this IRQ was requested at bus probe time. + */ +struct sdca_interrupt { + const char *name; + + struct device *dev; + struct regmap *device_regmap; + struct regmap *function_regmap; + struct snd_soc_component *component; + struct sdca_function_data *function; + struct sdca_entity *entity; + struct sdca_control *control; + irq_handler_t handler; + + void *priv; + void (*free_priv)(struct sdca_interrupt *interrupt); + + int irq; + bool early_request; +}; + +/** + * struct sdca_interrupt_info - contains top-level SDCA interrupt information + * @irq_chip: regmap irq chip structure. + * @irq_data: regmap irq chip data structure. + * @irqs: Array of data for each individual IRQ. + * @irq_lock: Protects access to the list of sdca_interrupt structures. + */ +struct sdca_interrupt_info { + struct regmap_irq_chip irq_chip; + struct regmap_irq_chip_data *irq_data; + + struct sdca_interrupt irqs[SDCA_MAX_INTERRUPTS]; + + struct mutex irq_lock; /* Protect irqs list across functions */ +}; + +int sdca_irq_request(struct device *dev, struct sdca_interrupt_info *interrupt_info, + int sdca_irq, const char *name, irq_handler_t handler, + void *data); +void sdca_irq_free(struct device *dev, struct sdca_interrupt_info *interrupt_info, + int sdca_irq, const char *name, void *data); +int sdca_irq_data_populate(struct device *dev, struct regmap *function_regmap, + struct snd_soc_component *component, + struct sdca_function_data *function, + struct sdca_entity *entity, + struct sdca_control *control, + struct sdca_interrupt *interrupt); +int sdca_irq_populate_early(struct device *dev, struct regmap *function_regmap, + struct sdca_function_data *function, + struct sdca_interrupt_info *info); +int sdca_irq_populate(struct sdca_function_data *function, + struct snd_soc_component *component, + struct sdca_interrupt_info *info); +void sdca_irq_cleanup(struct device *dev, + struct sdca_function_data *function, + struct sdca_interrupt_info *info); +void sdca_irq_cleanup_late(struct device *dev, + struct sdca_function_data *function, + struct sdca_interrupt_info *info); + +struct sdca_interrupt_info *devm_sdca_irq_allocate(struct device *dev, + struct regmap *regmap, int irq); + +void sdca_irq_enable_early(struct sdca_function_data *function, + struct sdca_interrupt_info *info); +void sdca_irq_enable(struct sdca_function_data *function, + struct sdca_interrupt_info *info); +void sdca_irq_disable(struct sdca_function_data *function, + struct sdca_interrupt_info *info); + +#endif diff --git a/include/sound/sdca_jack.h b/include/sound/sdca_jack.h new file mode 100644 index 000000000..871ba2d81 --- /dev/null +++ b/include/sound/sdca_jack.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright (C) 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __SDCA_JACK_H__ +#define __SDCA_JACK_H__ + +struct sdca_interrupt; +struct snd_kcontrol; +struct snd_soc_jack; + +/** + * struct jack_state - Jack state structure to keep data between interrupts + * @kctl: Pointer to the ALSA control attached to this jack + * @jack: Pointer to the ASoC jack struct for this jack + * @mask: Possible reported jack status bits for this jack + */ +struct jack_state { + struct snd_kcontrol *kctl; + struct snd_soc_jack *jack; + + unsigned int mask; +}; + +int sdca_jack_alloc_state(struct sdca_interrupt *interrupt); +int sdca_jack_init_state(struct sdca_interrupt *interrupt); +void sdca_jack_free_state(struct sdca_interrupt *interrupt); + +int sdca_jack_process(struct sdca_interrupt *interrupt); +int sdca_jack_set_jack(struct sdca_interrupt_info *info, struct snd_soc_jack *jack); +int sdca_jack_report(struct sdca_interrupt *interrupt); + +#endif // __SDCA_JACK_H__ diff --git a/include/sound/sdca_regmap.h b/include/sound/sdca_regmap.h new file mode 100644 index 000000000..792540a53 --- /dev/null +++ b/include/sound/sdca_regmap.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright (C) 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __SDCA_REGMAP_H__ +#define __SDCA_REGMAP_H__ + +struct device; +struct sdca_function_data; +struct regmap; +struct reg_default; + +bool sdca_regmap_readable(struct sdca_function_data *function, unsigned int reg); +bool sdca_regmap_writeable(struct sdca_function_data *function, unsigned int reg); +bool sdca_regmap_volatile(struct sdca_function_data *function, unsigned int reg); +bool sdca_regmap_deferrable(struct sdca_function_data *function, unsigned int reg); +int sdca_regmap_mbq_size(struct sdca_function_data *function, unsigned int reg); + +int sdca_regmap_count_constants(struct device *dev, struct sdca_function_data *function); +int sdca_regmap_populate_constants(struct device *dev, struct sdca_function_data *function, + struct reg_default *consts); + +int sdca_regmap_write_defaults(struct device *dev, struct regmap *regmap, + struct sdca_function_data *function); +int sdca_regmap_write_init(struct device *dev, struct regmap *regmap, + struct sdca_function_data *function); + +#endif // __SDCA_REGMAP_H__ diff --git a/include/sound/sdca_ump.h b/include/sound/sdca_ump.h new file mode 100644 index 000000000..f54f9d48c --- /dev/null +++ b/include/sound/sdca_ump.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The MIPI SDCA specification is available for public downloads at + * https://www.mipi.org/mipi-sdca-v1-0-download + * + * Copyright (C) 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef __SDCA_UMP_H__ +#define __SDCA_UMP_H__ + +struct regmap; +struct sdca_control; +struct sdca_entity; +struct sdca_function_data; +struct snd_soc_component; +struct delayed_work; + +int sdca_ump_get_owner_host(struct device *dev, + struct regmap *function_regmap, + struct sdca_function_data *function, + struct sdca_entity *entity, + struct sdca_control *control); +int sdca_ump_set_owner_device(struct device *dev, + struct regmap *function_regmap, + struct sdca_function_data *function, + struct sdca_entity *entity, + struct sdca_control *control); +int sdca_ump_read_message(struct device *dev, + struct regmap *device_regmap, + struct regmap *function_regmap, + struct sdca_function_data *function, + struct sdca_entity *entity, + unsigned int offset_sel, unsigned int length_sel, + void **msg); +int sdca_ump_write_message(struct device *dev, + struct regmap *device_regmap, + struct regmap *function_regmap, + struct sdca_function_data *function, + struct sdca_entity *entity, + unsigned int offset_sel, unsigned int msg_offset, + unsigned int length_sel, + void *msg, int msg_len); + +void sdca_ump_cancel_timeout(struct delayed_work *work); +void sdca_ump_schedule_timeout(struct delayed_work *work, + unsigned int timeout_us); + +#endif // __SDCA_UMP_H__ diff --git a/include/sound/sdw.h b/include/sound/sdw.h new file mode 100644 index 000000000..6dcdb3228 --- /dev/null +++ b/include/sound/sdw.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/sdw.h -- SoundWire helpers for ALSA/ASoC + * + * Copyright (c) 2022 Cirrus Logic Inc. + * + * Author: Charles Keepax + */ + +#include +#include +#include +#include + +#ifndef __INCLUDE_SOUND_SDW_H +#define __INCLUDE_SOUND_SDW_H + +/** + * snd_sdw_params_to_config() - Conversion from hw_params to SoundWire config + * + * @substream: Pointer to the PCM substream structure + * @params: Pointer to the hardware params structure + * @stream_config: Stream configuration for the SoundWire audio stream + * @port_config: Port configuration for the SoundWire audio stream + * + * This function provides a basic conversion from the hw_params structure to + * SoundWire configuration structures. The user will at a minimum need to also + * set the port number in the port config, but may also override more of the + * setup, or in the case of a complex user, not use this helper at all and + * open-code everything. + */ +static inline void snd_sdw_params_to_config(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct sdw_stream_config *stream_config, + struct sdw_port_config *port_config) +{ + stream_config->frame_rate = params_rate(params); + stream_config->ch_count = params_channels(params); + stream_config->bps = snd_pcm_format_width(params_format(params)); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + stream_config->direction = SDW_DATA_DIR_RX; + else + stream_config->direction = SDW_DATA_DIR_TX; + + port_config->ch_mask = GENMASK(stream_config->ch_count - 1, 0); +} + +#endif diff --git a/include/sound/seq_device.h b/include/sound/seq_device.h new file mode 100644 index 000000000..3137d4c5f --- /dev/null +++ b/include/sound/seq_device.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_DEVICE_H +#define __SOUND_SEQ_DEVICE_H + +/* + * ALSA sequencer device management + * Copyright (c) 1999 by Takashi Iwai + */ + +/* + * registered device information + */ + +struct snd_seq_device { + /* device info */ + struct snd_card *card; /* sound card */ + int device; /* device number */ + const char *id; /* driver id */ + char name[80]; /* device name */ + int argsize; /* size of the argument */ + void *driver_data; /* private data for driver */ + void *private_data; /* private data for the caller */ + void (*private_free)(struct snd_seq_device *device); + struct device dev; + unsigned char args[]; /* driver-specific argument */ +}; + +#define to_seq_dev(_dev) \ + container_of(_dev, struct snd_seq_device, dev) + +/* sequencer driver */ + +/* driver operators + * probe: + * Initialize the device with given parameters. + * Typically, + * 1. call snd_hwdep_new + * 2. allocate private data and initialize it + * 3. call snd_hwdep_register + * 4. store the instance to dev->driver_data pointer. + * + * remove: + * Release the private data. + * Typically, call snd_device_free(dev->card, dev->driver_data) + */ +struct snd_seq_driver { + int (*probe)(struct snd_seq_device *dev); + void (*remove)(struct snd_seq_device *dev); + struct device_driver driver; + char *id; + int argsize; +}; + +#define to_seq_drv(_drv) \ + container_of(_drv, struct snd_seq_driver, driver) + +/* + * prototypes + */ +#ifdef CONFIG_MODULES +void snd_seq_device_load_drivers(void); +#else +#define snd_seq_device_load_drivers() +#endif +int snd_seq_device_new(struct snd_card *card, int device, const char *id, + int argsize, struct snd_seq_device **result); + +#define SNDRV_SEQ_DEVICE_ARGPTR(dev) ((void *)(dev)->args) + +int __must_check __snd_seq_driver_register(struct snd_seq_driver *drv, + struct module *mod); +#define snd_seq_driver_register(drv) \ + __snd_seq_driver_register(drv, THIS_MODULE) +void snd_seq_driver_unregister(struct snd_seq_driver *drv); + +#define module_snd_seq_driver(drv) \ + module_driver(drv, snd_seq_driver_register, snd_seq_driver_unregister) + +/* + * id strings for generic devices + */ +#define SNDRV_SEQ_DEV_ID_MIDISYNTH "seq-midi" +#define SNDRV_SEQ_DEV_ID_OPL3 "opl3-synth" +#define SNDRV_SEQ_DEV_ID_UMP "seq-ump-client" + +#endif /* __SOUND_SEQ_DEVICE_H */ diff --git a/include/sound/seq_kernel.h b/include/sound/seq_kernel.h new file mode 100644 index 000000000..00c32eed2 --- /dev/null +++ b/include/sound/seq_kernel.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_KERNEL_H +#define __SOUND_SEQ_KERNEL_H + +/* + * Main kernel header file for the ALSA sequencer + * Copyright (c) 1998 by Frank van de Pol + */ +#include +#include + +typedef struct snd_seq_real_time snd_seq_real_time_t; +typedef union snd_seq_timestamp snd_seq_timestamp_t; + +/* maximum number of queues */ +#define SNDRV_SEQ_MAX_QUEUES 32 + +/* max number of concurrent clients */ +#define SNDRV_SEQ_MAX_CLIENTS 192 + +/* max number of concurrent ports */ +#define SNDRV_SEQ_MAX_PORTS 254 + +/* max number of events in memory pool */ +#define SNDRV_SEQ_MAX_EVENTS 2000 + +/* default number of events in memory pool */ +#define SNDRV_SEQ_DEFAULT_EVENTS 500 + +/* max number of events in memory pool for one client (outqueue) */ +#define SNDRV_SEQ_MAX_CLIENT_EVENTS 2000 + +/* default number of events in memory pool for one client (outqueue) */ +#define SNDRV_SEQ_DEFAULT_CLIENT_EVENTS 200 + +/* max delivery path length */ +/* NOTE: this shouldn't be greater than MAX_LOCKDEP_SUBCLASSES */ +#define SNDRV_SEQ_MAX_HOPS 8 + +/* max size of event size */ +#define SNDRV_SEQ_MAX_EVENT_LEN 0x3fffffff + +/* call-backs for kernel port */ +struct snd_seq_port_callback { + struct module *owner; + void *private_data; + int (*subscribe)(void *private_data, struct snd_seq_port_subscribe *info); + int (*unsubscribe)(void *private_data, struct snd_seq_port_subscribe *info); + int (*use)(void *private_data, struct snd_seq_port_subscribe *info); + int (*unuse)(void *private_data, struct snd_seq_port_subscribe *info); + int (*event_input)(struct snd_seq_event *ev, int direct, void *private_data, int atomic, int hop); + void (*private_free)(void *private_data); + /*...*/ +}; + +/* interface for kernel client */ +__printf(3, 4) +int snd_seq_create_kernel_client(struct snd_card *card, int client_index, + const char *name_fmt, ...); +int snd_seq_delete_kernel_client(int client); +int snd_seq_kernel_client_enqueue(int client, struct snd_seq_event *ev, + struct file *file, bool blocking); +int snd_seq_kernel_client_dispatch(int client, struct snd_seq_event *ev, int atomic, int hop); +int snd_seq_kernel_client_ctl(int client, unsigned int cmd, void *arg); + +#define SNDRV_SEQ_EXT_MASK 0xc0000000 +#define SNDRV_SEQ_EXT_USRPTR 0x80000000 +#define SNDRV_SEQ_EXT_CHAINED 0x40000000 + +typedef int (*snd_seq_dump_func_t)(void *ptr, void *buf, int count); +int snd_seq_expand_var_event(const struct snd_seq_event *event, int count, char *buf, + int in_kernel, int size_aligned); +int snd_seq_expand_var_event_at(const struct snd_seq_event *event, int count, + char *buf, int offset); +int snd_seq_dump_var_event(const struct snd_seq_event *event, + snd_seq_dump_func_t func, void *private_data); + +/* size of the event packet; it can be greater than snd_seq_event size */ +static inline size_t snd_seq_event_packet_size(struct snd_seq_event *ev) +{ + if (snd_seq_ev_is_ump(ev)) + return sizeof(struct snd_seq_ump_event); + return sizeof(struct snd_seq_event); +} + +/* interface for OSS emulation */ +int snd_seq_set_queue_tempo(int client, struct snd_seq_queue_tempo *tempo); + +/* port attach/detach */ +int snd_seq_event_port_attach(int client, struct snd_seq_port_callback *pcbp, + int cap, int type, int midi_channels, int midi_voices, char *portname); +int snd_seq_event_port_detach(int client, int port); + +#ifdef CONFIG_MODULES +void snd_seq_autoload_init(void); +void snd_seq_autoload_exit(void); +#else +#define snd_seq_autoload_init() +#define snd_seq_autoload_exit() +#endif + +#endif /* __SOUND_SEQ_KERNEL_H */ diff --git a/include/sound/seq_midi_emul.h b/include/sound/seq_midi_emul.h new file mode 100644 index 000000000..afc765437 --- /dev/null +++ b/include/sound/seq_midi_emul.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_MIDI_EMUL_H +#define __SOUND_SEQ_MIDI_EMUL_H + +/* + * Midi channel definition for optional channel management. + * + * Copyright (C) 1999 Steve Ratcliffe + */ + +#include + +/* + * This structure is used to keep track of the current state on each + * channel. All drivers for hardware that does not understand midi + * directly will probably need to use this structure. + */ +struct snd_midi_channel { + void *private; /* A back pointer to driver data */ + int number; /* The channel number */ + int client; /* The client associated with this channel */ + int port; /* The port associated with this channel */ + + unsigned char midi_mode; /* GM, GS, XG etc */ + unsigned int + drum_channel:1, /* Drum channel */ + param_type:1 /* RPN/NRPN */ + ; + + unsigned char midi_aftertouch; /* Aftertouch (key pressure) */ + unsigned char midi_pressure; /* Channel pressure */ + unsigned char midi_program; /* Instrument number */ + short midi_pitchbend; /* Pitch bend amount */ + + unsigned char control[128]; /* Current value of all controls */ + unsigned char note[128]; /* Current status for all notes */ + + short gm_rpn_pitch_bend_range; /* Pitch bend range */ + short gm_rpn_fine_tuning; /* Master fine tuning */ + short gm_rpn_coarse_tuning; /* Master coarse tuning */ + +}; + +/* + * A structure that represets a set of channels bound to a port. There + * would usually be 16 channels per port. But fewer could be used for + * particular cases. + * The channel set consists of information describing the client and + * port for this midi synth and an array of snd_midi_channel structures. + * A driver that had no need for snd_midi_channel could still use the + * channel set type if it wished with the channel array null. + */ +struct snd_midi_channel_set { + void *private_data; /* Driver data */ + int client; /* Client for this port */ + int port; /* The port number */ + + unsigned char midi_mode; /* MIDI operating mode */ + unsigned char gs_master_volume; /* SYSEX master volume: 0-127 */ + unsigned char gs_chorus_mode; + unsigned char gs_reverb_mode; + + int max_channels; /* Size of the channels array */ + struct snd_midi_channel channels[] __counted_by(max_channels); + +}; + +struct snd_midi_op { + void (*note_on)(void *private_data, int note, int vel, struct snd_midi_channel *chan); + void (*note_off)(void *private_data,int note, int vel, struct snd_midi_channel *chan); /* release note */ + void (*key_press)(void *private_data, int note, int vel, struct snd_midi_channel *chan); + void (*note_terminate)(void *private_data, int note, struct snd_midi_channel *chan); /* terminate note immediately */ + void (*control)(void *private_data, int type, struct snd_midi_channel *chan); + void (*nrpn)(void *private_data, struct snd_midi_channel *chan, + struct snd_midi_channel_set *chset); + void (*sysex)(void *private_data, unsigned char *buf, int len, int parsed, + struct snd_midi_channel_set *chset); +}; + +/* + * These defines are used so that pitchbend, aftertouch etc, can be + * distinguished from controller values. + */ +/* 0-127 controller values */ +#define MIDI_CTL_PITCHBEND 0x80 +#define MIDI_CTL_AFTERTOUCH 0x81 +#define MIDI_CTL_CHAN_PRESSURE 0x82 + +/* + * These names exist to allow symbolic access to the controls array. + * The usage is eg: chan->gm_bank_select. Another implementation would + * be really have these members in the struct, and not the array. + */ +#define gm_bank_select control[0] +#define gm_modulation control[1] +#define gm_breath control[2] +#define gm_foot_pedal control[4] +#define gm_portamento_time control[5] +#define gm_data_entry control[6] +#define gm_volume control[7] +#define gm_balance control[8] +#define gm_pan control[10] +#define gm_expression control[11] +#define gm_effect_control1 control[12] +#define gm_effect_control2 control[13] +#define gm_slider1 control[16] +#define gm_slider2 control[17] +#define gm_slider3 control[18] +#define gm_slider4 control[19] + +#define gm_bank_select_lsb control[32] +#define gm_modulation_wheel_lsb control[33] +#define gm_breath_lsb control[34] +#define gm_foot_pedal_lsb control[36] +#define gm_portamento_time_lsb control[37] +#define gm_data_entry_lsb control[38] +#define gm_volume_lsb control[39] +#define gm_balance_lsb control[40] +#define gm_pan_lsb control[42] +#define gm_expression_lsb control[43] +#define gm_effect_control1_lsb control[44] +#define gm_effect_control2_lsb control[45] + +#define gm_sustain control[MIDI_CTL_SUSTAIN] +#define gm_hold gm_sustain +#define gm_portamento control[MIDI_CTL_PORTAMENTO] +#define gm_sostenuto control[MIDI_CTL_SOSTENUTO] + +/* + * These macros give the complete value of the controls that consist + * of coarse and fine pairs. Of course the fine controls are seldom used + * but there is no harm in being complete. + */ +#define SNDRV_GM_BANK_SELECT(cp) (((cp)->control[0]<<7)|((cp)->control[32])) +#define SNDRV_GM_MODULATION_WHEEL(cp) (((cp)->control[1]<<7)|((cp)->control[33])) +#define SNDRV_GM_BREATH(cp) (((cp)->control[2]<<7)|((cp)->control[34])) +#define SNDRV_GM_FOOT_PEDAL(cp) (((cp)->control[4]<<7)|((cp)->control[36])) +#define SNDRV_GM_PORTAMENTO_TIME(cp) (((cp)->control[5]<<7)|((cp)->control[37])) +#define SNDRV_GM_DATA_ENTRY(cp) (((cp)->control[6]<<7)|((cp)->control[38])) +#define SNDRV_GM_VOLUME(cp) (((cp)->control[7]<<7)|((cp)->control[39])) +#define SNDRV_GM_BALANCE(cp) (((cp)->control[8]<<7)|((cp)->control[40])) +#define SNDRV_GM_PAN(cp) (((cp)->control[10]<<7)|((cp)->control[42])) +#define SNDRV_GM_EXPRESSION(cp) (((cp)->control[11]<<7)|((cp)->control[43])) + + +/* MIDI mode */ +#define SNDRV_MIDI_MODE_NONE 0 /* Generic midi */ +#define SNDRV_MIDI_MODE_GM 1 +#define SNDRV_MIDI_MODE_GS 2 +#define SNDRV_MIDI_MODE_XG 3 +#define SNDRV_MIDI_MODE_MT32 4 + +/* MIDI note state */ +#define SNDRV_MIDI_NOTE_OFF 0x00 +#define SNDRV_MIDI_NOTE_ON 0x01 +#define SNDRV_MIDI_NOTE_RELEASED 0x02 +#define SNDRV_MIDI_NOTE_SOSTENUTO 0x04 + +#define SNDRV_MIDI_PARAM_TYPE_REGISTERED 0 +#define SNDRV_MIDI_PARAM_TYPE_NONREGISTERED 1 + +/* SYSEX parse flag */ +enum { + SNDRV_MIDI_SYSEX_NOT_PARSED = 0, + SNDRV_MIDI_SYSEX_GM_ON, + SNDRV_MIDI_SYSEX_GS_ON, + SNDRV_MIDI_SYSEX_GS_RESET, + SNDRV_MIDI_SYSEX_GS_CHORUS_MODE, + SNDRV_MIDI_SYSEX_GS_REVERB_MODE, + SNDRV_MIDI_SYSEX_GS_MASTER_VOLUME, + SNDRV_MIDI_SYSEX_GS_PROGRAM, + SNDRV_MIDI_SYSEX_GS_DRUM_CHANNEL, + SNDRV_MIDI_SYSEX_XG_ON, +}; + +/* Prototypes for midi_process.c */ +void snd_midi_process_event(const struct snd_midi_op *ops, + struct snd_seq_event *ev, + struct snd_midi_channel_set *chanset); +void snd_midi_channel_set_clear(struct snd_midi_channel_set *chset); +struct snd_midi_channel_set *snd_midi_channel_alloc_set(int n); +void snd_midi_channel_free_set(struct snd_midi_channel_set *chset); + +#endif /* __SOUND_SEQ_MIDI_EMUL_H */ diff --git a/include/sound/seq_midi_event.h b/include/sound/seq_midi_event.h new file mode 100644 index 000000000..3b5d0d7e4 --- /dev/null +++ b/include/sound/seq_midi_event.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_MIDI_EVENT_H +#define __SOUND_SEQ_MIDI_EVENT_H + +/* + * MIDI byte <-> sequencer event coder + * + * Copyright (C) 1998,99 Takashi Iwai , + * Jaroslav Kysela + */ + +#include + +#define MAX_MIDI_EVENT_BUF 256 + +/* midi status */ +struct snd_midi_event { + int qlen; /* queue length */ + int read; /* chars read */ + int type; /* current event type */ + unsigned char lastcmd; /* last command (for MIDI state handling) */ + unsigned char nostat; /* no state flag */ + int bufsize; /* allocated buffer size */ + unsigned char *buf; /* input buffer */ + spinlock_t lock; +}; + +int snd_midi_event_new(int bufsize, struct snd_midi_event **rdev); +void snd_midi_event_free(struct snd_midi_event *dev); +void snd_midi_event_reset_encode(struct snd_midi_event *dev); +void snd_midi_event_reset_decode(struct snd_midi_event *dev); +void snd_midi_event_no_status(struct snd_midi_event *dev, int on); +bool snd_midi_event_encode_byte(struct snd_midi_event *dev, unsigned char c, + struct snd_seq_event *ev); +/* decode from event to bytes - return number of written bytes if success */ +long snd_midi_event_decode(struct snd_midi_event *dev, unsigned char *buf, long count, + struct snd_seq_event *ev); + +#endif /* __SOUND_SEQ_MIDI_EVENT_H */ diff --git a/include/sound/seq_oss.h b/include/sound/seq_oss.h new file mode 100644 index 000000000..7bf10a0fa --- /dev/null +++ b/include/sound/seq_oss.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_OSS_H +#define __SOUND_SEQ_OSS_H + +/* + * OSS compatible sequencer driver + * + * Copyright (C) 1998,99 Takashi Iwai + */ + +#include +#include + +/* + * argument structure for synthesizer operations + */ +struct snd_seq_oss_arg { + /* given by OSS sequencer */ + int app_index; /* application unique index */ + int file_mode; /* file mode - see below */ + int seq_mode; /* sequencer mode - see below */ + + /* following must be initialized in open callback */ + struct snd_seq_addr addr; /* opened port address */ + void *private_data; /* private data for lowlevel drivers */ + + /* note-on event passing mode: initially given by OSS seq, + * but configurable by drivers - see below + */ + int event_passing; +}; + + +/* + * synthesizer operation callbacks + */ +struct snd_seq_oss_callback { + struct module *owner; + int (*open)(struct snd_seq_oss_arg *p, void *closure); + int (*close)(struct snd_seq_oss_arg *p); + int (*ioctl)(struct snd_seq_oss_arg *p, unsigned int cmd, unsigned long arg); + int (*load_patch)(struct snd_seq_oss_arg *p, int format, const char __user *buf, int offs, int count); + int (*reset)(struct snd_seq_oss_arg *p); + int (*raw_event)(struct snd_seq_oss_arg *p, unsigned char *data); +}; + +/* flag: file_mode */ +#define SNDRV_SEQ_OSS_FILE_ACMODE 3 +#define SNDRV_SEQ_OSS_FILE_READ 1 +#define SNDRV_SEQ_OSS_FILE_WRITE 2 +#define SNDRV_SEQ_OSS_FILE_NONBLOCK 4 + +/* flag: seq_mode */ +#define SNDRV_SEQ_OSS_MODE_SYNTH 0 +#define SNDRV_SEQ_OSS_MODE_MUSIC 1 + +/* flag: event_passing */ +#define SNDRV_SEQ_OSS_PROCESS_EVENTS 0 /* key == 255 is processed as velocity change */ +#define SNDRV_SEQ_OSS_PASS_EVENTS 1 /* pass all events to callback */ +#define SNDRV_SEQ_OSS_PROCESS_KEYPRESS 2 /* key >= 128 will be processed as key-pressure */ + +/* default control rate: fixed */ +#define SNDRV_SEQ_OSS_CTRLRATE 100 + +/* default max queue length: configurable by module option */ +#define SNDRV_SEQ_OSS_MAX_QLEN 1024 + + +/* + * data pointer to snd_seq_register_device + */ +struct snd_seq_oss_reg { + int type; + int subtype; + int nvoices; + struct snd_seq_oss_callback oper; + void *private_data; +}; + +/* device id */ +#define SNDRV_SEQ_DEV_ID_OSS "seq-oss" + +#endif /* __SOUND_SEQ_OSS_H */ diff --git a/include/sound/seq_oss_legacy.h b/include/sound/seq_oss_legacy.h new file mode 100644 index 000000000..6cf2d7c0f --- /dev/null +++ b/include/sound/seq_oss_legacy.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_OSS_LEGACY_H +#define __SOUND_SEQ_OSS_LEGACY_H + +/* + * OSS compatible macro definitions + * + * Copyright (C) 2000 Abramo Bagnara + */ + +#include + +#ifndef SAMPLE_TYPE_AWE32 +#define SAMPLE_TYPE_AWE32 0x20 +#endif + +#endif /* __SOUND_SEQ_OSS_LEGACY_H */ + diff --git a/include/sound/seq_virmidi.h b/include/sound/seq_virmidi.h new file mode 100644 index 000000000..359cb3633 --- /dev/null +++ b/include/sound/seq_virmidi.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_VIRMIDI_H +#define __SOUND_SEQ_VIRMIDI_H + +/* + * Virtual Raw MIDI client on Sequencer + * Copyright (c) 2000 by Takashi Iwai , + * Jaroslav Kysela + */ + +#include +#include + +/* + * device file instance: + * This instance is created at each time the midi device file is + * opened. Each instance has its own input buffer and MIDI parser + * (buffer), and is associated with the device instance. + */ +struct snd_virmidi { + struct list_head list; + int seq_mode; + int client; + int port; + bool trigger; + struct snd_midi_event *parser; + struct snd_seq_event event; + struct snd_virmidi_dev *rdev; + struct snd_rawmidi_substream *substream; + struct work_struct output_work; +}; + +#define SNDRV_VIRMIDI_SUBSCRIBE (1<<0) +#define SNDRV_VIRMIDI_USE (1<<1) + +/* + * device record: + * Each virtual midi device has one device instance. It contains + * common information and the linked-list of opened files, + */ +struct snd_virmidi_dev { + struct snd_card *card; /* associated card */ + struct snd_rawmidi *rmidi; /* rawmidi device */ + int seq_mode; /* SNDRV_VIRMIDI_XXX */ + int device; /* sequencer device */ + int client; /* created/attached client */ + int port; /* created/attached port */ + unsigned int flags; /* SNDRV_VIRMIDI_* */ + struct rw_semaphore filelist_sem; + struct list_head filelist; +}; + +/* sequencer mode: + * ATTACH = input/output events from midi device are routed to the + * attached sequencer port. sequencer port is not created + * by virmidi itself. + * the input to rawmidi must be processed by passing the + * incoming events via snd_virmidi_receive() + * DISPATCH = input/output events are routed to subscribers. + * sequencer port is created in virmidi. + */ +#define SNDRV_VIRMIDI_SEQ_NONE 0 +#define SNDRV_VIRMIDI_SEQ_ATTACH 1 +#define SNDRV_VIRMIDI_SEQ_DISPATCH 2 + +int snd_virmidi_new(struct snd_card *card, int device, struct snd_rawmidi **rrmidi); + +#endif /* __SOUND_SEQ_VIRMIDI */ diff --git a/include/sound/sh_dac_audio.h b/include/sound/sh_dac_audio.h new file mode 100644 index 000000000..54f373e2a --- /dev/null +++ b/include/sound/sh_dac_audio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SH_DAC specific configuration, for the dac_audio platform_device + * + * Copyright (C) 2009 Rafael Ignacio Zurita + */ + +#ifndef __INCLUDE_SH_DAC_AUDIO_H +#define __INCLUDE_SH_DAC_AUDIO_H + +struct dac_audio_pdata { + int buffer_size; + int channel; + void (*start)(struct dac_audio_pdata *pd); + void (*stop)(struct dac_audio_pdata *pd); +}; + +#endif /* __INCLUDE_SH_DAC_AUDIO_H */ diff --git a/include/sound/sh_fsi.h b/include/sound/sh_fsi.h new file mode 100644 index 000000000..89eafe23e --- /dev/null +++ b/include/sound/sh_fsi.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Fifo-attached Serial Interface (FSI) support for SH7724 + * + * Copyright (C) 2009 Renesas Solutions Corp. + * Kuninori Morimoto + */ +#ifndef __SOUND_FSI_H +#define __SOUND_FSI_H + +#include +#include + +/* + * flags + */ +#define SH_FSI_FMT_SPDIF (1 << 0) /* spdif for HDMI */ +#define SH_FSI_ENABLE_STREAM_MODE (1 << 1) /* for 16bit data */ +#define SH_FSI_CLK_CPG (1 << 2) /* FSIxCK + FSI-DIV */ + +struct sh_fsi_port_info { + unsigned long flags; + int tx_id; + int rx_id; +}; + +struct sh_fsi_platform_info { + struct sh_fsi_port_info port_a; + struct sh_fsi_port_info port_b; +}; + +#endif /* __SOUND_FSI_H */ diff --git a/include/sound/simple_card.h b/include/sound/simple_card.h new file mode 100644 index 000000000..2e999916d --- /dev/null +++ b/include/sound/simple_card.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * ASoC simple sound card support + * + * Copyright (C) 2012 Renesas Solutions Corp. + * Kuninori Morimoto + */ + +#ifndef __SIMPLE_CARD_H +#define __SIMPLE_CARD_H + +#include +#include + +struct simple_util_info { + const char *name; + const char *card; + const char *codec; + const char *platform; + + unsigned int daifmt; + struct simple_util_dai cpu_dai; + struct simple_util_dai codec_dai; +}; + +#endif /* __SIMPLE_CARD_H */ diff --git a/include/sound/simple_card_utils.h b/include/sound/simple_card_utils.h new file mode 100644 index 000000000..bd8c3a033 --- /dev/null +++ b/include/sound/simple_card_utils.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * simple_card_utils.h + * + * Copyright (c) 2016 Kuninori Morimoto + */ + +#ifndef __SIMPLE_CARD_UTILS_H +#define __SIMPLE_CARD_UTILS_H + +#include +#include + +#define simple_util_init_hp(card, sjack, prefix) \ + simple_util_init_jack(card, sjack, 1, prefix, NULL) +#define simple_util_init_mic(card, sjack, prefix) \ + simple_util_init_jack(card, sjack, 0, prefix, NULL) + +struct simple_util_tdm_width_map { + u8 sample_bits; + u8 slot_count; + u16 slot_width; +}; + +struct simple_util_dai { + const char *name; + unsigned int sysclk; + int clk_direction; + int slots; + int slot_width; + unsigned int tx_slot_mask; + unsigned int rx_slot_mask; + struct clk *clk; + bool clk_fixed; + struct simple_util_tdm_width_map *tdm_width_map; + int n_tdm_widths; +}; + +struct simple_util_data { + u32 convert_rate; + u32 convert_channels; + const char *convert_sample_format; +}; + +struct simple_util_jack { + struct snd_soc_jack jack; + struct snd_soc_jack_pin pin; + struct snd_soc_jack_gpio gpio; +}; + +struct prop_nums { + int cpus; + int codecs; + int platforms; +}; + +enum simple_util_sysclk_order { + SIMPLE_SYSCLK_ORDER_CODEC_FIRST = 0, + SIMPLE_SYSCLK_ORDER_CPU_FIRST, +}; + +struct simple_util_priv { + struct snd_soc_card snd_card; + struct simple_dai_props { + struct simple_util_dai *cpu_dai; + struct simple_util_dai *codec_dai; + struct simple_util_data adata; + struct snd_soc_codec_conf *codec_conf; + struct prop_nums num; + unsigned int mclk_fs; + enum simple_util_sysclk_order sysclk_order; + } *dai_props; + struct simple_util_jack hp_jack; + struct simple_util_jack mic_jack; + struct snd_soc_jack *aux_jacks; + struct snd_soc_dai_link *dai_link; + struct simple_util_dai *dais; + struct snd_soc_dai_link_component *dlcs; + struct snd_soc_codec_conf *codec_conf; + struct gpio_desc *pa_gpio; + const struct snd_soc_ops *ops; + unsigned int dpcm_selectable:1; + unsigned int force_dpcm:1; +}; +#define simple_priv_to_card(priv) (&(priv)->snd_card) +#define simple_priv_to_props(priv, i) ((priv)->dai_props + (i)) +#define simple_priv_to_dev(priv) (simple_priv_to_card(priv)->dev) +#define simple_priv_to_link(priv, i) (simple_priv_to_card(priv)->dai_link + (i)) + +#define simple_props_to_dlc_cpu(props, i) ((props)->cpus + i) +#define simple_props_to_dlc_codec(props, i) ((props)->codecs + i) +#define simple_props_to_dlc_platform(props, i) ((props)->platforms + i) + +#define simple_props_to_dai_cpu(props, i) ((props)->cpu_dai + i) +#define simple_props_to_dai_codec(props, i) ((props)->codec_dai + i) +#define simple_props_to_codec_conf(props, i) ((props)->codec_conf + i) + +/* has the same effect as simple_priv_to_props(). Preferred over + * simple_priv_to_props() when dealing with PCM runtime data as + * the ID stored in rtd->id may not be a valid array index. + */ +#define runtime_simple_priv_to_props(priv, rtd) \ + ((priv)->dai_props + ((rtd)->dai_link - (priv)->dai_link)) + +#define for_each_prop_dlc_cpus(props, i, cpu) \ + for ((i) = 0; \ + ((i) < (props)->num.cpus) && \ + ((cpu) = simple_props_to_dlc_cpu(props, i)); \ + (i)++) +#define for_each_prop_dlc_codecs(props, i, codec) \ + for ((i) = 0; \ + ((i) < (props)->num.codecs) && \ + ((codec) = simple_props_to_dlc_codec(props, i)); \ + (i)++) +#define for_each_prop_dlc_platforms(props, i, platform) \ + for ((i) = 0; \ + ((i) < (props)->num.platforms) && \ + ((platform) = simple_props_to_dlc_platform(props, i)); \ + (i)++) +#define for_each_prop_codec_conf(props, i, conf) \ + for ((i) = 0; \ + ((i) < (props)->num.codecs) && \ + (props)->codec_conf && \ + ((conf) = simple_props_to_codec_conf(props, i)); \ + (i)++) + +#define for_each_prop_dai_cpu(props, i, cpu) \ + for ((i) = 0; \ + ((i) < (props)->num.cpus) && \ + ((cpu) = simple_props_to_dai_cpu(props, i)); \ + (i)++) +#define for_each_prop_dai_codec(props, i, codec) \ + for ((i) = 0; \ + ((i) < (props)->num.codecs) && \ + ((codec) = simple_props_to_dai_codec(props, i)); \ + (i)++) + +#define SNDRV_MAX_LINKS 512 + +struct link_info { + int link; /* number of link */ + int cpu; /* turn for CPU / Codec */ + struct prop_nums num[SNDRV_MAX_LINKS]; +}; + +int simple_util_parse_daifmt(struct device *dev, + struct device_node *node, + struct device_node *codec, + char *prefix, + unsigned int *retfmt); +int simple_util_parse_tdm_width_map(struct simple_util_priv *priv, struct device_node *np, + struct simple_util_dai *dai); + +__printf(3, 4) +int simple_util_set_dailink_name(struct simple_util_priv *priv, + struct snd_soc_dai_link *dai_link, + const char *fmt, ...); +int simple_util_parse_card_name(struct simple_util_priv *priv, + char *prefix); + +int simple_util_parse_clk(struct device *dev, + struct device_node *node, + struct simple_util_dai *simple_dai, + struct snd_soc_dai_link_component *dlc); +int simple_util_startup(struct snd_pcm_substream *substream); +void simple_util_shutdown(struct snd_pcm_substream *substream); +int simple_util_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int simple_util_dai_init(struct snd_soc_pcm_runtime *rtd); +int simple_util_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + +#define simple_util_parse_tdm(np, dai) \ + snd_soc_of_parse_tdm_slot(np, &(dai)->tx_slot_mask, \ + &(dai)->rx_slot_mask, \ + &(dai)->slots, \ + &(dai)->slot_width); + +void simple_util_canonicalize_platform(struct snd_soc_dai_link_component *platforms, + struct snd_soc_dai_link_component *cpus); +void simple_util_canonicalize_cpu(struct snd_soc_dai_link_component *cpus, + int is_single_links); + +void simple_util_clean_reference(struct simple_util_priv *priv); + +void simple_util_parse_convert(struct device_node *np, char *prefix, + struct simple_util_data *data); +bool simple_util_is_convert_required(const struct simple_util_data *data); + +int simple_util_get_sample_fmt(struct simple_util_data *data); + +int simple_util_parse_property(struct simple_util_priv *priv, + int (*func)(struct snd_soc_card *card, const char *propname), + char *prefix, char *property); +static inline int simple_util_parse_routing(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_audio_routing, + prefix, "routing"); +} + +static inline int simple_util_parse_widgets(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_audio_simple_widgets, + prefix, "widgets"); +} + +static inline int simple_util_parse_pin_switches(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_pin_switches, + prefix, "pin-switches"); +} + +static inline int simple_util_parse_aux_devs(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_aux_devs, + prefix, "aux-devs"); +} + +int simple_util_init_jack(struct snd_soc_card *card, + struct simple_util_jack *sjack, + int is_hp, char *prefix, char *pin); +int simple_util_init_aux_jacks(struct snd_soc_card *card, char *prefix); +int simple_util_init_priv(struct simple_util_priv *priv, + struct link_info *li); +void simple_util_remove(struct platform_device *pdev); + +int graph_util_card_probe(struct snd_soc_card *card); +int graph_util_is_ports0(struct device_node *port); +int graph_util_parse_dai(struct simple_util_priv *priv, struct device_node *ep, + struct snd_soc_dai_link_component *dlc, int *is_single_link); + +void graph_util_parse_link_direction(struct device_node *np, + bool *is_playback_only, bool *is_capture_only); +void graph_util_parse_trigger_order(struct simple_util_priv *priv, + struct device_node *np, + enum snd_soc_trigger_order *trigger_start, + enum snd_soc_trigger_order *trigger_stop); + +#ifdef DEBUG +static inline void simple_util_debug_dai(struct simple_util_priv *priv, + char *name, + struct simple_util_dai *dai) +{ + struct device *dev = simple_priv_to_dev(priv); + + /* dai might be NULL */ + if (!dai) + return; + + if (dai->name) + dev_dbg(dev, "%s dai name = %s\n", + name, dai->name); + + if (dai->slots) + dev_dbg(dev, "%s slots = %d\n", name, dai->slots); + if (dai->slot_width) + dev_dbg(dev, "%s slot width = %d\n", name, dai->slot_width); + if (dai->tx_slot_mask) + dev_dbg(dev, "%s tx slot mask = %d\n", name, dai->tx_slot_mask); + if (dai->rx_slot_mask) + dev_dbg(dev, "%s rx slot mask = %d\n", name, dai->rx_slot_mask); + if (dai->clk) + dev_dbg(dev, "%s clk %luHz\n", name, clk_get_rate(dai->clk)); + if (dai->sysclk) + dev_dbg(dev, "%s sysclk = %dHz\n", + name, dai->sysclk); + if (dai->clk || dai->sysclk) + dev_dbg(dev, "%s direction = %s\n", + name, dai->clk_direction ? "OUT" : "IN"); +} + +static inline void simple_util_debug_info(struct simple_util_priv *priv) +{ + struct snd_soc_card *card = simple_priv_to_card(priv); + struct device *dev = simple_priv_to_dev(priv); + + int i; + + if (card->name) + dev_dbg(dev, "Card Name: %s\n", card->name); + + for (i = 0; i < card->num_links; i++) { + struct simple_dai_props *props = simple_priv_to_props(priv, i); + struct snd_soc_dai_link *link = simple_priv_to_link(priv, i); + struct simple_util_dai *dai; + struct snd_soc_codec_conf *cnf; + int j; + + dev_dbg(dev, "DAI%d\n", i); + + dev_dbg(dev, "cpu num = %d\n", link->num_cpus); + for_each_prop_dai_cpu(props, j, dai) + simple_util_debug_dai(priv, "cpu", dai); + dev_dbg(dev, "codec num = %d\n", link->num_codecs); + for_each_prop_dai_codec(props, j, dai) + simple_util_debug_dai(priv, "codec", dai); + + if (link->name) + dev_dbg(dev, "link name = %s\n", link->name); + if (link->dai_fmt) + dev_dbg(dev, "link format = %04x\n", link->dai_fmt); + if (link->playback_only) + dev_dbg(dev, "link has playback_only"); + if (link->capture_only) + dev_dbg(dev, "link has capture_only"); + if (props->adata.convert_rate) + dev_dbg(dev, "convert_rate = %d\n", props->adata.convert_rate); + if (props->adata.convert_channels) + dev_dbg(dev, "convert_channels = %d\n", props->adata.convert_channels); + for_each_prop_codec_conf(props, j, cnf) + if (cnf->name_prefix) + dev_dbg(dev, "name prefix = %s\n", cnf->name_prefix); + if (props->mclk_fs) + dev_dbg(dev, "mclk-fs = %d\n", props->mclk_fs); + } +} +#else +#define simple_util_debug_info(priv) +#endif /* DEBUG */ + +#endif /* __SIMPLE_CARD_UTILS_H */ diff --git a/include/sound/snd_wavefront.h b/include/sound/snd_wavefront.h new file mode 100644 index 000000000..ac749bb2b --- /dev/null +++ b/include/sound/snd_wavefront.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_SND_WAVEFRONT_H__ +#define __SOUND_SND_WAVEFRONT_H__ + +#include +#include +#include +#include /* generic OSS/ALSA/user-level wavefront header */ + +/* MIDI interface */ + +struct _snd_wavefront_midi; +struct _snd_wavefront_card; +struct _snd_wavefront; +struct snd_wss; + +typedef struct _snd_wavefront_midi snd_wavefront_midi_t; +typedef struct _snd_wavefront_card snd_wavefront_card_t; +typedef struct _snd_wavefront snd_wavefront_t; + +typedef enum { internal_mpu = 0, external_mpu = 1 } snd_wavefront_mpu_id; + +struct _snd_wavefront_midi { + unsigned long base; /* I/O port address */ + char isvirtual; /* doing virtual MIDI stuff ? */ + char istimer; /* timer is used */ + snd_wavefront_mpu_id output_mpu; /* most-recently-used */ + snd_wavefront_mpu_id input_mpu; /* most-recently-used */ + unsigned int mode[2]; /* MPU401_MODE_XXX */ + struct snd_rawmidi_substream *substream_output[2]; + struct snd_rawmidi_substream *substream_input[2]; + struct timer_list timer; + snd_wavefront_card_t *timer_card; + spinlock_t open; + spinlock_t virtual; /* protects isvirtual */ +}; + +#define OUTPUT_READY 0x40 +#define INPUT_AVAIL 0x80 +#define MPU_ACK 0xFE +#define UART_MODE_ON 0x3F + +extern const struct snd_rawmidi_ops snd_wavefront_midi_output; +extern const struct snd_rawmidi_ops snd_wavefront_midi_input; + +extern void snd_wavefront_midi_enable_virtual (snd_wavefront_card_t *); +extern void snd_wavefront_midi_disable_virtual (snd_wavefront_card_t *); +extern void snd_wavefront_midi_interrupt (snd_wavefront_card_t *); +extern int snd_wavefront_midi_start (snd_wavefront_card_t *); +void snd_wavefront_midi_suspend(snd_wavefront_card_t *card); +void snd_wavefront_midi_resume(snd_wavefront_card_t *card); + +struct _snd_wavefront { + unsigned long irq; /* "you were one, one of the few ..." */ + unsigned long base; /* low i/o port address */ + struct resource *res_base; /* i/o port resource allocation */ + +#define mpu_data_port base +#define mpu_command_port base + 1 /* write semantics */ +#define mpu_status_port base + 1 /* read semantics */ +#define data_port base + 2 +#define status_port base + 3 /* read semantics */ +#define control_port base + 3 /* write semantics */ +#define block_port base + 4 /* 16 bit, writeonly */ +#define last_block_port base + 6 /* 16 bit, writeonly */ + + /* FX ports. These are mapped through the ICS2115 to the YS225. + The ICS2115 takes care of flipping the relevant pins on the + YS225 so that access to each of these ports does the right + thing. Note: these are NOT documented by Turtle Beach. + */ + +#define fx_status base + 8 +#define fx_op base + 8 +#define fx_lcr base + 9 +#define fx_dsp_addr base + 0xa +#define fx_dsp_page base + 0xb +#define fx_dsp_lsb base + 0xc +#define fx_dsp_msb base + 0xd +#define fx_mod_addr base + 0xe +#define fx_mod_data base + 0xf + + volatile int irq_ok; /* set by interrupt handler */ + volatile int irq_cnt; /* ditto */ + char debug; /* debugging flags */ + int freemem; /* installed RAM, in bytes */ + + char fw_version[2]; /* major = [0], minor = [1] */ + char hw_version[2]; /* major = [0], minor = [1] */ + char israw; /* needs Motorola microcode */ + char has_fx; /* has FX processor (Tropez+) */ + char fx_initialized; /* FX's register pages initialized */ + char prog_status[WF_MAX_PROGRAM]; /* WF_SLOT_* */ + char patch_status[WF_MAX_PATCH]; /* WF_SLOT_* */ + char sample_status[WF_MAX_SAMPLE]; /* WF_ST_* | WF_SLOT_* */ + int samples_used; /* how many */ + char interrupts_are_midi; /* h/w MPU interrupts enabled ? */ + char rom_samples_rdonly; /* can we write on ROM samples */ + char midi_in_to_synth; /* route external MIDI to synth */ + spinlock_t irq_lock; + wait_queue_head_t interrupt_sleeper; + snd_wavefront_midi_t midi; /* ICS2115 MIDI interface */ + struct snd_card *card; +}; + +struct _snd_wavefront_card { + snd_wavefront_t wavefront; + struct snd_wss *chip; +#ifdef CONFIG_PNP + struct pnp_dev *wss; + struct pnp_dev *ctrl; + struct pnp_dev *mpu; + struct pnp_dev *synth; +#endif /* CONFIG_PNP */ +}; + +extern void snd_wavefront_internal_interrupt (snd_wavefront_card_t *card); +void snd_wavefront_cache_firmware(snd_wavefront_t *dev); +extern int snd_wavefront_start (snd_wavefront_t *dev); +extern int snd_wavefront_detect (snd_wavefront_card_t *card); +int snd_wavefront_resume_synth(snd_wavefront_card_t *card); +extern int snd_wavefront_cmd (snd_wavefront_t *, int, unsigned char *, + unsigned char *); + +extern int snd_wavefront_synth_ioctl (struct snd_hwdep *, + struct file *, + unsigned int cmd, + unsigned long arg); +extern int snd_wavefront_synth_open (struct snd_hwdep *, struct file *); +extern int snd_wavefront_synth_release (struct snd_hwdep *, struct file *); + +/* FX processor - see also yss225.[ch] */ + +extern int snd_wavefront_fx_start (snd_wavefront_t *); +extern int snd_wavefront_fx_detect (snd_wavefront_t *); +extern int snd_wavefront_fx_ioctl (struct snd_hwdep *, + struct file *, + unsigned int cmd, + unsigned long arg); +extern int snd_wavefront_fx_open (struct snd_hwdep *, struct file *); +extern int snd_wavefront_fx_release (struct snd_hwdep *, struct file *); + +#endif /* __SOUND_SND_WAVEFRONT_H__ */ diff --git a/include/sound/soc-acpi-intel-match.h b/include/sound/soc-acpi-intel-match.h new file mode 100644 index 000000000..382029724 --- /dev/null +++ b/include/sound/soc-acpi-intel-match.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017, Intel Corporation + */ + +#ifndef __LINUX_SND_SOC_ACPI_INTEL_MATCH_H +#define __LINUX_SND_SOC_ACPI_INTEL_MATCH_H + +#include +#include +#include + +/* + * these tables are not constants, some fields can be used for + * pdata or machine ops + */ +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_broadwell_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_baytrail_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cherrytrail_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_skl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_kbl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_bxt_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_glk_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cnl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cfl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cml_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_icl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_ehl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_jsl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_adl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_rpl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_mtl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_lnl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_arl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_ptl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_nvl_machines[]; + +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cnl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cfl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cml_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_icl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_adl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_rpl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_mtl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_lnl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_arl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_ptl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_nvl_sdw_machines[]; + +/* + * generic table used for HDA codec-based platforms, possibly with + * additional ACPI-enumerated codecs + */ +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_hda_machines[]; + +#endif diff --git a/include/sound/soc-acpi-intel-ssp-common.h b/include/sound/soc-acpi-intel-ssp-common.h new file mode 100644 index 000000000..fdb2fce42 --- /dev/null +++ b/include/sound/soc-acpi-intel-ssp-common.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2023 Intel Corporation. + */ + +#ifndef __LINUX_SND_SOC_ACPI_INTEL_SSP_COMMON_H +#define __LINUX_SND_SOC_ACPI_INTEL_SSP_COMMON_H + +/* Cirrus Logic */ +#define CS35L41_ACPI_HID "CSC3541" +#define CS42L42_ACPI_HID "10134242" + +/* Dialog */ +#define DA7219_ACPI_HID "DLGS7219" + +/* Everest */ +#define ES8316_ACPI_HID "ESSX8316" +#define ES8326_ACPI_HID "ESSX8326" +#define ES8336_ACPI_HID "ESSX8336" + +#define MAX_98357A_ACPI_HID "MX98357A" +#define MAX_98360A_ACPI_HID "MX98360A" +#define MAX_98373_ACPI_HID "MX98373" +#define MAX_98390_ACPI_HID "MX98390" + +/* Nuvoton */ +#define NAU8318_ACPI_HID "NVTN2012" +#define NAU8825_ACPI_HID "10508825" + +/* Realtek */ +#define RT1011_ACPI_HID "10EC1011" +#define RT1015_ACPI_HID "10EC1015" +#define RT1015P_ACPI_HID "RTL1015" +#define RT1019P_ACPI_HID "RTL1019" +#define RT1308_ACPI_HID "10EC1308" +#define RT5650_ACPI_HID "10EC5650" +#define RT5682_ACPI_HID "10EC5682" +#define RT5682S_ACPI_HID "RTL5682" + +/* Texas Instruments */ +#define TAS2563_ACPI_HID "TXNW2563" + +enum snd_soc_acpi_intel_codec { + CODEC_NONE, + + /* headphone codec */ + CODEC_CS42L42, + CODEC_DA7219, + CODEC_ES8316, + CODEC_ES8326, + CODEC_ES8336, + CODEC_NAU8825, + CODEC_RT5650, + CODEC_RT5682, + CODEC_RT5682S, + + /* speaker amplifier */ + CODEC_CS35L41, + CODEC_MAX98357A, + CODEC_MAX98360A, + CODEC_MAX98373, + CODEC_MAX98390, + CODEC_NAU8318, + CODEC_RT1011, + CODEC_RT1015, + CODEC_RT1015P, + CODEC_RT1019P, + CODEC_RT1308, + CODEC_TAS2563, +}; + +enum snd_soc_acpi_intel_codec +snd_soc_acpi_intel_detect_codec_type(struct device *dev); +enum snd_soc_acpi_intel_codec +snd_soc_acpi_intel_detect_amp_type(struct device *dev); + +const char * +snd_soc_acpi_intel_get_codec_name(enum snd_soc_acpi_intel_codec codec_type); + +const char * +snd_soc_acpi_intel_get_codec_tplg_suffix(enum snd_soc_acpi_intel_codec codec_type); +const char * +snd_soc_acpi_intel_get_amp_tplg_suffix(enum snd_soc_acpi_intel_codec codec_type); + +#endif /* __LINUX_SND_SOC_ACPI_INTEL_SSP_COMMON_H */ diff --git a/include/sound/soc-acpi.h b/include/sound/soc-acpi.h new file mode 100644 index 000000000..2ee303b79 --- /dev/null +++ b/include/sound/soc-acpi.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (C) 2013-15, Intel Corporation + */ + +#ifndef __LINUX_SND_SOC_ACPI_H +#define __LINUX_SND_SOC_ACPI_H + +#include +#include +#include +#include +#include + +struct snd_soc_acpi_package_context { + char *name; /* package name */ + int length; /* number of elements */ + struct acpi_buffer *format; + struct acpi_buffer *state; + bool data_valid; +}; + +/* codec name is used in DAIs is i2c-:00 with HID being 8 chars */ +#define SND_ACPI_I2C_ID_LEN (4 + ACPI_ID_LEN + 3 + 1) + +#if IS_ENABLED(CONFIG_ACPI) +/* acpi match */ +struct snd_soc_acpi_mach * +snd_soc_acpi_find_machine(struct snd_soc_acpi_mach *machines); + +bool snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN], + struct snd_soc_acpi_package_context *ctx); + +/* check all codecs */ +struct snd_soc_acpi_mach *snd_soc_acpi_codec_list(void *arg); + +#else +/* acpi match */ +static inline struct snd_soc_acpi_mach * +snd_soc_acpi_find_machine(struct snd_soc_acpi_mach *machines) +{ + return NULL; +} + +static inline bool +snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN], + struct snd_soc_acpi_package_context *ctx) +{ + return false; +} + +/* check all codecs */ +static inline struct snd_soc_acpi_mach *snd_soc_acpi_codec_list(void *arg) +{ + return NULL; +} +#endif + +/** + * struct snd_soc_acpi_mach_params - interface for machine driver configuration + * + * @acpi_ipc_irq_index: used for BYT-CR detection + * @platform: string used for HDAudio codec support + * @codec_mask: used for HDAudio support + * @dmic_num: number of SoC- or chipset-attached PDM digital microphones + * @link_mask: SoundWire links enabled on the board + * @links: array of SoundWire link _ADR descriptors, null terminated + * @i2s_link_mask: I2S/TDM links enabled on the board + * @num_dai_drivers: number of elements in @dai_drivers + * @dai_drivers: pointer to dai_drivers, used e.g. in nocodec mode + * @subsystem_vendor: optional PCI SSID vendor value + * @subsystem_device: optional PCI SSID device value + * @subsystem_rev: optional PCI SSID revision value + * @subsystem_id_set: true if a value has been written to + * subsystem_vendor and subsystem_device. + * @bt_link_mask: BT offload link enabled on the board + */ +struct snd_soc_acpi_mach_params { + u32 acpi_ipc_irq_index; + const char *platform; + u32 codec_mask; + u32 dmic_num; + u32 link_mask; + const struct snd_soc_acpi_link_adr *links; + u32 i2s_link_mask; + u32 num_dai_drivers; + struct snd_soc_dai_driver *dai_drivers; + unsigned short subsystem_vendor; + unsigned short subsystem_device; + unsigned short subsystem_rev; + bool subsystem_id_set; + u32 bt_link_mask; +}; + +/** + * struct snd_soc_acpi_endpoint - endpoint descriptor + * @num: endpoint number (mandatory, unique per device) + * @aggregated: 0 (independent) or 1 (logically grouped) + * @group_position: zero-based order (only when @aggregated is 1) + * @group_id: platform-unique group identifier (only when @aggregrated is 1) + */ +struct snd_soc_acpi_endpoint { + u8 num; + u8 aggregated; + u8 group_position; + u8 group_id; +}; + +/** + * struct snd_soc_acpi_adr_device - descriptor for _ADR-enumerated device + * @adr: 64 bit ACPI _ADR value + * @num_endpoints: number of endpoints for this device + * @endpoints: array of endpoints + * @name_prefix: string used for codec controls + */ +struct snd_soc_acpi_adr_device { + u64 adr; + u8 num_endpoints; + const struct snd_soc_acpi_endpoint *endpoints; + const char *name_prefix; +}; + +/** + * struct snd_soc_acpi_link_adr - ACPI-based list of _ADR enumerated devices + * @mask: one bit set indicates the link this list applies to + * @num_adr: ARRAY_SIZE of devices + * @adr_d: array of devices + * + * The number of devices per link can be more than 1, e.g. in SoundWire + * multi-drop configurations. + */ + +struct snd_soc_acpi_link_adr { + u32 mask; + u32 num_adr; + const struct snd_soc_acpi_adr_device *adr_d; +}; + +/* + * when set the topology uses the -ssp suffix, where N is determined based on + * BIOS or DMI information + */ +#define SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER BIT(0) + +/* + * when more than one SSP is reported in the link mask, use the most significant. + * This choice was found to be valid on platforms with ES8336 codecs. + */ +#define SND_SOC_ACPI_TPLG_INTEL_SSP_MSB BIT(1) + +/* + * when set the topology uses the -dmicch suffix, where N is determined based on + * BIOS or DMI information + */ +#define SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER BIT(2) + +/* + * when set the speaker amplifier name suffix (i.e. "-max98360a") will be + * appended to topology file name + */ +#define SND_SOC_ACPI_TPLG_INTEL_AMP_NAME BIT(3) + +/* + * when set the headphone codec name suffix (i.e. "-rt5682") will be appended to + * topology file name + */ +#define SND_SOC_ACPI_TPLG_INTEL_CODEC_NAME BIT(4) + +/** + * struct snd_soc_acpi_mach - ACPI-based machine descriptor. Most of the fields + * are related to the hardware, except for the firmware and topology file names. + * A platform supported by legacy and Sound Open Firmware (SOF) would expose + * all firmware/topology related fields. + * + * @id: ACPI ID (usually the codec's) used to find a matching machine driver. + * @uid: ACPI Unique ID, can be used to disambiguate matches. + * @comp_ids: list of compatible audio codecs using the same machine driver, + * firmware and topology + * @link_mask: describes required board layout, e.g. for SoundWire. + * @links: array of link _ADR descriptors, null terminated. + * @drv_name: machine driver name + * @fw_filename: firmware file name. Used when SOF is not enabled. + * @tplg_filename: topology file name. Used when SOF is not enabled. + * @board: board name + * @machine_quirk: pointer to quirk, usually based on DMI information when + * ACPI ID alone is not sufficient, wrong or misleading + * @quirk_data: data used to uniquely identify a machine, usually a list of + * audio codecs whose presence if checked with ACPI + * @machine_check: pointer to quirk function. The functionality is similar to + * the use of @machine_quirk, except that the return value is a boolean: the intent + * is to skip a machine if the additional hardware/firmware verification invalidates + * the initial selection in the snd_soc_acpi_mach table. + * @pdata: intended for platform data or machine specific-ops. This structure + * is not constant since this field may be updated at run-time + * @mach_params: machine driver configuration + * @sof_tplg_filename: Sound Open Firmware topology file name, if enabled + * @tplg_quirk_mask: quirks to select different topology files dynamically + * @get_function_tplg_files: This is an optional callback, if specified then instead of + * the single sof_tplg_filename the callback will return the list of function topology + * files to be loaded. + * Return value: The number of the files or negative ERRNO. 0 means that the single topology + * file should be used, no function topology split can be used on the machine. + * card: the pointer of the card + * mach: the pointer of the machine driver + * prefix: the prefix of the topology file name. Typically, it is the path. + * tplg_files: the pointer of the array of the topology file names. + * best_effort: ignore non supported links and try to build the card in best effort + * with supported links + */ +/* Descriptor for SST ASoC machine driver */ +struct snd_soc_acpi_mach { + u8 id[ACPI_ID_LEN]; + const char *uid; + const struct snd_soc_acpi_codecs *comp_ids; + const u32 link_mask; + const struct snd_soc_acpi_link_adr *links; + const char *drv_name; + const char *fw_filename; + const char *tplg_filename; + const char *board; + struct snd_soc_acpi_mach * (*machine_quirk)(void *arg); + const void *quirk_data; + bool (*machine_check)(void *arg); + void *pdata; + struct snd_soc_acpi_mach_params mach_params; + const char *sof_tplg_filename; + const u32 tplg_quirk_mask; + int (*get_function_tplg_files)(struct snd_soc_card *card, + const struct snd_soc_acpi_mach *mach, + const char *prefix, const char ***tplg_files, + bool best_effort); +}; + +#define SND_SOC_ACPI_MAX_CODECS 3 + +/** + * struct snd_soc_acpi_codecs: Structure to hold secondary codec information + * apart from the matched one, this data will be passed to the quirk function + * to match with the ACPI detected devices + * + * @num_codecs: number of secondary codecs used in the platform + * @codecs: holds the codec IDs + * + */ +struct snd_soc_acpi_codecs { + int num_codecs; + u8 codecs[SND_SOC_ACPI_MAX_CODECS][ACPI_ID_LEN]; +}; + +static inline bool snd_soc_acpi_sof_parent(struct device *dev) +{ + return dev->parent && dev->parent->driver && dev->parent->driver->name && + !strncmp(dev->parent->driver->name, "sof-audio-acpi", strlen("sof-audio-acpi")); +} + +bool snd_soc_acpi_sdw_link_slaves_found(struct device *dev, + const struct snd_soc_acpi_link_adr *link, + struct sdw_peripherals *peripherals); + +#endif diff --git a/include/sound/soc-card.h b/include/sound/soc-card.h new file mode 100644 index 000000000..1f1e7d45f --- /dev/null +++ b/include/sound/soc-card.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-card.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto + */ +#ifndef __SOC_CARD_H +#define __SOC_CARD_H + +enum snd_soc_card_subclass { + SND_SOC_CARD_CLASS_ROOT = 0, + SND_SOC_CARD_CLASS_RUNTIME = 1, +}; + +static inline void snd_soc_card_mutex_lock_root(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->mutex, SND_SOC_CARD_CLASS_ROOT); +} + +static inline void snd_soc_card_mutex_lock(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->mutex, SND_SOC_CARD_CLASS_RUNTIME); +} + +static inline void snd_soc_card_mutex_unlock(struct snd_soc_card *card) +{ + mutex_unlock(&card->mutex); +} + +struct snd_kcontrol *snd_soc_card_get_kcontrol(struct snd_soc_card *soc_card, + const char *name); +int snd_soc_card_jack_new(struct snd_soc_card *card, const char *id, int type, + struct snd_soc_jack *jack); +int snd_soc_card_jack_new_pins(struct snd_soc_card *card, const char *id, + int type, struct snd_soc_jack *jack, + struct snd_soc_jack_pin *pins, + unsigned int num_pins); + +int snd_soc_card_suspend_pre(struct snd_soc_card *card); +int snd_soc_card_suspend_post(struct snd_soc_card *card); +int snd_soc_card_resume_pre(struct snd_soc_card *card); +int snd_soc_card_resume_post(struct snd_soc_card *card); + +int snd_soc_card_probe(struct snd_soc_card *card); +int snd_soc_card_late_probe(struct snd_soc_card *card); +void snd_soc_card_fixup_controls(struct snd_soc_card *card); +int snd_soc_card_remove(struct snd_soc_card *card); + +void snd_soc_card_set_topology_name(struct snd_soc_card *card, const char *preifx); + +int snd_soc_card_set_bias_level(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); +int snd_soc_card_set_bias_level_post(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + +int snd_soc_card_add_dai_link(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); +void snd_soc_card_remove_dai_link(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); + +#ifdef CONFIG_PCI +static inline void snd_soc_card_set_pci_ssid(struct snd_soc_card *card, + unsigned short vendor, + unsigned short device) +{ + card->pci_subsystem_vendor = vendor; + card->pci_subsystem_device = device; + card->pci_subsystem_set = true; +} + +static inline int snd_soc_card_get_pci_ssid(struct snd_soc_card *card, + unsigned short *vendor, + unsigned short *device) +{ + if (!card->pci_subsystem_set) + return -ENOENT; + + *vendor = card->pci_subsystem_vendor; + *device = card->pci_subsystem_device; + + return 0; +} +#else /* !CONFIG_PCI */ +static inline void snd_soc_card_set_pci_ssid(struct snd_soc_card *card, + unsigned short vendor, + unsigned short device) +{ +} + +static inline int snd_soc_card_get_pci_ssid(struct snd_soc_card *card, + unsigned short *vendor, + unsigned short *device) +{ + return -ENOENT; +} +#endif /* CONFIG_PCI */ + +/* device driver data */ +static inline void snd_soc_card_set_drvdata(struct snd_soc_card *card, + void *data) +{ + card->drvdata = data; +} + +static inline void *snd_soc_card_get_drvdata(struct snd_soc_card *card) +{ + return card->drvdata; +} + +static inline +struct snd_soc_dai *snd_soc_card_get_codec_dai(struct snd_soc_card *card, + const char *dai_name) +{ + struct snd_soc_pcm_runtime *rtd; + + for_each_card_rtds(card, rtd) { + if (!strcmp(snd_soc_rtd_to_codec(rtd, 0)->name, dai_name)) + return snd_soc_rtd_to_codec(rtd, 0); + } + + return NULL; +} + +#endif /* __SOC_CARD_H */ diff --git a/include/sound/soc-component.h b/include/sound/soc-component.h new file mode 100644 index 000000000..c49b59630 --- /dev/null +++ b/include/sound/soc-component.h @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-component.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto + */ +#ifndef __SOC_COMPONENT_H +#define __SOC_COMPONENT_H + +#include + +struct device_link; + +/* + * Component probe and remove ordering levels for components with runtime + * dependencies. + */ +#define SND_SOC_COMP_ORDER_FIRST -2 +#define SND_SOC_COMP_ORDER_EARLY -1 +#define SND_SOC_COMP_ORDER_NORMAL 0 +#define SND_SOC_COMP_ORDER_LATE 1 +#define SND_SOC_COMP_ORDER_LAST 2 + +#define for_each_comp_order(order) \ + for (order = SND_SOC_COMP_ORDER_FIRST; \ + order <= SND_SOC_COMP_ORDER_LAST; \ + order++) + +/* component interface */ +struct snd_compress_ops { + int (*open)(struct snd_soc_component *component, + struct snd_compr_stream *stream); + int (*free)(struct snd_soc_component *component, + struct snd_compr_stream *stream); + int (*set_params)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_params *params); + int (*get_params)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_codec *params); + int (*set_metadata)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*get_metadata)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*trigger)(struct snd_soc_component *component, + struct snd_compr_stream *stream, int cmd); + int (*pointer)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_tstamp64 *tstamp); + int (*copy)(struct snd_soc_component *component, + struct snd_compr_stream *stream, char __user *buf, + size_t count); + int (*mmap)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct vm_area_struct *vma); + int (*ack)(struct snd_soc_component *component, + struct snd_compr_stream *stream, size_t bytes); + int (*get_caps)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_caps *caps); + int (*get_codec_caps)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_codec_caps *codec); +}; + +struct snd_soc_component_driver { + const char *name; + + /* Default control and setup, added after probe() is run */ + const struct snd_kcontrol_new *controls; + unsigned int num_controls; + const struct snd_soc_dapm_widget *dapm_widgets; + unsigned int num_dapm_widgets; + const struct snd_soc_dapm_route *dapm_routes; + unsigned int num_dapm_routes; + + int (*probe)(struct snd_soc_component *component); + int (*fixup_controls)(struct snd_soc_component *component); + void (*remove)(struct snd_soc_component *component); + int (*suspend)(struct snd_soc_component *component); + int (*resume)(struct snd_soc_component *component); + + unsigned int (*read)(struct snd_soc_component *component, + unsigned int reg); + int (*write)(struct snd_soc_component *component, + unsigned int reg, unsigned int val); + + /* pcm creation and destruction */ + int (*pcm_new)(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd); + void (*pcm_free)(struct snd_soc_component *component, + struct snd_pcm *pcm); + + /* component wide operations */ + int (*set_sysclk)(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir); + int (*set_pll)(struct snd_soc_component *component, int pll_id, + int source, unsigned int freq_in, unsigned int freq_out); + int (*set_jack)(struct snd_soc_component *component, + struct snd_soc_jack *jack, void *data); + int (*get_jack_type)(struct snd_soc_component *component); + + /* DT */ + int (*of_xlate_dai_name)(struct snd_soc_component *component, + const struct of_phandle_args *args, + const char **dai_name); + int (*of_xlate_dai_id)(struct snd_soc_component *comment, + struct device_node *endpoint); + void (*seq_notifier)(struct snd_soc_component *component, + enum snd_soc_dapm_type type, int subseq); + int (*stream_event)(struct snd_soc_component *component, int event); + int (*set_bias_level)(struct snd_soc_component *component, + enum snd_soc_bias_level level); + + int (*open)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*close)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*ioctl)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); + int (*hw_params)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); + int (*hw_free)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*prepare)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*trigger)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int cmd); + int (*sync_stop)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + snd_pcm_uframes_t (*pointer)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*get_time_info)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, struct timespec64 *system_ts, + struct timespec64 *audio_ts, + struct snd_pcm_audio_tstamp_config *audio_tstamp_config, + struct snd_pcm_audio_tstamp_report *audio_tstamp_report); + int (*copy)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int channel, + unsigned long pos, struct iov_iter *iter, + unsigned long bytes); + struct page *(*page)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + unsigned long offset); + int (*mmap)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct vm_area_struct *vma); + int (*ack)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + snd_pcm_sframes_t (*delay)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + + const struct snd_compress_ops *compress_ops; + + /* probe ordering - for components with runtime dependencies */ + int probe_order; + int remove_order; + + /* + * soc_pcm_trigger() start/stop sequence. + * see also + * snd_soc_dai_link + * soc_pcm_trigger() + */ + enum snd_soc_trigger_order trigger_start; + enum snd_soc_trigger_order trigger_stop; + + /* + * signal if the module handling the component should not be removed + * if a pcm is open. Setting this would prevent the module + * refcount being incremented in probe() but allow it be incremented + * when a pcm is opened and decremented when it is closed. + */ + unsigned int module_get_upon_open:1; + + /* bits */ + unsigned int idle_bias_on:1; + unsigned int suspend_bias_off:1; + unsigned int use_pmdown_time:1; /* care pmdown_time at stop */ + /* + * Indicates that the component does not care about the endianness of + * PCM audio data and the core will ensure that both LE and BE variants + * of each used format are present. Typically this is because the + * component sits behind a bus that abstracts away the endian of the + * original data, ie. one for which the transmission endian is defined + * (I2S/SLIMbus/SoundWire), or the concept of endian doesn't exist (PDM, + * analogue). + */ + unsigned int endianness:1; + unsigned int legacy_dai_naming:1; + + /* this component uses topology and ignore machine driver FEs */ + const char *ignore_machine; + const char *topology_name_prefix; + int (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + bool use_dai_pcm_id; /* use DAI link PCM ID as PCM device number */ + int be_pcm_base; /* base device ID for all BE PCMs */ + + const char *debugfs_prefix; +}; + +struct snd_soc_component { + const char *name; + const char *name_prefix; + struct device *dev; + struct snd_soc_card *card; + + unsigned int active; + + unsigned int suspended:1; /* is in suspend PM state */ + + struct list_head list; + struct list_head card_aux_list; /* for auxiliary bound components */ + struct list_head card_list; + + struct device_link *card_device_link; + + const struct snd_soc_component_driver *driver; + + struct list_head dai_list; + int num_dai; + + struct regmap *regmap; + + struct mutex io_mutex; + + /* attached dynamic objects */ + struct list_head dobj_list; + + /* + * DO NOT use any of the fields below in drivers, they are temporary and + * are going to be removed again soon. If you use them in driver code + * the driver will be marked as BROKEN when these fields are removed. + */ + + struct snd_soc_dapm_context *dapm; + + /* machine specific init */ + int (*init)(struct snd_soc_component *component); + + /* function mark */ + void *mark_module; + struct snd_pcm_substream *mark_open; + struct snd_pcm_substream *mark_hw_params; + struct snd_pcm_substream *mark_trigger; + struct snd_compr_stream *mark_compr_open; + void *mark_pm; + + struct dentry *debugfs_root; + + /* Component private data */ + void *priv; +}; + +#define for_each_component_dais(component, dai)\ + list_for_each_entry(dai, &(component)->dai_list, list) +#define for_each_component_dais_safe(component, dai, _dai)\ + list_for_each_entry_safe(dai, _dai, &(component)->dai_list, list) + +/** + * snd_soc_component_to_dapm() - Returns the DAPM context associated with a + * component + * @component: The component for which to get the DAPM context + */ +static inline struct snd_soc_dapm_context *snd_soc_component_to_dapm( + struct snd_soc_component *component) +{ + return component->dapm; +} + +/** + * snd_soc_component_cache_sync() - Sync the register cache with the hardware + * @component: COMPONENT to sync + * + * Note: This function will call regcache_sync() + */ +static inline int snd_soc_component_cache_sync( + struct snd_soc_component *component) +{ + return regcache_sync(component->regmap); +} + +struct snd_soc_component *snd_soc_component_alloc(struct device *dev); + +void snd_soc_component_set_name(struct snd_soc_component *component, const char *name); +const char *snd_soc_component_name(struct snd_soc_component *component); + +void snd_soc_component_set_priv(struct snd_soc_component *component, void *priv); +void *snd_soc_component_to_priv(struct snd_soc_component *component); + +void snd_soc_component_set_aux(struct snd_soc_component *component, + struct snd_soc_aux_dev *aux); +int snd_soc_component_init(struct snd_soc_component *component); +int snd_soc_component_is_dummy(struct snd_soc_component *component); + +/* component IO */ +unsigned int snd_soc_component_read(struct snd_soc_component *component, + unsigned int reg); +int snd_soc_component_write(struct snd_soc_component *component, + unsigned int reg, unsigned int val); +int snd_soc_component_update_bits(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int val); +int snd_soc_component_update_bits_async(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int val); +void snd_soc_component_async_complete(struct snd_soc_component *component); +int snd_soc_component_test_bits(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int value); + +unsigned int snd_soc_component_read_field(struct snd_soc_component *component, + unsigned int reg, unsigned int mask); +int snd_soc_component_write_field(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int val); + +/* component wide operations */ +int snd_soc_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, + unsigned int freq, int dir); +int snd_soc_component_set_pll(struct snd_soc_component *component, int pll_id, + int source, unsigned int freq_in, + unsigned int freq_out); +int snd_soc_component_set_jack(struct snd_soc_component *component, + struct snd_soc_jack *jack, void *data); +int snd_soc_component_get_jack_type(struct snd_soc_component *component); + +void snd_soc_component_seq_notifier(struct snd_soc_component *component, + enum snd_soc_dapm_type type, int subseq); +int snd_soc_component_stream_event(struct snd_soc_component *component, + int event); +int snd_soc_component_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level); + +int snd_soc_component_regmap_val_bytes(struct snd_soc_component *component); +#ifdef CONFIG_REGMAP +void snd_soc_component_init_regmap(struct snd_soc_component *component, + struct regmap *regmap); +void snd_soc_component_exit_regmap(struct snd_soc_component *component); +#endif + +#define snd_soc_component_module_get_when_probe(component)\ + snd_soc_component_module_get(component, NULL, 0) +#define snd_soc_component_module_get_when_open(component, substream) \ + snd_soc_component_module_get(component, substream, 1) +int snd_soc_component_module_get(struct snd_soc_component *component, + void *mark, int upon_open); +#define snd_soc_component_module_put_when_remove(component) \ + snd_soc_component_module_put(component, NULL, 0, 0) +#define snd_soc_component_module_put_when_close(component, substream, rollback) \ + snd_soc_component_module_put(component, substream, 1, rollback) +void snd_soc_component_module_put(struct snd_soc_component *component, + void *mark, int upon_open, int rollback); + +static inline void snd_soc_component_set_drvdata(struct snd_soc_component *c, + void *data) +{ + dev_set_drvdata(c->dev, data); +} + +static inline void *snd_soc_component_get_drvdata(struct snd_soc_component *c) +{ + return dev_get_drvdata(c->dev); +} + +static inline unsigned int +snd_soc_component_active(struct snd_soc_component *component) +{ + return component->active; +} + +/* component controls */ +struct snd_kcontrol *snd_soc_component_get_kcontrol(struct snd_soc_component *component, + const char * const ctl); +int snd_soc_component_notify_control(struct snd_soc_component *component, + const char * const ctl); + +/* component driver ops */ +int snd_soc_component_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream); +int snd_soc_component_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + int rollback); +void snd_soc_component_suspend(struct snd_soc_component *component); +void snd_soc_component_resume(struct snd_soc_component *component); +int snd_soc_component_is_suspended(struct snd_soc_component *component); +int snd_soc_component_probe(struct snd_soc_component *component); +int snd_soc_component_fixup_controls(struct snd_soc_component *component); +void snd_soc_component_remove(struct snd_soc_component *component); +int snd_soc_component_of_xlate_dai_id(struct snd_soc_component *component, + struct device_node *ep); +int snd_soc_component_of_xlate_dai_name(struct snd_soc_component *component, + const struct of_phandle_args *args, + const char **dai_name); +int snd_soc_component_compr_open(struct snd_soc_component *component, + struct snd_compr_stream *cstream); +void snd_soc_component_compr_free(struct snd_soc_component *component, + struct snd_compr_stream *cstream, + int rollback); +int snd_soc_component_compr_trigger(struct snd_compr_stream *cstream, int cmd); +int snd_soc_component_compr_set_params(struct snd_compr_stream *cstream, + struct snd_compr_params *params); +int snd_soc_component_compr_get_params(struct snd_compr_stream *cstream, + struct snd_codec *params); +int snd_soc_component_compr_get_caps(struct snd_compr_stream *cstream, + struct snd_compr_caps *caps); +int snd_soc_component_compr_get_codec_caps(struct snd_compr_stream *cstream, + struct snd_compr_codec_caps *codec); +int snd_soc_component_compr_ack(struct snd_compr_stream *cstream, size_t bytes); +int snd_soc_component_compr_pointer(struct snd_compr_stream *cstream, + struct snd_compr_tstamp64 *tstamp); +int snd_soc_component_compr_copy(struct snd_compr_stream *cstream, + char __user *buf, size_t count); +int snd_soc_component_compr_set_metadata(struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); +int snd_soc_component_compr_get_metadata(struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); + +int snd_soc_pcm_component_pointer(struct snd_pcm_substream *substream); +int snd_soc_pcm_component_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); +int snd_soc_pcm_component_sync_stop(struct snd_pcm_substream *substream); +int snd_soc_pcm_component_copy(struct snd_pcm_substream *substream, + int channel, unsigned long pos, + struct iov_iter *iter, unsigned long bytes); +struct page *snd_soc_pcm_component_page(struct snd_pcm_substream *substream, + unsigned long offset); +int snd_soc_pcm_component_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *vma); +int snd_soc_pcm_component_new(struct snd_soc_pcm_runtime *rtd); +void snd_soc_pcm_component_free(struct snd_soc_pcm_runtime *rtd); +int snd_soc_pcm_component_prepare(struct snd_pcm_substream *substream); +int snd_soc_pcm_component_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +void snd_soc_pcm_component_hw_free(struct snd_pcm_substream *substream, + int rollback); +int snd_soc_pcm_component_trigger(struct snd_pcm_substream *substream, + int cmd, int rollback); +int snd_soc_pcm_component_pm_runtime_get(struct snd_soc_pcm_runtime *rtd, + void *stream); +void snd_soc_pcm_component_pm_runtime_put(struct snd_soc_pcm_runtime *rtd, + void *stream, int rollback); +int snd_soc_pcm_component_ack(struct snd_pcm_substream *substream); +void snd_soc_pcm_component_delay(struct snd_pcm_substream *substream, + snd_pcm_sframes_t *cpu_delay, snd_pcm_sframes_t *codec_delay); + +#endif /* __SOC_COMPONENT_H */ diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h new file mode 100644 index 000000000..ba3ae56c6 --- /dev/null +++ b/include/sound/soc-dai.h @@ -0,0 +1,608 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-dai.h -- ALSA SoC Layer + * + * Copyright: 2005-2008 Wolfson Microelectronics. PLC. + * + * Digital Audio Interface (DAI) API. + */ + +#ifndef __LINUX_SND_SOC_DAI_H +#define __LINUX_SND_SOC_DAI_H + + +#include +#include + +struct snd_pcm_substream; +struct snd_soc_dapm_widget; +struct snd_compr_stream; +struct clk; + +/* + * DAI hardware audio formats. + * + * Describes the physical PCM data formating and clocking. Add new formats + * to the end. + */ +#define SND_SOC_DAIFMT_I2S SND_SOC_DAI_FORMAT_I2S +#define SND_SOC_DAIFMT_RIGHT_J SND_SOC_DAI_FORMAT_RIGHT_J +#define SND_SOC_DAIFMT_LEFT_J SND_SOC_DAI_FORMAT_LEFT_J +#define SND_SOC_DAIFMT_DSP_A SND_SOC_DAI_FORMAT_DSP_A +#define SND_SOC_DAIFMT_DSP_B SND_SOC_DAI_FORMAT_DSP_B +#define SND_SOC_DAIFMT_AC97 SND_SOC_DAI_FORMAT_AC97 +#define SND_SOC_DAIFMT_PDM SND_SOC_DAI_FORMAT_PDM + +/* left and right justified also known as MSB and LSB respectively */ +#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J +#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J + +/* Describes the possible PCM format */ +/* + * use SND_SOC_DAI_FORMAT_xx as eash shift. + * see + * snd_soc_runtime_get_dai_fmt() + */ +#define SND_SOC_POSSIBLE_DAIFMT_FORMAT_SHIFT 0 +#define SND_SOC_POSSIBLE_DAIFMT_FORMAT_MASK (0xFFFF << SND_SOC_POSSIBLE_DAIFMT_FORMAT_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_I2S (1 << SND_SOC_DAI_FORMAT_I2S) +#define SND_SOC_POSSIBLE_DAIFMT_RIGHT_J (1 << SND_SOC_DAI_FORMAT_RIGHT_J) +#define SND_SOC_POSSIBLE_DAIFMT_LEFT_J (1 << SND_SOC_DAI_FORMAT_LEFT_J) +#define SND_SOC_POSSIBLE_DAIFMT_DSP_A (1 << SND_SOC_DAI_FORMAT_DSP_A) +#define SND_SOC_POSSIBLE_DAIFMT_DSP_B (1 << SND_SOC_DAI_FORMAT_DSP_B) +#define SND_SOC_POSSIBLE_DAIFMT_AC97 (1 << SND_SOC_DAI_FORMAT_AC97) +#define SND_SOC_POSSIBLE_DAIFMT_PDM (1 << SND_SOC_DAI_FORMAT_PDM) + +/* + * DAI TDM slot idle modes + * + * Describes a CODEC/CPU's behaviour when not actively receiving or + * transmitting on a given TDM slot. NONE is undefined behaviour. + * Add new modes to the end. + */ +#define SND_SOC_DAI_TDM_IDLE_NONE 0 +#define SND_SOC_DAI_TDM_IDLE_OFF 1 +#define SND_SOC_DAI_TDM_IDLE_ZERO 2 +#define SND_SOC_DAI_TDM_IDLE_PULLDOWN 3 +#define SND_SOC_DAI_TDM_IDLE_HIZ 4 +#define SND_SOC_DAI_TDM_IDLE_PULLUP 5 +#define SND_SOC_DAI_TDM_IDLE_DRIVE_HIGH 6 + +/* + * DAI Clock gating. + * + * DAI bit clocks can be gated (disabled) when the DAI is not + * sending or receiving PCM data in a frame. This can be used to save power. + */ +#define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */ +#define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */ + +/* Describes the possible PCM format */ +/* + * define GATED -> CONT. GATED will be selected if both are selected. + * see + * soc_dai_convert_possiblefmt_to_daifmt() + */ +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT 16 +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_MASK (0xFFFFULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_GATED (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CONT (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) + +/* + * DAI hardware signal polarity. + * + * Specifies whether the DAI can also support inverted clocks for the specified + * format. + * + * BCLK: + * - "normal" polarity means signal is available at rising edge of BCLK + * - "inverted" polarity means signal is available at falling edge of BCLK + * + * FSYNC "normal" polarity depends on the frame format: + * - I2S: frame consists of left then right channel data. Left channel starts + * with falling FSYNC edge, right channel starts with rising FSYNC edge. + * - Left/Right Justified: frame consists of left then right channel data. + * Left channel starts with rising FSYNC edge, right channel starts with + * falling FSYNC edge. + * - DSP A/B: Frame starts with rising FSYNC edge. + * - AC97: Frame starts with rising FSYNC edge. + * + * "Negative" FSYNC polarity is the one opposite of "normal" polarity. + */ +#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */ +#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ +#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ +#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ + +/* Describes the possible PCM format */ +#define SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT 32 +#define SND_SOC_POSSIBLE_DAIFMT_INV_MASK (0xFFFFULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_NB_NF (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_NB_IF (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_IB_NF (0x4ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_IB_IF (0x8ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) + +/* + * DAI hardware clock providers/consumers + * + * This is wrt the codec, the inverse is true for the interface + * i.e. if the codec is clk and FRM provider then the interface is + * clk and frame consumer. + */ +#define SND_SOC_DAIFMT_CBP_CFP (1 << 12) /* codec clk provider & frame provider */ +#define SND_SOC_DAIFMT_CBC_CFP (2 << 12) /* codec clk consumer & frame provider */ +#define SND_SOC_DAIFMT_CBP_CFC (3 << 12) /* codec clk provider & frame consumer */ +#define SND_SOC_DAIFMT_CBC_CFC (4 << 12) /* codec clk consumer & frame consumer */ + +/* when passed to set_fmt directly indicate if the device is provider or consumer */ +#define SND_SOC_DAIFMT_BP_FP SND_SOC_DAIFMT_CBP_CFP +#define SND_SOC_DAIFMT_BC_FP SND_SOC_DAIFMT_CBC_CFP +#define SND_SOC_DAIFMT_BP_FC SND_SOC_DAIFMT_CBP_CFC +#define SND_SOC_DAIFMT_BC_FC SND_SOC_DAIFMT_CBC_CFC + +#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f +#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 +#define SND_SOC_DAIFMT_INV_MASK 0x0f00 +#define SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK 0xf000 + +#define SND_SOC_DAIFMT_MASTER_MASK SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK + +/* + * Master Clock Directions + */ +#define SND_SOC_CLOCK_IN 0 +#define SND_SOC_CLOCK_OUT 1 + +#define SND_SOC_STD_AC97_FMTS (SNDRV_PCM_FMTBIT_S8 |\ + SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S16_BE |\ + SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S20_3BE |\ + SNDRV_PCM_FMTBIT_S20_LE |\ + SNDRV_PCM_FMTBIT_S20_BE |\ + SNDRV_PCM_FMTBIT_S24_3LE |\ + SNDRV_PCM_FMTBIT_S24_3BE |\ + SNDRV_PCM_FMTBIT_S32_LE |\ + SNDRV_PCM_FMTBIT_S32_BE) + +struct snd_soc_dai_driver; +struct snd_soc_dai; +struct snd_ac97_bus_ops; + +/* Digital Audio Interface clocking API.*/ +int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir); + +int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai, + int div_id, int div); + +int snd_soc_dai_set_pll(struct snd_soc_dai *dai, + int pll_id, int source, unsigned int freq_in, unsigned int freq_out); + +int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); + +void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); + +/* Digital Audio interface formatting */ +unsigned int snd_soc_dai_auto_select_format(const struct snd_soc_pcm_runtime *rtd); +int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt); + +int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width); + +int snd_soc_dai_set_tdm_idle(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int tx_mode, int rx_mode); + +int snd_soc_dai_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, const unsigned int *tx_slot, + unsigned int rx_num, const unsigned int *rx_slot); + +int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate); + +int snd_soc_dai_prepare(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream); + +/* Digital Audio Interface mute */ +int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute, + int direction); +int snd_soc_dai_mute_is_ctrled_at_trigger(struct snd_soc_dai *dai); + +int snd_soc_dai_get_channel_map(const struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot); + +int snd_soc_dai_is_dummy(const struct snd_soc_dai *dai); + +int snd_soc_dai_hw_params(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +void snd_soc_dai_hw_free(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream, + int rollback); +int snd_soc_dai_startup(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream); +void snd_soc_dai_shutdown(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream, int rollback); +void snd_soc_dai_suspend(struct snd_soc_dai *dai); +void snd_soc_dai_resume(struct snd_soc_dai *dai); +int snd_soc_dai_compress_new(struct snd_soc_dai *dai, struct snd_soc_pcm_runtime *rtd); +bool snd_soc_dai_stream_valid(const struct snd_soc_dai *dai, int stream); +void snd_soc_dai_action(struct snd_soc_dai *dai, + int stream, int action); +static inline void snd_soc_dai_activate(struct snd_soc_dai *dai, + int stream) +{ + snd_soc_dai_action(dai, stream, 1); +} +static inline void snd_soc_dai_deactivate(struct snd_soc_dai *dai, + int stream) +{ + snd_soc_dai_action(dai, stream, -1); +} +int snd_soc_dai_active(const struct snd_soc_dai *dai); + +int snd_soc_pcm_dai_probe(struct snd_soc_pcm_runtime *rtd, int order); +int snd_soc_pcm_dai_remove(struct snd_soc_pcm_runtime *rtd, int order); +int snd_soc_pcm_dai_new(struct snd_soc_pcm_runtime *rtd); +int snd_soc_pcm_dai_prepare(struct snd_pcm_substream *substream); +int snd_soc_pcm_dai_trigger(struct snd_pcm_substream *substream, int cmd, + int rollback); +void snd_soc_pcm_dai_delay(struct snd_pcm_substream *substream, + snd_pcm_sframes_t *cpu_delay, snd_pcm_sframes_t *codec_delay); + +int snd_soc_dai_compr_startup(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream); +void snd_soc_dai_compr_shutdown(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + int rollback); +int snd_soc_dai_compr_trigger(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, int cmd); +int snd_soc_dai_compr_set_params(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_params *params); +int snd_soc_dai_compr_get_params(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_codec *params); +int snd_soc_dai_compr_ack(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + size_t bytes); +int snd_soc_dai_compr_pointer(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_tstamp64 *tstamp); +int snd_soc_dai_compr_set_metadata(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); +int snd_soc_dai_compr_get_metadata(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); + +const char *snd_soc_dai_name_get(const struct snd_soc_dai *dai); + +struct snd_soc_dai_ops { + /* DAI driver callbacks */ + int (*probe)(struct snd_soc_dai *dai); + int (*remove)(struct snd_soc_dai *dai); + /* compress dai */ + int (*compress_new)(struct snd_soc_pcm_runtime *rtd); + /* Optional Callback used at pcm creation*/ + int (*pcm_new)(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai); + + /* + * DAI clocking configuration, all optional. + * Called by soc_card drivers, normally in their hw_params. + */ + int (*set_sysclk)(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir); + int (*set_pll)(struct snd_soc_dai *dai, int pll_id, int source, + unsigned int freq_in, unsigned int freq_out); + int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div); + int (*set_bclk_ratio)(struct snd_soc_dai *dai, unsigned int ratio); + + /* + * DAI format configuration + * Called by soc_card drivers, normally in their hw_params. + */ + int (*set_fmt)(struct snd_soc_dai *dai, unsigned int fmt); + int (*xlate_tdm_slot_mask)(unsigned int slots, + unsigned int *tx_mask, unsigned int *rx_mask); + int (*set_tdm_slot)(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int slots, int slot_width); + int (*set_tdm_idle)(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int tx_mode, int rx_mode); + int (*set_channel_map)(struct snd_soc_dai *dai, + unsigned int tx_num, const unsigned int *tx_slot, + unsigned int rx_num, const unsigned int *rx_slot); + int (*get_channel_map)(const struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot); + int (*set_tristate)(struct snd_soc_dai *dai, int tristate); + + int (*set_stream)(struct snd_soc_dai *dai, + void *stream, int direction); + void *(*get_stream)(struct snd_soc_dai *dai, int direction); + + /* + * DAI digital mute - optional. + * Called by soc-core to minimise any pops. + */ + int (*mute_stream)(struct snd_soc_dai *dai, int mute, int stream); + + /* + * ALSA PCM audio operations - all optional. + * Called by soc-core during audio PCM operations. + */ + int (*startup)(struct snd_pcm_substream *, + struct snd_soc_dai *); + void (*shutdown)(struct snd_pcm_substream *, + struct snd_soc_dai *); + int (*hw_params)(struct snd_pcm_substream *, + struct snd_pcm_hw_params *, struct snd_soc_dai *); + int (*hw_free)(struct snd_pcm_substream *, + struct snd_soc_dai *); + int (*prepare)(struct snd_pcm_substream *, + struct snd_soc_dai *); + /* + * NOTE: Commands passed to the trigger function are not necessarily + * compatible with the current state of the dai. For example this + * sequence of commands is possible: START STOP STOP. + * So do not unconditionally use refcounting functions in the trigger + * function, e.g. clk_enable/disable. + */ + int (*trigger)(struct snd_pcm_substream *, int, + struct snd_soc_dai *); + + /* + * For hardware based FIFO caused delay reporting. + * Optional. + */ + snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *, + struct snd_soc_dai *); + + /* + * Format list for auto selection. + * Format will be increased if priority format was + * not selected. + * see + * snd_soc_dai_get_fmt() + */ + const u64 *auto_selectable_formats; + int num_auto_selectable_formats; + + /* probe ordering - for components with runtime dependencies */ + int probe_order; + int remove_order; + + /* bit field */ + unsigned int no_capture_mute:1; + unsigned int mute_unmute_on_trigger:1; +}; + +struct snd_soc_cdai_ops { + /* + * for compress ops + */ + int (*startup)(struct snd_compr_stream *, + struct snd_soc_dai *); + int (*shutdown)(struct snd_compr_stream *, + struct snd_soc_dai *); + int (*set_params)(struct snd_compr_stream *, + struct snd_compr_params *, struct snd_soc_dai *); + int (*get_params)(struct snd_compr_stream *, + struct snd_codec *, struct snd_soc_dai *); + int (*set_metadata)(struct snd_compr_stream *, + struct snd_compr_metadata *, struct snd_soc_dai *); + int (*get_metadata)(struct snd_compr_stream *, + struct snd_compr_metadata *, struct snd_soc_dai *); + int (*trigger)(struct snd_compr_stream *, int, + struct snd_soc_dai *); + int (*pointer)(struct snd_compr_stream *stream, + struct snd_compr_tstamp64 *tstamp, + struct snd_soc_dai *dai); + int (*ack)(struct snd_compr_stream *, size_t, + struct snd_soc_dai *); +}; + +/* + * Digital Audio Interface Driver. + * + * Describes the Digital Audio Interface in terms of its ALSA, DAI and AC97 + * operations and capabilities. Codec and platform drivers will register this + * structure for every DAI they have. + * + * This structure covers the clocking, formating and ALSA operations for each + * interface. + */ +struct snd_soc_dai_driver { + /* DAI description */ + const char *name; + unsigned int id; + unsigned int base; + struct snd_soc_dobj dobj; + const struct of_phandle_args *dai_args; + + /* ops */ + const struct snd_soc_dai_ops *ops; + const struct snd_soc_cdai_ops *cops; + + /* DAI capabilities */ + struct snd_soc_pcm_stream capture; + struct snd_soc_pcm_stream playback; + unsigned int symmetric_rate:1; + unsigned int symmetric_channels:1; + unsigned int symmetric_sample_bits:1; +}; + +/* for Playback/Capture */ +struct snd_soc_dai_stream { + struct snd_soc_dapm_widget *widget; + + unsigned int active; /* usage count */ + unsigned int tdm_mask; /* CODEC TDM slot masks and params (for fixup) */ + + void *dma_data; /* DAI DMA data */ +}; + +/* + * Digital Audio Interface runtime data. + * + * Holds runtime data for a DAI. + */ +struct snd_soc_dai { + const char *name; + int id; + struct device *dev; + + /* driver ops */ + struct snd_soc_dai_driver *driver; + + /* DAI runtime info */ + struct snd_soc_dai_stream stream[SNDRV_PCM_STREAM_LAST + 1]; + + /* Symmetry data - only valid if symmetry is being enforced */ + unsigned int symmetric_rate; + unsigned int symmetric_channels; + unsigned int symmetric_sample_bits; + + /* shared BCLK clock for cross-DAI rate constraints */ + struct clk *bclk; + unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ + + /* parent platform/codec */ + struct snd_soc_component *component; + + struct list_head list; + + /* function mark */ + struct snd_pcm_substream *mark_startup; + struct snd_pcm_substream *mark_hw_params; + struct snd_pcm_substream *mark_trigger; + struct snd_compr_stream *mark_compr_startup; + + /* bit field */ + unsigned int probed:1; + + /* DAI private data */ + void *priv; +}; + +static inline const struct snd_soc_pcm_stream * +snd_soc_dai_get_pcm_stream(const struct snd_soc_dai *dai, int stream) +{ + return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? + &dai->driver->playback : &dai->driver->capture; +} + +#define snd_soc_dai_get_widget_playback(dai) snd_soc_dai_get_widget(dai, SNDRV_PCM_STREAM_PLAYBACK) +#define snd_soc_dai_get_widget_capture(dai) snd_soc_dai_get_widget(dai, SNDRV_PCM_STREAM_CAPTURE) +static inline +struct snd_soc_dapm_widget *snd_soc_dai_get_widget(struct snd_soc_dai *dai, int stream) +{ + return dai->stream[stream].widget; +} + +#define snd_soc_dai_set_widget_playback(dai, widget) snd_soc_dai_set_widget(dai, SNDRV_PCM_STREAM_PLAYBACK, widget) +#define snd_soc_dai_set_widget_capture(dai, widget) snd_soc_dai_set_widget(dai, SNDRV_PCM_STREAM_CAPTURE, widget) +static inline +void snd_soc_dai_set_widget(struct snd_soc_dai *dai, int stream, struct snd_soc_dapm_widget *widget) +{ + dai->stream[stream].widget = widget; +} + +#define snd_soc_dai_dma_data_get_playback(dai) snd_soc_dai_dma_data_get(dai, SNDRV_PCM_STREAM_PLAYBACK) +#define snd_soc_dai_dma_data_get_capture(dai) snd_soc_dai_dma_data_get(dai, SNDRV_PCM_STREAM_CAPTURE) +#define snd_soc_dai_get_dma_data(dai, ss) snd_soc_dai_dma_data_get(dai, ss->stream) +static inline void *snd_soc_dai_dma_data_get(const struct snd_soc_dai *dai, int stream) +{ + return dai->stream[stream].dma_data; +} + +#define snd_soc_dai_dma_data_set_playback(dai, data) snd_soc_dai_dma_data_set(dai, SNDRV_PCM_STREAM_PLAYBACK, data) +#define snd_soc_dai_dma_data_set_capture(dai, data) snd_soc_dai_dma_data_set(dai, SNDRV_PCM_STREAM_CAPTURE, data) +#define snd_soc_dai_set_dma_data(dai, ss, data) snd_soc_dai_dma_data_set(dai, ss->stream, data) +static inline void snd_soc_dai_dma_data_set(struct snd_soc_dai *dai, int stream, void *data) +{ + dai->stream[stream].dma_data = data; +} + +static inline void snd_soc_dai_init_dma_data(struct snd_soc_dai *dai, void *playback, void *capture) +{ + snd_soc_dai_dma_data_set_playback(dai, playback); + snd_soc_dai_dma_data_set_capture(dai, capture); +} + +static inline unsigned int snd_soc_dai_tdm_mask_get(const struct snd_soc_dai *dai, + int stream) +{ + return dai->stream[stream].tdm_mask; +} + +static inline void snd_soc_dai_tdm_mask_set(struct snd_soc_dai *dai, int stream, + unsigned int tdm_mask) +{ + dai->stream[stream].tdm_mask = tdm_mask; +} + +static inline unsigned int snd_soc_dai_stream_active(const struct snd_soc_dai *dai, + int stream) +{ + /* see snd_soc_dai_action() for setup */ + return dai->stream[stream].active; +} + +static inline void snd_soc_dai_set_drvdata(struct snd_soc_dai *dai, + void *data) +{ + dev_set_drvdata(dai->dev, data); +} + +static inline void *snd_soc_dai_get_drvdata(struct snd_soc_dai *dai) +{ + return dev_get_drvdata(dai->dev); +} + +/** + * snd_soc_dai_set_stream() - Configures a DAI for stream operation + * @dai: DAI + * @stream: STREAM (opaque structure depending on DAI type) + * @direction: Stream direction(Playback/Capture) + * Some subsystems, such as SoundWire, don't have a notion of direction and we reuse + * the ASoC stream direction to configure sink/source ports. + * Playback maps to source ports and Capture for sink ports. + * + * This should be invoked with NULL to clear the stream set previously. + * Returns 0 on success, a negative error code otherwise. + */ +static inline int snd_soc_dai_set_stream(struct snd_soc_dai *dai, + void *stream, int direction) +{ + if (dai->driver->ops->set_stream) + return dai->driver->ops->set_stream(dai, stream, direction); + else + return -ENOTSUPP; +} + +/** + * snd_soc_dai_get_stream() - Retrieves stream from DAI + * @dai: DAI + * @direction: Stream direction(Playback/Capture) + * + * This routine only retrieves that was previously configured + * with snd_soc_dai_get_stream() + * + * Returns pointer to stream or an ERR_PTR value, e.g. + * ERR_PTR(-ENOTSUPP) if callback is not supported; + */ +static inline void *snd_soc_dai_get_stream(struct snd_soc_dai *dai, + int direction) +{ + if (dai->driver->ops->get_stream) + return dai->driver->ops->get_stream(dai, direction); + else + return ERR_PTR(-ENOTSUPP); +} + +#endif diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h new file mode 100644 index 000000000..33c4a3e9c --- /dev/null +++ b/include/sound/soc-dapm.h @@ -0,0 +1,757 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-dapm.h -- ALSA SoC Dynamic Audio Power Management + * + * Author: Liam Girdwood + * Created: Aug 11th 2005 + * Copyright: Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_SOC_DAPM_H +#define __LINUX_SND_SOC_DAPM_H + +#include +#include +#include +#include + +struct device; +struct regulator; +struct soc_enum; +struct snd_pcm_substream; +struct snd_soc_pcm_runtime; +struct snd_soc_dapm_context; + +/* widget has no PM register bit */ +#define SND_SOC_NOPM -1 + +/* + * SoC dynamic audio power management + * + * We can have up to 4 power domains + * 1. Codec domain - VREF, VMID + * Usually controlled at codec probe/remove, although can be set + * at stream time if power is not needed for sidetone, etc. + * 2. Platform/Machine domain - physically connected inputs and outputs + * Is platform/machine and user action specific, is set in the machine + * driver and by userspace e.g when HP are inserted + * 3. Path domain - Internal codec path mixers + * Are automatically set when mixer and mux settings are + * changed by the user. + * 4. Stream domain - DAC's and ADC's. + * Enabled when stream playback/capture is started. + */ + +/* codec domain */ +#define SND_SOC_DAPM_VMID(wname) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_vmid, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0} + +/* platform domain */ +#define SND_SOC_DAPM_SIGGEN(wname) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_siggen, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_SINK(wname) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_sink, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_INPUT(wname) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_input, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_OUTPUT(wname) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_output, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_MIC(wname, wevent) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mic, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD} +#define SND_SOC_DAPM_HP(wname, wevent) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_hp, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} +#define SND_SOC_DAPM_SPK(wname, wevent) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_spk, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} +#define SND_SOC_DAPM_LINE(wname, wevent) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_line, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} + +#define SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert) \ + .reg = wreg, .mask = 1, .shift = wshift, \ + .on_val = winvert ? 0 : 1, .off_val = winvert ? 1 : 0 + +/* path domain */ +#define SND_SOC_DAPM_PGA(wname, wreg, wshift, winvert,\ + wcontrols, wncontrols) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_OUT_DRV(wname, wreg, wshift, winvert,\ + wcontrols, wncontrols) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_MIXER(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols)\ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_MIXER_NAMED_CTL(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols)\ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +/* DEPRECATED: use SND_SOC_DAPM_SUPPLY */ +#define SND_SOC_DAPM_MICBIAS(wname, wreg, wshift, winvert) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_micbias, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = NULL, .num_kcontrols = 0} +#define SND_SOC_DAPM_SWITCH(wname, wreg, wshift, winvert, wcontrols) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_switch, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1} +#define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mux, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1} +#define SND_SOC_DAPM_DEMUX(wname, wreg, wshift, winvert, wcontrols) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_demux, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1} + +/* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ +#define SOC_PGA_ARRAY(wname, wreg, wshift, winvert,\ + wcontrols) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} +#define SOC_MIXER_ARRAY(wname, wreg, wshift, winvert, \ + wcontrols)\ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} +#define SOC_MIXER_NAMED_CTL_ARRAY(wname, wreg, wshift, winvert, \ + wcontrols)\ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} + +/* path domain with event - event handler must return 0 for success */ +#define SND_SOC_DAPM_PGA_E(wname, wreg, wshift, winvert, wcontrols, \ + wncontrols, wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_OUT_DRV_E(wname, wreg, wshift, winvert, wcontrols, \ + wncontrols, wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MIXER_E(wname, wreg, wshift, winvert, wcontrols, \ + wncontrols, wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MIXER_NAMED_CTL_E(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols, wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, \ + .num_kcontrols = wncontrols, .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_SWITCH_E(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_switch, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MUX_E(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mux, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1, \ + .event = wevent, .event_flags = wflags} + +/* additional sequencing control within an event type */ +#define SND_SOC_DAPM_PGA_S(wname, wsubseq, wreg, wshift, winvert, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags, \ + .subseq = wsubseq} +#define SND_SOC_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, winvert, wevent, \ + wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_supply, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags, .subseq = wsubseq} + +/* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ +#define SOC_PGA_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ + .event = wevent, .event_flags = wflags} +#define SOC_MIXER_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ + .event = wevent, .event_flags = wflags} +#define SOC_MIXER_NAMED_CTL_E_ARRAY(wname, wreg, wshift, winvert, \ + wcontrols, wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ + .event = wevent, .event_flags = wflags} + +/* events that are pre and post DAPM */ +#define SND_SOC_DAPM_PRE(wname, wevent) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pre, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD} +#define SND_SOC_DAPM_POST(wname, wevent) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_post, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD} + +/* stream domain */ +#define SND_SOC_DAPM_AIF_IN(wname, stname, wchan, wreg, wshift, winvert) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } +#define SND_SOC_DAPM_AIF_IN_E(wname, stname, wchan, wreg, wshift, winvert, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags } +#define SND_SOC_DAPM_AIF_OUT(wname, stname, wchan, wreg, wshift, winvert) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } +#define SND_SOC_DAPM_AIF_OUT_E(wname, stname, wchan, wreg, wshift, winvert, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags } +#define SND_SOC_DAPM_DAC(wname, stname, wreg, wshift, winvert) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert) } +#define SND_SOC_DAPM_DAC_E(wname, stname, wreg, wshift, winvert, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags} + +#define SND_SOC_DAPM_ADC(wname, stname, wreg, wshift, winvert) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } +#define SND_SOC_DAPM_ADC_E(wname, stname, wreg, wshift, winvert, \ + wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_CLOCK_SUPPLY(wname) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_clock_supply, .name = wname, \ + .reg = SND_SOC_NOPM, .event = snd_soc_dapm_clock_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD } + +/* generic widgets */ +#define SND_SOC_DAPM_REG(wid, wname, wreg, wshift, wmask, won_val, woff_val) \ +(struct snd_soc_dapm_widget) { \ + .id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \ + .reg = wreg, .shift = wshift, .mask = wmask, \ + .on_val = won_val, .off_val = woff_val, } +#define SND_SOC_DAPM_SUPPLY(wname, wreg, wshift, winvert, wevent, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_supply, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_REGULATOR_SUPPLY(wname, wdelay, wflags) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_regulator_supply, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = wdelay, .event = snd_soc_dapm_regulator_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD, \ + .on_val = wflags} +#define SND_SOC_DAPM_PINCTRL(wname, active, sleep) \ +(struct snd_soc_dapm_widget) { \ + .id = snd_soc_dapm_pinctrl, .name = wname, \ + .priv = (&(struct snd_soc_dapm_pinctrl_priv) \ + { .active_state = active, .sleep_state = sleep,}), \ + .reg = SND_SOC_NOPM, .event = snd_soc_dapm_pinctrl_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD } + + + +/* dapm kcontrol types */ +#define SOC_DAPM_DOUBLE(xname, reg, lshift, rshift, max, invert) \ + SOC_DOUBLE_EXT(xname, reg, lshift, rshift, max, invert, \ + snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw) +#define SOC_DAPM_DOUBLE_R(xname, lreg, rreg, shift, max, invert) \ + SOC_DOUBLE_R_EXT(xname, lreg, rreg, shift, max, invert, \ + snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw) +#define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \ + SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ + snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw) +#define SOC_DAPM_SINGLE_VIRT(xname, max) \ + SOC_DAPM_SINGLE(xname, SND_SOC_NOPM, 0, max, 0) +#define SOC_DAPM_DOUBLE_R_TLV(xname, lreg, rreg, shift, max, invert, tlv_array) \ + SOC_DOUBLE_R_EXT_TLV(xname, lreg, rreg, shift, max, invert, \ + snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw, \ + tlv_array) +#define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ + SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ + snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw, \ + tlv_array) +#define SOC_DAPM_SINGLE_TLV_VIRT(xname, max, tlv_array) \ + SOC_DAPM_SINGLE(xname, SND_SOC_NOPM, 0, max, 0, tlv_array) +#define SOC_DAPM_ENUM(xname, xenum) \ + SOC_ENUM_EXT(xname, xenum, snd_soc_dapm_get_enum_double, \ + snd_soc_dapm_put_enum_double) +#define SOC_DAPM_ENUM_EXT(xname, xenum, xget, xput) \ + SOC_ENUM_EXT(xname, xenum, xget, xput) + +#define SOC_DAPM_SINGLE_AUTODISABLE(xname, reg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, 0, max, invert, 1) } +#define SOC_DAPM_SINGLE_TLV_AUTODISABLE(xname, reg, shift, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, 0, max, invert, 1) } +#define SOC_DAPM_PIN_SWITCH(xname) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname " Switch", \ + .info = snd_soc_dapm_info_pin_switch, \ + .get = snd_soc_dapm_get_pin_switch, \ + .put = snd_soc_dapm_put_pin_switch, \ + .private_value = (unsigned long)xname } + +/* dapm stream operations */ +#define SND_SOC_DAPM_STREAM_NOP 0x0 +#define SND_SOC_DAPM_STREAM_START 0x1 +#define SND_SOC_DAPM_STREAM_STOP 0x2 +#define SND_SOC_DAPM_STREAM_SUSPEND 0x4 +#define SND_SOC_DAPM_STREAM_RESUME 0x8 +#define SND_SOC_DAPM_STREAM_PAUSE_PUSH 0x10 +#define SND_SOC_DAPM_STREAM_PAUSE_RELEASE 0x20 + +/* dapm event types */ +#define SND_SOC_DAPM_PRE_PMU 0x1 /* before widget power up */ +#define SND_SOC_DAPM_POST_PMU 0x2 /* after widget power up */ +#define SND_SOC_DAPM_PRE_PMD 0x4 /* before widget power down */ +#define SND_SOC_DAPM_POST_PMD 0x8 /* after widget power down */ +#define SND_SOC_DAPM_PRE_REG 0x10 /* before audio path setup */ +#define SND_SOC_DAPM_POST_REG 0x20 /* after audio path setup */ +#define SND_SOC_DAPM_WILL_PMU 0x40 /* called at start of sequence */ +#define SND_SOC_DAPM_WILL_PMD 0x80 /* called at start of sequence */ +#define SND_SOC_DAPM_PRE_POST_PMD (SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD) +#define SND_SOC_DAPM_PRE_POST_PMU (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU) + +/* convenience event type detection */ +#define SND_SOC_DAPM_EVENT_ON(e) (e & (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU)) +#define SND_SOC_DAPM_EVENT_OFF(e) (e & (SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD)) + +/* regulator widget flags */ +#define SND_SOC_DAPM_REGULATOR_BYPASS 0x1 /* bypass when disabled */ + +/* + * Bias levels + * + * @ON: Bias is fully on for audio playback and capture operations. + * @PREPARE: Prepare for audio operations. Called before DAPM switching for + * stream start and stop operations. + * @STANDBY: Low power standby state when no playback/capture operations are + * in progress. NOTE: The transition time between STANDBY and ON + * should be as fast as possible and no longer than 10ms. + * @OFF: Power Off. No restrictions on transition times. + */ +enum snd_soc_bias_level { + SND_SOC_BIAS_OFF = 0, + SND_SOC_BIAS_STANDBY = 1, + SND_SOC_BIAS_PREPARE = 2, + SND_SOC_BIAS_ON = 3, +}; + +/* dapm widget types */ +enum snd_soc_dapm_type { + snd_soc_dapm_input = 0, /* input pin */ + snd_soc_dapm_output, /* output pin */ + snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */ + snd_soc_dapm_mux_named_ctl, /* mux with named controls */ + snd_soc_dapm_demux, /* connects the input to one of multiple outputs */ + snd_soc_dapm_mixer, /* mixes several analog signals together */ + snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */ + snd_soc_dapm_pga, /* programmable gain/attenuation (volume) */ + snd_soc_dapm_out_drv, /* output driver */ + snd_soc_dapm_adc, /* analog to digital converter */ + snd_soc_dapm_dac, /* digital to analog converter */ + snd_soc_dapm_micbias, /* microphone bias (power) - DEPRECATED: use snd_soc_dapm_supply */ + snd_soc_dapm_mic, /* microphone */ + snd_soc_dapm_hp, /* headphones */ + snd_soc_dapm_spk, /* speaker */ + snd_soc_dapm_line, /* line input/output */ + snd_soc_dapm_switch, /* analog switch */ + snd_soc_dapm_vmid, /* codec bias/vmid - to minimise pops */ + snd_soc_dapm_pre, /* machine specific pre widget - exec first */ + snd_soc_dapm_post, /* machine specific post widget - exec last */ + snd_soc_dapm_supply, /* power/clock supply */ + snd_soc_dapm_pinctrl, /* pinctrl */ + snd_soc_dapm_regulator_supply, /* external regulator */ + snd_soc_dapm_clock_supply, /* external clock */ + snd_soc_dapm_aif_in, /* audio interface input */ + snd_soc_dapm_aif_out, /* audio interface output */ + snd_soc_dapm_siggen, /* signal generator */ + snd_soc_dapm_sink, + snd_soc_dapm_dai_in, /* link to DAI structure */ + snd_soc_dapm_dai_out, + snd_soc_dapm_dai_link, /* link between two DAI structures */ + snd_soc_dapm_kcontrol, /* Auto-disabled kcontrol */ + snd_soc_dapm_buffer, /* DSP/CODEC internal buffer */ + snd_soc_dapm_scheduler, /* DSP/CODEC internal scheduler */ + snd_soc_dapm_effect, /* DSP/CODEC effect component */ + snd_soc_dapm_src, /* DSP/CODEC SRC component */ + snd_soc_dapm_asrc, /* DSP/CODEC ASRC component */ + snd_soc_dapm_encoder, /* FW/SW audio encoder component */ + snd_soc_dapm_decoder, /* FW/SW audio decoder component */ + + /* Don't edit below this line */ + SND_SOC_DAPM_TYPE_COUNT +}; + +/* + * DAPM audio route definition. + * + * Defines an audio route originating at source via control and finishing + * at sink. + */ +struct snd_soc_dapm_route { + const char *sink; + const char *control; + const char *source; + + /* Note: currently only supported for links where source is a supply */ + int (*connected)(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink); + + struct snd_soc_dobj dobj; +}; + +/* dapm audio path between two widgets */ +struct snd_soc_dapm_path { + const char *name; + + /* + * source (input) and sink (output) widgets + * The union is for convience, since it is a lot nicer to type + * p->source, rather than p->node[SND_SOC_DAPM_DIR_IN] + */ + union { + struct { + struct snd_soc_dapm_widget *source; + struct snd_soc_dapm_widget *sink; + }; + struct snd_soc_dapm_widget *node[2]; + }; + + /* status */ + u32 connect:1; /* source and sink widgets are connected */ + u32 walking:1; /* path is in the process of being walked */ + u32 is_supply:1; /* At least one of the connected widgets is a supply */ + + int (*connected)(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink); + + struct list_head list_node[2]; + struct list_head list_kcontrol; + struct list_head list; +}; + +/* dapm widget */ +struct snd_soc_dapm_widget { + enum snd_soc_dapm_type id; + const char *name; /* widget name */ + const char *sname; /* stream name */ + struct list_head list; + struct snd_soc_dapm_context *dapm; + + void *priv; /* widget specific data */ + struct regulator *regulator; /* attached regulator */ + struct pinctrl *pinctrl; /* attached pinctrl */ + + /* dapm control */ + int reg; /* negative reg = no direct dapm */ + unsigned char shift; /* bits to shift */ + unsigned int mask; /* non-shifted mask */ + unsigned int on_val; /* on state value */ + unsigned int off_val; /* off state value */ + unsigned char power:1; /* block power status */ + unsigned char active:1; /* active stream on DAC, ADC's */ + unsigned char connected:1; /* connected codec pin */ + unsigned char new:1; /* cnew complete */ + unsigned char force:1; /* force state */ + unsigned char ignore_suspend:1; /* kept enabled over suspend */ + unsigned char new_power:1; /* power from this run */ + unsigned char power_checked:1; /* power checked this run */ + unsigned char is_supply:1; /* Widget is a supply type widget */ + unsigned char is_ep:2; /* Widget is a endpoint type widget */ + unsigned char no_wname_in_kcontrol_name:1; /* No widget name prefix in kcontrol name */ + int subseq; /* sort within widget type */ + + int (*power_check)(struct snd_soc_dapm_widget *w); + + /* external events */ + unsigned short event_flags; /* flags to specify event types */ + int (*event)(struct snd_soc_dapm_widget*, struct snd_kcontrol *, int); + + /* kcontrols that relate to this widget */ + int num_kcontrols; + const struct snd_kcontrol_new *kcontrol_news; + struct snd_kcontrol **kcontrols; + struct snd_soc_dobj dobj; + + /* widget input and output edges */ + struct list_head edges[2]; + + /* used during DAPM updates */ + struct list_head work_list; + struct list_head power_list; + struct list_head dirty; + int endpoints[2]; + + struct clk *clk; + + int channel; +}; + +struct snd_soc_dapm_update { + struct snd_kcontrol *kcontrol; + int reg; + int mask; + int val; + int reg2; + int mask2; + int val2; + bool has_second_set; +}; + +/* A list of widgets associated with an object, typically a snd_kcontrol */ +struct snd_soc_dapm_widget_list { + int num_widgets; + struct snd_soc_dapm_widget *widgets[] __counted_by(num_widgets); +}; + +struct snd_soc_dapm_stats { + int power_checks; + int path_checks; + int neighbour_checks; +}; + +struct snd_soc_dapm_pinctrl_priv { + const char *active_state; + const char *sleep_state; +}; + +enum snd_soc_dapm_direction { + SND_SOC_DAPM_DIR_IN, + SND_SOC_DAPM_DIR_OUT +}; + +#define SND_SOC_DAPM_DIR_TO_EP(x) BIT(x) + +#define SND_SOC_DAPM_EP_SOURCE SND_SOC_DAPM_DIR_TO_EP(SND_SOC_DAPM_DIR_IN) +#define SND_SOC_DAPM_EP_SINK SND_SOC_DAPM_DIR_TO_EP(SND_SOC_DAPM_DIR_OUT) + +struct snd_soc_dapm_context *snd_soc_dapm_alloc(struct device *dev); + +int snd_soc_dapm_regulator_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); +int snd_soc_dapm_clock_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); +int snd_soc_dapm_pinctrl_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); + +/* dapm controls */ +int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_info_pin_switch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); +int snd_soc_dapm_get_pin_switch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *uncontrol); +int snd_soc_dapm_put_pin_switch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *uncontrol); +int snd_soc_dapm_get_component_pin_switch(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uncontrol); +int snd_soc_dapm_put_component_pin_switch(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uncontrol); +int snd_soc_dapm_new_controls(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_widget *widget, unsigned int num); +struct snd_soc_dapm_widget *snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_widget *widget); +struct snd_soc_dapm_widget *snd_soc_dapm_new_control_unlocked(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_widget *widget); +int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm, struct snd_soc_dai *dai); +void snd_soc_dapm_free_widget(struct snd_soc_dapm_widget *w); +int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card); +void snd_soc_dapm_connect_dai_link_widgets(struct snd_soc_card *card); +int snd_soc_dapm_ignore_suspend_widgets(struct snd_soc_card *card); + +int snd_soc_dapm_update_dai(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai); +int snd_soc_dapm_widget_name_cmp(struct snd_soc_dapm_widget *widget, const char *s); +struct device *snd_soc_dapm_to_dev(struct snd_soc_dapm_context *dapm); +struct snd_soc_card *snd_soc_dapm_to_card(struct snd_soc_dapm_context *dapm); +struct snd_soc_component *snd_soc_dapm_to_component(struct snd_soc_dapm_context *dapm); + +bool snd_soc_dapm_get_idle_bias(struct snd_soc_dapm_context *dapm); +void snd_soc_dapm_set_idle_bias(struct snd_soc_dapm_context *dapm, bool on); + +/* dapm path setup */ +int snd_soc_dapm_new_widgets(struct snd_soc_card *card); +void snd_soc_dapm_free(struct snd_soc_dapm_context *dapm); +void snd_soc_dapm_init(struct snd_soc_dapm_context *dapm, + struct snd_soc_card *card, struct snd_soc_component *component); +int snd_soc_dapm_add_routes(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_route *route, int num); +int snd_soc_dapm_del_routes(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_route *route, int num); +void snd_soc_dapm_free_widget(struct snd_soc_dapm_widget *w); + +/* dapm events */ +void snd_soc_dapm_stream_event(struct snd_soc_pcm_runtime *rtd, int stream, int event); +void snd_soc_dapm_stream_stop(struct snd_soc_pcm_runtime *rtd, int stream); +void snd_soc_dapm_shutdown(struct snd_soc_card *card); + +/* external DAPM widget events */ +int snd_soc_dapm_mixer_update_power(struct snd_soc_dapm_context *dapm, + struct snd_kcontrol *kcontrol, int connect, struct snd_soc_dapm_update *update); +int snd_soc_dapm_mux_update_power(struct snd_soc_dapm_context *dapm, + struct snd_kcontrol *kcontrol, int mux, struct soc_enum *e, + struct snd_soc_dapm_update *update); + +/* dapm sys fs - used by the core */ +extern struct attribute *snd_soc_dapm_dev_attrs[]; +void snd_soc_dapm_debugfs_init(struct snd_soc_dapm_context *dapm, struct dentry *parent); +void snd_soc_dapm_debugfs_pop_time(struct dentry *parent); + +/* dapm audio pin control and status */ +int snd_soc_dapm_enable_pin(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_disable_pin(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_disable_pin_unlocked(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_get_pin_status(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_sync(struct snd_soc_dapm_context *dapm); +int snd_soc_dapm_sync_unlocked(struct snd_soc_dapm_context *dapm); +int snd_soc_dapm_force_enable_pin(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_force_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_ignore_suspend(struct snd_soc_dapm_context *dapm, const char *pin); +bool snd_soc_dapm_pin_has_prefix(struct snd_soc_card *card, const char *pin); +void snd_soc_dapm_mark_endpoints_dirty(struct snd_soc_card *card); + +/* dapm path query */ +int snd_soc_dapm_dai_get_connected_widgets(struct snd_soc_dai *dai, int stream, + struct snd_soc_dapm_widget_list **list, + bool (*custom_stop_condition)(struct snd_soc_dapm_widget *, enum snd_soc_dapm_direction)); +void snd_soc_dapm_dai_free_widgets(struct snd_soc_dapm_widget_list **list); + +struct snd_soc_dapm_context *snd_soc_dapm_kcontrol_to_dapm(struct snd_kcontrol *kcontrol); +struct snd_soc_dapm_widget *snd_soc_dapm_kcontrol_to_widget(struct snd_kcontrol *kcontrol); +struct snd_soc_component *snd_soc_dapm_kcontrol_to_component(struct snd_kcontrol *kcontrol); +unsigned int snd_soc_dapm_kcontrol_get_value(const struct snd_kcontrol *kcontrol); + +int snd_soc_dapm_force_bias_level(struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level); +enum snd_soc_bias_level snd_soc_dapm_get_bias_level(struct snd_soc_dapm_context *dapm); +void snd_soc_dapm_init_bias_level(struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level); + +#define for_each_dapm_widgets(list, i, widget) \ + for ((i) = 0; \ + (i) < list->num_widgets && (widget = list->widgets[i]); \ + (i)++) + +/** + * snd_soc_dapm_widget_for_each_path - Iterates over all paths in the + * specified direction of a widget + * @w: The widget + * @dir: Whether to iterate over the paths where the specified widget is the + * incoming or outgoing widgets + * @p: The path iterator variable + */ +#define snd_soc_dapm_widget_for_each_path(w, dir, p) \ + list_for_each_entry(p, &w->edges[dir], list_node[dir]) + +/** + * snd_soc_dapm_widget_for_each_path_safe - Iterates over all paths in the + * specified direction of a widget + * @w: The widget + * @dir: Whether to iterate over the paths where the specified widget is the + * incoming or outgoing widgets + * @p: The path iterator variable + * @next_p: Temporary storage for the next path + * + * This function works like snd_soc_dapm_widget_for_each_path, expect that + * it is safe to remove the current path from the list while iterating + */ +#define snd_soc_dapm_widget_for_each_path_safe(w, dir, p, next_p) \ + list_for_each_entry_safe(p, next_p, &w->edges[dir], list_node[dir]) + +/** + * snd_soc_dapm_widget_for_each_sink_path - Iterates over all paths leaving a + * widget + * @w: The widget + * @p: The path iterator variable + */ +#define snd_soc_dapm_widget_for_each_sink_path(w, p) \ + snd_soc_dapm_widget_for_each_path(w, SND_SOC_DAPM_DIR_IN, p) + +/** + * snd_soc_dapm_widget_for_each_source_path - Iterates over all paths leading to + * a widget + * @w: The widget + * @p: The path iterator variable + */ +#define snd_soc_dapm_widget_for_each_source_path(w, p) \ + snd_soc_dapm_widget_for_each_path(w, SND_SOC_DAPM_DIR_OUT, p) + +#endif diff --git a/include/sound/soc-dpcm.h b/include/sound/soc-dpcm.h new file mode 100644 index 000000000..af24665e3 --- /dev/null +++ b/include/sound/soc-dpcm.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-dpcm.h -- ALSA SoC Dynamic PCM Support + * + * Author: Liam Girdwood + */ + +#ifndef __LINUX_SND_SOC_DPCM_H +#define __LINUX_SND_SOC_DPCM_H + +#include +#include +#include + +struct snd_soc_pcm_runtime; + +/* + * Types of runtime_update to perform. e.g. originated from FE PCM ops + * or audio route changes triggered by muxes/mixers. + */ +enum snd_soc_dpcm_update { + SND_SOC_DPCM_UPDATE_NO = 0, + SND_SOC_DPCM_UPDATE_BE, + SND_SOC_DPCM_UPDATE_FE, +}; + +/* + * Dynamic PCM Frontend -> Backend link management states. + */ +enum snd_soc_dpcm_link_state { + SND_SOC_DPCM_LINK_STATE_NEW = 0, /* newly created link */ + SND_SOC_DPCM_LINK_STATE_FREE, /* link to be dismantled */ +}; + +/* + * Dynamic PCM Frontend -> Backend link PCM states. + */ +enum snd_soc_dpcm_state { + SND_SOC_DPCM_STATE_NEW = 0, + SND_SOC_DPCM_STATE_OPEN, + SND_SOC_DPCM_STATE_HW_PARAMS, + SND_SOC_DPCM_STATE_PREPARE, + SND_SOC_DPCM_STATE_START, + SND_SOC_DPCM_STATE_STOP, + SND_SOC_DPCM_STATE_PAUSED, + SND_SOC_DPCM_STATE_SUSPEND, + SND_SOC_DPCM_STATE_HW_FREE, + SND_SOC_DPCM_STATE_CLOSE, +}; + +/* + * Dynamic PCM trigger ordering. Triggering flexibility is required as some + * DSPs require triggering before/after their CPU platform and DAIs. + * + * i.e. some clients may want to manually order this call in their PCM + * trigger() whilst others will just use the regular core ordering. + */ +enum snd_soc_dpcm_trigger { + SND_SOC_DPCM_TRIGGER_PRE = 0, + SND_SOC_DPCM_TRIGGER_POST, +}; + +/* + * Dynamic PCM link + * This links together a FE and BE DAI at runtime and stores the link + * state information and the hw_params configuration. + */ +struct snd_soc_dpcm { + /* FE and BE DAIs*/ + struct snd_soc_pcm_runtime *be; + struct snd_soc_pcm_runtime *fe; + + /* link state */ + enum snd_soc_dpcm_link_state state; + + /* list of BE and FE for this DPCM link */ + struct list_head list_be; + struct list_head list_fe; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_state; +#endif +}; + +/* + * Dynamic PCM runtime data. + */ +struct snd_soc_dpcm_runtime { + struct list_head be_clients; + struct list_head fe_clients; + + int users; + struct snd_pcm_hw_params hw_params; + + /* state and update */ + enum snd_soc_dpcm_update runtime_update; + enum snd_soc_dpcm_state state; + + int trigger_pending; /* trigger cmd + 1 if pending, 0 if not */ + + int be_start; /* refcount protected by BE stream pcm lock */ + int be_pause; /* refcount protected by BE stream pcm lock */ + bool fe_pause; /* used to track STOP after PAUSE */ +}; + +#define for_each_dpcm_fe(be, stream, _dpcm) \ + list_for_each_entry(_dpcm, &(be)->dpcm[stream].fe_clients, list_fe) + +#define for_each_dpcm_be(fe, stream, _dpcm) \ + list_for_each_entry(_dpcm, &(fe)->dpcm[stream].be_clients, list_be) +#define for_each_dpcm_be_safe(fe, stream, _dpcm, __dpcm) \ + list_for_each_entry_safe(_dpcm, __dpcm, &(fe)->dpcm[stream].be_clients, list_be) +#define for_each_dpcm_be_rollback(fe, stream, _dpcm) \ + list_for_each_entry_continue_reverse(_dpcm, &(fe)->dpcm[stream].be_clients, list_be) + + +/* get the substream for this BE */ +struct snd_pcm_substream * + snd_soc_dpcm_get_substream(struct snd_soc_pcm_runtime *be, int stream); + +/* update audio routing between PCMs and any DAI links */ +int snd_soc_dpcm_runtime_update(struct snd_soc_card *card); + +#ifdef CONFIG_DEBUG_FS +void soc_dpcm_debugfs_add(struct snd_soc_pcm_runtime *rtd); +#else +static inline void soc_dpcm_debugfs_add(struct snd_soc_pcm_runtime *rtd) +{ +} +#endif + +int dpcm_path_get(struct snd_soc_pcm_runtime *fe, + int stream, struct snd_soc_dapm_widget_list **list_); +void dpcm_path_put(struct snd_soc_dapm_widget_list **list); +int dpcm_add_paths(struct snd_soc_pcm_runtime *fe, int stream, + struct snd_soc_dapm_widget_list **list_); +int dpcm_be_dai_startup(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_be_dai_stop(struct snd_soc_pcm_runtime *fe, int stream, + int do_hw_free, struct snd_soc_dpcm *last); +void dpcm_be_disconnect(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_clear_pending_state(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_be_dai_hw_free(struct snd_soc_pcm_runtime *fe, int stream); +int dpcm_be_dai_hw_params(struct snd_soc_pcm_runtime *fe, int tream); +int dpcm_be_dai_trigger(struct snd_soc_pcm_runtime *fe, int stream, int cmd); +int dpcm_be_dai_prepare(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_dapm_stream_event(struct snd_soc_pcm_runtime *fe, int dir, int event); + +bool dpcm_end_walk_at_be(struct snd_soc_dapm_widget *widget, enum snd_soc_dapm_direction dir); +int widget_in_list(struct snd_soc_dapm_widget_list *list, + struct snd_soc_dapm_widget *widget); + +#define dpcm_be_dai_startup_rollback(fe, stream, last) \ + dpcm_be_dai_stop(fe, stream, 0, last) +#define dpcm_be_dai_startup_unwind(fe, stream) dpcm_be_dai_stop(fe, stream, 0, NULL) +#define dpcm_be_dai_shutdown(fe, stream) dpcm_be_dai_stop(fe, stream, 1, NULL) + +#endif diff --git a/include/sound/soc-jack.h b/include/sound/soc-jack.h new file mode 100644 index 000000000..3a81d4b8c --- /dev/null +++ b/include/sound/soc-jack.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-jack.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto + */ +#ifndef __SOC_JACK_H +#define __SOC_JACK_H + +/** + * struct snd_soc_jack_pin - Describes a pin to update based on jack detection + * + * @pin: name of the pin to update + * @mask: bits to check for in reported jack status + * @invert: if non-zero then pin is enabled when status is not reported + * @list: internal list entry + */ +struct snd_soc_jack_pin { + struct list_head list; + const char *pin; + int mask; + bool invert; +}; + +/** + * struct snd_soc_jack_zone - Describes voltage zones of jack detection + * + * @min_mv: start voltage in mv + * @max_mv: end voltage in mv + * @jack_type: type of jack that is expected for this voltage + * @debounce_time: debounce_time for jack, codec driver should wait for this + * duration before reading the adc for voltages + * @list: internal list entry + */ +struct snd_soc_jack_zone { + unsigned int min_mv; + unsigned int max_mv; + unsigned int jack_type; + unsigned int debounce_time; + struct list_head list; +}; + +/** + * struct snd_soc_jack_gpio - Describes a gpio pin for jack detection + * + * @idx: gpio descriptor index within the function of the GPIO + * consumer device + * @gpiod_dev: GPIO consumer device + * @name: gpio name. Also as connection ID for the GPIO consumer + * device function name lookup + * @report: value to report when jack detected + * @invert: report presence in low state + * @debounce_time: debounce time in ms + * @wake: enable as wake source + * @jack_status_check: callback function which overrides the detection + * to provide more complex checks (eg, reading an + * ADC). + */ +struct snd_soc_jack_gpio { + unsigned int idx; + struct device *gpiod_dev; + const char *name; + int report; + int invert; + int debounce_time; + bool wake; + + /* private: */ + struct snd_soc_jack *jack; + struct delayed_work work; + struct notifier_block pm_notifier; + struct gpio_desc *desc; + + void *data; + /* public: */ + int (*jack_status_check)(void *data); +}; + +struct snd_soc_jack { + struct mutex mutex; + struct snd_jack *jack; + struct snd_soc_card *card; + struct list_head pins; + int status; + struct blocking_notifier_head notifier; + struct list_head jack_zones; +}; + +/* Jack reporting */ +void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask); +int snd_soc_jack_add_pins(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_pin *pins); +void snd_soc_jack_notifier_register(struct snd_soc_jack *jack, + struct notifier_block *nb); +void snd_soc_jack_notifier_unregister(struct snd_soc_jack *jack, + struct notifier_block *nb); +int snd_soc_jack_add_zones(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_zone *zones); +int snd_soc_jack_get_type(struct snd_soc_jack *jack, int micbias_voltage); +#ifdef CONFIG_GPIOLIB +int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios); +int snd_soc_jack_add_gpiods(struct device *gpiod_dev, + struct snd_soc_jack *jack, + int count, struct snd_soc_jack_gpio *gpios); +void snd_soc_jack_free_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios); +#else +static inline int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios) +{ + return 0; +} + +static inline int snd_soc_jack_add_gpiods(struct device *gpiod_dev, + struct snd_soc_jack *jack, + int count, + struct snd_soc_jack_gpio *gpios) +{ + return 0; +} + +static inline void snd_soc_jack_free_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios) +{ +} +#endif + +#endif /* __SOC_JACK_H */ diff --git a/include/sound/soc-link.h b/include/sound/soc-link.h new file mode 100644 index 000000000..9314cde17 --- /dev/null +++ b/include/sound/soc-link.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-link.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto + */ +#ifndef __SOC_LINK_H +#define __SOC_LINK_H + +int snd_soc_link_init(struct snd_soc_pcm_runtime *rtd); +void snd_soc_link_exit(struct snd_soc_pcm_runtime *rtd); +int snd_soc_link_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + +int snd_soc_link_startup(struct snd_pcm_substream *substream); +void snd_soc_link_shutdown(struct snd_pcm_substream *substream, + int rollback); +int snd_soc_link_prepare(struct snd_pcm_substream *substream); +int snd_soc_link_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +void snd_soc_link_hw_free(struct snd_pcm_substream *substream, + int rollback); + +int snd_soc_link_trigger(struct snd_pcm_substream *substream, int cmd, + int rollback); +int snd_soc_link_compr_startup(struct snd_compr_stream *cstream); +void snd_soc_link_compr_shutdown(struct snd_compr_stream *cstream, + int rollback); +int snd_soc_link_compr_set_params(struct snd_compr_stream *cstream); + +#endif /* __SOC_LINK_H */ diff --git a/include/sound/soc-topology.h b/include/sound/soc-topology.h new file mode 100644 index 000000000..1eedd203a --- /dev/null +++ b/include/sound/soc-topology.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-topology.h -- ALSA SoC Firmware Controls and DAPM + * + * Copyright (C) 2012 Texas Instruments Inc. + * Copyright (C) 2015 Intel Corporation. + * + * Simple file API to load FW that includes mixers, coefficients, DAPM graphs, + * algorithms, equalisers, DAIs, widgets, FE caps, BE caps, codec link caps etc. + */ + +#ifndef __LINUX_SND_SOC_TPLG_H +#define __LINUX_SND_SOC_TPLG_H + +#include +#include + +struct firmware; +struct snd_kcontrol; +struct snd_soc_tplg_pcm_be; +struct snd_ctl_elem_value; +struct snd_ctl_elem_info; +struct snd_soc_dapm_widget; +struct snd_soc_component; +struct snd_soc_tplg_pcm_fe; +struct snd_soc_dapm_context; +struct snd_soc_card; +struct snd_kcontrol_new; +struct snd_soc_dai_link; +struct snd_soc_dai_driver; +struct snd_soc_dai; +struct snd_soc_dapm_route; + +/* dynamic object type */ +enum snd_soc_dobj_type { + SND_SOC_DOBJ_NONE = 0, /* object is not dynamic */ + SND_SOC_DOBJ_MIXER, + SND_SOC_DOBJ_BYTES, + SND_SOC_DOBJ_ENUM, + SND_SOC_DOBJ_GRAPH, + SND_SOC_DOBJ_WIDGET, + SND_SOC_DOBJ_DAI_LINK, + SND_SOC_DOBJ_PCM, + SND_SOC_DOBJ_CODEC_LINK, + SND_SOC_DOBJ_BACKEND_LINK, +}; + +/* dynamic control object */ +struct snd_soc_dobj_control { + struct snd_kcontrol *kcontrol; + char **dtexts; + unsigned long *dvalues; +}; + +/* dynamic widget object */ +struct snd_soc_dobj_widget { + unsigned int *kcontrol_type; /* kcontrol type: mixer, enum, bytes */ +}; + +/* generic dynamic object - all dynamic objects belong to this struct */ +struct snd_soc_dobj { + enum snd_soc_dobj_type type; + unsigned int index; /* objects can belong in different groups */ + struct list_head list; + int (*unload)(struct snd_soc_component *comp, struct snd_soc_dobj *dobj); + union { + struct snd_soc_dobj_control control; + struct snd_soc_dobj_widget widget; + }; + void *private; /* core does not touch this */ +}; + +/* + * Kcontrol operations - used to map handlers onto firmware based controls. + */ +struct snd_soc_tplg_kcontrol_ops { + u32 id; + int (*get)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*put)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*info)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +}; + +/* Bytes ext operations, for TLV byte controls */ +struct snd_soc_tplg_bytes_ext_ops { + u32 id; + int (*get)(struct snd_kcontrol *kcontrol, unsigned int __user *bytes, + unsigned int size); + int (*put)(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, unsigned int size); +}; + +/* + * DAPM widget event handlers - used to map handlers onto widgets. + */ +struct snd_soc_tplg_widget_events { + u16 type; + int (*event_handler)(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *k, int event); +}; + +/* + * Public API - Used by component drivers to load and unload dynamic objects + * and their resources. + */ +struct snd_soc_tplg_ops { + + /* external kcontrol init - used for any driver specific init */ + int (*control_load)(struct snd_soc_component *, int index, + struct snd_kcontrol_new *, struct snd_soc_tplg_ctl_hdr *); + int (*control_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* DAPM graph route element loading and unloading */ + int (*dapm_route_load)(struct snd_soc_component *, int index, + struct snd_soc_dapm_route *route); + int (*dapm_route_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* external widget init - used for any driver specific init */ + int (*widget_load)(struct snd_soc_component *, int index, + struct snd_soc_dapm_widget *, + struct snd_soc_tplg_dapm_widget *); + int (*widget_ready)(struct snd_soc_component *, int index, + struct snd_soc_dapm_widget *, + struct snd_soc_tplg_dapm_widget *); + int (*widget_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* FE DAI - used for any driver specific init */ + int (*dai_load)(struct snd_soc_component *, int index, + struct snd_soc_dai_driver *dai_drv, + struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); + + int (*dai_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* DAI link - used for any driver specific init */ + int (*link_load)(struct snd_soc_component *, int index, + struct snd_soc_dai_link *link, + struct snd_soc_tplg_link_config *cfg); + int (*link_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* callback to handle vendor bespoke data */ + int (*vendor_load)(struct snd_soc_component *, int index, + struct snd_soc_tplg_hdr *); + int (*vendor_unload)(struct snd_soc_component *, + struct snd_soc_tplg_hdr *); + + /* completion - called at completion of firmware loading */ + int (*complete)(struct snd_soc_component *comp); + + /* manifest - optional to inform component of manifest */ + int (*manifest)(struct snd_soc_component *, int index, + struct snd_soc_tplg_manifest *); + + /* vendor specific kcontrol handlers available for binding */ + const struct snd_soc_tplg_kcontrol_ops *io_ops; + int io_ops_count; + + /* vendor specific bytes ext handlers available for binding */ + const struct snd_soc_tplg_bytes_ext_ops *bytes_ext_ops; + int bytes_ext_ops_count; +}; + +#ifdef CONFIG_SND_SOC_TOPOLOGY + +/* gets a pointer to data from the firmware block header */ +static inline const void *snd_soc_tplg_get_data(struct snd_soc_tplg_hdr *hdr) +{ + const void *ptr = hdr; + + return ptr + sizeof(*hdr); +} + +/* Dynamic Object loading and removal for component drivers */ +int snd_soc_tplg_component_load(struct snd_soc_component *comp, + const struct snd_soc_tplg_ops *ops, const struct firmware *fw); +int snd_soc_tplg_component_remove(struct snd_soc_component *comp); + +/* Binds event handlers to dynamic widgets */ +int snd_soc_tplg_widget_bind_event(struct snd_soc_dapm_widget *w, + const struct snd_soc_tplg_widget_events *events, int num_events, + u16 event_type); + +#else + +static inline int snd_soc_tplg_component_remove(struct snd_soc_component *comp) +{ + return 0; +} + +#endif + +#endif diff --git a/include/sound/soc-usb.h b/include/sound/soc-usb.h new file mode 100644 index 000000000..124acb193 --- /dev/null +++ b/include/sound/soc-usb.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __LINUX_SND_SOC_USB_H +#define __LINUX_SND_SOC_USB_H + +#include + +enum snd_soc_usb_kctl { + SND_SOC_USB_KCTL_CARD_ROUTE, + SND_SOC_USB_KCTL_PCM_ROUTE, +}; + +/** + * struct snd_soc_usb_device - SoC USB representation of a USB sound device + * @card_idx: sound card index associated with USB device + * @chip_idx: USB sound chip array index + * @cpcm_idx: capture PCM index array associated with USB device + * @ppcm_idx: playback PCM index array associated with USB device + * @num_capture: number of capture streams + * @num_playback: number of playback streams + * @list: list head for SoC USB devices + **/ +struct snd_soc_usb_device { + int card_idx; + int chip_idx; + + /* PCM index arrays */ + unsigned int *cpcm_idx; /* TODO: capture path is not tested yet */ + unsigned int *ppcm_idx; + int num_capture; /* TODO: capture path is not tested yet */ + int num_playback; + + struct list_head list; +}; + +/** + * struct snd_soc_usb - representation of a SoC USB backend entity + * @list: list head for SND SOC struct list + * @component: reference to ASoC component + * @connection_status_cb: callback to notify connection events + * @update_offload_route_info: callback to fetch mapped ASoC card and pcm + * device pair. This is unrelated to the concept + * of DAPM route. The "route" argument carries + * an array used for a kcontrol output for either + * the card or pcm index. "path" determines the + * which entry to look for. (ie mapped card or pcm) + * @priv_data: driver data + **/ +struct snd_soc_usb { + struct list_head list; + struct snd_soc_component *component; + int (*connection_status_cb)(struct snd_soc_usb *usb, + struct snd_soc_usb_device *sdev, + bool connected); + int (*update_offload_route_info)(struct snd_soc_component *component, + int card, int pcm, int direction, + enum snd_soc_usb_kctl path, + long *route); + void *priv_data; +}; + +#if IS_ENABLED(CONFIG_SND_SOC_USB) +int snd_soc_usb_find_supported_format(int card_idx, + struct snd_pcm_hw_params *params, + int direction); + +int snd_soc_usb_connect(struct device *usbdev, struct snd_soc_usb_device *sdev); +int snd_soc_usb_disconnect(struct device *usbdev, struct snd_soc_usb_device *sdev); +void *snd_soc_usb_find_priv_data(struct device *usbdev); + +int snd_soc_usb_setup_offload_jack(struct snd_soc_component *component, + struct snd_soc_jack *jack); +int snd_soc_usb_update_offload_route(struct device *dev, int card, int pcm, + int direction, enum snd_soc_usb_kctl path, + long *route); + +struct snd_soc_usb *snd_soc_usb_allocate_port(struct snd_soc_component *component, + void *data); +void snd_soc_usb_free_port(struct snd_soc_usb *usb); +void snd_soc_usb_add_port(struct snd_soc_usb *usb); +void snd_soc_usb_remove_port(struct snd_soc_usb *usb); +#else +static inline int +snd_soc_usb_find_supported_format(int card_idx, struct snd_pcm_hw_params *params, + int direction) +{ + return -EINVAL; +} + +static inline int snd_soc_usb_connect(struct device *usbdev, + struct snd_soc_usb_device *sdev) +{ + return -ENODEV; +} + +static inline int snd_soc_usb_disconnect(struct device *usbdev, + struct snd_soc_usb_device *sdev) +{ + return -EINVAL; +} + +static inline void *snd_soc_usb_find_priv_data(struct device *usbdev) +{ + return NULL; +} + +static inline int snd_soc_usb_setup_offload_jack(struct snd_soc_component *component, + struct snd_soc_jack *jack) +{ + return 0; +} + +static int snd_soc_usb_update_offload_route(struct device *dev, int card, int pcm, + int direction, enum snd_soc_usb_kctl path, + long *route) +{ + return -ENODEV; +} + +static inline struct snd_soc_usb * +snd_soc_usb_allocate_port(struct snd_soc_component *component, void *data) +{ + return ERR_PTR(-ENOMEM); +} + +static inline void snd_soc_usb_free_port(struct snd_soc_usb *usb) +{ } + +static inline void snd_soc_usb_add_port(struct snd_soc_usb *usb) +{ } + +static inline void snd_soc_usb_remove_port(struct snd_soc_usb *usb) +{ } +#endif /* IS_ENABLED(CONFIG_SND_SOC_USB) */ +#endif /*__LINUX_SND_SOC_USB_H */ diff --git a/include/sound/soc.h b/include/sound/soc.h new file mode 100644 index 000000000..f46b2bc2a --- /dev/null +++ b/include/sound/soc.h @@ -0,0 +1,1553 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc.h -- ALSA SoC Layer + * + * Author: Liam Girdwood + * Created: Aug 11th 2005 + * Copyright: Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_SOC_H +#define __LINUX_SND_SOC_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +struct module; +struct platform_device; + +/* For the current users of sound/soc.h to avoid build issues */ +#include +#include + +/* + * Convenience kcontrol builders + */ +#define SOC_DOUBLE_S_VALUE(xreg, shift_left, shift_right, xmin, xmax, xsign_bit, \ + xinvert, xautodisable) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, .shift = shift_left, \ + .rshift = shift_right, .min = xmin, .max = xmax, \ + .sign_bit = xsign_bit, .invert = xinvert, .autodisable = xautodisable}) +#define SOC_DOUBLE_VALUE(xreg, shift_left, shift_right, xmin, xmax, xinvert, xautodisable) \ + SOC_DOUBLE_S_VALUE(xreg, shift_left, shift_right, xmin, xmax, 0, xinvert, \ + xautodisable) +#define SOC_SINGLE_VALUE(xreg, xshift, xmin, xmax, xinvert, xautodisable) \ + SOC_DOUBLE_VALUE(xreg, xshift, xshift, xmin, xmax, xinvert, xautodisable) +#define SOC_DOUBLE_R_S_VALUE(xlreg, xrreg, xshift, xmin, xmax, xsign_bit, xinvert) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ + .max = xmax, .min = xmin, .sign_bit = xsign_bit, \ + .invert = xinvert}) +#define SOC_DOUBLE_R_VALUE(xlreg, xrreg, xshift, xmin, xmax, xinvert) \ + SOC_DOUBLE_R_S_VALUE(xlreg, xrreg, xshift, xmin, xmax, 0, xinvert) + +#define SOC_SINGLE(xname, reg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, 0, max, invert, 0) } +#define SOC_SINGLE_RANGE(xname, xreg, xshift, xmin, xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .put = snd_soc_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmin, xmax, xinvert, 0) } +#define SOC_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, 0, max, invert, 0) } +#define SOC_SINGLE_SX_TLV(xname, xreg, xshift, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array),\ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx,\ + .put = snd_soc_put_volsw_sx, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmin, xmax, 0, 0) } +#define SOC_SINGLE_RANGE_TLV(xname, xreg, xshift, xmin, xmax, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmin, xmax, xinvert, 0) } +#define SOC_DOUBLE(xname, reg, shift_left, shift_right, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ + 0, max, invert, 0) } +#define SOC_DOUBLE_STS(xname, reg, shift_left, shift_right, max, invert) \ +{ \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .access = SNDRV_CTL_ELEM_ACCESS_READ | \ + SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ + .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ + 0, max, invert, 0) } +#define SOC_DOUBLE_R(xname, reg_left, reg_right, xshift, xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + 0, xmax, xinvert) } +#define SOC_DOUBLE_R_RANGE(xname, reg_left, reg_right, xshift, xmin, \ + xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, \ + xshift, xmin, xmax, xinvert) } +#define SOC_DOUBLE_TLV(xname, reg, shift_left, shift_right, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ + 0, max, invert, 0) } +#define SOC_DOUBLE_SX_TLV(xname, xreg, shift_left, shift_right, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx, \ + .put = snd_soc_put_volsw_sx, \ + .private_value = SOC_DOUBLE_VALUE(xreg, shift_left, shift_right, \ + xmin, xmax, 0, 0) } +#define SOC_DOUBLE_RANGE_TLV(xname, xreg, xshift_left, xshift_right, xmin, xmax, \ + xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_VALUE(xreg, xshift_left, xshift_right, \ + xmin, xmax, xinvert, 0) } +#define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + 0, xmax, xinvert) } +#define SOC_DOUBLE_R_RANGE_TLV(xname, reg_left, reg_right, xshift, xmin, \ + xmax, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, \ + xshift, xmin, xmax, xinvert) } +#define SOC_DOUBLE_R_SX_TLV(xname, xreg, xrreg, xshift, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx, \ + .put = snd_soc_put_volsw_sx, \ + .private_value = SOC_DOUBLE_R_VALUE(xreg, xrreg, xshift, xmin, xmax, 0) } +#define SOC_DOUBLE_R_S_TLV(xname, reg_left, reg_right, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_S_VALUE(reg_left, reg_right, xshift, \ + xmin, xmax, xsign_bit, xinvert) } +#define SOC_SINGLE_S_TLV(xname, xreg, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) \ + SOC_DOUBLE_R_S_TLV(xname, xreg, xreg, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) +#define SOC_SINGLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, \ + .min = xmin, .max = xmax, \ + .sign_bit = 7,} } +#define SOC_DOUBLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_S_VALUE(xreg, 0, 8, xmin, xmax, 7, 0, 0) } +#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xitems, xtexts) \ +{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ + .items = xitems, .texts = xtexts, \ + .mask = xitems ? roundup_pow_of_two(xitems) - 1 : 0} +#define SOC_ENUM_SINGLE(xreg, xshift, xitems, xtexts) \ + SOC_ENUM_DOUBLE(xreg, xshift, xshift, xitems, xtexts) +#define SOC_ENUM_SINGLE_EXT(xitems, xtexts) \ +{ .items = xitems, .texts = xtexts } +#define SOC_VALUE_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xitems, xtexts, xvalues) \ +{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ + .mask = xmask, .items = xitems, .texts = xtexts, .values = xvalues} +#define SOC_VALUE_ENUM_SINGLE(xreg, xshift, xmask, xitems, xtexts, xvalues) \ + SOC_VALUE_ENUM_DOUBLE(xreg, xshift, xshift, xmask, xitems, xtexts, xvalues) +#define SOC_VALUE_ENUM_SINGLE_AUTODISABLE(xreg, xshift, xmask, xitems, xtexts, xvalues) \ +{ .reg = xreg, .shift_l = xshift, .shift_r = xshift, \ + .mask = xmask, .items = xitems, .texts = xtexts, \ + .values = xvalues, .autodisable = 1} +#define SOC_ENUM_SINGLE_VIRT(xitems, xtexts) \ + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, xitems, xtexts) +#define SOC_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_get_enum_double, .put = snd_soc_put_enum_double, \ + .private_value = (unsigned long)&xenum } +#define SOC_SINGLE_EXT(xname, xreg, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, 0, xmax, xinvert, 0) } +#define SOC_DOUBLE_EXT(xname, reg, shift_left, shift_right, max, invert,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = \ + SOC_DOUBLE_VALUE(reg, shift_left, shift_right, 0, max, invert, 0) } +#define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + 0, xmax, xinvert) } +#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, 0, xmax, xinvert, 0) } +#define SOC_SINGLE_RANGE_EXT_TLV(xname, xreg, xshift, xmin, xmax, xinvert, \ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmin, xmax, xinvert, 0) } +#define SOC_DOUBLE_EXT_TLV(xname, xreg, shift_left, shift_right, xmax, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_VALUE(xreg, shift_left, shift_right, \ + 0, xmax, xinvert, 0) } +#define SOC_DOUBLE_R_EXT_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + 0, xmax, xinvert) } +#define SOC_DOUBLE_R_S_EXT_TLV(xname, reg_left, reg_right, xshift, xmin, xmax, \ + xsign_bit, xinvert, xhandler_get, xhandler_put, \ + tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_R_S_VALUE(reg_left, reg_right, xshift, \ + xmin, xmax, xsign_bit, xinvert) } +#define SOC_SINGLE_S_EXT_TLV(xname, xreg, xshift, xmin, xmax, \ + xsign_bit, xinvert, xhandler_get, xhandler_put, \ + tlv_array) \ + SOC_DOUBLE_R_S_EXT_TLV(xname, xreg, xreg, xshift, xmin, xmax, \ + xsign_bit, xinvert, xhandler_get, xhandler_put, \ + tlv_array) +#define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_bool_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = xdata } +#define SOC_SINGLE_BOOL_EXT_ACC(xname, xdata, xhandler_get, xhandler_put, xaccess) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = xaccess, \ + .info = snd_soc_info_bool_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = xdata } +#define SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&xenum } +#define SOC_VALUE_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) \ + SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) + +#define SOC_ENUM_EXT_ACC(xname, xenum, xhandler_get, xhandler_put, xaccess) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = xaccess, \ + .info = snd_soc_info_enum_double, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&xenum } + +#define SND_SOC_BYTES(xname, xbase, xregs) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = snd_soc_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } +#define SND_SOC_BYTES_E(xname, xbase, xregs, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = xhandler_get, \ + .put = xhandler_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } +#define SND_SOC_BYTES_E_ACC(xname, xbase, xregs, xhandler_get, xhandler_put, xaccess) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = xaccess, \ + .info = snd_soc_bytes_info, .get = xhandler_get, \ + .put = xhandler_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } + +#define SND_SOC_BYTES_MASK(xname, xbase, xregs, xmask) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = snd_soc_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs, \ + .mask = xmask }) } + +/* + * SND_SOC_BYTES_EXT is deprecated, please USE SND_SOC_BYTES_TLV instead + */ +#define SND_SOC_BYTES_EXT(xname, xcount, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&(struct soc_bytes_ext) \ + {.max = xcount} } +#define SND_SOC_BYTES_TLV(xname, xcount, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE | \ + SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ + .tlv.c = (snd_soc_bytes_tlv_callback), \ + .info = snd_soc_bytes_info_ext, \ + .private_value = (unsigned long)&(struct soc_bytes_ext) \ + {.max = xcount, .get = xhandler_get, .put = xhandler_put, } } +#define SOC_SINGLE_XR_SX(xname, xregbase, xregcount, xnbits, \ + xmin, xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_xr_sx, .get = snd_soc_get_xr_sx, \ + .put = snd_soc_put_xr_sx, \ + .private_value = (unsigned long)&(struct soc_mreg_control) \ + {.regbase = xregbase, .regcount = xregcount, .nbits = xnbits, \ + .invert = xinvert, .min = xmin, .max = xmax} } + +#define SOC_SINGLE_STROBE(xname, xreg, xshift, xinvert) \ + SOC_SINGLE_EXT(xname, xreg, xshift, 1, xinvert, \ + snd_soc_get_strobe, snd_soc_put_strobe) + +/* + * Simplified versions of above macros, declaring a struct and calculating + * ARRAY_SIZE internally + */ +#define SOC_ENUM_DOUBLE_DECL(name, xreg, xshift_l, xshift_r, xtexts) \ + const struct soc_enum name = SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, \ + ARRAY_SIZE(xtexts), xtexts) +#define SOC_ENUM_SINGLE_DECL(name, xreg, xshift, xtexts) \ + SOC_ENUM_DOUBLE_DECL(name, xreg, xshift, xshift, xtexts) +#define SOC_ENUM_SINGLE_EXT_DECL(name, xtexts) \ + const struct soc_enum name = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(xtexts), xtexts) +#define SOC_VALUE_ENUM_DOUBLE_DECL(name, xreg, xshift_l, xshift_r, xmask, xtexts, xvalues) \ + const struct soc_enum name = SOC_VALUE_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, \ + ARRAY_SIZE(xtexts), xtexts, xvalues) +#define SOC_VALUE_ENUM_SINGLE_DECL(name, xreg, xshift, xmask, xtexts, xvalues) \ + SOC_VALUE_ENUM_DOUBLE_DECL(name, xreg, xshift, xshift, xmask, xtexts, xvalues) + +#define SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(name, xreg, xshift, xmask, xtexts, xvalues) \ + const struct soc_enum name = SOC_VALUE_ENUM_SINGLE_AUTODISABLE(xreg, \ + xshift, xmask, ARRAY_SIZE(xtexts), xtexts, xvalues) + +#define SOC_ENUM_SINGLE_VIRT_DECL(name, xtexts) \ + const struct soc_enum name = SOC_ENUM_SINGLE_VIRT(ARRAY_SIZE(xtexts), xtexts) + +struct snd_soc_card; +struct snd_soc_pcm_runtime; +struct snd_soc_dai; +struct snd_soc_dai_driver; +struct snd_soc_dai_link; +struct snd_soc_component; +struct snd_soc_component_driver; +struct snd_soc_jack; +struct snd_soc_jack_pin; + +#include +#include +#include + +int snd_soc_register_card(struct snd_soc_card *card); +void snd_soc_unregister_card(struct snd_soc_card *card); +int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card); +#define devm_snd_soc_register_deferrable_card(d, c) devm_snd_soc_register_card(d, c) +#ifdef CONFIG_PM_SLEEP +int snd_soc_suspend(struct device *dev); +int snd_soc_resume(struct device *dev); +#else +static inline int snd_soc_suspend(struct device *dev) +{ + return 0; +} + +static inline int snd_soc_resume(struct device *dev) +{ + return 0; +} +#endif +int snd_soc_poweroff(struct device *dev); +int snd_soc_register_component_c(struct snd_soc_component *component, + const struct snd_soc_component_driver *component_driver, + struct snd_soc_dai_driver *dai_drv, int num_dai); +int snd_soc_register_component_d(struct device *dev, + const struct snd_soc_component_driver *component_driver, + struct snd_soc_dai_driver *dai_drv, int num_dai); +#define snd_soc_register_component(x, ...) _Generic((x), \ +struct device * : snd_soc_register_component_d, \ +struct snd_soc_component * : snd_soc_register_component_c)(x, __VA_ARGS__) + +int devm_snd_soc_register_component(struct device *dev, + const struct snd_soc_component_driver *component_driver, + struct snd_soc_dai_driver *dai_drv, int num_dai); +#define snd_soc_unregister_component(dev) snd_soc_unregister_component_by_driver(dev, NULL) +void snd_soc_unregister_component_by_driver(struct device *dev, + const struct snd_soc_component_driver *component_driver); +struct snd_soc_component *snd_soc_lookup_component_nolocked(struct device *dev, + const char *driver_name); +struct snd_soc_component *snd_soc_lookup_component(struct device *dev, + const char *driver_name); +struct snd_soc_component *snd_soc_lookup_component_by_name(const char *component_name); + +int soc_new_pcm(struct snd_soc_pcm_runtime *rtd); +#ifdef CONFIG_SND_SOC_COMPRESS +int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd); +#else +static inline int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd) +{ + return 0; +} +#endif + +struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); + +bool snd_soc_runtime_ignore_pmdown_time(struct snd_soc_pcm_runtime *rtd); + +void snd_soc_runtime_action(struct snd_soc_pcm_runtime *rtd, + int stream, int action); +static inline void snd_soc_runtime_activate(struct snd_soc_pcm_runtime *rtd, + int stream) +{ + snd_soc_runtime_action(rtd, stream, 1); +} +static inline void snd_soc_runtime_deactivate(struct snd_soc_pcm_runtime *rtd, + int stream) +{ + snd_soc_runtime_action(rtd, stream, -1); +} + +int snd_soc_runtime_calc_hw(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hardware *hw, int stream); + +int snd_soc_runtime_set_dai_fmt(struct snd_soc_pcm_runtime *rtd, + unsigned int dai_fmt); + +/* Utility functions to get clock rates from various things */ +int snd_soc_calc_frame_size(int sample_size, int channels, int tdm_slots); +int snd_soc_params_to_frame_size(const struct snd_pcm_hw_params *params); +int snd_soc_calc_bclk(int fs, int sample_size, int channels, int tdm_slots); +int snd_soc_params_to_bclk(const struct snd_pcm_hw_params *parms); +int snd_soc_tdm_params_to_bclk(const struct snd_pcm_hw_params *params, + int tdm_width, int tdm_slots, int slot_multiple); +int snd_soc_ret(const struct device *dev, int ret, const char *fmt, ...); + +/* set runtime hw params */ +static inline int snd_soc_set_runtime_hwparams(struct snd_pcm_substream *substream, + const struct snd_pcm_hardware *hw) +{ + substream->runtime->hw = *hw; + + return 0; +} + +struct snd_ac97 *snd_soc_alloc_ac97_component(struct snd_soc_component *component); +struct snd_ac97 *snd_soc_new_ac97_component(struct snd_soc_component *component, + unsigned int id, unsigned int id_mask); +void snd_soc_free_ac97_component(struct snd_ac97 *ac97); + +#ifdef CONFIG_SND_SOC_AC97_BUS +int snd_soc_set_ac97_ops(struct snd_ac97_bus_ops *ops); +int snd_soc_set_ac97_ops_of_reset(struct snd_ac97_bus_ops *ops, + struct platform_device *pdev); + +extern struct snd_ac97_bus_ops *soc_ac97_ops; +#else +static inline int snd_soc_set_ac97_ops_of_reset(struct snd_ac97_bus_ops *ops, + struct platform_device *pdev) +{ + return 0; +} + +static inline int snd_soc_set_ac97_ops(struct snd_ac97_bus_ops *ops) +{ + return 0; +} +#endif + +/* + *Controls + */ +struct snd_kcontrol *snd_soc_cnew(const struct snd_kcontrol_new *_template, + void *data, const char *long_name, + const char *prefix); +int snd_soc_add_component_controls(struct snd_soc_component *component, + const struct snd_kcontrol_new *controls, unsigned int num_controls); +int snd_soc_add_card_controls(struct snd_soc_card *soc_card, + const struct snd_kcontrol_new *controls, int num_controls); +int snd_soc_add_dai_controls(struct snd_soc_dai *dai, + const struct snd_kcontrol_new *controls, int num_controls); +int snd_soc_info_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_get_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_info_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_info_volsw_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +#define snd_soc_info_bool_ext snd_ctl_boolean_mono_info +int snd_soc_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +#define snd_soc_get_volsw_2r snd_soc_get_volsw +#define snd_soc_put_volsw_2r snd_soc_put_volsw +int snd_soc_get_volsw_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_volsw_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_limit_volume(struct snd_soc_card *card, + const char *name, int max); +int snd_soc_bytes_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_bytes_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_bytes_info_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *ucontrol); +int snd_soc_bytes_tlv_callback(struct snd_kcontrol *kcontrol, int op_flag, + unsigned int size, unsigned int __user *tlv); +int snd_soc_info_xr_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_get_xr_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_xr_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_get_strobe(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_strobe(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +enum snd_soc_trigger_order { + /* start stop */ + SND_SOC_TRIGGER_ORDER_DEFAULT = 0, /* Link->Component->DAI DAI->Component->Link */ + SND_SOC_TRIGGER_ORDER_LDC, /* Link->DAI->Component Component->DAI->Link */ + + SND_SOC_TRIGGER_ORDER_MAX, +}; + +/* SoC PCM stream information */ +struct snd_soc_pcm_stream { + const char *stream_name; + u64 formats; /* SNDRV_PCM_FMTBIT_* */ + u32 subformats; /* for S32_LE format, SNDRV_PCM_SUBFMTBIT_* */ + unsigned int rates; /* SNDRV_PCM_RATE_* */ + unsigned int rate_min; /* min rate */ + unsigned int rate_max; /* max rate */ + unsigned int channels_min; /* min channels */ + unsigned int channels_max; /* max channels */ + unsigned int sig_bits; /* number of bits of content */ +}; + +/* SoC audio ops */ +struct snd_soc_ops { + int (*startup)(struct snd_pcm_substream *); + void (*shutdown)(struct snd_pcm_substream *); + int (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *); + int (*hw_free)(struct snd_pcm_substream *); + int (*prepare)(struct snd_pcm_substream *); + int (*trigger)(struct snd_pcm_substream *, int); +}; + +struct snd_soc_compr_ops { + int (*startup)(struct snd_compr_stream *); + void (*shutdown)(struct snd_compr_stream *); + int (*set_params)(struct snd_compr_stream *); +}; + +struct snd_soc_component* +snd_soc_rtdcom_lookup(struct snd_soc_pcm_runtime *rtd, + const char *driver_name); + +struct snd_soc_dai_link_component { + const char *name; + struct device_node *of_node; + const char *dai_name; + const struct of_phandle_args *dai_args; + + /* + * Extra format = SND_SOC_DAIFMT_Bx_Fx + * + * [Note] it is Bx_Fx base, not CBx_CFx + * + * It will be used with dai_link->dai_fmt + * see + * snd_soc_runtime_set_dai_fmt() + */ + unsigned int ext_fmt; +}; + +/* + * [dai_link->ch_maps Image sample] + * + *------------------------- + * CPU0 <---> Codec0 + * + * ch-map[0].cpu = 0 ch-map[0].codec = 0 + * + *------------------------- + * CPU0 <---> Codec0 + * CPU1 <---> Codec1 + * CPU2 <---> Codec2 + * + * ch-map[0].cpu = 0 ch-map[0].codec = 0 + * ch-map[1].cpu = 1 ch-map[1].codec = 1 + * ch-map[2].cpu = 2 ch-map[2].codec = 2 + * + *------------------------- + * CPU0 <---> Codec0 + * CPU1 <-+-> Codec1 + * CPU2 <-/ + * + * ch-map[0].cpu = 0 ch-map[0].codec = 0 + * ch-map[1].cpu = 1 ch-map[1].codec = 1 + * ch-map[2].cpu = 2 ch-map[2].codec = 1 + * + *------------------------- + * CPU0 <---> Codec0 + * CPU1 <-+-> Codec1 + * \-> Codec2 + * + * ch-map[0].cpu = 0 ch-map[0].codec = 0 + * ch-map[1].cpu = 1 ch-map[1].codec = 1 + * ch-map[2].cpu = 1 ch-map[2].codec = 2 + * + */ +struct snd_soc_dai_link_ch_map { + unsigned int cpu; + unsigned int codec; + unsigned int ch_mask; +}; + +struct snd_soc_dai_link { + /* config - must be set by machine driver */ + const char *name; /* Codec name */ + const char *stream_name; /* Stream name */ + + /* + * You MAY specify the link's CPU-side device, either by device name, + * or by DT/OF node, but not both. If this information is omitted, + * the CPU-side DAI is matched using .cpu_dai_name only, which hence + * must be globally unique. These fields are currently typically used + * only for codec to codec links, or systems using device tree. + */ + /* + * You MAY specify the DAI name of the CPU DAI. If this information is + * omitted, the CPU-side DAI is matched using .cpu_name/.cpu_of_node + * only, which only works well when that device exposes a single DAI. + */ + struct snd_soc_dai_link_component *cpus; + unsigned int num_cpus; + + /* + * You MUST specify the link's codec, either by device name, or by + * DT/OF node, but not both. + */ + /* You MUST specify the DAI name within the codec */ + struct snd_soc_dai_link_component *codecs; + unsigned int num_codecs; + + /* num_ch_maps = max(num_cpu, num_codecs) */ + struct snd_soc_dai_link_ch_map *ch_maps; + + /* + * You MAY specify the link's platform/PCM/DMA driver, either by + * device name, or by DT/OF node, but not both. Some forms of link + * do not need a platform. In such case, platforms are not mandatory. + */ + struct snd_soc_dai_link_component *platforms; + unsigned int num_platforms; + + int id; /* optional ID for machine driver link identification */ + + /* + * for Codec2Codec + */ + const struct snd_soc_pcm_stream *c2c_params; + unsigned int num_c2c_params; + + unsigned int dai_fmt; /* format to set on init */ + + enum snd_soc_dpcm_trigger trigger[2]; /* trigger type for DPCM */ + + /* codec/machine specific init - e.g. add machine controls */ + int (*init)(struct snd_soc_pcm_runtime *rtd); + + /* codec/machine specific exit - dual of init() */ + void (*exit)(struct snd_soc_pcm_runtime *rtd); + + /* optional hw_params re-writing for BE and FE sync */ + int (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + + /* machine stream operations */ + const struct snd_soc_ops *ops; + const struct snd_soc_compr_ops *compr_ops; + + /* + * soc_pcm_trigger() start/stop sequence. + * see also + * snd_soc_component_driver + * soc_pcm_trigger() + */ + enum snd_soc_trigger_order trigger_start; + enum snd_soc_trigger_order trigger_stop; + + /* Mark this pcm with non atomic ops */ + unsigned int nonatomic:1; + + /* For unidirectional dai links */ + unsigned int playback_only:1; + unsigned int capture_only:1; + + /* Keep DAI active over suspend */ + unsigned int ignore_suspend:1; + + /* Symmetry requirements */ + unsigned int symmetric_rate:1; + unsigned int symmetric_channels:1; + unsigned int symmetric_sample_bits:1; + + /* Do not create a PCM for this DAI link (Backend link) */ + unsigned int no_pcm:1; + + /* This DAI link can route to other DAI links at runtime (Frontend)*/ + unsigned int dynamic:1; + + /* DPCM used FE & BE merged format */ + unsigned int dpcm_merged_format:1; + /* DPCM used FE & BE merged channel */ + unsigned int dpcm_merged_chan:1; + /* DPCM used FE & BE merged rate */ + unsigned int dpcm_merged_rate:1; + + /* pmdown_time is ignored at stop */ + unsigned int ignore_pmdown_time:1; + + /* Do not create a PCM for this DAI link (Backend link) */ + unsigned int ignore:1; + +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; /* For topology */ +#endif +}; + +static inline int snd_soc_link_num_ch_map(const struct snd_soc_dai_link *link) +{ + return max(link->num_cpus, link->num_codecs); +} + +static inline struct snd_soc_dai_link_component* +snd_soc_link_to_cpu(struct snd_soc_dai_link *link, int n) { + return &(link)->cpus[n]; +} + +static inline struct snd_soc_dai_link_component* +snd_soc_link_to_codec(struct snd_soc_dai_link *link, int n) { + return &(link)->codecs[n]; +} + +static inline struct snd_soc_dai_link_component* +snd_soc_link_to_platform(struct snd_soc_dai_link *link, int n) { + return &(link)->platforms[n]; +} + +#define for_each_link_codecs(link, i, codec) \ + for ((i) = 0; \ + ((i) < link->num_codecs) && \ + ((codec) = snd_soc_link_to_codec(link, i)); \ + (i)++) + +#define for_each_link_platforms(link, i, platform) \ + for ((i) = 0; \ + ((i) < link->num_platforms) && \ + ((platform) = snd_soc_link_to_platform(link, i)); \ + (i)++) + +#define for_each_link_cpus(link, i, cpu) \ + for ((i) = 0; \ + ((i) < link->num_cpus) && \ + ((cpu) = snd_soc_link_to_cpu(link, i)); \ + (i)++) + +#define for_each_link_ch_maps(link, i, ch_map) \ + for ((i) = 0; \ + ((i) < snd_soc_link_num_ch_map(link) && \ + ((ch_map) = link->ch_maps + i)); \ + (i)++) + +/* + * Sample 1 : Single CPU/Codec/Platform + * + * SND_SOC_DAILINK_DEFS(test, + * DAILINK_COMP_ARRAY(COMP_CPU("cpu_dai")), + * DAILINK_COMP_ARRAY(COMP_CODEC("codec", "codec_dai")), + * DAILINK_COMP_ARRAY(COMP_PLATFORM("platform"))); + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test), + * }; + * + * Sample 2 : Multi CPU/Codec, no Platform + * + * SND_SOC_DAILINK_DEFS(test, + * DAILINK_COMP_ARRAY(COMP_CPU("cpu_dai1"), + * COMP_CPU("cpu_dai2")), + * DAILINK_COMP_ARRAY(COMP_CODEC("codec1", "codec_dai1"), + * COMP_CODEC("codec2", "codec_dai2"))); + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test), + * }; + * + * Sample 3 : Define each CPU/Codec/Platform manually + * + * SND_SOC_DAILINK_DEF(test_cpu, + * DAILINK_COMP_ARRAY(COMP_CPU("cpu_dai1"), + * COMP_CPU("cpu_dai2"))); + * SND_SOC_DAILINK_DEF(test_codec, + * DAILINK_COMP_ARRAY(COMP_CODEC("codec1", "codec_dai1"), + * COMP_CODEC("codec2", "codec_dai2"))); + * SND_SOC_DAILINK_DEF(test_platform, + * DAILINK_COMP_ARRAY(COMP_PLATFORM("platform"))); + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test_cpu, + * test_codec, + * test_platform), + * }; + * + * Sample 4 : Sample3 without platform + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test_cpu, + * test_codec); + * }; + */ + +#define SND_SOC_DAILINK_REG1(name) SND_SOC_DAILINK_REG3(name##_cpus, name##_codecs, name##_platforms) +#define SND_SOC_DAILINK_REG2(cpu, codec) SND_SOC_DAILINK_REG3(cpu, codec, null_dailink_component) +#define SND_SOC_DAILINK_REG3(cpu, codec, platform) \ + .cpus = cpu, \ + .num_cpus = ARRAY_SIZE(cpu), \ + .codecs = codec, \ + .num_codecs = ARRAY_SIZE(codec), \ + .platforms = platform, \ + .num_platforms = ARRAY_SIZE(platform) + +#define SND_SOC_DAILINK_REG(...) \ + CONCATENATE(SND_SOC_DAILINK_REG, COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__) + +#define SND_SOC_DAILINK_DEF(name, def...) \ + static struct snd_soc_dai_link_component name[] = { def } + +#define SND_SOC_DAILINK_DEFS(name, cpu, codec, platform...) \ + SND_SOC_DAILINK_DEF(name##_cpus, cpu); \ + SND_SOC_DAILINK_DEF(name##_codecs, codec); \ + SND_SOC_DAILINK_DEF(name##_platforms, platform) + +#define DAILINK_COMP_ARRAY(param...) param +#define COMP_EMPTY() { } +#define COMP_CPU(_dai) { .dai_name = _dai, } +#define COMP_CODEC(_name, _dai) { .name = _name, .dai_name = _dai, } +#define COMP_PLATFORM(_name) { .name = _name } +#define COMP_AUX(_name) { .name = _name } +#define COMP_CODEC_CONF(_name) { .name = _name } +#define COMP_DUMMY() /* see snd_soc_fill_dummy_dai() */ + +extern struct snd_soc_dai_link_component null_dailink_component[0]; +extern struct snd_soc_dai_link_component snd_soc_dummy_dlc; +int snd_soc_dlc_is_dummy(struct snd_soc_dai_link_component *dlc); + +struct snd_soc_codec_conf { + /* + * specify device either by device name, or by + * DT/OF node, but not both. + */ + struct snd_soc_dai_link_component dlc; + + /* + * optional map of kcontrol, widget and path name prefixes that are + * associated per device + */ + const char *name_prefix; +}; + +struct snd_soc_aux_dev { + /* + * specify multi-codec either by device name, or by + * DT/OF node, but not both. + */ + struct snd_soc_dai_link_component dlc; + + /* codec/machine specific init - e.g. add machine controls */ + int (*init)(struct snd_soc_component *component); +}; + +/* SoC card */ +struct snd_soc_card { + const char *name; + const char *long_name; + const char *driver_name; + const char *components; + +#ifdef CONFIG_PCI + /* + * PCI does not define 0 as invalid, so pci_subsystem_set indicates + * whether a value has been written to these fields. + */ + unsigned short pci_subsystem_vendor; + unsigned short pci_subsystem_device; + bool pci_subsystem_set; +#endif /* CONFIG_PCI */ + + char *topology_shortname; + + struct device *dev; + struct snd_card *snd_card; + struct module *owner; + + struct mutex mutex; + struct mutex dapm_mutex; + + /* Mutex for PCM operations */ + struct mutex pcm_mutex; + + int (*probe)(struct snd_soc_card *card); + int (*late_probe)(struct snd_soc_card *card); + void (*fixup_controls)(struct snd_soc_card *card); + int (*remove)(struct snd_soc_card *card); + + /* the pre and post PM functions are used to do any PM work before and + * after the codec and DAI's do any PM work. */ + int (*suspend_pre)(struct snd_soc_card *card); + int (*suspend_post)(struct snd_soc_card *card); + int (*resume_pre)(struct snd_soc_card *card); + int (*resume_post)(struct snd_soc_card *card); + + /* callbacks */ + int (*set_bias_level)(struct snd_soc_card *, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + int (*set_bias_level_post)(struct snd_soc_card *, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + + int (*add_dai_link)(struct snd_soc_card *, + struct snd_soc_dai_link *link); + void (*remove_dai_link)(struct snd_soc_card *, + struct snd_soc_dai_link *link); + + /* CPU <--> Codec DAI links */ + struct snd_soc_dai_link *dai_link; /* predefined links only */ + int num_links; /* predefined links only */ + + struct list_head rtd_list; + int num_rtd; + + /* optional codec specific configuration */ + struct snd_soc_codec_conf *codec_conf; + int num_configs; + + /* + * optional auxiliary devices such as amplifiers or codecs with DAI + * link unused + */ + struct snd_soc_aux_dev *aux_dev; + int num_aux_devs; + struct list_head aux_comp_list; + + const struct snd_kcontrol_new *controls; + int num_controls; + + /* + * Card-specific routes and widgets. + * Note: of_dapm_xxx for Device Tree; Otherwise for driver build-in. + */ + const struct snd_soc_dapm_widget *dapm_widgets; + int num_dapm_widgets; + const struct snd_soc_dapm_route *dapm_routes; + int num_dapm_routes; + const char **ignore_suspend_widgets; + int num_ignore_suspend_widgets; + const struct snd_soc_dapm_widget *of_dapm_widgets; + int num_of_dapm_widgets; + const struct snd_soc_dapm_route *of_dapm_routes; + int num_of_dapm_routes; + const char **of_ignore_suspend_widgets; + int num_of_ignore_suspend_widgets; + + /* lists of probed devices belonging to this card */ + struct list_head component_dev_list; + struct list_head list; + + struct list_head widgets; + struct list_head paths; + struct list_head dapm_list; + struct list_head dapm_dirty; + + /* Generic DAPM context for the card */ + struct snd_soc_dapm_context *dapm; + struct snd_soc_dapm_stats dapm_stats; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_card_root; +#endif +#ifdef CONFIG_PM_SLEEP + struct work_struct deferred_resume_work; +#endif + /* bit field */ + unsigned int instantiated:1; + unsigned int fully_routed:1; + unsigned int probed:1; + unsigned int component_chaining:1; + struct device *devres_dev; + + void *drvdata; +}; +#define for_each_card_prelinks(card, i, link) \ + for ((i) = 0; \ + ((i) < (card)->num_links) && ((link) = &(card)->dai_link[i]); \ + (i)++) +#define for_each_card_pre_auxs(card, i, aux) \ + for ((i) = 0; \ + ((i) < (card)->num_aux_devs) && ((aux) = &(card)->aux_dev[i]); \ + (i)++) + +#define for_each_card_rtds(card, rtd) \ + list_for_each_entry(rtd, &(card)->rtd_list, list) +#define for_each_card_rtds_safe(card, rtd, _rtd) \ + list_for_each_entry_safe(rtd, _rtd, &(card)->rtd_list, list) + +#define for_each_card_auxs(card, component) \ + list_for_each_entry(component, &card->aux_comp_list, card_aux_list) +#define for_each_card_auxs_safe(card, component, _comp) \ + list_for_each_entry_safe(component, _comp, \ + &card->aux_comp_list, card_aux_list) + +#define for_each_card_components(card, component) \ + list_for_each_entry(component, &(card)->component_dev_list, card_list) + +#define for_each_card_dapms(card, dapm) \ + list_for_each_entry(dapm, &card->dapm_list, list) + +#define for_each_card_widgets(card, w)\ + list_for_each_entry(w, &card->widgets, list) +#define for_each_card_widgets_safe(card, w, _w) \ + list_for_each_entry_safe(w, _w, &card->widgets, list) + + +static inline int snd_soc_card_is_instantiated(struct snd_soc_card *card) +{ + return card && card->instantiated; +} + +static inline struct snd_soc_dapm_context *snd_soc_card_to_dapm(struct snd_soc_card *card) +{ + return card->dapm; +} + +/* SoC machine DAI configuration, glues a codec and cpu DAI together */ +struct snd_soc_pcm_runtime { + struct device *dev; + struct snd_soc_card *card; + struct snd_soc_dai_link *dai_link; + struct snd_pcm_ops ops; + + unsigned int c2c_params_select; /* currently selected c2c_param for dai link */ + + /* Dynamic PCM BE runtime data */ + struct snd_soc_dpcm_runtime dpcm[SNDRV_PCM_STREAM_LAST + 1]; + struct snd_soc_dapm_widget *c2c_widget[SNDRV_PCM_STREAM_LAST + 1]; + + long pmdown_time; + + /* runtime devices */ + struct snd_pcm *pcm; + struct snd_compr *compr; + + /* + * dais = cpu_dai + codec_dai + * see + * soc_new_pcm_runtime() + * snd_soc_rtd_to_cpu() + * snd_soc_rtd_to_codec() + */ + struct snd_soc_dai **dais; + + struct delayed_work delayed_work; + void (*close_delayed_work_func)(struct snd_soc_pcm_runtime *rtd); +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_dpcm_root; +#endif + + unsigned int id; /* 0-based and monotonic increasing */ + struct list_head list; /* rtd list of the soc card */ + + /* function mark */ + struct snd_pcm_substream *mark_startup; + struct snd_pcm_substream *mark_hw_params; + struct snd_pcm_substream *mark_trigger; + struct snd_compr_stream *mark_compr_startup; + + /* bit field */ + unsigned int pop_wait:1; + unsigned int fe_compr:1; /* for Dynamic PCM */ + unsigned int initialized:1; + + /* CPU/Codec/Platform */ + int num_components; + struct snd_soc_component *components[] __counted_by(num_components); +}; + +/* see soc_new_pcm_runtime() */ +#define snd_soc_rtd_to_cpu(rtd, n) (rtd)->dais[n] +#define snd_soc_rtd_to_codec(rtd, n) (rtd)->dais[n + (rtd)->dai_link->num_cpus] + +static inline struct snd_soc_pcm_runtime * +snd_soc_substream_to_rtd(const struct snd_pcm_substream *substream) +{ + return snd_pcm_substream_chip(substream); +} + +#define for_each_rtd_components(rtd, i, component) \ + for ((i) = 0, component = NULL; \ + ((i) < rtd->num_components) && ((component) = rtd->components[i]);\ + (i)++) +#define for_each_rtd_cpu_dais(rtd, i, dai) \ + for ((i) = 0; \ + ((i) < rtd->dai_link->num_cpus) && ((dai) = snd_soc_rtd_to_cpu(rtd, i)); \ + (i)++) +#define for_each_rtd_codec_dais(rtd, i, dai) \ + for ((i) = 0; \ + ((i) < rtd->dai_link->num_codecs) && ((dai) = snd_soc_rtd_to_codec(rtd, i)); \ + (i)++) +#define for_each_rtd_dais(rtd, i, dai) \ + for ((i) = 0; \ + ((i) < (rtd)->dai_link->num_cpus + (rtd)->dai_link->num_codecs) && \ + ((dai) = (rtd)->dais[i]); \ + (i)++) +#define for_each_rtd_dais_reverse(rtd, i, dai) \ + for ((i) = (rtd)->dai_link->num_cpus + (rtd)->dai_link->num_codecs - 1; \ + (i) >= 0 && ((dai) = (rtd)->dais[i]); \ + (i)--) +#define for_each_rtd_ch_maps(rtd, i, ch_maps) for_each_link_ch_maps(rtd->dai_link, i, ch_maps) + +void snd_soc_close_delayed_work(struct snd_soc_pcm_runtime *rtd); + +/* mixer control */ +struct soc_mixer_control { + /* Minimum and maximum specified as written to the hardware */ + int min, max; + /* Limited maximum value specified as presented through the control */ + int platform_max; + int reg, rreg; + unsigned int shift, rshift; + u32 num_channels; + unsigned int sign_bit; + unsigned int invert:1; + unsigned int autodisable:1; +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; +#endif +}; + +struct soc_bytes { + int base; + int num_regs; + u32 mask; +}; + +struct soc_bytes_ext { + int max; +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; +#endif + /* used for TLV byte control */ + int (*get)(struct snd_kcontrol *kcontrol, unsigned int __user *bytes, + unsigned int size); + int (*put)(struct snd_kcontrol *kcontrol, const unsigned int __user *bytes, + unsigned int size); +}; + +/* multi register control */ +struct soc_mreg_control { + long min, max; + unsigned int regbase, regcount, nbits, invert; +}; + +/* enumerated kcontrol */ +struct soc_enum { + int reg; + unsigned char shift_l; + unsigned char shift_r; + unsigned int items; + unsigned int mask; + const char * const *texts; + const unsigned int *values; + unsigned int autodisable:1; +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; +#endif +}; + +static inline bool snd_soc_volsw_is_stereo(const struct soc_mixer_control *mc) +{ + if (mc->reg == mc->rreg && mc->shift == mc->rshift) + return false; + /* + * mc->reg == mc->rreg && mc->shift != mc->rshift, or + * mc->reg != mc->rreg means that the control is + * stereo (bits in one register or in two registers) + */ + return true; +} + +static inline unsigned int snd_soc_enum_val_to_item(const struct soc_enum *e, + unsigned int val) +{ + unsigned int i; + + if (!e->values) + return val; + + for (i = 0; i < e->items; i++) + if (val == e->values[i]) + return i; + + return 0; +} + +static inline unsigned int snd_soc_enum_item_to_val(const struct soc_enum *e, + unsigned int item) +{ + if (!e->values) + return item; + + return e->values[item]; +} + +int snd_soc_util_init(void); +void snd_soc_util_exit(void); + +int snd_soc_of_parse_card_name(struct snd_soc_card *card, + const char *propname); +int snd_soc_of_parse_audio_simple_widgets(struct snd_soc_card *card, + const char *propname); +int snd_soc_of_parse_pin_switches(struct snd_soc_card *card, const char *prop); +int snd_soc_of_get_slot_mask(struct device_node *np, + const char *prop_name, + unsigned int *mask); +int snd_soc_of_parse_tdm_slot(struct device_node *np, + unsigned int *tx_mask, + unsigned int *rx_mask, + unsigned int *slots, + unsigned int *slot_width); +void snd_soc_of_parse_node_prefix(struct device_node *np, + struct snd_soc_codec_conf *codec_conf, + struct device_node *of_node, + const char *propname); + +int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, + const char *propname); +int snd_soc_of_parse_aux_devs(struct snd_soc_card *card, const char *propname); +int snd_soc_of_parse_ignore_suspend_widgets(struct snd_soc_card *card, const char *propname); + +unsigned int snd_soc_daifmt_clock_provider_flipped(unsigned int dai_fmt); +unsigned int snd_soc_daifmt_clock_provider_from_bitmap(unsigned int bit_frame); + +unsigned int snd_soc_daifmt_parse_format(struct device_node *np, const char *prefix); +unsigned int snd_soc_daifmt_parse_clock_provider_raw(struct device_node *np, + const char *prefix, + struct device_node **bitclkmaster, + struct device_node **framemaster); +#define snd_soc_daifmt_parse_clock_provider_as_bitmap(np, prefix) \ + snd_soc_daifmt_parse_clock_provider_raw(np, prefix, NULL, NULL) +#define snd_soc_daifmt_parse_clock_provider_as_phandle \ + snd_soc_daifmt_parse_clock_provider_raw +#define snd_soc_daifmt_parse_clock_provider_as_flag(np, prefix) \ + snd_soc_daifmt_clock_provider_from_bitmap( \ + snd_soc_daifmt_parse_clock_provider_as_bitmap(np, prefix)) + +int snd_soc_get_stream_cpu(const struct snd_soc_dai_link *dai_link, int stream); +int snd_soc_get_dlc(const struct of_phandle_args *args, + struct snd_soc_dai_link_component *dlc); +int snd_soc_of_get_dlc(struct device_node *of_node, + struct of_phandle_args *args, + struct snd_soc_dai_link_component *dlc, + int index); +int snd_soc_get_dai_id(struct device_node *ep); +int snd_soc_get_dai_name(const struct of_phandle_args *args, + const char **dai_name); +int snd_soc_of_get_dai_name(struct device_node *of_node, + const char **dai_name, int index); +int snd_soc_of_get_dai_link_codecs(struct device *dev, + struct device_node *of_node, + struct snd_soc_dai_link *dai_link); +void snd_soc_of_put_dai_link_codecs(struct snd_soc_dai_link *dai_link); +int snd_soc_of_get_dai_link_cpus(struct device *dev, + struct device_node *of_node, + struct snd_soc_dai_link *dai_link); +void snd_soc_of_put_dai_link_cpus(struct snd_soc_dai_link *dai_link); + +int snd_soc_add_pcm_runtimes(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link, + int num_dai_link); +void snd_soc_remove_pcm_runtime(struct snd_soc_card *card, + struct snd_soc_pcm_runtime *rtd); + +void snd_soc_dlc_use_cpu_as_platform(struct snd_soc_dai_link_component *platforms, + struct snd_soc_dai_link_component *cpus); +struct of_phandle_args *snd_soc_copy_dai_args(struct device *dev, + const struct of_phandle_args *args); +struct snd_soc_dai *snd_soc_get_dai_via_args(const struct of_phandle_args *dai_args); +struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, + struct snd_soc_dai_driver *dai_drv, + bool legacy_dai_naming); +void snd_soc_unregister_dai(struct snd_soc_dai *dai); + +struct snd_soc_dai *snd_soc_find_dai( + const struct snd_soc_dai_link_component *dlc); +struct snd_soc_dai *snd_soc_find_dai_with_mutex( + const struct snd_soc_dai_link_component *dlc); + +void soc_pcm_set_dai_params(struct snd_soc_dai *dai, + struct snd_pcm_hw_params *params); + +#include + +static inline +int snd_soc_fixup_dai_links_platform_name(struct snd_soc_card *card, + const char *platform_name) +{ + struct snd_soc_dai_link *dai_link; + const char *name; + int i; + + if (!platform_name) /* nothing to do */ + return 0; + + /* set platform name for each dailink */ + for_each_card_prelinks(card, i, dai_link) { + /* only single platform is supported for now */ + if (dai_link->num_platforms != 1) + return -EINVAL; + + if (!dai_link->platforms) + return -EINVAL; + + name = devm_kstrdup(card->dev, platform_name, GFP_KERNEL); + if (!name) + return -ENOMEM; + + /* only single platform is supported for now */ + dai_link->platforms->name = name; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +extern struct dentry *snd_soc_debugfs_root; +#endif + +extern const struct dev_pm_ops snd_soc_pm_ops; + +/* + * DAPM helper functions + */ +enum snd_soc_dapm_subclass { + SND_SOC_DAPM_CLASS_ROOT = 0, + SND_SOC_DAPM_CLASS_RUNTIME = 1, +}; + +static inline void _snd_soc_dapm_mutex_lock_root_c(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_ROOT); +} + +static inline void _snd_soc_dapm_mutex_lock_c(struct snd_soc_card *card) +{ + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); +} + +static inline void _snd_soc_dapm_mutex_unlock_c(struct snd_soc_card *card) +{ + mutex_unlock(&card->dapm_mutex); +} + +static inline void _snd_soc_dapm_mutex_assert_held_c(struct snd_soc_card *card) +{ + lockdep_assert_held(&card->dapm_mutex); +} + +static inline void _snd_soc_dapm_mutex_lock_root_d(struct snd_soc_dapm_context *dapm) +{ + _snd_soc_dapm_mutex_lock_root_c(snd_soc_dapm_to_card(dapm)); +} + +static inline void _snd_soc_dapm_mutex_lock_d(struct snd_soc_dapm_context *dapm) +{ + _snd_soc_dapm_mutex_lock_c(snd_soc_dapm_to_card(dapm)); +} + +static inline void _snd_soc_dapm_mutex_unlock_d(struct snd_soc_dapm_context *dapm) +{ + _snd_soc_dapm_mutex_unlock_c(snd_soc_dapm_to_card(dapm)); +} + +static inline void _snd_soc_dapm_mutex_assert_held_d(struct snd_soc_dapm_context *dapm) +{ + _snd_soc_dapm_mutex_assert_held_c(snd_soc_dapm_to_card(dapm)); +} + +#define snd_soc_dapm_mutex_lock_root(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_lock_root_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_lock_root_d)(x) +#define snd_soc_dapm_mutex_lock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_lock_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_lock_d)(x) +#define snd_soc_dapm_mutex_unlock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_unlock_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_unlock_d)(x) +#define snd_soc_dapm_mutex_assert_held(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dapm_mutex_assert_held_c, \ + struct snd_soc_dapm_context * : _snd_soc_dapm_mutex_assert_held_d)(x) + +/* + * PCM helper functions + */ +static inline void _snd_soc_dpcm_mutex_lock_c(struct snd_soc_card *card) +{ + mutex_lock(&card->pcm_mutex); +} + +static inline void _snd_soc_dpcm_mutex_unlock_c(struct snd_soc_card *card) +{ + mutex_unlock(&card->pcm_mutex); +} + +static inline void _snd_soc_dpcm_mutex_assert_held_c(struct snd_soc_card *card) +{ + lockdep_assert_held(&card->pcm_mutex); +} + +static inline void _snd_soc_dpcm_mutex_lock_r(struct snd_soc_pcm_runtime *rtd) +{ + _snd_soc_dpcm_mutex_lock_c(rtd->card); +} + +static inline void _snd_soc_dpcm_mutex_unlock_r(struct snd_soc_pcm_runtime *rtd) +{ + _snd_soc_dpcm_mutex_unlock_c(rtd->card); +} + +static inline void _snd_soc_dpcm_mutex_assert_held_r(struct snd_soc_pcm_runtime *rtd) +{ + _snd_soc_dpcm_mutex_assert_held_c(rtd->card); +} + +#define snd_soc_dpcm_mutex_lock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dpcm_mutex_lock_c, \ + struct snd_soc_pcm_runtime * : _snd_soc_dpcm_mutex_lock_r)(x) + +#define snd_soc_dpcm_mutex_unlock(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dpcm_mutex_unlock_c, \ + struct snd_soc_pcm_runtime * : _snd_soc_dpcm_mutex_unlock_r)(x) + +#define snd_soc_dpcm_mutex_assert_held(x) _Generic((x), \ + struct snd_soc_card * : _snd_soc_dpcm_mutex_assert_held_c, \ + struct snd_soc_pcm_runtime * : _snd_soc_dpcm_mutex_assert_held_r)(x) + +#include +#include +#include + +#endif diff --git a/include/sound/soc_sdw_utils.h b/include/sound/soc_sdw_utils.h new file mode 100644 index 000000000..9b28e9aef --- /dev/null +++ b/include/sound/soc_sdw_utils.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This file incorporates work covered by the following copyright notice: + * Copyright (c) 2020 Intel Corporation + * Copyright(c) 2024 Advanced Micro Devices, Inc. + * + */ + +#ifndef SOC_SDW_UTILS_H +#define SOC_SDW_UTILS_H + +#include +#include + +#define SOC_SDW_MAX_DAI_NUM 8 +#define SOC_SDW_MAX_AUX_NUM 2 +#define SOC_SDW_MAX_NO_PROPS 2 +#define SOC_SDW_JACK_JDSRC(quirk) ((quirk) & GENMASK(3, 0)) + +/* If a CODEC has an optional speaker output, this quirk will enable it */ +#define SOC_SDW_CODEC_SPKR BIT(15) +/* + * If the CODEC has additional devices attached directly to it. + * + * For the cs42l43: + * - 0 - No speaker output + * - SOC_SDW_CODEC_SPKR - CODEC internal speaker + * - SOC_SDW_SIDECAR_AMPS - 2x Sidecar amplifiers + CODEC internal speaker + * - SOC_SDW_CODEC_SPKR | SOF_SIDECAR_AMPS - Not currently supported + */ +#define SOC_SDW_SIDECAR_AMPS BIT(16) +#define SOC_SDW_CODEC_MIC BIT(17) + +#define SOC_SDW_UNUSED_DAI_ID -1 +#define SOC_SDW_JACK_OUT_DAI_ID 0 +#define SOC_SDW_JACK_IN_DAI_ID 1 +#define SOC_SDW_AMP_OUT_DAI_ID 2 +#define SOC_SDW_AMP_IN_DAI_ID 3 +#define SOC_SDW_DMIC_DAI_ID 4 + +#define SOC_SDW_DAI_TYPE_JACK 0 +#define SOC_SDW_DAI_TYPE_AMP 1 +#define SOC_SDW_DAI_TYPE_MIC 2 + +struct asoc_sdw_codec_info; + +struct asoc_sdw_mc_private { + struct snd_soc_card card; + struct snd_soc_jack sdw_headset; + struct device *headset_codec_dev; /* only one headset per card */ + struct device *amp_dev1, *amp_dev2; + bool append_dai_type; + bool ignore_internal_dmic; + void *private; + unsigned long mc_quirk; + int codec_info_list_count; +}; + +struct asoc_sdw_dai_info { + const bool direction[2]; /* playback & capture support */ + const char *codec_name; + const char *dai_name; + const char *component_name; + const int dai_type; + const int dailink[2]; /* dailink id for each direction */ + const struct snd_kcontrol_new *controls; + const int num_controls; + const struct snd_soc_dapm_widget *widgets; + const int num_widgets; + int (*init)(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); + int (*exit)(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); + int (*rtd_init)(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); + bool rtd_init_done; /* Indicate that the rtd_init callback is done */ + unsigned long quirk; + bool quirk_exclude; +}; + +struct asoc_sdw_aux_info { + const char *codec_name; +}; + +struct asoc_sdw_codec_info { + const int vendor_id; + const int part_id; + const int version_id; + const char *name_prefix; + int amp_num; + const u8 acpi_id[ACPI_ID_LEN]; + const bool ignore_internal_dmic; + const struct snd_soc_ops *ops; + struct asoc_sdw_dai_info dais[SOC_SDW_MAX_DAI_NUM]; + const int dai_num; + struct asoc_sdw_aux_info auxs[SOC_SDW_MAX_AUX_NUM]; + const int aux_num; + /* Force AMP-style name_prefix handling (append AMP index) even if MIC/Jack DAIs exist */ + const bool is_amp; + + int (*codec_card_late_probe)(struct snd_soc_card *card); + + int (*count_sidecar)(struct asoc_sdw_mc_private *ctx, + int *num_dais, int *num_devs); + int (*add_sidecar)(struct snd_soc_card *card, + struct snd_soc_dai_link **dai_links, + struct snd_soc_codec_conf **codec_conf); +}; + +struct asoc_sdw_endpoint { + struct list_head list; + + u32 link_mask; + const char *codec_name; + const char *name_prefix; + bool include_sidecar; + + struct asoc_sdw_codec_info *codec_info; + const struct asoc_sdw_dai_info *dai_info; +}; + +struct asoc_sdw_dailink { + bool initialised; + + u8 group_id; + u32 link_mask[SNDRV_PCM_STREAM_LAST + 1]; + int num_devs[SNDRV_PCM_STREAM_LAST + 1]; + struct list_head endpoints; +}; + +extern struct asoc_sdw_codec_info codec_info_list[]; +int asoc_sdw_get_codec_info_list_count(void); + +int asoc_sdw_startup(struct snd_pcm_substream *substream); +int asoc_sdw_prepare(struct snd_pcm_substream *substream); +int asoc_sdw_prepare(struct snd_pcm_substream *substream); +int asoc_sdw_trigger(struct snd_pcm_substream *substream, int cmd); +int asoc_sdw_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int asoc_sdw_hw_free(struct snd_pcm_substream *substream); +void asoc_sdw_shutdown(struct snd_pcm_substream *substream); + +const char *asoc_sdw_get_codec_name(struct device *dev, + const struct asoc_sdw_dai_info *dai_info, + const struct snd_soc_acpi_link_adr *adr_link, + int adr_index); + +struct asoc_sdw_codec_info *asoc_sdw_find_codec_info_part(const u64 adr); + +struct asoc_sdw_codec_info *asoc_sdw_find_codec_info_acpi(const u8 *acpi_id); + +struct asoc_sdw_codec_info *asoc_sdw_find_codec_info_dai(const char *dai_name, + int *dai_index); + +struct snd_soc_dai_link *asoc_sdw_mc_find_codec_dai_used(struct snd_soc_card *card, + const char *dai_name); + +void asoc_sdw_mc_dailink_exit_loop(struct snd_soc_card *card); + +int asoc_sdw_card_late_probe(struct snd_soc_card *card); + +void asoc_sdw_init_dai_link(struct device *dev, struct snd_soc_dai_link *dai_links, + int *be_id, char *name, int playback, int capture, + struct snd_soc_dai_link_component *cpus, int cpus_num, + struct snd_soc_dai_link_component *platform_component, + int num_platforms, struct snd_soc_dai_link_component *codecs, + int codecs_num, int no_pcm, + int (*init)(struct snd_soc_pcm_runtime *rtd), + const struct snd_soc_ops *ops); + +int asoc_sdw_init_simple_dai_link(struct device *dev, struct snd_soc_dai_link *dai_links, + int *be_id, char *name, int playback, int capture, + const char *cpu_dai_name, const char *platform_comp_name, + const char *codec_name, const char *codec_dai_name, + int no_pcm, int (*init)(struct snd_soc_pcm_runtime *rtd), + const struct snd_soc_ops *ops); + +int asoc_sdw_count_sdw_endpoints(struct snd_soc_card *card, + int *num_devs, int *num_ends, int *num_aux); + +struct asoc_sdw_dailink *asoc_sdw_find_dailink(struct asoc_sdw_dailink *dailinks, + const struct snd_soc_acpi_endpoint *new); +int asoc_sdw_get_dai_type(u32 type); + +int asoc_sdw_parse_sdw_endpoints(struct device *dev, + struct asoc_sdw_mc_private *ctx, + struct snd_soc_aux_dev *soc_aux, + struct asoc_sdw_dailink *soc_dais, + struct asoc_sdw_endpoint *soc_ends, + int *num_devs); + +int asoc_sdw_rtd_init(struct snd_soc_pcm_runtime *rtd); + +/* DMIC support */ +int asoc_sdw_dmic_init(struct snd_soc_pcm_runtime *rtd); + +/* RT711 support */ +int asoc_sdw_rt711_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_rt711_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); + +/* RT711-SDCA support */ +int asoc_sdw_rt_sdca_jack_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_rt_sdca_jack_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); + +/* RT1308 I2S support */ +extern const struct snd_soc_ops soc_sdw_rt1308_i2s_ops; + +/* generic amp support */ +int asoc_sdw_rt_amp_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_rt_amp_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); + +/* CS42L43 support */ +int asoc_sdw_cs42l43_spk_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); + +/* es9356 codec support */ +int asoc_sdw_es9356_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_es9356_amp_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_es9356_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); + +/* CS AMP support */ +int asoc_sdw_bridge_cs35l56_count_sidecar(struct asoc_sdw_mc_private *ctx, + int *num_dais, int *num_devs); +int asoc_sdw_bridge_cs35l56_add_sidecar(struct snd_soc_card *card, + struct snd_soc_dai_link **dai_links, + struct snd_soc_codec_conf **codec_conf); +int asoc_sdw_bridge_cs35l56_spk_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); + +int asoc_sdw_cs_amp_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_cs_spk_feedback_rtd_init(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai); +int asoc_sdw_cs35l56_volume_limit(struct snd_soc_card *card, const char *name_prefix); + +/* MAXIM codec support */ +int asoc_sdw_maxim_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); + +/* dai_link init callbacks */ +int asoc_sdw_rt_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_rt_sdca_jack_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_rt_amp_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_rt700_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_rt711_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_rt_mf_sdca_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_rt5682_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs42l42_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs42l43_hs_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs42l43_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs42l43_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs42l45_hs_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs42l45_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs47l47_hs_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs47l47_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_cs_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_maxim_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +/* TI */ +int asoc_sdw_ti_amp_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_ti_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_ti_tac5xx2_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai); +int asoc_sdw_ti_amp_initial_settings(struct snd_soc_card *card, + const char *name_prefix); +int asoc_sdw_ti_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_ti_sdca_jack_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_es9356_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_es9356_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_es9356_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); + +#endif diff --git a/include/sound/sof.h b/include/sound/sof.h new file mode 100644 index 000000000..38d6c8cb5 --- /dev/null +++ b/include/sound/sof.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + * + * Author: Liam Girdwood + */ + +#ifndef __INCLUDE_SOUND_SOF_H +#define __INCLUDE_SOUND_SOF_H + +#include +#include +#include + +struct snd_sof_dsp_ops; +struct snd_sof_dev; + +/** + * enum sof_fw_state - DSP firmware state definitions + * @SOF_FW_BOOT_NOT_STARTED: firmware boot is not yet started + * @SOF_DSPLESS_MODE: DSP is not used + * @SOF_FW_BOOT_PREPARE: preparing for boot (firmware loading for exaqmple) + * @SOF_FW_BOOT_IN_PROGRESS: firmware boot is in progress + * @SOF_FW_BOOT_FAILED: firmware boot failed + * @SOF_FW_BOOT_READY_FAILED: firmware booted but fw_ready op failed + * @SOF_FW_BOOT_READY_OK: firmware booted and fw_ready op passed + * @SOF_FW_BOOT_COMPLETE: firmware is booted up and functional + * @SOF_FW_CRASHED: firmware crashed after successful boot + */ +enum sof_fw_state { + SOF_FW_BOOT_NOT_STARTED = 0, + SOF_DSPLESS_MODE, + SOF_FW_BOOT_PREPARE, + SOF_FW_BOOT_IN_PROGRESS, + SOF_FW_BOOT_FAILED, + SOF_FW_BOOT_READY_FAILED, + SOF_FW_BOOT_READY_OK, + SOF_FW_BOOT_COMPLETE, + SOF_FW_CRASHED, +}; + +/* DSP power states */ +enum sof_dsp_power_states { + SOF_DSP_PM_D0, + SOF_DSP_PM_D1, + SOF_DSP_PM_D2, + SOF_DSP_PM_D3, +}; + +/* Definitions for multiple IPCs */ +enum sof_ipc_type { + SOF_IPC_TYPE_3, + SOF_IPC_TYPE_4, + SOF_IPC_TYPE_COUNT +}; + +struct sof_loadable_file_profile { + enum sof_ipc_type ipc_type; + + const char *fw_path; + const char *fw_path_postfix; + const char *fw_name; + const char *fw_lib_path; + const char *fw_lib_path_postfix; + const char *tplg_path; + const char *tplg_name; +}; + +/* + * SOF Platform data. + */ +struct snd_sof_pdata { + const char *name; + const char *platform; + + /* + * PCI SSID. As PCI does not define 0 as invalid, the subsystem_id_set + * flag indicates that a value has been written to these members. + */ + unsigned short subsystem_vendor; + unsigned short subsystem_device; + bool subsystem_id_set; + + struct device *dev; + + /* + * notification callback used if the hardware initialization + * can take time or is handled in a workqueue. This callback + * can be used by the caller to e.g. enable runtime_pm + * or limit functionality until all low-level inits are + * complete. + */ + void (*sof_probe_complete)(struct device *dev); + + /* descriptor */ + const struct sof_dev_desc *desc; + + /* platform's preferred IPC type and path overrides */ + struct sof_loadable_file_profile ipc_file_profile_base; + + /* firmware and topology filenames */ + const char *fw_filename_prefix; + const char *fw_filename; + const char *tplg_filename_prefix; + const char *tplg_filename; + bool disable_function_topology; + + /* loadable external libraries available under this directory */ + const char *fw_lib_prefix; + + /* machine */ + struct platform_device *pdev_mach; + const struct snd_soc_acpi_mach *machine; + const struct snd_sof_of_mach *of_machine; + + void *hw_pdata; + + enum sof_ipc_type ipc_type; +}; + +/* + * Descriptor used for setting up SOF platform data. This is used when + * ACPI/PCI data is missing or mapped differently. + */ +struct sof_dev_desc { + /* list of machines using this configuration */ + struct snd_soc_acpi_mach *machines; + struct snd_sof_of_mach *of_machines; + + /* alternate list of machines using this configuration */ + struct snd_soc_acpi_mach *alt_machines; + + bool use_acpi_target_states; + + /* Platform resource indexes in BAR / ACPI resources. */ + /* Must set to -1 if not used - add new items to end */ + int resindex_lpe_base; + int resindex_pcicfg_base; + int resindex_imr_base; + int irqindex_host_ipc; + + /* IPC timeouts in ms */ + int ipc_timeout; + int boot_timeout; + + /* chip information for dsp */ + const void *chip_info; + + /* defaults for no codec mode */ + const char *nocodec_tplg_filename; + + /* information on supported IPCs */ + unsigned int ipc_supported_mask; + enum sof_ipc_type ipc_default; + + /* The platform supports DSPless mode */ + bool dspless_mode_supported; + + /* On demand DSP booting is possible on the platform */ + bool on_demand_dsp_boot; + + /* defaults paths for firmware, library and topology files */ + const char *default_fw_path[SOF_IPC_TYPE_COUNT]; + const char *default_lib_path[SOF_IPC_TYPE_COUNT]; + const char *default_tplg_path[SOF_IPC_TYPE_COUNT]; + + /* default firmware name */ + const char *default_fw_filename[SOF_IPC_TYPE_COUNT]; + + const struct snd_sof_dsp_ops *ops; + int (*ops_init)(struct snd_sof_dev *sdev); + void (*ops_free)(struct snd_sof_dev *sdev); +}; + +int sof_dai_get_mclk(struct snd_soc_pcm_runtime *rtd); +int sof_dai_get_bclk(struct snd_soc_pcm_runtime *rtd); +int sof_dai_get_tdm_slots(struct snd_soc_pcm_runtime *rtd); + +#endif diff --git a/include/sound/sof/channel_map.h b/include/sound/sof/channel_map.h new file mode 100644 index 000000000..2a177a193 --- /dev/null +++ b/include/sound/sof/channel_map.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2019 Intel Corporation + */ + +#ifndef __IPC_CHANNEL_MAP_H__ +#define __IPC_CHANNEL_MAP_H__ + +#include +#include + +/** + * \brief Channel map, specifies transformation of one-to-many or many-to-one. + * + * In case of one-to-many specifies how the output channels are computed out of + * a single source channel, + * in case of many-to-one specifies how a single target channel is computed + * from a multichannel input stream. + * + * Channel index specifies position of the channel in the stream on the 'one' + * side. + * + * Ext ID is the identifier of external part of the transformation. Depending + * on the context, it may be pipeline ID, dai ID, ... + * + * Channel mask describes which channels are taken into account on the "many" + * side. Bit[i] set to 1 means that i-th channel is used for computation + * (either as source or as a target). + * + * Channel mask is followed by array of coefficients in Q2.30 format, + * one per each channel set in the mask (left to right, LS bit set in the + * mask corresponds to ch_coeffs[0]). + */ +struct sof_ipc_channel_map { + uint32_t ch_index; + uint32_t ext_id; + uint32_t ch_mask; + uint32_t reserved; + int32_t ch_coeffs[]; +} __packed; + +/** + * \brief Complete map for each channel of a multichannel stream. + * + * num_ch_map Specifies number of items in the ch_map. + * More than one transformation per a single channel is allowed (in case + * multiple external entities are transformed). + * A channel may be skipped in the transformation list, then it is filled + * with 0's by the transformation function. + */ +struct sof_ipc_stream_map { + struct sof_ipc_cmd_hdr hdr; + uint32_t num_ch_map; + uint32_t reserved[3]; + struct sof_ipc_channel_map ch_map[]; +} __packed; + +#endif /* __IPC_CHANNEL_MAP_H__ */ diff --git a/include/sound/sof/control.h b/include/sound/sof/control.h new file mode 100644 index 000000000..8d3300dd9 --- /dev/null +++ b/include/sound/sof/control.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_CONTROL_H__ +#define __INCLUDE_SOUND_SOF_CONTROL_H__ + +#include +#include + +/* + * Component Mixers and Controls + */ + +/* channel positions - uses same values as ALSA */ +enum sof_ipc_chmap { + SOF_CHMAP_UNKNOWN = 0, + SOF_CHMAP_NA, /**< N/A, silent */ + SOF_CHMAP_MONO, /**< mono stream */ + SOF_CHMAP_FL, /**< front left */ + SOF_CHMAP_FR, /**< front right */ + SOF_CHMAP_RL, /**< rear left */ + SOF_CHMAP_RR, /**< rear right */ + SOF_CHMAP_FC, /**< front centre */ + SOF_CHMAP_LFE, /**< LFE */ + SOF_CHMAP_SL, /**< side left */ + SOF_CHMAP_SR, /**< side right */ + SOF_CHMAP_RC, /**< rear centre */ + SOF_CHMAP_FLC, /**< front left centre */ + SOF_CHMAP_FRC, /**< front right centre */ + SOF_CHMAP_RLC, /**< rear left centre */ + SOF_CHMAP_RRC, /**< rear right centre */ + SOF_CHMAP_FLW, /**< front left wide */ + SOF_CHMAP_FRW, /**< front right wide */ + SOF_CHMAP_FLH, /**< front left high */ + SOF_CHMAP_FCH, /**< front centre high */ + SOF_CHMAP_FRH, /**< front right high */ + SOF_CHMAP_TC, /**< top centre */ + SOF_CHMAP_TFL, /**< top front left */ + SOF_CHMAP_TFR, /**< top front right */ + SOF_CHMAP_TFC, /**< top front centre */ + SOF_CHMAP_TRL, /**< top rear left */ + SOF_CHMAP_TRR, /**< top rear right */ + SOF_CHMAP_TRC, /**< top rear centre */ + SOF_CHMAP_TFLC, /**< top front left centre */ + SOF_CHMAP_TFRC, /**< top front right centre */ + SOF_CHMAP_TSL, /**< top side left */ + SOF_CHMAP_TSR, /**< top side right */ + SOF_CHMAP_LLFE, /**< left LFE */ + SOF_CHMAP_RLFE, /**< right LFE */ + SOF_CHMAP_BC, /**< bottom centre */ + SOF_CHMAP_BLC, /**< bottom left centre */ + SOF_CHMAP_BRC, /**< bottom right centre */ + SOF_CHMAP_LAST = SOF_CHMAP_BRC, +}; + +/* control data type and direction */ +enum sof_ipc_ctrl_type { + /* per channel data - uses struct sof_ipc_ctrl_value_chan */ + SOF_CTRL_TYPE_VALUE_CHAN_GET = 0, + SOF_CTRL_TYPE_VALUE_CHAN_SET, + /* component data - uses struct sof_ipc_ctrl_value_comp */ + SOF_CTRL_TYPE_VALUE_COMP_GET, + SOF_CTRL_TYPE_VALUE_COMP_SET, + /* bespoke data - uses struct sof_abi_hdr */ + SOF_CTRL_TYPE_DATA_GET, + SOF_CTRL_TYPE_DATA_SET, +}; + +/* control command type */ +enum sof_ipc_ctrl_cmd { + SOF_CTRL_CMD_VOLUME = 0, /**< maps to ALSA volume style controls */ + SOF_CTRL_CMD_ENUM, /**< maps to ALSA enum style controls */ + SOF_CTRL_CMD_SWITCH, /**< maps to ALSA switch style controls */ + SOF_CTRL_CMD_BINARY, /**< maps to ALSA binary style controls */ +}; + +/* generic channel mapped value data */ +struct sof_ipc_ctrl_value_chan { + uint32_t channel; /**< channel map - enum sof_ipc_chmap */ + uint32_t value; +} __packed; + +/* generic component mapped value data */ +struct sof_ipc_ctrl_value_comp { + uint32_t index; /**< component source/sink/control index in control */ + union { + uint32_t uvalue; + int32_t svalue; + }; +} __packed; + +/* generic control data */ +struct sof_ipc_ctrl_data { + struct sof_ipc_reply rhdr; + uint32_t comp_id; + + /* control access and data type */ + uint32_t type; /**< enum sof_ipc_ctrl_type */ + uint32_t cmd; /**< enum sof_ipc_ctrl_cmd */ + uint32_t index; /**< control index for comps > 1 control */ + + /* control data - can either be appended or DMAed from host */ + struct sof_ipc_host_buffer buffer; + uint32_t num_elems; /**< in array elems or bytes for data type */ + uint32_t elems_remaining; /**< elems remaining if sent in parts */ + + uint32_t msg_index; /**< for large messages sent in parts */ + + /* reserved for future use */ + uint32_t reserved[6]; + + /* control data - add new types if needed */ + union { + /* channel values can be used by volume type controls */ + DECLARE_FLEX_ARRAY(struct sof_ipc_ctrl_value_chan, chanv); + /* component values used by routing controls like mux, mixer */ + DECLARE_FLEX_ARRAY(struct sof_ipc_ctrl_value_comp, compv); + /* data can be used by binary controls */ + DECLARE_FLEX_ARRAY(struct sof_abi_hdr, data); + }; +} __packed; + +/** Event type */ +enum sof_ipc_ctrl_event_type { + SOF_CTRL_EVENT_GENERIC = 0, /**< generic event */ + SOF_CTRL_EVENT_GENERIC_METADATA, /**< generic event with metadata */ + SOF_CTRL_EVENT_KD, /**< keyword detection event */ + SOF_CTRL_EVENT_VAD, /**< voice activity detection event */ +}; + +/** + * Generic notification data. + */ +struct sof_ipc_comp_event { + struct sof_ipc_reply rhdr; + uint16_t src_comp_type; /**< COMP_TYPE_ */ + uint32_t src_comp_id; /**< source component id */ + uint32_t event_type; /**< event type - SOF_CTRL_EVENT_* */ + uint32_t num_elems; /**< in array elems or bytes for data type */ + + /* reserved for future use */ + uint32_t reserved[8]; + + /* control data - add new types if needed */ + union { + /* data can be used by binary controls */ + struct sof_abi_hdr data[0]; + /* event specific values */ + uint32_t event_value; + }; +} __packed; + +#endif diff --git a/include/sound/sof/dai-amd.h b/include/sound/sof/dai-amd.h new file mode 100644 index 000000000..e2107da65 --- /dev/null +++ b/include/sound/sof/dai-amd.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2021 Advanced Micro Devices, Inc.. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_AMD_H__ +#define __INCLUDE_SOUND_SOF_DAI_AMD_H__ + +#include + +/* ACP Configuration Request - SOF_IPC_DAI_AMD_CONFIG */ +struct sof_ipc_dai_acp_params { + struct sof_ipc_hdr hdr; + + uint32_t fsync_rate; /* FSYNC frequency in Hz */ + uint32_t tdm_slots; + uint32_t tdm_mode; + uint32_t format; +} __packed; + +/* ACPDMIC Configuration Request - SOF_IPC_DAI_AMD_CONFIG */ +struct sof_ipc_dai_acpdmic_params { + uint32_t pdm_rate; + uint32_t pdm_ch; +} __packed; + +/* ACP_SDW Configuration Request - SOF_IPC_DAI_AMD_SDW_CONFIG */ +struct sof_ipc_dai_acp_sdw_params { + struct sof_ipc_hdr hdr; + u32 rate; + u32 channels; +} __packed; + +#endif diff --git a/include/sound/sof/dai-imx.h b/include/sound/sof/dai-imx.h new file mode 100644 index 000000000..6bc987bd4 --- /dev/null +++ b/include/sound/sof/dai-imx.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright 2019 NXP + * + * Author: Daniel Baluta + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_IMX_H__ +#define __INCLUDE_SOUND_SOF_DAI_IMX_H__ + +#include + +/* ESAI Configuration Request - SOF_IPC_DAI_ESAI_CONFIG */ +struct sof_ipc_dai_esai_params { + struct sof_ipc_hdr hdr; + + /* MCLK */ + uint16_t reserved1; + uint16_t mclk_id; + uint32_t mclk_direction; + + uint32_t mclk_rate; /* MCLK frequency in Hz */ + uint32_t fsync_rate; /* FSYNC frequency in Hz */ + uint32_t bclk_rate; /* BCLK frequency in Hz */ + + /* TDM */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + uint16_t tdm_slot_width; + uint16_t reserved2; /* alignment */ +} __packed; + +/* SAI Configuration Request - SOF_IPC_DAI_SAI_CONFIG */ +struct sof_ipc_dai_sai_params { + struct sof_ipc_hdr hdr; + + /* MCLK */ + uint16_t reserved1; + uint16_t mclk_id; + uint32_t mclk_direction; + + uint32_t mclk_rate; /* MCLK frequency in Hz */ + uint32_t fsync_rate; /* FSYNC frequency in Hz */ + uint32_t bclk_rate; /* BCLK frequency in Hz */ + + /* TDM */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + uint16_t tdm_slot_width; + uint16_t reserved2; /* alignment */ +} __packed; + +/* MICFIL Configuration Request - SOF_IPC_DAI_MICFIL_CONFIG */ +struct sof_ipc_dai_micfil_params { + uint32_t pdm_rate; + uint32_t pdm_ch; +} __packed; + +#endif diff --git a/include/sound/sof/dai-intel.h b/include/sound/sof/dai-intel.h new file mode 100644 index 000000000..e4e710b43 --- /dev/null +++ b/include/sound/sof/dai-intel.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__ +#define __INCLUDE_SOUND_SOF_DAI_INTEL_H__ + +#include + + /* ssc1: TINTE */ +#define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) + /* ssc1: PINTE */ +#define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) + /* ssc2: SMTATF */ +#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) + /* ssc2: MMRATF */ +#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) + /* ssc2: PSPSTWFDFD */ +#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) + /* ssc2: PSPSRWFDFD */ +#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) +/* ssc1: LBM */ +#define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) + + /* here is the possibility to define others aux macros */ + +#define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 +#define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 + +/* SSP clocks control settings + * + * Macros for clks_control field in sof_ipc_dai_ssp_params struct. + */ + +/* mclk 0 disable */ +#define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) +/* mclk 1 disable */ +#define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) +/* mclk keep active */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) +/* bclk keep active */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) +/* fs keep active */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) +/* bclk idle */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) +/* mclk early start */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6) +/* bclk early start */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7) +/* mclk always on */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON BIT(8) + +/* DMIC max. four controllers for eight microphone channels */ +#define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 + +/* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ +struct sof_ipc_dai_ssp_params { + struct sof_ipc_hdr hdr; + uint16_t reserved1; + uint16_t mclk_id; + + uint32_t mclk_rate; /* mclk frequency in Hz */ + uint32_t fsync_rate; /* fsync frequency in Hz */ + uint32_t bclk_rate; /* bclk frequency in Hz */ + + /* TDM */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + + /* data */ + uint32_t sample_valid_bits; + uint16_t tdm_slot_width; + uint16_t reserved2; /* alignment */ + + /* MCLK */ + uint32_t mclk_direction; + + uint16_t frame_pulse_width; + uint16_t tdm_per_slot_padding_flag; + uint32_t clks_control; + uint32_t quirks; + uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK + * will be driven, before sending data + */ +} __packed; + +/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ +struct sof_ipc_dai_hda_params { + struct sof_ipc_hdr hdr; + uint32_t link_dma_ch; + uint32_t rate; + uint32_t channels; +} __packed; + +/* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ +struct sof_ipc_dai_alh_params { + struct sof_ipc_hdr hdr; + uint32_t stream_id; + uint32_t rate; + uint32_t channels; + + /* reserved for future use */ + uint32_t reserved[13]; +} __packed; + +/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ + +/* This struct is defined per 2ch PDM controller available in the platform. + * Normally it is sufficient to set the used microphone specific enables to 1 + * and keep other parameters as zero. The customizations are: + * + * 1. If a device mixes different microphones types with different polarity + * and/or the absolute polarity matters the PCM signal from a microphone + * can be inverted with the controls. + * + * 2. If the microphones in a stereo pair do not appear in captured stream + * in desired order due to board schematics choises they can be swapped with + * the clk_edge parameter. + * + * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter + * that delays the sampling time of data by half cycles of DMIC source clock + * can be tried for improvement. However there is no guarantee for this to fix + * data integrity problems. + */ +struct sof_ipc_dai_dmic_pdm_ctrl { + struct sof_ipc_hdr hdr; + uint16_t id; /**< PDM controller ID */ + + uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ + uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ + + uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ + uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ + + uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ + uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ + + uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ +} __packed; + +/* This struct contains the global settings for all 2ch PDM controllers. The + * version number used in configuration data is checked vs. version used by + * device driver src/drivers/dmic.c need to match. It is incremented from + * initial value 1 if updates done for the to driver would alter the operation + * of the microphone. + * + * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) + * parameters need to be set as defined in microphone data sheet. E.g. clock + * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are + * multi-mode capable and there may be denied mic clock frequencies between + * the modes. In such case set the clock range limits of the desired mode to + * avoid the driver to set clock to an illegal rate. + * + * The duty cycle could be set to 48-52% if not known. Generally these + * parameters can be altered within data sheet specified limits to match + * required audio application performance power. + * + * The microphone clock needs to be usually about 50-80 times the used audio + * sample rate. With highest sample rates above 48 kHz this can relaxed + * somewhat. + * + * The parameter wake_up_time describes how long time the microphone needs + * for the data line to produce valid output from mic clock start. The driver + * will mute the captured audio for the given time. The min_clock_on_time + * parameter is used to prevent too short clock bursts to happen. The driver + * will keep the clock active after capture stop if this time is not yet + * met. The unit for both is microseconds (us). Exceed of 100 ms will be + * treated as an error. + */ +struct sof_ipc_dai_dmic_params { + struct sof_ipc_hdr hdr; + uint32_t driver_ipc_version; /**< Version (1..N) */ + + uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ + uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ + + uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ + uint32_t reserved_1; /**< Reserved */ + uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ + uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */ + + uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ + uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ + + uint32_t num_pdm_active; /**< Number of active pdm controllers. */ + /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */ + + uint32_t wake_up_time; /**< Time from clock start to data (us) */ + uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ + uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ + + /* reserved for future use */ + uint32_t reserved[5]; + + /**< PDM controllers configuration */ + struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL]; +} __packed; + +#endif diff --git a/include/sound/sof/dai-mediatek.h b/include/sound/sof/dai-mediatek.h new file mode 100644 index 000000000..62dd47205 --- /dev/null +++ b/include/sound/sof/dai-mediatek.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright(c) 2021 Mediatek Corporation. All rights reserved. + * + * Author: Bo Pan + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__ +#define __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__ + +#include + +struct sof_ipc_dai_mtk_afe_params { + struct sof_ipc_hdr hdr; + u32 channels; + u32 rate; + u32 format; + u32 stream_id; + u32 reserved[4]; /* reserve for future */ +} __packed; + +#endif + diff --git a/include/sound/sof/dai.h b/include/sound/sof/dai.h new file mode 100644 index 000000000..e3fe492e7 --- /dev/null +++ b/include/sound/sof/dai.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_H__ +#define __INCLUDE_SOUND_SOF_DAI_H__ + +#include +#include +#include +#include +#include + +/* + * DAI Configuration. + * + * Each different DAI type will have it's own structure and IPC cmd. + */ + +#define SOF_DAI_FMT_I2S 1 /**< I2S mode */ +#define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */ +#define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */ +#define SOF_DAI_FMT_DSP_A 4 /**< L data MSB after FRM LRC */ +#define SOF_DAI_FMT_DSP_B 5 /**< L data MSB during FRM LRC */ +#define SOF_DAI_FMT_PDM 6 /**< Pulse density modulation */ + +#define SOF_DAI_FMT_CONT (1 << 4) /**< continuous clock */ +#define SOF_DAI_FMT_GATED (0 << 4) /**< clock is gated */ + +#define SOF_DAI_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */ +#define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */ +#define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */ +#define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */ + +#define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */ +#define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */ +#define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */ +#define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */ + +/* keep old definitions for backwards compatibility */ +#define SOF_DAI_FMT_CBM_CFM SOF_DAI_FMT_CBP_CFP +#define SOF_DAI_FMT_CBS_CFM SOF_DAI_FMT_CBC_CFP +#define SOF_DAI_FMT_CBM_CFS SOF_DAI_FMT_CBP_CFC +#define SOF_DAI_FMT_CBS_CFS SOF_DAI_FMT_CBC_CFC + +#define SOF_DAI_FMT_FORMAT_MASK 0x000f +#define SOF_DAI_FMT_CLOCK_MASK 0x00f0 +#define SOF_DAI_FMT_INV_MASK 0x0f00 +#define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000 + +/* + * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE + * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above + * commands. + */ +#define SOF_DAI_CONFIG_FLAGS_CMD_MASK 0xF +#define SOF_DAI_CONFIG_FLAGS_NONE 0 /**< DAI_CONFIG sent without stage information */ +#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< DAI_CONFIG sent during hw_params stage */ +#define SOF_DAI_CONFIG_FLAGS_HW_FREE BIT(1) /**< DAI_CONFIG sent during hw_free stage */ +/**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */ +#define SOF_DAI_CONFIG_FLAGS_PAUSE BIT(2) +#define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4 +#define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT) +/* + * This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline + * stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available + * ABI 3.20 onwards. + */ +#define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0) + +/** \brief Types of DAI */ +enum sof_ipc_dai_type { + SOF_DAI_INTEL_NONE = 0, /**< None */ + SOF_DAI_INTEL_SSP, /**< Intel SSP */ + SOF_DAI_INTEL_DMIC, /**< Intel DMIC */ + SOF_DAI_INTEL_HDA, /**< Intel HD/A */ + SOF_DAI_INTEL_ALH, /**< Intel ALH */ + SOF_DAI_IMX_SAI, /**< i.MX SAI */ + SOF_DAI_IMX_ESAI, /**< i.MX ESAI */ + SOF_DAI_AMD_BT, /**< AMD ACP BT*/ + SOF_DAI_AMD_SP, /**< AMD ACP SP */ + SOF_DAI_AMD_DMIC, /**< AMD ACP DMIC */ + SOF_DAI_MEDIATEK_AFE, /**< Mediatek AFE */ + SOF_DAI_AMD_HS, /**< Amd HS */ + SOF_DAI_AMD_SP_VIRTUAL, /**< AMD ACP SP VIRTUAL */ + SOF_DAI_AMD_HS_VIRTUAL, /**< AMD ACP HS VIRTUAL */ + SOF_DAI_IMX_MICFIL, /** < i.MX MICFIL PDM */ + SOF_DAI_AMD_SDW, /**< AMD ACP SDW */ + SOF_DAI_INTEL_UAOL, /**< Intel UAOL */ + SOF_DAI_AMD_I2S, /**< AMD ACP I2S */ +}; + +/* general purpose DAI configuration */ +struct sof_ipc_dai_config { + struct sof_ipc_cmd_hdr hdr; + uint32_t type; /**< DAI type - enum sof_ipc_dai_type */ + uint32_t dai_index; /**< index of this type dai */ + + /* physical protocol and clocking */ + uint16_t format; /**< SOF_DAI_FMT_ */ + uint8_t group_id; /**< group ID, 0 means no group (ABI 3.17) */ + uint8_t flags; /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */ + + /* reserved for future use */ + uint32_t reserved[8]; + + /* HW specific data */ + union { + struct sof_ipc_dai_ssp_params ssp; + struct sof_ipc_dai_dmic_params dmic; + struct sof_ipc_dai_hda_params hda; + struct sof_ipc_dai_alh_params alh; + struct sof_ipc_dai_esai_params esai; + struct sof_ipc_dai_sai_params sai; + struct sof_ipc_dai_acp_params acpbt; + struct sof_ipc_dai_acp_params acpsp; + struct sof_ipc_dai_acpdmic_params acpdmic; + struct sof_ipc_dai_acp_params acphs; + struct sof_ipc_dai_mtk_afe_params afe; + struct sof_ipc_dai_micfil_params micfil; + struct sof_ipc_dai_acp_sdw_params acp_sdw; + struct sof_ipc_dai_acp_params acp_i2s; + }; +} __packed; + +struct sof_dai_private_data { + struct sof_ipc_comp_dai *comp_dai; + struct sof_ipc_dai_config *dai_config; +}; + +#endif diff --git a/include/sound/sof/debug.h b/include/sound/sof/debug.h new file mode 100644 index 000000000..8b308d7e5 --- /dev/null +++ b/include/sound/sof/debug.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2020 Intel Corporation + * + * Author: Karol Trzcinski + */ + +#ifndef __INCLUDE_SOUND_SOF_DEBUG_H__ +#define __INCLUDE_SOUND_SOF_DEBUG_H__ + +#include + +/** ABI3.18 */ +enum sof_ipc_dbg_mem_zone { + SOF_IPC_MEM_ZONE_SYS = 0, /**< System zone */ + SOF_IPC_MEM_ZONE_SYS_RUNTIME = 1, /**< System-runtime zone */ + SOF_IPC_MEM_ZONE_RUNTIME = 2, /**< Runtime zone */ + SOF_IPC_MEM_ZONE_BUFFER = 3, /**< Buffer zone */ + SOF_IPC_MEM_ZONE_RUNTIME_SHARED = 4, /**< System runtime zone */ + SOF_IPC_MEM_ZONE_SYS_SHARED = 5, /**< System shared zone */ +}; + +/** ABI3.18 */ +struct sof_ipc_dbg_mem_usage_elem { + uint32_t zone; /**< see sof_ipc_dbg_mem_zone */ + uint32_t id; /**< heap index within zone */ + uint32_t used; /**< number of bytes used in zone */ + uint32_t free; /**< number of bytes free to use within zone */ + uint32_t reserved; /**< for future use */ +} __packed; + +/** ABI3.18 */ +struct sof_ipc_dbg_mem_usage { + struct sof_ipc_reply rhdr; /**< generic IPC reply header */ + uint32_t reserved[4]; /**< reserved for future use */ + uint32_t num_elems; /**< elems[] counter */ + struct sof_ipc_dbg_mem_usage_elem elems[]; /**< memory usage information */ +} __packed; + +#endif diff --git a/include/sound/sof/ext_manifest.h b/include/sound/sof/ext_manifest.h new file mode 100644 index 000000000..7dfe3ccf1 --- /dev/null +++ b/include/sound/sof/ext_manifest.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2020 Intel Corporation + */ + +/* + * Extended manifest is a place to store metadata about firmware, known during + * compilation time - for example firmware version or used compiler. + * Given information are read on host side before firmware startup. + * This part of output binary is not signed. + */ + +#ifndef __SOF_FIRMWARE_EXT_MANIFEST_H__ +#define __SOF_FIRMWARE_EXT_MANIFEST_H__ + +#include +#include +#include +#include + +/* In ASCII `XMan` */ +#define SOF_EXT_MAN_MAGIC_NUMBER 0x6e614d58 + +/* Build u32 number in format MMmmmppp */ +#define SOF_EXT_MAN_BUILD_VERSION(MAJOR, MINOR, PATH) ((uint32_t)( \ + ((MAJOR) << 24) | \ + ((MINOR) << 12) | \ + (PATH))) + +/* check extended manifest version consistency */ +#define SOF_EXT_MAN_VERSION_INCOMPATIBLE(host_ver, cli_ver) ( \ + ((host_ver) & GENMASK(31, 24)) != \ + ((cli_ver) & GENMASK(31, 24))) + +/* used extended manifest header version */ +#define SOF_EXT_MAN_VERSION SOF_EXT_MAN_BUILD_VERSION(1, 0, 0) + +/* extended manifest header, deleting any field breaks backward compatibility */ +struct sof_ext_man_header { + uint32_t magic; /*< identification number, */ + /*< EXT_MAN_MAGIC_NUMBER */ + uint32_t full_size; /*< [bytes] full size of ext_man, */ + /*< (header + content + padding) */ + uint32_t header_size; /*< [bytes] makes header extensionable, */ + /*< after append new field to ext_man header */ + /*< then backward compatible won't be lost */ + uint32_t header_version; /*< value of EXT_MAN_VERSION */ + /*< not related with following content */ + + /* just after this header should be list of ext_man_elem_* elements */ +} __packed; + +/* Now define extended manifest elements */ + +/* Extended manifest elements types */ +enum sof_ext_man_elem_type { + SOF_EXT_MAN_ELEM_FW_VERSION = 0, + SOF_EXT_MAN_ELEM_WINDOW = 1, + SOF_EXT_MAN_ELEM_CC_VERSION = 2, + SOF_EXT_MAN_ELEM_PROBE_INFO = 3, + SOF_EXT_MAN_ELEM_DBG_ABI = 4, + SOF_EXT_MAN_ELEM_CONFIG_DATA = 5, /**< ABI3.17 */ + SOF_EXT_MAN_ELEM_PLATFORM_CONFIG_DATA = 6, +}; + +/* extended manifest element header */ +struct sof_ext_man_elem_header { + uint32_t type; /*< SOF_EXT_MAN_ELEM_ */ + uint32_t size; /*< in bytes, including header size */ + + /* just after this header should be type dependent content */ +} __packed; + +/* FW version */ +struct sof_ext_man_fw_version { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_fw_version version; + uint32_t flags; +} __packed; + +/* extended data memory windows for IPC, trace and debug */ +struct sof_ext_man_window { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_window ipc_window; +} __packed; + +/* Used C compiler description */ +struct sof_ext_man_cc_version { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_cc_version cc_version; +} __packed; + +struct ext_man_dbg_abi { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_user_abi_version dbg_abi; +} __packed; + +/* EXT_MAN_ELEM_CONFIG_DATA elements identificators, ABI3.17 */ +enum config_elem_type { + SOF_EXT_MAN_CONFIG_EMPTY = 0, + SOF_EXT_MAN_CONFIG_IPC_MSG_SIZE = 1, + SOF_EXT_MAN_CONFIG_MEMORY_USAGE_SCAN = 2, /**< ABI 3.18 */ +}; + +struct sof_config_elem { + uint32_t token; + uint32_t value; +} __packed; + +/* firmware configuration information */ +struct sof_ext_man_config_data { + struct sof_ext_man_elem_header hdr; + + struct sof_config_elem elems[]; +} __packed; + +#endif /* __SOF_FIRMWARE_EXT_MANIFEST_H__ */ diff --git a/include/sound/sof/ext_manifest4.h b/include/sound/sof/ext_manifest4.h new file mode 100644 index 000000000..4e1d379d9 --- /dev/null +++ b/include/sound/sof/ext_manifest4.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2022 Intel Corporation + */ + +/* + * Extended manifest is a place to store metadata about firmware, known during + * compilation time - for example firmware version or used compiler. + * Given information are read on host side before firmware startup. + * This part of output binary is not signed. + */ + +#ifndef __SOF_FIRMWARE_EXT_MANIFEST4_H__ +#define __SOF_FIRMWARE_EXT_MANIFEST4_H__ + +#include + +/* In ASCII $AE1 */ +#define SOF_EXT_MAN4_MAGIC_NUMBER 0x31454124 + +#define MAX_MODULE_NAME_LEN 8 +#define MAX_FW_BINARY_NAME 8 +#define DEFAULT_HASH_SHA256_LEN 32 +#define SOF_MAN4_FW_HDR_OFFSET 0x2000 +#define SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5 0x284 + +/********************************************************************* + * extended manifest (struct sof_ext_manifest4_hdr) + *------------------- + * css_manifest hdr + *------------------- + * offset reserved for future + *------------------- + * fw_hdr (struct sof_man4_fw_binary_header) + *------------------- + * module_entry[0] (struct sof_man4_module) + *------------------- + * module_entry[1] + *------------------- + * ... + *------------------- + * module_entry[n] + *------------------- + * module_config[0] (struct sof_man4_module_config) + *------------------- + * module_config[1] + *------------------- + * ... + *------------------- + * module_config[m] + *------------------- + * FW content + *------------------- + *********************************************************************/ + +struct sof_ext_manifest4_hdr { + uint32_t id; + uint32_t len; /* length of extension manifest */ + uint16_t version_major; /* header version */ + uint16_t version_minor; + uint32_t num_module_entries; +} __packed; + +struct sof_man4_fw_binary_header { + /* This part must be unchanged to be backward compatible with SPT-LP ROM */ + uint32_t id; + uint32_t len; /* sizeof(sof_man4_fw_binary_header) in bytes */ + uint8_t name[MAX_FW_BINARY_NAME]; + uint32_t preload_page_count; /* number of pages of preloaded image */ + uint32_t fw_image_flags; + uint32_t feature_mask; + uint16_t major_version; /* Firmware version */ + uint16_t minor_version; + uint16_t hotfix_version; + uint16_t build_version; + uint32_t num_module_entries; + + /* This part may change to contain any additional data for BaseFw that is skipped by ROM */ + uint32_t hw_buf_base_addr; + uint32_t hw_buf_length; + uint32_t load_offset; /* This value is used by ROM */ +} __packed; + +struct sof_man4_segment_desc { + uint32_t flags; + uint32_t v_base_addr; + uint32_t file_offset; +} __packed; + +struct sof_man4_module { + uint32_t id; + uint8_t name[MAX_MODULE_NAME_LEN]; + guid_t uuid; + uint32_t type; + uint8_t hash[DEFAULT_HASH_SHA256_LEN]; + uint32_t entry_point; + uint16_t cfg_offset; + uint16_t cfg_count; + uint32_t affinity_mask; + uint16_t instance_max_count; + uint16_t instance_stack_size; + struct sof_man4_segment_desc segments[3]; +} __packed; + +struct sof_man4_module_config { + uint32_t par[4]; /* module parameters */ + uint32_t is_bytes; /* actual size of instance .bss (bytes) */ + uint32_t cps; /* cycles per second */ + uint32_t ibs; /* input buffer size (bytes) */ + uint32_t obs; /* output buffer size (bytes) */ + uint32_t module_flags; /* flags, reserved for future use */ + uint32_t cpc; /* cycles per single run */ + uint32_t obls; /* output block size, reserved for future use */ +} __packed; + +#endif /* __SOF_FIRMWARE_EXT_MANIFEST4_H__ */ diff --git a/include/sound/sof/header.h b/include/sound/sof/header.h new file mode 100644 index 000000000..6c2c3a5fc --- /dev/null +++ b/include/sound/sof/header.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_HEADER_H__ +#define __INCLUDE_SOUND_SOF_HEADER_H__ + +#include +#include + +/** \addtogroup sof_uapi uAPI + * SOF uAPI specification. + * @{ + */ + +/* + * IPC messages have a prefixed 32 bit identifier made up as follows :- + * + * 0xGCCCNNNN where + * G is global cmd type (4 bits) + * C is command type (12 bits) + * I is the ID number (16 bits) - monotonic and overflows + * + * This is sent at the start of the IPM message in the mailbox. Messages should + * not be sent in the doorbell (special exceptions for firmware . + */ + +/* Global Message - Generic */ +#define SOF_GLB_TYPE_SHIFT 28 +#define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT) +#define SOF_GLB_TYPE(x) ((x) << SOF_GLB_TYPE_SHIFT) + +/* Command Message - Generic */ +#define SOF_CMD_TYPE_SHIFT 16 +#define SOF_CMD_TYPE_MASK (0xfffL << SOF_CMD_TYPE_SHIFT) +#define SOF_CMD_TYPE(x) ((x) << SOF_CMD_TYPE_SHIFT) + +/* Global Message Types */ +#define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U) +#define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U) +#define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U) +#define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U) +#define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U) +#define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U) +#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U) +#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U) +#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U) +#define SOF_IPC_GLB_GDB_DEBUG SOF_GLB_TYPE(0xAU) +#define SOF_IPC_GLB_TEST_MSG SOF_GLB_TYPE(0xBU) +#define SOF_IPC_GLB_PROBE SOF_GLB_TYPE(0xCU) +#define SOF_IPC_GLB_DEBUG SOF_GLB_TYPE(0xDU) + +/* + * DSP Command Message Types + */ + +/* topology */ +#define SOF_IPC_TPLG_COMP_NEW SOF_CMD_TYPE(0x001) +#define SOF_IPC_TPLG_COMP_FREE SOF_CMD_TYPE(0x002) +#define SOF_IPC_TPLG_COMP_CONNECT SOF_CMD_TYPE(0x003) +#define SOF_IPC_TPLG_PIPE_NEW SOF_CMD_TYPE(0x010) +#define SOF_IPC_TPLG_PIPE_FREE SOF_CMD_TYPE(0x011) +#define SOF_IPC_TPLG_PIPE_CONNECT SOF_CMD_TYPE(0x012) +#define SOF_IPC_TPLG_PIPE_COMPLETE SOF_CMD_TYPE(0x013) +#define SOF_IPC_TPLG_BUFFER_NEW SOF_CMD_TYPE(0x020) +#define SOF_IPC_TPLG_BUFFER_FREE SOF_CMD_TYPE(0x021) + +/* PM */ +#define SOF_IPC_PM_CTX_SAVE SOF_CMD_TYPE(0x001) +#define SOF_IPC_PM_CTX_RESTORE SOF_CMD_TYPE(0x002) +#define SOF_IPC_PM_CTX_SIZE SOF_CMD_TYPE(0x003) +#define SOF_IPC_PM_CLK_SET SOF_CMD_TYPE(0x004) +#define SOF_IPC_PM_CLK_GET SOF_CMD_TYPE(0x005) +#define SOF_IPC_PM_CLK_REQ SOF_CMD_TYPE(0x006) +#define SOF_IPC_PM_CORE_ENABLE SOF_CMD_TYPE(0x007) +#define SOF_IPC_PM_GATE SOF_CMD_TYPE(0x008) + +/* component runtime config - multiple different types */ +#define SOF_IPC_COMP_SET_VALUE SOF_CMD_TYPE(0x001) +#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002) +#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003) +#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004) +#define SOF_IPC_COMP_NOTIFICATION SOF_CMD_TYPE(0x005) + +/* DAI messages */ +#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001) +#define SOF_IPC_DAI_LOOPBACK SOF_CMD_TYPE(0x002) + +/* stream */ +#define SOF_IPC_STREAM_PCM_PARAMS SOF_CMD_TYPE(0x001) +#define SOF_IPC_STREAM_PCM_PARAMS_REPLY SOF_CMD_TYPE(0x002) +#define SOF_IPC_STREAM_PCM_FREE SOF_CMD_TYPE(0x003) +#define SOF_IPC_STREAM_TRIG_START SOF_CMD_TYPE(0x004) +#define SOF_IPC_STREAM_TRIG_STOP SOF_CMD_TYPE(0x005) +#define SOF_IPC_STREAM_TRIG_PAUSE SOF_CMD_TYPE(0x006) +#define SOF_IPC_STREAM_TRIG_RELEASE SOF_CMD_TYPE(0x007) +#define SOF_IPC_STREAM_TRIG_DRAIN SOF_CMD_TYPE(0x008) +#define SOF_IPC_STREAM_TRIG_XRUN SOF_CMD_TYPE(0x009) +#define SOF_IPC_STREAM_POSITION SOF_CMD_TYPE(0x00a) +#define SOF_IPC_STREAM_VORBIS_PARAMS SOF_CMD_TYPE(0x010) +#define SOF_IPC_STREAM_VORBIS_FREE SOF_CMD_TYPE(0x011) + +/* probe */ +#define SOF_IPC_PROBE_INIT SOF_CMD_TYPE(0x001) +#define SOF_IPC_PROBE_DEINIT SOF_CMD_TYPE(0x002) +#define SOF_IPC_PROBE_DMA_ADD SOF_CMD_TYPE(0x003) +#define SOF_IPC_PROBE_DMA_INFO SOF_CMD_TYPE(0x004) +#define SOF_IPC_PROBE_DMA_REMOVE SOF_CMD_TYPE(0x005) +#define SOF_IPC_PROBE_POINT_ADD SOF_CMD_TYPE(0x006) +#define SOF_IPC_PROBE_POINT_INFO SOF_CMD_TYPE(0x007) +#define SOF_IPC_PROBE_POINT_REMOVE SOF_CMD_TYPE(0x008) + +/* trace */ +#define SOF_IPC_TRACE_DMA_PARAMS SOF_CMD_TYPE(0x001) +#define SOF_IPC_TRACE_DMA_POSITION SOF_CMD_TYPE(0x002) +#define SOF_IPC_TRACE_DMA_PARAMS_EXT SOF_CMD_TYPE(0x003) +#define SOF_IPC_TRACE_FILTER_UPDATE SOF_CMD_TYPE(0x004) /**< ABI3.17 */ +#define SOF_IPC_TRACE_DMA_FREE SOF_CMD_TYPE(0x005) /**< ABI3.20 */ + +/* debug */ +#define SOF_IPC_DEBUG_MEM_USAGE SOF_CMD_TYPE(0x001) + +/* test */ +#define SOF_IPC_TEST_IPC_FLOOD SOF_CMD_TYPE(0x001) + +/* Get message component id */ +#define SOF_IPC_MESSAGE_ID(x) ((x) & 0xffff) + +/* maximum message size for mailbox Tx/Rx */ +#define SOF_IPC_MSG_MAX_SIZE 384 + +/* + * Structure Header - Header for all IPC structures except command structs. + * The size can be greater than the structure size and that means there is + * extended bespoke data beyond the end of the structure including variable + * arrays. + */ + +struct sof_ipc_hdr { + uint32_t size; /**< size of structure */ +} __packed; + +/* + * Command Header - Header for all IPC commands. Identifies IPC message. + * The size can be greater than the structure size and that means there is + * extended bespoke data beyond the end of the structure including variable + * arrays. + */ + +struct sof_ipc_cmd_hdr { + uint32_t size; /**< size of structure */ + uint32_t cmd; /**< SOF_IPC_GLB_ + cmd */ +} __packed; + +/* + * Generic reply message. Some commands override this with their own reply + * types that must include this at start. + */ +struct sof_ipc_reply { + struct sof_ipc_cmd_hdr hdr; + int32_t error; /**< negative error numbers */ +} __packed; + +/* + * Compound commands - SOF_IPC_GLB_COMPOUND. + * + * Compound commands are sent to the DSP as a single IPC operation. The + * commands are split into blocks and each block has a header. This header + * identifies the command type and the number of commands before the next + * header. + */ + +struct sof_ipc_compound_hdr { + struct sof_ipc_cmd_hdr hdr; + uint32_t count; /**< count of 0 means end of compound sequence */ +} __packed; + +/* + * OOPS header architecture specific data. + */ +struct sof_ipc_dsp_oops_arch_hdr { + uint32_t arch; /* Identifier of architecture */ + uint32_t totalsize; /* Total size of oops message */ +} __packed; + +/* + * OOPS header platform specific data. + */ +struct sof_ipc_dsp_oops_plat_hdr { + uint32_t configidhi; /* ConfigID hi 32bits */ + uint32_t configidlo; /* ConfigID lo 32bits */ + uint32_t numaregs; /* Special regs num */ + uint32_t stackoffset; /* Offset to stack pointer from beginning of + * oops message + */ + uint32_t stackptr; /* Stack ptr */ +} __packed; + +/** @}*/ + +#endif diff --git a/include/sound/sof/info.h b/include/sound/sof/info.h new file mode 100644 index 000000000..08400fbe5 --- /dev/null +++ b/include/sound/sof/info.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_INFO_H__ +#define __INCLUDE_SOUND_SOF_INFO_H__ + +#include +#include + +/* + * Firmware boot and version + */ + +#define SOF_IPC_MAX_ELEMS 16 + +/* + * Firmware boot info flag bits (64-bit) + */ +#define SOF_IPC_INFO_BUILD BIT(0) +#define SOF_IPC_INFO_LOCKS BIT(1) +#define SOF_IPC_INFO_LOCKSV BIT(2) +#define SOF_IPC_INFO_GDB BIT(3) +#define SOF_IPC_INFO_D3_PERSISTENT BIT(4) + +/* extended data types that can be appended onto end of sof_ipc_fw_ready */ +enum sof_ipc_ext_data { + SOF_IPC_EXT_UNUSED = 0, + SOF_IPC_EXT_WINDOW = 1, + SOF_IPC_EXT_CC_INFO = 2, + SOF_IPC_EXT_PROBE_INFO = 3, + SOF_IPC_EXT_USER_ABI_INFO = 4, +}; + +/* Build u32 number in format MMmmmppp */ +#define SOF_FW_VER(MAJOR, MINOR, PATCH) ((uint32_t)( \ + ((MAJOR) << 24) | ((MINOR) << 12) | (PATCH))) + +/* FW version - SOF_IPC_GLB_VERSION */ +struct sof_ipc_fw_version { + struct sof_ipc_hdr hdr; + uint16_t major; + uint16_t minor; + uint16_t micro; + uint16_t build; + uint8_t date[12]; + uint8_t time[10]; + uint8_t tag[6]; + uint32_t abi_version; + /* used to check FW and ldc file compatibility, reproducible value */ + uint32_t src_hash; + + /* reserved for future use */ + uint32_t reserved[3]; +} __packed; + +/* FW ready Message - sent by firmware when boot has completed */ +struct sof_ipc_fw_ready { + struct sof_ipc_cmd_hdr hdr; + uint32_t dspbox_offset; /* dsp initiated IPC mailbox */ + uint32_t hostbox_offset; /* host initiated IPC mailbox */ + uint32_t dspbox_size; + uint32_t hostbox_size; + struct sof_ipc_fw_version version; + + /* Miscellaneous flags */ + uint64_t flags; + + /* reserved for future use */ + uint32_t reserved[4]; +} __packed; + +/* + * Extended Firmware data. All optional, depends on platform/arch. + */ +enum sof_ipc_region { + SOF_IPC_REGION_DOWNBOX = 0, + SOF_IPC_REGION_UPBOX, + SOF_IPC_REGION_TRACE, + SOF_IPC_REGION_DEBUG, + SOF_IPC_REGION_STREAM, + SOF_IPC_REGION_REGS, + SOF_IPC_REGION_EXCEPTION, +}; + +struct sof_ipc_ext_data_hdr { + struct sof_ipc_cmd_hdr hdr; + uint32_t type; /**< SOF_IPC_EXT_ */ +} __packed; + +struct sof_ipc_window_elem { + struct sof_ipc_hdr hdr; + uint32_t type; /**< SOF_IPC_REGION_ */ + uint32_t id; /**< platform specific - used to map to host memory */ + uint32_t flags; /**< R, W, RW, etc - to define */ + uint32_t size; /**< size of region in bytes */ + /* offset in window region as windows can be partitioned */ + uint32_t offset; +} __packed; + +/* extended data memory windows for IPC, trace and debug */ +struct sof_ipc_window { + struct sof_ipc_ext_data_hdr ext_hdr; + uint32_t num_windows; + struct sof_ipc_window_elem window[SOF_IPC_MAX_ELEMS]; +} __packed; + +struct sof_ipc_cc_version { + struct sof_ipc_ext_data_hdr ext_hdr; + uint32_t major; + uint32_t minor; + uint32_t micro; + + /* reserved for future use */ + uint32_t reserved[4]; + + uint8_t name[16]; /* null terminated compiler name */ + uint8_t optim[4]; /* null terminated compiler -O flag value */ + uint8_t desc[32]; /* null terminated compiler description */ +} __packed; + +/* extended data: Probe setup */ +struct sof_ipc_probe_support { + struct sof_ipc_ext_data_hdr ext_hdr; + + uint32_t probe_points_max; + uint32_t injection_dmas_max; + + /* reserved for future use */ + uint32_t reserved[2]; +} __packed; + +/* extended data: user abi version(s) */ +struct sof_ipc_user_abi_version { + struct sof_ipc_ext_data_hdr ext_hdr; + + uint32_t abi_dbg_version; +} __packed; + +#endif diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h new file mode 100644 index 000000000..cea3d9453 --- /dev/null +++ b/include/sound/sof/ipc4/header.h @@ -0,0 +1,791 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2022 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ +#define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ + +#include +#include + +/* maximum message size for mailbox Tx/Rx */ +#define SOF_IPC4_MSG_MAX_SIZE 4096 + +/** \addtogroup sof_uapi uAPI + * SOF uAPI specification. + * @{ + */ + +/** + * struct sof_ipc4_msg - Placeholder of an IPC4 message + * @header_u64: IPC4 header as single u64 number + * @primary: Primary, mandatory part of the header + * @extension: Extended part of the header, if not used it should be + * set to 0 + * @data_size: Size of data in bytes pointed by @data_ptr + * @data_ptr: Pointer to the optional payload of a message + */ +struct sof_ipc4_msg { + union { + u64 header_u64; + struct { + u32 primary; + u32 extension; + }; + }; + + size_t data_size; + void *data_ptr; +}; + +/** + * struct sof_ipc4_tuple - Generic type/ID and parameter tuple + * @type: type/ID + * @size: size of the @value array in bytes + * @value: value for the given type + */ +struct sof_ipc4_tuple { + uint32_t type; + uint32_t size; + uint32_t value[]; +} __packed; + +/* + * IPC4 messages have two 32 bit identifier made up as follows :- + * + * header - msg type, msg id, msg direction ... + * extension - extra params such as msg data size in mailbox + * + * These are sent at the start of the IPC message in the mailbox. Messages + * should not be sent in the doorbell (special exceptions for firmware). + */ + +/* + * IPC4 primary header bit allocation for messages + * bit 0-23: message type specific + * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG + * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG + * bit 29: response - sof_ipc4_msg_dir + * bit 30: target - enum sof_ipc4_msg_target + * bit 31: reserved, unused + */ + +/* Value of target field - must fit into 1 bit */ +enum sof_ipc4_msg_target { + /* Global FW message */ + SOF_IPC4_FW_GEN_MSG, + + /* Module message */ + SOF_IPC4_MODULE_MSG +}; + +/* Value of type field - must fit into 5 bits */ +enum sof_ipc4_global_msg { + SOF_IPC4_GLB_BOOT_CONFIG, + SOF_IPC4_GLB_ROM_CONTROL, + SOF_IPC4_GLB_IPCGATEWAY_CMD, + + /* 3 .. 12: RESERVED - do not use */ + + SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13, + SOF_IPC4_GLB_CHAIN_DMA, + + SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES, + SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES, + + /* pipeline settings */ + SOF_IPC4_GLB_CREATE_PIPELINE, + SOF_IPC4_GLB_DELETE_PIPELINE, + SOF_IPC4_GLB_SET_PIPELINE_STATE, + SOF_IPC4_GLB_GET_PIPELINE_STATE, + SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE, + SOF_IPC4_GLB_SAVE_PIPELINE, + SOF_IPC4_GLB_RESTORE_PIPELINE, + + /* + * library loading + * + * Loads library (using Code Load or HD/A Host Output DMA) + */ + SOF_IPC4_GLB_LOAD_LIBRARY, + /* + * Prepare the host DMA channel for library loading, must be followed by + * a SOF_IPC4_GLB_LOAD_LIBRARY message as the library loading step + */ + SOF_IPC4_GLB_LOAD_LIBRARY_PREPARE, + + SOF_IPC4_GLB_INTERNAL_MESSAGE, + + /* Notification (FW to SW driver) */ + SOF_IPC4_GLB_NOTIFICATION, + + /* 28 .. 31: RESERVED - do not use */ + + SOF_IPC4_GLB_TYPE_LAST, +}; + +/* Value of response field - must fit into 1 bit */ +enum sof_ipc4_msg_dir { + SOF_IPC4_MSG_REQUEST, + SOF_IPC4_MSG_REPLY, +}; + +enum sof_ipc4_pipeline_state { + SOF_IPC4_PIPE_INVALID_STATE, + SOF_IPC4_PIPE_UNINITIALIZED, + SOF_IPC4_PIPE_RESET, + SOF_IPC4_PIPE_PAUSED, + SOF_IPC4_PIPE_RUNNING, + SOF_IPC4_PIPE_EOS +}; + +/* Generic message fields (bit 24-30) */ + +/* encoded to header's msg_tgt field */ +#define SOF_IPC4_MSG_TARGET_SHIFT 30 +#define SOF_IPC4_MSG_TARGET_MASK BIT(30) +#define SOF_IPC4_MSG_TARGET(x) ((x) << SOF_IPC4_MSG_TARGET_SHIFT) +#define SOF_IPC4_MSG_IS_MODULE_MSG(x) ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0) + +/* encoded to header's rsp field */ +#define SOF_IPC4_MSG_DIR_SHIFT 29 +#define SOF_IPC4_MSG_DIR_MASK BIT(29) +#define SOF_IPC4_MSG_DIR(x) ((x) << SOF_IPC4_MSG_DIR_SHIFT) + +/* encoded to header's type field */ +#define SOF_IPC4_MSG_TYPE_SHIFT 24 +#define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24) +#define SOF_IPC4_MSG_TYPE_SET(x) (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \ + SOF_IPC4_MSG_TYPE_MASK) +#define SOF_IPC4_MSG_TYPE_GET(x) (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \ + SOF_IPC4_MSG_TYPE_SHIFT) + +/* Global message type specific field definitions */ + +/* pipeline creation ipc msg */ +#define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT 16 +#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16) +#define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT) + +#define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT 11 +#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11) +#define SOF_IPC4_GLB_PIPE_PRIORITY(x) ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT) + +#define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0) +#define SOF_IPC4_GLB_PIPE_MEM_SIZE(x) ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0) +#define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT 20 +#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20) +#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT) + +#define SOF_IPC4_GLB_PIPE_PAYLOAD_SHIFT 29 +#define SOF_IPC4_GLB_PIPE_PAYLOAD_MASK BIT(29) +#define SOF_IPC4_GLB_PIPE_PAYLOAD(x) ((x) << SOF_IPC4_GLB_PIPE_PAYLOAD_SHIFT) + +/* pipeline set state ipc msg */ +#define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16 +#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16) +#define SOF_IPC4_GLB_PIPE_STATE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT) + +#define SOF_IPC4_GLB_PIPE_STATE_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0) +#define SOF_IPC4_GLB_PIPE_STATE(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT) + +/* pipeline set state IPC msg extension */ +#define SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI BIT(0) + +/* load library ipc msg */ +#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16 +#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT) + +/* chain dma ipc message */ +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0 +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0) +#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \ + SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK) + +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8 +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8) +#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \ + SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK) + +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16 +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16) +#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT) + +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17 +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17) +#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT) + +#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18 +#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18) +#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT) + +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0 +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0) +#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \ + SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \ + SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK) + +enum sof_ipc4_channel_config { + /* one channel only. */ + SOF_IPC4_CHANNEL_CONFIG_MONO, + /* L & R. */ + SOF_IPC4_CHANNEL_CONFIG_STEREO, + /* L, R & LFE; PCM only. */ + SOF_IPC4_CHANNEL_CONFIG_2_POINT_1, + /* L, C & R; MP3 & AAC only. */ + SOF_IPC4_CHANNEL_CONFIG_3_POINT_0, + /* L, C, R & LFE; PCM only. */ + SOF_IPC4_CHANNEL_CONFIG_3_POINT_1, + /* L, R, Ls & Rs; PCM only. */ + SOF_IPC4_CHANNEL_CONFIG_QUATRO, + /* L, C, R & Cs; MP3 & AAC only. */ + SOF_IPC4_CHANNEL_CONFIG_4_POINT_0, + /* L, C, R, Ls & Rs. */ + SOF_IPC4_CHANNEL_CONFIG_5_POINT_0, + /* L, C, R, Ls, Rs & LFE. */ + SOF_IPC4_CHANNEL_CONFIG_5_POINT_1, + /* one channel replicated in two. */ + SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO, + /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */ + SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0, + /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */ + SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1, + /* L, C, R, Ls, Rs & LFE., LS, RS */ + SOF_IPC4_CHANNEL_CONFIG_7_POINT_1, +}; + +enum sof_ipc4_interleaved_style { + SOF_IPC4_CHANNELS_INTERLEAVED, + SOF_IPC4_CHANNELS_NONINTERLEAVED, +}; + +enum sof_ipc4_sample_type { + SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */ + SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */ +}; + +struct sof_ipc4_audio_format { + uint32_t sampling_frequency; + uint32_t bit_depth; + uint32_t ch_map; + uint32_t ch_cfg; /* sof_ipc4_channel_config */ + uint32_t interleaving_style; + uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */ +} __packed __aligned(4); + +#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT 0 +#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0) +#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \ + ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK) +#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8 +#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8) +#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x) \ + (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \ + SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT) +#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16 +#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16) +#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x) \ + (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >> \ + SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT) + +/* Module message type specific field definitions */ + +enum sof_ipc4_module_type { + SOF_IPC4_MOD_INIT_INSTANCE, + SOF_IPC4_MOD_CONFIG_GET, + SOF_IPC4_MOD_CONFIG_SET, + SOF_IPC4_MOD_LARGE_CONFIG_GET, + SOF_IPC4_MOD_LARGE_CONFIG_SET, + SOF_IPC4_MOD_BIND, + SOF_IPC4_MOD_UNBIND, + SOF_IPC4_MOD_SET_DX, + SOF_IPC4_MOD_SET_D0IX, + SOF_IPC4_MOD_ENTER_MODULE_RESTORE, + SOF_IPC4_MOD_EXIT_MODULE_RESTORE, + SOF_IPC4_MOD_DELETE_INSTANCE, + + SOF_IPC4_MOD_TYPE_LAST, +}; + +struct sof_ipc4_base_module_cfg { + uint32_t cpc; /* the max count of Cycles Per Chunk processing */ + uint32_t ibs; /* input Buffer Size (in bytes) */ + uint32_t obs; /* output Buffer Size (in bytes) */ + uint32_t is_pages; /* number of physical pages used */ + struct sof_ipc4_audio_format audio_fmt; +} __packed __aligned(4); + +/* common module ipc msg */ +#define SOF_IPC4_MOD_INSTANCE_SHIFT 16 +#define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16) +#define SOF_IPC4_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT) +#define SOF_IPC4_MOD_INSTANCE_GET(x) (((x) & SOF_IPC4_MOD_INSTANCE_MASK) \ + >> SOF_IPC4_MOD_INSTANCE_SHIFT) + +#define SOF_IPC4_MOD_ID_SHIFT 0 +#define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0) +#define SOF_IPC4_MOD_ID(x) ((x) << SOF_IPC4_MOD_ID_SHIFT) +#define SOF_IPC4_MOD_ID_GET(x) (((x) & SOF_IPC4_MOD_ID_MASK) \ + >> SOF_IPC4_MOD_ID_SHIFT) + +/* init module ipc msg */ +#define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT 0 +#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0) +#define SOF_IPC4_MOD_EXT_PARAM_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT) + +#define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT 16 +#define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16) +#define SOF_IPC4_MOD_EXT_PPL_ID(x) ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT 24 +#define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24) +#define SOF_IPC4_MOD_EXT_CORE_ID(x) ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT 28 +#define SOF_IPC4_MOD_EXT_DOMAIN_MASK BIT(28) +#define SOF_IPC4_MOD_EXT_DOMAIN(x) ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT) + +#define SOF_IPC4_MOD_EXT_EXTENDED_INIT_SHIFT 29 +#define SOF_IPC4_MOD_EXT_EXTENDED_INIT_MASK BIT(29) +#define SOF_IPC4_MOD_EXT_EXTENDED_INIT(x) ((x) << SOF_IPC4_MOD_EXT_EXTENDED_SHIFT) + +/* bind/unbind module ipc msg */ +#define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT 0 +#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0) +#define SOF_IPC4_MOD_EXT_DST_MOD_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16 +#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16) +#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT) + +#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24 +#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24) +#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27 +#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27) +#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT) + +#define MOD_ENABLE_LOG 6 +#define MOD_SYSTEM_TIME 20 + +/* set module large config */ +#define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT 0 +#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0) +#define SOF_IPC4_MOD_EXT_MSG_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT) + +#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20 +#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20) +#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x) ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT 28 +#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK BIT(28) +#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT) + +#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT 29 +#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK BIT(29) +#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT) + +/* Init instance messagees */ +#define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID 0 +#define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID 0 + +enum sof_ipc4_base_fw_params { + SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6, + SOF_IPC4_FW_PARAM_FW_CONFIG, + SOF_IPC4_FW_PARAM_HW_CONFIG_GET, + SOF_IPC4_FW_PARAM_MODULES_INFO_GET, + SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16, + SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20, + SOF_IPC4_FW_PARAM_MIC_PRIVACY_STATE_CHANGE = 35, +}; + +enum sof_ipc4_fw_config_params { + SOF_IPC4_FW_CFG_FW_VERSION, + SOF_IPC4_FW_CFG_MEMORY_RECLAIMED, + SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ, + SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ, + SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG, + SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL, + SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES, + SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES, + SOF_IPC4_FW_CFG_TRACE_LOG_BYTES, + SOF_IPC4_FW_CFG_MAX_PPL_COUNT, + SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT, + SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT, + SOF_IPC4_FW_CFG_MODULES_COUNT, + SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT, + SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT, + SOF_IPC4_FW_CFG_LL_PRI_COUNT, + SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT, + SOF_IPC4_FW_CFG_MAX_LIBS_COUNT, + SOF_IPC4_FW_CFG_SCHEDULER_CONFIG, + SOF_IPC4_FW_CFG_XTAL_FREQ_HZ, + SOF_IPC4_FW_CFG_CLOCKS_CONFIG, + SOF_IPC4_FW_CFG_RESERVED, + SOF_IPC4_FW_CFG_POWER_GATING_POLICY, + SOF_IPC4_FW_CFG_ASSERT_MODE, + SOF_IPC4_FW_RESERVED1, + SOF_IPC4_FW_RESERVED2, + SOF_IPC4_FW_RESERVED3, + SOF_IPC4_FW_RESERVED4, + SOF_IPC4_FW_RESERVED5, + SOF_IPC4_FW_CONTEXT_SAVE +}; + +struct sof_ipc4_fw_version { + uint16_t major; + uint16_t minor; + uint16_t hotfix; + uint16_t build; +} __packed; + +/* Payload data for SOF_IPC4_MOD_SET_DX */ +struct sof_ipc4_dx_state_info { + /* core(s) to apply the change */ + uint32_t core_mask; + /* core state: 0: put core_id to D3; 1: put core_id to D0 */ + uint32_t dx_mask; +} __packed __aligned(4); + +enum sof_ipc4_hw_config_params { + SOF_IPC4_HW_CFG_INTEL_MIC_PRIVACY_CAPS = 11, +}; + +#define SOF_IPC_INTEL_MIC_PRIVACY_VERSION_PTL 1 + +struct sof_ipc4_intel_mic_privacy_cap { + uint32_t version; + uint32_t capabilities_length; + uint32_t capabilities[]; +} __packed; + +/* Reply messages */ + +/* + * IPC4 primary header bit allocation for replies + * bit 0-23: status + * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG + * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG + * bit 29: response - sof_ipc4_msg_dir + * bit 30: target - enum sof_ipc4_msg_target + * bit 31: reserved, unused + */ + +#define SOF_IPC4_REPLY_STATUS GENMASK(23, 0) + +/* Notification messages */ + +/* + * IPC4 primary header bit allocation for notifications + * bit 0-15: notification type specific + * bit 16-23: enum sof_ipc4_notification_type + * bit 24-28: SOF_IPC4_GLB_NOTIFICATION + * bit 29: response - sof_ipc4_msg_dir + * bit 30: target - enum sof_ipc4_msg_target + * bit 31: reserved, unused + */ + +#define SOF_IPC4_MSG_IS_NOTIFICATION(x) (SOF_IPC4_MSG_TYPE_GET(x) == \ + SOF_IPC4_GLB_NOTIFICATION) + +#define SOF_IPC4_NOTIFICATION_TYPE_SHIFT 16 +#define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16) +#define SOF_IPC4_NOTIFICATION_TYPE_GET(x) (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \ + SOF_IPC4_NOTIFICATION_TYPE_SHIFT) + +#define SOF_IPC4_LOG_CORE_SHIFT 12 +#define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12) +#define SOF_IPC4_LOG_CORE_GET(x) (((x) & SOF_IPC4_LOG_CORE_MASK) >> \ + SOF_IPC4_LOG_CORE_SHIFT) + +#define SOF_IPC4_FW_READY_LIB_RESTORED BIT(15) + +/* Value of notification type field - must fit into 8 bits */ +enum sof_ipc4_notification_type { + /* Phrase detected (notification from WoV module) */ + SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4, + /* Event from a resource (pipeline or module instance) */ + SOF_IPC4_NOTIFY_RESOURCE_EVENT, + /* Debug log buffer status changed */ + SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS, + /* Timestamp captured at the link */ + SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED, + /* FW complete initialization */ + SOF_IPC4_NOTIFY_FW_READY, + /* Audio classifier result (ACA) */ + SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT, + /* Exception caught by DSP FW */ + SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT, + /* 11 is skipped by the existing cavs firmware */ + /* Custom module notification */ + SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12, + /* 13 is reserved - do not use */ + /* Probe notify data available */ + SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14, + /* AM module notifications */ + SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE, + + SOF_IPC4_NOTIFY_TYPE_LAST, +}; + +enum sof_ipc4_resource_type { + SOF_IPC4_MODULE_INSTANCE, + SOF_IPC4_PIPELINE, + SOF_IPC4_GATEWAY, + SOF_IPC4_EDF_TASK, + SOF_IPC4_INVALID_RESOURCE_TYPE, +}; + +enum sof_ipc4_event_type { + /* Underrun detected by the Mixer */ + SOF_IPC4_MIXER_UNDERRUN_DETECTED = 1, + /* Error caught during data processing */ + SOF_IPC4_PROCESS_DATA_ERROR = 3, + /* Underrun detected by gateway. */ + SOF_IPC4_GATEWAY_UNDERRUN_DETECTED = 6, + /* Overrun detected by gateway */ + SOF_IPC4_GATEWAY_OVERRUN_DETECTED, +}; + +/** + * struct sof_ipc4_process_data_error_event_data - process data error event payload + * @error_code: Error code returned by data processing function + */ +struct sof_ipc4_process_data_error_event_data { + uint32_t error_code; +}; + +/** + * struct sof_ipc4_mixer_underrun_event_data - mixer underrun event payload + * @eos_flag: Indicates EndOfStream + * @data_mixed: Data processed by module (in bytes) + * @expected_data_mixed: Expected data to be processed (in bytes) + */ +struct sof_ipc4_mixer_underrun_event_data { + uint32_t eos_flag; + uint32_t data_mixed; + uint32_t expected_data_mixed; +}; + +/** + * union sof_ipc4_resource_event_data - resource event specific payload + * @dws: Raw event data payload as six dwords + * @process_data_error: SOF_IPC4_PROCESS_DATA_ERROR payload + * @mixer_underrun: SOF_IPC4_MIXER_UNDERRUN_DETECTED payload + */ +union sof_ipc4_resource_event_data { + uint32_t dws[6]; + struct sof_ipc4_process_data_error_event_data process_data_error; + struct sof_ipc4_mixer_underrun_event_data mixer_underrun; +}; + +struct sof_ipc4_notify_resource_data { + uint32_t resource_type; + uint32_t resource_id; + uint32_t event_type; + uint32_t reserved; + union sof_ipc4_resource_event_data data; +} __packed __aligned(4); + +#define SOF_IPC4_DEBUG_DESCRIPTOR_SIZE 12 /* 3 x u32 */ + +/* + * The debug memory window is divided into 16 slots, and the + * first slot is used as a recorder for the other 15 slots. + */ +#define SOF_IPC4_MAX_DEBUG_SLOTS 15 +#define SOF_IPC4_DEBUG_SLOT_SIZE 0x1000 + +/* debug log slot types */ +#define SOF_IPC4_DEBUG_SLOT_UNUSED 0x00000000 +#define SOF_IPC4_DEBUG_SLOT_CRITICAL_LOG 0x54524300 /* byte 0: core ID */ +#define SOF_IPC4_DEBUG_SLOT_DEBUG_LOG 0x474f4c00 /* byte 0: core ID */ +#define SOF_IPC4_DEBUG_SLOT_GDB_STUB 0x42444700 +#define SOF_IPC4_DEBUG_SLOT_TELEMETRY 0x4c455400 +#define SOF_IPC4_DEBUG_SLOT_BROKEN 0x44414544 + +/** + * struct sof_ipc4_notify_module_data - payload for module notification + * @instance_id: instance ID of the originator module of the notification + * @module_id: module ID of the originator of the notification + * @event_id: module specific event id + * @event_data_size: Size of the @event_data (if any) in bytes + * @event_data: Optional notification data, module and notification dependent + */ +struct sof_ipc4_notify_module_data { + uint16_t instance_id; + uint16_t module_id; + uint32_t event_id; + uint32_t event_data_size; + uint8_t event_data[]; +} __packed __aligned(4); + +/* + * ALSA kcontrol change notification + * + * The event_id of struct sof_ipc4_notify_module_data is divided into two u16: + * upper u16: magic number for ALSA kcontrol types: 0xA15A + * lower u16: param_id of the control, which is the type of the control + * The event_data contains the struct sof_ipc4_control_msg_payload of the control + * which sent the notification. + */ +#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_MASK GENMASK(31, 16) +#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_VAL 0xA15A0000 +#define SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_PARAMID_MASK GENMASK(15, 0) + +/* + * Macros for creating struct sof_ipc4_module_init_ext_init payload + * with its associated data. ext_init payload should be the first + * piece of payload following SOF_IPC4_MOD_INIT_INSTANCE msg, and its + * existence is indicated with SOF_IPC4_MOD_EXT_EXTENDED-bit. + * + * The macros below apply to sof_ipc4_module_init_ext_init.word0 + */ +#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_SHIFT 0 +#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_MASK BIT(0) +#define SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN(x) ((x) << SOF_IPC4_MOD_INIT_EXT_RTOS_DOMAIN_SHIFT) + +#define SOF_IPC4_MOD_INIT_EXT_GNA_USED_SHIFT 1 +#define SOF_IPC4_MOD_INIT_EXT_GNA_USED_MASK BIT(1) +#define SOF_IPC4_MOD_INIT_EXT_GNA_USED(x) ((x) << SOF_IPC4_MOD_INIT_EXT_GNA_USED_SHIFT) + +#define SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_SHIFT 2 +#define SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_MASK BIT(2) +#define SOF_IPC4_MOD_INIT_EXT_DATA_ARRAY(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_ARRAY_SHIFT) + +struct sof_ipc4_module_init_ext_init { + u32 word0; + u32 rsvd1; + u32 rsvd2; +} __packed __aligned(4); + +/* + * SOF_IPC4_MOD_EXT_EXTENDED payload may be followed by arbitrary + * number of object array objects. SOF_IPC4_MOD_INIT_EXT_DATA_ARRAY + * -bit indicates that an array object follows struct + * sof_ipc4_module_init_ext_init. + * + * The object header's SOF_IPC4_MOD_INIT_EXT_OBJ_LAST-bit in struct + * sof_ipc4_module_init_ext_object indicates if the array is continued + * with another object. The header has also fields to identify the + * object, SOF_IPC4_MOD_INIT_EXT_OBJ_ID, and to indicate the object's + * size in 32-bit words, SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS, not + * including the header itself. + * + * The macros below apply to sof_ipc4_module_init_ext_object.header + */ +#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_SHIFT 0 +#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_MASK BIT(0) +#define SOF_IPC4_MOD_INIT_EXT_OBJ_LAST(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_LAST_SHIFT) + +#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_SHIFT 1 +#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID_MASK GENMASK(15, 1) +#define SOF_IPC4_MOD_INIT_EXT_OBJ_ID(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_ID_SHIFT) + +#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_SHIFT 16 +#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_MASK GENMASK(31, 16) +#define SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS(x) ((x) << SOF_IPC4_MOD_INIT_EXT_OBJ_WORDS_SHIFT) + +struct sof_ipc4_module_init_ext_object { + u32 header; + u32 data[]; +} __packed __aligned(4); + +enum sof_ipc4_mod_init_ext_obj_id { + SOF_IPC4_MOD_INIT_DATA_ID_INVALID = 0, + SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA, + SOF_IPC4_MOD_INIT_DATA_ID_MAX = SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA, +}; + +/* DP module memory configuration data object for object array */ +struct sof_ipc4_mod_init_ext_dp_memory_data { + u32 domain_id; /* userspace domain ID */ + u32 stack_bytes; /* required stack size in bytes */ + u32 heap_bytes; /* required heap size in bytes */ +} __packed __aligned(4); + +/* + * This set of macros are very similar to the set above, but these are + * for building payload to SOF_IPC4_GLB_CREATE_PIPELINE message. + * + * Macros for creating struct sof_ipc4_glb_pipe_payload payload with + * its associated data. struct sof_ipc4_glb_pipe_payload should be the + * first piece of payload following SOF_IPC4_GLB_CREATE_PIPELINE msg, + * and its existence is indicated with SOF_IPC4_GLB_PIPE_PAYLOAD bit. + * + * The macros below apply to sof_ipc4_glb_pipe_payload.word0 + */ +#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_MASK GENMASK(23, 0) +#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS(x) ((x) << SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_SHIFT 24 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_MASK BIT(24) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_SHIFT) + +struct sof_ipc4_glb_pipe_payload { + u32 word0; + u32 rsvd1; + u32 rsvd2; +} __packed __aligned(4); + +/* + * SOF_IPC4_GLB_CREATE_PIPELINE payload may be followed by arbitrary + * number of object array objects. SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY-bit + * indicates that an array object follows struct + * sof_ipc4_glb_pipe_payload. + * + * The object header's SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST-bit in struct + * sof_ipc4_glb_pipe_ext_object indicates if the array is continued + * with another object. The header has also fields to identify the + * object, SOF_IPC4_GLB_PIPE_EXT_OBJ_ID, and to indicate the object's + * size in 32-bit words, SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS, not + * including the header itself. + * + * The macros below apply to sof_ipc4_glb_pipe_ext_object.header + */ +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_MASK BIT(0) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_SHIFT 1 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_MASK GENMASK(15, 1) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_SHIFT 16 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_MASK GENMASK(31, 16) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_SHIFT) + +struct sof_ipc4_glb_pipe_ext_object { + u32 header; + u32 data[]; +} __packed __aligned(4); + +enum sof_ipc4_glb_pipe_ext_obj_id { + SOF_IPC4_GLB_PIPE_DATA_ID_INVALID = 0, + SOF_IPC4_GLB_PIPE_DATA_ID_MEM_DATA, + SOF_IPC4_GLB_PIPE_DATA_ID_MAX = SOF_IPC4_GLB_PIPE_DATA_ID_MEM_DATA, +}; + +/* Pipeline memory configuration data object for ext_init object array */ +struct sof_ipc4_glb_pipe_ext_obj_memory_data { + u32 domain_id; /* userspace domain ID */ + u32 stack_bytes; /* stack size in bytes */ + u32 heap_bytes; /* heap size in bytes */ +} __packed __aligned(4); + +/** @}*/ + +#endif diff --git a/include/sound/sof/pm.h b/include/sound/sof/pm.h new file mode 100644 index 000000000..df55bfe58 --- /dev/null +++ b/include/sound/sof/pm.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_PM_H__ +#define __INCLUDE_SOUND_SOF_PM_H__ + +#include + +/* + * PM + */ + +/* PM context element */ +struct sof_ipc_pm_ctx_elem { + struct sof_ipc_hdr hdr; + uint32_t type; + uint32_t size; + uint64_t addr; +} __packed; + +/* + * PM context - SOF_IPC_PM_CTX_SAVE, SOF_IPC_PM_CTX_RESTORE, + * SOF_IPC_PM_CTX_SIZE + */ +struct sof_ipc_pm_ctx { + struct sof_ipc_cmd_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t num_elems; + uint32_t size; + + /* reserved for future use */ + uint32_t reserved[8]; + + struct sof_ipc_pm_ctx_elem elems[]; +} __packed; + +/* enable or disable cores - SOF_IPC_PM_CORE_ENABLE */ +struct sof_ipc_pm_core_config { + struct sof_ipc_cmd_hdr hdr; + uint32_t enable_mask; +} __packed; + +struct sof_ipc_pm_gate { + struct sof_ipc_cmd_hdr hdr; + uint32_t flags; /* platform specific */ + + /* reserved for future use */ + uint32_t reserved[5]; +} __packed; + +#endif diff --git a/include/sound/sof/stream.h b/include/sound/sof/stream.h new file mode 100644 index 000000000..1bb25487d --- /dev/null +++ b/include/sound/sof/stream.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_STREAM_H__ +#define __INCLUDE_SOUND_SOF_STREAM_H__ + +#include + +/* + * Stream configuration. + */ + +#define SOF_IPC_MAX_CHANNELS 8 + +/* common sample rates for use in masks */ +#define SOF_RATE_8000 (1 << 0) /**< 8000Hz */ +#define SOF_RATE_11025 (1 << 1) /**< 11025Hz */ +#define SOF_RATE_12000 (1 << 2) /**< 12000Hz */ +#define SOF_RATE_16000 (1 << 3) /**< 16000Hz */ +#define SOF_RATE_22050 (1 << 4) /**< 22050Hz */ +#define SOF_RATE_24000 (1 << 5) /**< 24000Hz */ +#define SOF_RATE_32000 (1 << 6) /**< 32000Hz */ +#define SOF_RATE_44100 (1 << 7) /**< 44100Hz */ +#define SOF_RATE_48000 (1 << 8) /**< 48000Hz */ +#define SOF_RATE_64000 (1 << 9) /**< 64000Hz */ +#define SOF_RATE_88200 (1 << 10) /**< 88200Hz */ +#define SOF_RATE_96000 (1 << 11) /**< 96000Hz */ +#define SOF_RATE_176400 (1 << 12) /**< 176400Hz */ +#define SOF_RATE_192000 (1 << 13) /**< 192000Hz */ + +/* continuous and non-standard rates for flexibility */ +#define SOF_RATE_CONTINUOUS (1 << 30) /**< range */ +#define SOF_RATE_KNOT (1 << 31) /**< non-continuous */ + +/* generic PCM flags for runtime settings */ +#define SOF_PCM_FLAG_XRUN_STOP (1 << 0) /**< Stop on any XRUN */ + +/* stream PCM frame format */ +enum sof_ipc_frame { + SOF_IPC_FRAME_S16_LE = 0, + SOF_IPC_FRAME_S24_4LE, + SOF_IPC_FRAME_S32_LE, + SOF_IPC_FRAME_FLOAT, + /* other formats here */ +}; + +/* stream buffer format */ +enum sof_ipc_buffer_format { + SOF_IPC_BUFFER_INTERLEAVED, + SOF_IPC_BUFFER_NONINTERLEAVED, + /* other formats here */ +}; + +/* stream direction */ +enum sof_ipc_stream_direction { + SOF_IPC_STREAM_PLAYBACK = 0, + SOF_IPC_STREAM_CAPTURE, +}; + +/* stream ring info */ +struct sof_ipc_host_buffer { + struct sof_ipc_hdr hdr; + uint32_t phy_addr; + uint32_t pages; + uint32_t size; + uint32_t reserved[3]; +} __packed; + +struct sof_ipc_stream_params { + struct sof_ipc_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t direction; /**< enum sof_ipc_stream_direction */ + uint32_t frame_fmt; /**< enum sof_ipc_frame */ + uint32_t buffer_fmt; /**< enum sof_ipc_buffer_format */ + uint32_t rate; + uint16_t stream_tag; + uint16_t channels; + uint16_t sample_valid_bytes; + uint16_t sample_container_bytes; + + uint32_t host_period_bytes; + uint16_t no_stream_position; /**< 1 means don't send stream position */ + uint8_t cont_update_posn; /**< 1 means continuous update stream position */ + uint8_t reserved0; + int16_t ext_data_length; /**< 0, means no extended data */ + uint8_t reserved[2]; + uint16_t chmap[SOF_IPC_MAX_CHANNELS]; /**< channel map - SOF_CHMAP_ */ + uint8_t ext_data[]; /**< extended data */ +} __packed; + +/* PCM params info - SOF_IPC_STREAM_PCM_PARAMS */ +struct sof_ipc_pcm_params { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; + uint32_t flags; /**< generic PCM flags - SOF_PCM_FLAG_ */ + uint32_t reserved[2]; + struct sof_ipc_stream_params params; +} __packed; + +/* PCM params info reply - SOF_IPC_STREAM_PCM_PARAMS_REPLY */ +struct sof_ipc_pcm_params_reply { + struct sof_ipc_reply rhdr; + uint32_t comp_id; + uint32_t posn_offset; +} __packed; + +/* free stream - SOF_IPC_STREAM_PCM_PARAMS */ +struct sof_ipc_stream { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; +} __packed; + +/* flags indicating which time stamps are in sync with each other */ +#define SOF_TIME_HOST_SYNC (1 << 0) +#define SOF_TIME_DAI_SYNC (1 << 1) +#define SOF_TIME_WALL_SYNC (1 << 2) +#define SOF_TIME_STAMP_SYNC (1 << 3) + +/* flags indicating which time stamps are valid */ +#define SOF_TIME_HOST_VALID (1 << 8) +#define SOF_TIME_DAI_VALID (1 << 9) +#define SOF_TIME_WALL_VALID (1 << 10) +#define SOF_TIME_STAMP_VALID (1 << 11) + +/* flags indicating time stamps are 64bit else 3use low 32bit */ +#define SOF_TIME_HOST_64 (1 << 16) +#define SOF_TIME_DAI_64 (1 << 17) +#define SOF_TIME_WALL_64 (1 << 18) +#define SOF_TIME_STAMP_64 (1 << 19) + +struct sof_ipc_stream_posn { + struct sof_ipc_reply rhdr; + uint32_t comp_id; /**< host component ID */ + uint32_t flags; /**< SOF_TIME_ */ + uint32_t wallclock_hz; /**< frequency of wallclock in Hz */ + uint32_t timestamp_ns; /**< resolution of timestamp in ns */ + uint64_t host_posn; /**< host DMA position in bytes */ + uint64_t dai_posn; /**< DAI DMA position in bytes */ + uint64_t comp_posn; /**< comp position in bytes */ + uint64_t wallclock; /**< audio wall clock */ + uint64_t timestamp; /**< system time stamp */ + uint32_t xrun_comp_id; /**< comp ID of XRUN component */ + int32_t xrun_size; /**< XRUN size in bytes */ +} __packed; + +#endif diff --git a/include/sound/sof/topology.h b/include/sound/sof/topology.h new file mode 100644 index 000000000..449e93c25 --- /dev/null +++ b/include/sound/sof/topology.h @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ +#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ + +#include + +/* + * Component + */ + +/* types of component */ +enum sof_comp_type { + SOF_COMP_NONE = 0, + SOF_COMP_HOST, + SOF_COMP_DAI, + SOF_COMP_SG_HOST, /**< scatter gather variant */ + SOF_COMP_SG_DAI, /**< scatter gather variant */ + SOF_COMP_VOLUME, + SOF_COMP_MIXER, + SOF_COMP_MUX, + SOF_COMP_SRC, + SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */ + SOF_COMP_TONE, + SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */ + SOF_COMP_BUFFER, + SOF_COMP_EQ_IIR, + SOF_COMP_EQ_FIR, + SOF_COMP_KEYWORD_DETECT, + SOF_COMP_KPB, /* A key phrase buffer component */ + SOF_COMP_SELECTOR, /**< channel selector component */ + SOF_COMP_DEMUX, + SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ + SOF_COMP_DCBLOCK, + SOF_COMP_SMART_AMP, /**< smart amplifier component */ + SOF_COMP_MODULE_ADAPTER, /**< module adapter */ + /* keep FILEREAD/FILEWRITE as the last ones */ + SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ + SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ +}; + +/* XRUN action for component */ +#define SOF_XRUN_STOP 1 /**< stop stream */ +#define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ +#define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ + +/* create new generic component - SOF_IPC_TPLG_COMP_NEW */ +struct sof_ipc_comp { + struct sof_ipc_cmd_hdr hdr; + uint32_t id; + uint32_t type; + uint32_t pipeline_id; + uint32_t core; + + /* extended data length, 0 if no extended data */ + uint32_t ext_data_length; +} __packed __aligned(4); + +/* + * Component Buffers + */ + +/* + * SOF memory capabilities, add new ones at the end + */ +#define SOF_MEM_CAPS_RAM BIT(0) +#define SOF_MEM_CAPS_ROM BIT(1) +#define SOF_MEM_CAPS_EXT BIT(2) /**< external */ +#define SOF_MEM_CAPS_LP BIT(3) /**< low power */ +#define SOF_MEM_CAPS_HP BIT(4) /**< high performance */ +#define SOF_MEM_CAPS_DMA BIT(5) /**< DMA'able */ +#define SOF_MEM_CAPS_CACHE BIT(6) /**< cacheable */ +#define SOF_MEM_CAPS_EXEC BIT(7) /**< executable */ +#define SOF_MEM_CAPS_L3 BIT(8) /**< L3 memory */ + +/* + * overrun will cause ring buffer overwrite, instead of XRUN. + */ +#define SOF_BUF_OVERRUN_PERMITTED BIT(0) + +/* + * underrun will cause readback of 0s, instead of XRUN. + */ +#define SOF_BUF_UNDERRUN_PERMITTED BIT(1) + +/* the UUID size in bytes, shared between FW and host */ +#define SOF_UUID_SIZE 16 + +/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ +struct sof_ipc_buffer { + struct sof_ipc_comp comp; + uint32_t size; /**< buffer size in bytes */ + uint32_t caps; /**< SOF_MEM_CAPS_ */ + uint32_t flags; /**< SOF_BUF_ flags defined above */ + uint32_t reserved; /**< reserved for future use */ +} __packed __aligned(4); + +/* generic component config data - must always be after struct sof_ipc_comp */ +struct sof_ipc_comp_config { + struct sof_ipc_cmd_hdr hdr; + uint32_t periods_sink; /**< 0 means variable */ + uint32_t periods_source;/**< 0 means variable */ + uint32_t reserved1; /**< reserved */ + uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ + uint32_t xrun_action; + + /* reserved for future use */ + uint32_t reserved[2]; +} __packed __aligned(4); + +/* generic host component */ +struct sof_ipc_comp_host { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t direction; /**< SOF_IPC_STREAM_ */ + uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ + uint32_t dmac_config; /**< DMA engine specific */ +} __packed __aligned(4); + +/* generic DAI component */ +struct sof_ipc_comp_dai { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t direction; /**< SOF_IPC_STREAM_ */ + uint32_t dai_index; /**< index of this type dai */ + uint32_t type; /**< DAI type - SOF_DAI_ */ + uint32_t reserved; /**< reserved */ +} __packed __aligned(4); + +/* generic mixer component */ +struct sof_ipc_comp_mixer { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; +} __packed __aligned(4); + +/* volume ramping types */ +enum sof_volume_ramp { + SOF_VOLUME_LINEAR = 0, + SOF_VOLUME_LOG, + SOF_VOLUME_LINEAR_ZC, + SOF_VOLUME_LOG_ZC, + SOF_VOLUME_WINDOWS_FADE, + SOF_VOLUME_WINDOWS_NO_FADE, +}; + +/* generic volume component */ +struct sof_ipc_comp_volume { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t channels; + uint32_t min_value; + uint32_t max_value; + uint32_t ramp; /**< SOF_VOLUME_ */ + uint32_t initial_ramp; /**< ramp space in ms */ +} __packed __aligned(4); + +/* generic SRC component */ +struct sof_ipc_comp_src { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + /* either source or sink rate must be non zero */ + uint32_t source_rate; /**< source rate or 0 for variable */ + uint32_t sink_rate; /**< sink rate or 0 for variable */ + uint32_t rate_mask; /**< SOF_RATE_ supported rates */ +} __packed __aligned(4); + +/* generic ASRC component */ +struct sof_ipc_comp_asrc { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + /* either source or sink rate must be non zero */ + uint32_t source_rate; /**< Define fixed source rate or */ + /**< use 0 to indicate need to get */ + /**< the rate from stream */ + uint32_t sink_rate; /**< Define fixed sink rate or */ + /**< use 0 to indicate need to get */ + /**< the rate from stream */ + uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ + /**< When 1 the ASRC tracks and */ + /**< compensates for drift. */ + uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ + /**< ASRC consumes a defined number */ + /**< of frames at input, with varying */ + /**< number of frames at output. */ + /**< In pull mode the ASRC outputs */ + /**< a defined number of frames while */ + /**< number of input frames varies. */ + + /* reserved for future use */ + uint32_t reserved[4]; +} __packed __aligned(4); + +/* generic MUX component */ +struct sof_ipc_comp_mux { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; +} __packed __aligned(4); + +/* generic tone generator component */ +struct sof_ipc_comp_tone { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + int32_t sample_rate; + int32_t frequency; + int32_t amplitude; + int32_t freq_mult; + int32_t ampl_mult; + int32_t length; + int32_t period; + int32_t repeats; + int32_t ramp_step; +} __packed __aligned(4); + +/** \brief Types of processing components */ +enum sof_ipc_process_type { + SOF_PROCESS_NONE = 0, /**< None */ + SOF_PROCESS_EQFIR, /**< Intel FIR */ + SOF_PROCESS_EQIIR, /**< Intel IIR */ + SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */ + SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */ + SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */ + SOF_PROCESS_MUX, + SOF_PROCESS_DEMUX, + SOF_PROCESS_DCBLOCK, + SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */ +}; + +/* generic "effect", "codec" or proprietary processing component */ +struct sof_ipc_comp_process { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t size; /**< size of bespoke data section in bytes */ + uint32_t type; /**< sof_ipc_process_type */ + + /* reserved for future use */ + uint32_t reserved[7]; + + unsigned char data[]; +} __packed __aligned(4); + +/* frees components, buffers and pipelines + * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE + */ +struct sof_ipc_free { + struct sof_ipc_cmd_hdr hdr; + uint32_t id; +} __packed __aligned(4); + +struct sof_ipc_comp_reply { + struct sof_ipc_reply rhdr; + uint32_t id; + uint32_t offset; +} __packed __aligned(4); + +/* + * Pipeline + */ + +/** \brief Types of pipeline scheduling time domains */ +enum sof_ipc_pipe_sched_time_domain { + SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ + SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ +}; + +/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ +struct sof_ipc_pipe_new { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; /**< component id for pipeline */ + uint32_t pipeline_id; /**< pipeline id */ + uint32_t sched_id; /**< Scheduling component id */ + uint32_t core; /**< core we run on */ + uint32_t period; /**< execution period in us*/ + uint32_t priority; /**< priority level 0 (low) to 10 (max) */ + uint32_t period_mips; /**< worst case instruction count per period */ + uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ + uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ + uint32_t time_domain; /**< scheduling time domain */ +} __packed __aligned(4); + +/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ +struct sof_ipc_pipe_ready { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; +} __packed __aligned(4); + +struct sof_ipc_pipe_free { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; +} __packed __aligned(4); + +/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ +struct sof_ipc_pipe_comp_connect { + struct sof_ipc_cmd_hdr hdr; + uint32_t source_id; + uint32_t sink_id; +} __packed __aligned(4); + +/* external events */ +enum sof_event_types { + SOF_EVENT_NONE = 0, + SOF_KEYWORD_DETECT_DAPM_EVENT, +}; + +#endif diff --git a/include/sound/sof/trace.h b/include/sound/sof/trace.h new file mode 100644 index 000000000..ac2ebb6fb --- /dev/null +++ b/include/sound/sof/trace.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_TRACE_H__ +#define __INCLUDE_SOUND_SOF_TRACE_H__ + +#include +#include + +/* + * DMA for Trace + */ + +#define SOF_TRACE_FILENAME_SIZE 32 + +/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */ +/* Deprecated - use sof_ipc_dma_trace_params_ext */ +struct sof_ipc_dma_trace_params { + struct sof_ipc_cmd_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t stream_tag; +} __packed; + +/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS_EXT */ +struct sof_ipc_dma_trace_params_ext { + struct sof_ipc_cmd_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t stream_tag; + uint64_t timestamp_ns; /* in nanosecond */ + uint32_t reserved[8]; +} __packed; + +/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */ +struct sof_ipc_dma_trace_posn { + struct sof_ipc_reply rhdr; + uint32_t host_offset; /* Offset of DMA host buffer */ + uint32_t overflow; /* overflow bytes if any */ + uint32_t messages; /* total trace messages */ +} __packed; + +/* Values used in sof_ipc_trace_filter_elem: */ + +/* bits 6..0 */ +#define SOF_IPC_TRACE_FILTER_ELEM_SET_LEVEL 0x01 /**< trace level for selected components */ +#define SOF_IPC_TRACE_FILTER_ELEM_BY_UUID 0x02 /**< filter by uuid key */ +#define SOF_IPC_TRACE_FILTER_ELEM_BY_PIPE 0x03 /**< filter by pipeline */ +#define SOF_IPC_TRACE_FILTER_ELEM_BY_COMP 0x04 /**< filter by component id */ + +/* bit 7 */ +#define SOF_IPC_TRACE_FILTER_ELEM_FIN 0x80 /**< mark last filter in set */ + +/* bits 31..8: Unused */ + +/** part of sof_ipc_trace_filter, ABI3.17 */ +struct sof_ipc_trace_filter_elem { + uint32_t key; /**< SOF_IPC_TRACE_FILTER_ELEM_ {LEVEL, UUID, COMP, PIPE} */ + uint32_t value; /**< element value */ +} __packed; + +/** Runtime tracing filtration data - SOF_IPC_TRACE_FILTER_UPDATE, ABI3.17 */ +struct sof_ipc_trace_filter { + struct sof_ipc_cmd_hdr hdr; /**< IPC command header */ + uint32_t elem_cnt; /**< number of entries in elems[] array */ + uint32_t reserved[8]; /**< reserved for future usage */ + /** variable size array with new filtering settings */ + struct sof_ipc_trace_filter_elem elems[]; +} __packed; + +/* + * Commom debug + */ + +/* + * SOF panic codes + */ +#define SOF_IPC_PANIC_MAGIC 0x0dead000 +#define SOF_IPC_PANIC_MAGIC_MASK 0x0ffff000 +#define SOF_IPC_PANIC_CODE_MASK 0x00000fff +#define SOF_IPC_PANIC_MEM (SOF_IPC_PANIC_MAGIC | 0x0) +#define SOF_IPC_PANIC_WORK (SOF_IPC_PANIC_MAGIC | 0x1) +#define SOF_IPC_PANIC_IPC (SOF_IPC_PANIC_MAGIC | 0x2) +#define SOF_IPC_PANIC_ARCH (SOF_IPC_PANIC_MAGIC | 0x3) +#define SOF_IPC_PANIC_PLATFORM (SOF_IPC_PANIC_MAGIC | 0x4) +#define SOF_IPC_PANIC_TASK (SOF_IPC_PANIC_MAGIC | 0x5) +#define SOF_IPC_PANIC_EXCEPTION (SOF_IPC_PANIC_MAGIC | 0x6) +#define SOF_IPC_PANIC_DEADLOCK (SOF_IPC_PANIC_MAGIC | 0x7) +#define SOF_IPC_PANIC_STACK (SOF_IPC_PANIC_MAGIC | 0x8) +#define SOF_IPC_PANIC_IDLE (SOF_IPC_PANIC_MAGIC | 0x9) +#define SOF_IPC_PANIC_WFI (SOF_IPC_PANIC_MAGIC | 0xa) +#define SOF_IPC_PANIC_ASSERT (SOF_IPC_PANIC_MAGIC | 0xb) + +/* panic info include filename and line number + * filename array will not include null terminator if fully filled + */ +struct sof_ipc_panic_info { + struct sof_ipc_hdr hdr; + uint32_t code; /* SOF_IPC_PANIC_ */ + uint8_t filename[SOF_TRACE_FILENAME_SIZE]; + uint32_t linenum; +} __packed; + +#endif diff --git a/include/sound/sof/xtensa.h b/include/sound/sof/xtensa.h new file mode 100644 index 000000000..ef70f8e26 --- /dev/null +++ b/include/sound/sof/xtensa.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation + */ + +#ifndef __INCLUDE_SOUND_SOF_XTENSA_H__ +#define __INCLUDE_SOUND_SOF_XTENSA_H__ + +#include + +/* + * Architecture specific debug + */ + +/* Xtensa Firmware Oops data */ +struct sof_ipc_dsp_oops_xtensa { + struct sof_ipc_dsp_oops_arch_hdr arch_hdr; + struct sof_ipc_dsp_oops_plat_hdr plat_hdr; + uint32_t exccause; + uint32_t excvaddr; + uint32_t ps; + uint32_t epc1; + uint32_t epc2; + uint32_t epc3; + uint32_t epc4; + uint32_t epc5; + uint32_t epc6; + uint32_t epc7; + uint32_t eps2; + uint32_t eps3; + uint32_t eps4; + uint32_t eps5; + uint32_t eps6; + uint32_t eps7; + uint32_t depc; + uint32_t intenable; + uint32_t interrupt; + uint32_t sar; + uint32_t debugcause; + uint32_t windowbase; + uint32_t windowstart; + uint32_t excsave1; + uint32_t ar[]; +} __packed; + +#endif diff --git a/include/sound/soundfont.h b/include/sound/soundfont.h new file mode 100644 index 000000000..48f8cf6de --- /dev/null +++ b/include/sound/soundfont.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SOUNDFONT_H +#define __SOUND_SOUNDFONT_H + +/* + * Soundfont defines and definitions. + * + * Copyright (C) 1999 Steve Ratcliffe + * Copyright (c) 1999-2000 Takashi iwai + */ + +#include +#include + +#define SF_MAX_INSTRUMENTS 128 /* maximum instrument number */ +#define SF_MAX_PRESETS 256 /* drums are mapped from 128 to 256 */ +#define SF_IS_DRUM_BANK(z) ((z) == 128) + +struct snd_sf_zone { + struct snd_sf_zone *next; /* Link to next */ + unsigned char bank; /* Midi bank for this zone */ + unsigned char instr; /* Midi program for this zone */ + unsigned char mapped; /* True if mapped to something else */ + + struct soundfont_voice_info v; /* All the soundfont parameters */ + int counter; + struct snd_sf_sample *sample; /* Link to sample */ + + /* The following deals with preset numbers (programs) */ + struct snd_sf_zone *next_instr; /* Next zone of this instrument */ + struct snd_sf_zone *next_zone; /* Next zone in play list */ +}; + +struct snd_sf_sample { + struct soundfont_sample_info v; + int counter; + struct snd_util_memblk *block; /* allocated data block */ + struct snd_sf_sample *next; +}; + +/* + * This represents all the information relating to a soundfont. + */ +struct snd_soundfont { + struct snd_soundfont *next; /* Link to next */ + /*struct snd_soundfont *prev;*/ /* Link to previous */ + short id; /* file id */ + short type; /* font type */ + unsigned char name[SNDRV_SFNT_PATCH_NAME_LEN]; /* identifier */ + struct snd_sf_zone *zones; /* Font information */ + struct snd_sf_sample *samples; /* The sample headers */ +}; + +/* + * Type of the sample access callback + */ +struct snd_sf_callback { + void *private_data; + int (*sample_new)(void *private_data, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr, + const void __user *buf, long count); + int (*sample_free)(void *private_data, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr); + void (*sample_reset)(void *private); +}; + +/* + * List of soundfonts. + */ +struct snd_sf_list { + struct snd_soundfont *currsf; /* The currently open soundfont */ + int open_client; /* client pointer for lock */ + int mem_used; /* used memory size */ + struct snd_sf_zone *presets[SF_MAX_PRESETS]; + struct snd_soundfont *fonts; /* The list of soundfonts */ + int fonts_size; /* number of fonts allocated */ + int zone_counter; /* last allocated time for zone */ + int sample_counter; /* last allocated time for sample */ + int zone_locked; /* locked time for zone */ + int sample_locked; /* locked time for sample */ + struct snd_sf_callback callback; /* callback functions */ + int presets_locked; + struct mutex presets_mutex; + spinlock_t lock; + struct snd_util_memhdr *memhdr; +}; + +/* Prototypes for soundfont.c */ +int snd_soundfont_load(struct snd_card *card, + struct snd_sf_list *sflist, const void __user *data, + long count, int client); +int snd_soundfont_load_guspatch(struct snd_card *card, + struct snd_sf_list *sflist, const char __user *data, + long count); +int snd_soundfont_close_check(struct snd_sf_list *sflist, int client); + +struct snd_sf_list *snd_sf_new(struct snd_sf_callback *callback, + struct snd_util_memhdr *hdr); +void snd_sf_free(struct snd_sf_list *sflist); + +int snd_soundfont_remove_samples(struct snd_sf_list *sflist); +int snd_soundfont_remove_unlocked(struct snd_sf_list *sflist); + +int snd_soundfont_search_zone(struct snd_sf_list *sflist, int *notep, int vel, + int preset, int bank, + int def_preset, int def_bank, + struct snd_sf_zone **table, int max_layers); + +/* Parameter conversions */ +int snd_sf_calc_parm_hold(int msec); +int snd_sf_calc_parm_attack(int msec); +int snd_sf_calc_parm_decay(int msec); +#define snd_sf_calc_parm_delay(msec) (0x8000 - (msec) * 1000 / 725) +extern int snd_sf_vol_table[128]; +int snd_sf_linear_to_log(unsigned int amount, int offset, int ratio); + +/* lock access to sflist */ +static inline void snd_soundfont_lock_preset(struct snd_sf_list *sflist) +{ + mutex_lock(&sflist->presets_mutex); + guard(spinlock_irqsave)(&sflist->lock); + sflist->presets_locked = 1; +} + +/* remove lock */ +static inline void snd_soundfont_unlock_preset(struct snd_sf_list *sflist) +{ + guard(spinlock_irqsave)(&sflist->lock); + sflist->presets_locked = 0; + mutex_unlock(&sflist->presets_mutex); +} + +DEFINE_GUARD(snd_soundfont_lock_preset, struct snd_sf_list *, + snd_soundfont_lock_preset(_T), snd_soundfont_unlock_preset(_T)) + +#endif /* __SOUND_SOUNDFONT_H */ diff --git a/include/sound/spear_dma.h b/include/sound/spear_dma.h new file mode 100644 index 000000000..0269a07b8 --- /dev/null +++ b/include/sound/spear_dma.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* +* linux/spear_dma.h +* +* Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) +*/ + +#ifndef SPEAR_DMA_H +#define SPEAR_DMA_H + +#include + +struct spear_dma_data { + void *data; + dma_addr_t addr; + u32 max_burst; + enum dma_slave_buswidth addr_width; +}; + +#endif /* SPEAR_DMA_H */ diff --git a/include/sound/spear_spdif.h b/include/sound/spear_spdif.h new file mode 100644 index 000000000..f52f5268c --- /dev/null +++ b/include/sound/spear_spdif.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (ST) 2012 Vipin Kumar (vipin.kumar@st.com) + */ + +#ifndef __SOUND_SPDIF_H +#define __SOUND_SPDIF_H + +struct spear_spdif_platform_data { + /* DMA params */ + void *dma_params; + bool (*filter)(struct dma_chan *chan, void *slave); + void (*reset_perip)(void); +}; + +#endif /* SOUND_SPDIF_H */ diff --git a/include/sound/sta32x.h b/include/sound/sta32x.h new file mode 100644 index 000000000..600494251 --- /dev/null +++ b/include/sound/sta32x.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for ST STA32x ASoC codec driver. + * + * Copyright: 2011 Raumfeld GmbH + * Author: Johannes Stezenbach + */ +#ifndef __LINUX_SND__STA32X_H +#define __LINUX_SND__STA32X_H + +#define STA32X_OCFG_2CH 0 +#define STA32X_OCFG_2_1CH 1 +#define STA32X_OCFG_1CH 3 + +#define STA32X_OM_CH1 0 +#define STA32X_OM_CH2 1 +#define STA32X_OM_CH3 2 + +#define STA32X_THERMAL_ADJUSTMENT_ENABLE 1 +#define STA32X_THERMAL_RECOVERY_ENABLE 2 + +struct sta32x_platform_data { + u8 output_conf; + u8 ch1_output_mapping; + u8 ch2_output_mapping; + u8 ch3_output_mapping; + int needs_esd_watchdog; + u8 drop_compensation_ns; + unsigned int thermal_warning_recovery:1; + unsigned int thermal_warning_adjustment:1; + unsigned int fault_detect_recovery:1; + unsigned int max_power_use_mpcc:1; + unsigned int max_power_correction:1; + unsigned int am_reduction_mode:1; + unsigned int odd_pwm_speed_mode:1; + unsigned int invalid_input_detect_mute:1; +}; + +#endif /* __LINUX_SND__STA32X_H */ diff --git a/include/sound/sta350.h b/include/sound/sta350.h new file mode 100644 index 000000000..2d9170484 --- /dev/null +++ b/include/sound/sta350.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for ST STA350 ASoC codec driver. + * + * Copyright: 2014 Raumfeld GmbH + * Author: Sven Brandau + */ +#ifndef __LINUX_SND__STA350_H +#define __LINUX_SND__STA350_H + +#define STA350_OCFG_2CH 0 +#define STA350_OCFG_2_1CH 1 +#define STA350_OCFG_1CH 3 + +#define STA350_OM_CH1 0 +#define STA350_OM_CH2 1 +#define STA350_OM_CH3 2 + +#define STA350_THERMAL_ADJUSTMENT_ENABLE 1 +#define STA350_THERMAL_RECOVERY_ENABLE 2 +#define STA350_FAULT_DETECT_RECOVERY_BYPASS 1 + +#define STA350_FFX_PM_DROP_COMP 0 +#define STA350_FFX_PM_TAPERED_COMP 1 +#define STA350_FFX_PM_FULL_POWER 2 +#define STA350_FFX_PM_VARIABLE_DROP_COMP 3 + + +struct sta350_platform_data { + u8 output_conf; + u8 ch1_output_mapping; + u8 ch2_output_mapping; + u8 ch3_output_mapping; + u8 ffx_power_output_mode; + u8 drop_compensation_ns; + u8 powerdown_delay_divider; + unsigned int thermal_warning_recovery:1; + unsigned int thermal_warning_adjustment:1; + unsigned int fault_detect_recovery:1; + unsigned int oc_warning_adjustment:1; + unsigned int max_power_use_mpcc:1; + unsigned int max_power_correction:1; + unsigned int am_reduction_mode:1; + unsigned int odd_pwm_speed_mode:1; + unsigned int distortion_compensation:1; + unsigned int invalid_input_detect_mute:1; + unsigned int activate_mute_output:1; + unsigned int bridge_immediate_off:1; + unsigned int noise_shape_dc_cut:1; + unsigned int powerdown_master_vol:1; +}; + +#endif /* __LINUX_SND__STA350_H */ diff --git a/include/sound/tas2552-plat.h b/include/sound/tas2552-plat.h new file mode 100644 index 000000000..6f087b22f --- /dev/null +++ b/include/sound/tas2552-plat.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TAS2552 driver platform header + * + * Copyright (C) 2014 Texas Instruments Inc. + * + * Author: Dan Murphy + */ + +#ifndef TAS2552_PLAT_H +#define TAS2552_PLAT_H + +struct tas2552_platform_data { + int enable_gpio; +}; + +#endif diff --git a/include/sound/tas2563-tlv.h b/include/sound/tas2563-tlv.h new file mode 100644 index 000000000..bb269b21f --- /dev/null +++ b/include/sound/tas2563-tlv.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2563 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2024 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2563 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2563 chips. +// +// Author: Shenghao Ding +// + +#ifndef __TAS2563_TLV_H__ +#define __TAS2563_TLV_H__ + +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2563_dvc_tlv, -12150, 50, 1); + +/* pow(10, db/20) * pow(2,30) */ +static const __maybe_unused unsigned char tas2563_dvc_table[][4] = { + { 0X00, 0X00, 0X00, 0X00 }, /* -121.5db */ + { 0X00, 0X00, 0X03, 0XBC }, /* -121.0db */ + { 0X00, 0X00, 0X03, 0XF5 }, /* -120.5db */ + { 0X00, 0X00, 0X04, 0X31 }, /* -120.0db */ + { 0X00, 0X00, 0X04, 0X71 }, /* -119.5db */ + { 0X00, 0X00, 0X04, 0XB4 }, /* -119.0db */ + { 0X00, 0X00, 0X04, 0XFC }, /* -118.5db */ + { 0X00, 0X00, 0X05, 0X47 }, /* -118.0db */ + { 0X00, 0X00, 0X05, 0X97 }, /* -117.5db */ + { 0X00, 0X00, 0X05, 0XEC }, /* -117.0db */ + { 0X00, 0X00, 0X06, 0X46 }, /* -116.5db */ + { 0X00, 0X00, 0X06, 0XA5 }, /* -116.0db */ + { 0X00, 0X00, 0X07, 0X0A }, /* -115.5db */ + { 0X00, 0X00, 0X07, 0X75 }, /* -115.0db */ + { 0X00, 0X00, 0X07, 0XE6 }, /* -114.5db */ + { 0X00, 0X00, 0X08, 0X5E }, /* -114.0db */ + { 0X00, 0X00, 0X08, 0XDD }, /* -113.5db */ + { 0X00, 0X00, 0X09, 0X63 }, /* -113.0db */ + { 0X00, 0X00, 0X09, 0XF2 }, /* -112.5db */ + { 0X00, 0X00, 0X0A, 0X89 }, /* -112.0db */ + { 0X00, 0X00, 0X0B, 0X28 }, /* -111.5db */ + { 0X00, 0X00, 0X0B, 0XD2 }, /* -111.0db */ + { 0X00, 0X00, 0X0C, 0X85 }, /* -110.5db */ + { 0X00, 0X00, 0X0D, 0X43 }, /* -110.0db */ + { 0X00, 0X00, 0X0E, 0X0C }, /* -109.5db */ + { 0X00, 0X00, 0X0E, 0XE1 }, /* -109.0db */ + { 0X00, 0X00, 0X0F, 0XC3 }, /* -108.5db */ + { 0X00, 0X00, 0X10, 0XB2 }, /* -108.0db */ + { 0X00, 0X00, 0X11, 0XAF }, /* -107.5db */ + { 0X00, 0X00, 0X12, 0XBC }, /* -107.0db */ + { 0X00, 0X00, 0X13, 0XD8 }, /* -106.5db */ + { 0X00, 0X00, 0X15, 0X05 }, /* -106.0db */ + { 0X00, 0X00, 0X16, 0X44 }, /* -105.5db */ + { 0X00, 0X00, 0X17, 0X96 }, /* -105.0db */ + { 0X00, 0X00, 0X18, 0XFB }, /* -104.5db */ + { 0X00, 0X00, 0X1A, 0X76 }, /* -104.0db */ + { 0X00, 0X00, 0X1C, 0X08 }, /* -103.5db */ + { 0X00, 0X00, 0X1D, 0XB1 }, /* -103.0db */ + { 0X00, 0X00, 0X1F, 0X73 }, /* -102.5db */ + { 0X00, 0X00, 0X21, 0X51 }, /* -102.0db */ + { 0X00, 0X00, 0X23, 0X4A }, /* -101.5db */ + { 0X00, 0X00, 0X25, 0X61 }, /* -101.0db */ + { 0X00, 0X00, 0X27, 0X98 }, /* -100.5db */ + { 0X00, 0X00, 0X29, 0XF1 }, /* -100.0db */ + { 0X00, 0X00, 0X2C, 0X6D }, /* -99.5db */ + { 0X00, 0X00, 0X2F, 0X0F }, /* -99.0db */ + { 0X00, 0X00, 0X31, 0XD9 }, /* -98.5db */ + { 0X00, 0X00, 0X34, 0XCD }, /* -98.0db */ + { 0X00, 0X00, 0X37, 0XEE }, /* -97.5db */ + { 0X00, 0X00, 0X3B, 0X3F }, /* -97.0db */ + { 0X00, 0X00, 0X3E, 0XC1 }, /* -96.5db */ + { 0X00, 0X00, 0X42, 0X79 }, /* -96.0db */ + { 0X00, 0X00, 0X46, 0X6A }, /* -95.5db */ + { 0X00, 0X00, 0X4A, 0X96 }, /* -95.0db */ + { 0X00, 0X00, 0X4F, 0X01 }, /* -94.5db */ + { 0X00, 0X00, 0X53, 0XAF }, /* -94.0db */ + { 0X00, 0X00, 0X58, 0XA5 }, /* -93.5db */ + { 0X00, 0X00, 0X5D, 0XE6 }, /* -93.0db */ + { 0X00, 0X00, 0X63, 0X76 }, /* -92.5db */ + { 0X00, 0X00, 0X69, 0X5B }, /* -92.0db */ + { 0X00, 0X00, 0X6F, 0X99 }, /* -91.5db */ + { 0X00, 0X00, 0X76, 0X36 }, /* -91.0db */ + { 0X00, 0X00, 0X7D, 0X37 }, /* -90.5db */ + { 0X00, 0X00, 0X84, 0XA2 }, /* -90.0db */ + { 0X00, 0X00, 0X8C, 0X7E }, /* -89.5db */ + { 0X00, 0X00, 0X94, 0XD1 }, /* -89.0db */ + { 0X00, 0X00, 0X9D, 0XA3 }, /* -88.5db */ + { 0X00, 0X00, 0XA6, 0XFA }, /* -88.0db */ + { 0X00, 0X00, 0XB0, 0XDF }, /* -87.5db */ + { 0X00, 0X00, 0XBB, 0X5A }, /* -87.0db */ + { 0X00, 0X00, 0XC6, 0X74 }, /* -86.5db */ + { 0X00, 0X00, 0XD2, 0X36 }, /* -86.0db */ + { 0X00, 0X00, 0XDE, 0XAB }, /* -85.5db */ + { 0X00, 0X00, 0XEB, 0XDC }, /* -85.0db */ + { 0X00, 0X00, 0XF9, 0XD6 }, /* -84.5db */ + { 0X00, 0X01, 0X08, 0XA4 }, /* -84.0db */ + { 0X00, 0X01, 0X18, 0X52 }, /* -83.5db */ + { 0X00, 0X01, 0X28, 0XEF }, /* -83.0db */ + { 0X00, 0X01, 0X3A, 0X87 }, /* -82.5db */ + { 0X00, 0X01, 0X4D, 0X2A }, /* -82.0db */ + { 0X00, 0X01, 0X60, 0XE8 }, /* -81.5db */ + { 0X00, 0X01, 0X75, 0XD1 }, /* -81.0db */ + { 0X00, 0X01, 0X8B, 0XF7 }, /* -80.5db */ + { 0X00, 0X01, 0XA3, 0X6E }, /* -80.0db */ + { 0X00, 0X01, 0XBC, 0X48 }, /* -79.5db */ + { 0X00, 0X01, 0XD6, 0X9B }, /* -79.0db */ + { 0X00, 0X01, 0XF2, 0X7E }, /* -78.5db */ + { 0X00, 0X02, 0X10, 0X08 }, /* -78.0db */ + { 0X00, 0X02, 0X2F, 0X51 }, /* -77.5db */ + { 0X00, 0X02, 0X50, 0X76 }, /* -77.0db */ + { 0X00, 0X02, 0X73, 0X91 }, /* -76.5db */ + { 0X00, 0X02, 0X98, 0XC0 }, /* -76.0db */ + { 0X00, 0X02, 0XC0, 0X24 }, /* -75.5db */ + { 0X00, 0X02, 0XE9, 0XDD }, /* -75.0db */ + { 0X00, 0X03, 0X16, 0X0F }, /* -74.5db */ + { 0X00, 0X03, 0X44, 0XDF }, /* -74.0db */ + { 0X00, 0X03, 0X76, 0X76 }, /* -73.5db */ + { 0X00, 0X03, 0XAA, 0XFC }, /* -73.0db */ + { 0X00, 0X03, 0XE2, 0XA0 }, /* -72.5db */ + { 0X00, 0X04, 0X1D, 0X8F }, /* -72.0db */ + { 0X00, 0X04, 0X5B, 0XFD }, /* -71.5db */ + { 0X00, 0X04, 0X9E, 0X1D }, /* -71.0db */ + { 0X00, 0X04, 0XE4, 0X29 }, /* -70.5db */ + { 0X00, 0X05, 0X2E, 0X5A }, /* -70.0db */ + { 0X00, 0X05, 0X7C, 0XF2 }, /* -69.5db */ + { 0X00, 0X05, 0XD0, 0X31 }, /* -69.0db */ + { 0X00, 0X06, 0X28, 0X60 }, /* -68.5db */ + { 0X00, 0X06, 0X85, 0XC8 }, /* -68.0db */ + { 0X00, 0X06, 0XE8, 0XB9 }, /* -67.5db */ + { 0X00, 0X07, 0X51, 0X86 }, /* -67.0db */ + { 0X00, 0X07, 0XC0, 0X8A }, /* -66.5db */ + { 0X00, 0X08, 0X36, 0X21 }, /* -66.0db */ + { 0X00, 0X08, 0XB2, 0XB0 }, /* -65.5db */ + { 0X00, 0X09, 0X36, 0XA1 }, /* -65.0db */ + { 0X00, 0X09, 0XC2, 0X63 }, /* -64.5db */ + { 0X00, 0X0A, 0X56, 0X6D }, /* -64.0db */ + { 0X00, 0X0A, 0XF3, 0X3C }, /* -63.5db */ + { 0X00, 0X0B, 0X99, 0X56 }, /* -63.0db */ + { 0X00, 0X0C, 0X49, 0X48 }, /* -62.5db */ + { 0X00, 0X0D, 0X03, 0XA7 }, /* -62.0db */ + { 0X00, 0X0D, 0XC9, 0X11 }, /* -61.5db */ + { 0X00, 0X0E, 0X9A, 0X2D }, /* -61.0db */ + { 0X00, 0X0F, 0X77, 0XAD }, /* -60.5db */ + { 0X00, 0X10, 0X62, 0X4D }, /* -60.0db */ + { 0X00, 0X11, 0X5A, 0XD5 }, /* -59.5db */ + { 0X00, 0X12, 0X62, 0X16 }, /* -59.0db */ + { 0X00, 0X13, 0X78, 0XF0 }, /* -58.5db */ + { 0X00, 0X14, 0XA0, 0X50 }, /* -58.0db */ + { 0X00, 0X15, 0XD9, 0X31 }, /* -57.5db */ + { 0X00, 0X17, 0X24, 0X9C }, /* -57.0db */ + { 0X00, 0X18, 0X83, 0XAA }, /* -56.5db */ + { 0X00, 0X19, 0XF7, 0X86 }, /* -56.0db */ + { 0X00, 0X1B, 0X81, 0X6A }, /* -55.5db */ + { 0X00, 0X1D, 0X22, 0XA4 }, /* -55.0db */ + { 0X00, 0X1E, 0XDC, 0X98 }, /* -54.5db */ + { 0X00, 0X20, 0XB0, 0XBC }, /* -54.0db */ + { 0X00, 0X22, 0XA0, 0X9D }, /* -53.5db */ + { 0X00, 0X24, 0XAD, 0XE0 }, /* -53.0db */ + { 0X00, 0X26, 0XDA, 0X43 }, /* -52.5db */ + { 0X00, 0X29, 0X27, 0X9D }, /* -52.0db */ + { 0X00, 0X2B, 0X97, 0XE3 }, /* -51.5db */ + { 0X00, 0X2E, 0X2D, 0X27 }, /* -51.0db */ + { 0X00, 0X30, 0XE9, 0X9A }, /* -50.5db */ + { 0X00, 0X33, 0XCF, 0X8D }, /* -50.0db */ + { 0X00, 0X36, 0XE1, 0X78 }, /* -49.5db */ + { 0X00, 0X3A, 0X21, 0XF3 }, /* -49.0db */ + { 0X00, 0X3D, 0X93, 0XC3 }, /* -48.5db */ + { 0X00, 0X41, 0X39, 0XD3 }, /* -48.0db */ + { 0X00, 0X45, 0X17, 0X3B }, /* -47.5db */ + { 0X00, 0X49, 0X2F, 0X44 }, /* -47.0db */ + { 0X00, 0X4D, 0X85, 0X66 }, /* -46.5db */ + { 0X00, 0X52, 0X1D, 0X50 }, /* -46.0db */ + { 0X00, 0X56, 0XFA, 0XE8 }, /* -45.5db */ + { 0X00, 0X5C, 0X22, 0X4E }, /* -45.0db */ + { 0X00, 0X61, 0X97, 0XE1 }, /* -44.5db */ + { 0X00, 0X67, 0X60, 0X44 }, /* -44.0db */ + { 0X00, 0X6D, 0X80, 0X60 }, /* -43.5db */ + { 0X00, 0X73, 0XFD, 0X65 }, /* -43.0db */ + { 0X00, 0X7A, 0XDC, 0XD7 }, /* -42.5db */ + { 0X00, 0X82, 0X24, 0X8A }, /* -42.0db */ + { 0X00, 0X89, 0XDA, 0XAB }, /* -41.5db */ + { 0X00, 0X92, 0X05, 0XC6 }, /* -41.0db */ + { 0X00, 0X9A, 0XAC, 0XC8 }, /* -40.5db */ + { 0X00, 0XA3, 0XD7, 0X0A }, /* -40.0db */ + { 0X00, 0XAD, 0X8C, 0X52 }, /* -39.5db */ + { 0X00, 0XB7, 0XD4, 0XDD }, /* -39.0db */ + { 0X00, 0XC2, 0XB9, 0X65 }, /* -38.5db */ + { 0X00, 0XCE, 0X43, 0X28 }, /* -38.0db */ + { 0X00, 0XDA, 0X7B, 0XF1 }, /* -37.5db */ + { 0X00, 0XE7, 0X6E, 0X1E }, /* -37.0db */ + { 0X00, 0XF5, 0X24, 0XAC }, /* -36.5db */ + { 0X01, 0X03, 0XAB, 0X3D }, /* -36.0db */ + { 0X01, 0X13, 0X0E, 0X24 }, /* -35.5db */ + { 0X01, 0X23, 0X5A, 0X71 }, /* -35.0db */ + { 0X01, 0X34, 0X9D, 0XF8 }, /* -34.5db */ + { 0X01, 0X46, 0XE7, 0X5D }, /* -34.0db */ + { 0X01, 0X5A, 0X46, 0X27 }, /* -33.5db */ + { 0X01, 0X6E, 0XCA, 0XC5 }, /* -33.0db */ + { 0X01, 0X84, 0X86, 0X9F }, /* -32.5db */ + { 0X01, 0X9B, 0X8C, 0X27 }, /* -32.0db */ + { 0X01, 0XB3, 0XEE, 0XE5 }, /* -31.5db */ + { 0X01, 0XCD, 0XC3, 0X8C }, /* -31.0db */ + { 0X01, 0XE9, 0X20, 0X05 }, /* -30.5db */ + { 0X02, 0X06, 0X1B, 0X89 }, /* -30.0db */ + { 0X02, 0X24, 0XCE, 0XB0 }, /* -29.5db */ + { 0X02, 0X45, 0X53, 0X85 }, /* -29.0db */ + { 0X02, 0X67, 0XC5, 0XA2 }, /* -28.5db */ + { 0X02, 0X8C, 0X42, 0X3F }, /* -28.0db */ + { 0X02, 0XB2, 0XE8, 0X55 }, /* -27.5db */ + { 0X02, 0XDB, 0XD8, 0XAD }, /* -27.0db */ + { 0X03, 0X07, 0X36, 0X05 }, /* -26.5db */ + { 0X03, 0X35, 0X25, 0X29 }, /* -26.0db */ + { 0X03, 0X65, 0XCD, 0X13 }, /* -25.5db */ + { 0X03, 0X99, 0X57, 0X0C }, /* -25.0db */ + { 0X03, 0XCF, 0XEE, 0XCF }, /* -24.5db */ + { 0X04, 0X09, 0XC2, 0XB0 }, /* -24.0db */ + { 0X04, 0X47, 0X03, 0XC1 }, /* -23.5db */ + { 0X04, 0X87, 0XE5, 0XFB }, /* -23.0db */ + { 0X04, 0XCC, 0XA0, 0X6D }, /* -22.5db */ + { 0X05, 0X15, 0X6D, 0X68 }, /* -22.0db */ + { 0X05, 0X62, 0X8A, 0XB3 }, /* -21.5db */ + { 0X05, 0XB4, 0X39, 0XBC }, /* -21.0db */ + { 0X06, 0X0A, 0XBF, 0XD4 }, /* -20.5db */ + { 0X06, 0X66, 0X66, 0X66 }, /* -20.0db */ + { 0X06, 0XC7, 0X7B, 0X36 }, /* -19.5db */ + { 0X07, 0X2E, 0X50, 0XA6 }, /* -19.0db */ + { 0X07, 0X9B, 0X3D, 0XF6 }, /* -18.5db */ + { 0X08, 0X0E, 0X9F, 0X96 }, /* -18.0db */ + { 0X08, 0X88, 0XD7, 0X6D }, /* -17.5db */ + { 0X09, 0X0A, 0X4D, 0X2F }, /* -17.0db */ + { 0X09, 0X93, 0X6E, 0XB8 }, /* -16.5db */ + { 0X0A, 0X24, 0XB0, 0X62 }, /* -16.0db */ + { 0X0A, 0XBE, 0X8D, 0X70 }, /* -15.5db */ + { 0X0B, 0X61, 0X88, 0X71 }, /* -15.0db */ + { 0X0C, 0X0E, 0X2B, 0XB0 }, /* -14.5db */ + { 0X0C, 0XC5, 0X09, 0XAB }, /* -14.0db */ + { 0X0D, 0X86, 0XBD, 0X8D }, /* -13.5db */ + { 0X0E, 0X53, 0XEB, 0XB3 }, /* -13.0db */ + { 0X0F, 0X2D, 0X42, 0X38 }, /* -12.5db */ + { 0X10, 0X13, 0X79, 0X87 }, /* -12.0db */ + { 0X11, 0X07, 0X54, 0XF9 }, /* -11.5db */ + { 0X12, 0X09, 0XA3, 0X7A }, /* -11.0db */ + { 0X13, 0X1B, 0X40, 0X39 }, /* -10.5db */ + { 0X14, 0X3D, 0X13, 0X62 }, /* -10.0db */ + { 0X15, 0X70, 0X12, 0XE1 }, /* -9.5db */ + { 0X16, 0XB5, 0X43, 0X37 }, /* -9.0db */ + { 0X18, 0X0D, 0XB8, 0X54 }, /* -8.5db */ + { 0X19, 0X7A, 0X96, 0X7F }, /* -8.0db */ + { 0X1A, 0XFD, 0X13, 0X54 }, /* -7.5db */ + { 0X1C, 0X96, 0X76, 0XC6 }, /* -7.0db */ + { 0X1E, 0X48, 0X1C, 0X37 }, /* -6.5db */ + { 0X20, 0X13, 0X73, 0X9E }, /* -6.0db */ + { 0X21, 0XFA, 0X02, 0XBF }, /* -5.5db */ + { 0X23, 0XFD, 0X66, 0X78 }, /* -5.0db */ + { 0X26, 0X1F, 0X54, 0X1C }, /* -4.5db */ + { 0X28, 0X61, 0X9A, 0XE9 }, /* -4.0db */ + { 0X2A, 0XC6, 0X25, 0X91 }, /* -3.5db */ + { 0X2D, 0X4E, 0XFB, 0XD5 }, /* -3.0db */ + { 0X2F, 0XFE, 0X44, 0X48 }, /* -2.5db */ + { 0X32, 0XD6, 0X46, 0X17 }, /* -2.0db */ + { 0X35, 0XD9, 0X6B, 0X02 }, /* -1.5db */ + { 0X39, 0X0A, 0X41, 0X5F }, /* -1.0db */ + { 0X3C, 0X6B, 0X7E, 0X4F }, /* -0.5db */ + { 0X40, 0X00, 0X00, 0X00 }, /* 0.0db */ + { 0X43, 0XCA, 0XD0, 0X22 }, /* 0.5db */ + { 0X47, 0XCF, 0X26, 0X7D }, /* 1.0db */ + { 0X4C, 0X10, 0X6B, 0XA5 }, /* 1.5db */ + { 0X50, 0X92, 0X3B, 0XE3 }, /* 2.0db */ + { 0X55, 0X58, 0X6A, 0X46 }, /* 2.5db */ + { 0X5A, 0X67, 0X03, 0XDF }, /* 3.0db */ + { 0X5F, 0XC2, 0X53, 0X32 }, /* 3.5db */ + { 0X65, 0X6E, 0XE3, 0XDB }, /* 4.0db */ + { 0X6B, 0X71, 0X86, 0X68 }, /* 4.5db */ + { 0X71, 0XCF, 0X54, 0X71 }, /* 5.0db */ + { 0X78, 0X8D, 0XB4, 0XE9 }, /* 5.5db */ + { 0X7F, 0XFF, 0XFF, 0XFF }, /* 6.0db */ +}; +#endif diff --git a/include/sound/tas2770-tlv.h b/include/sound/tas2770-tlv.h new file mode 100644 index 000000000..c73809254 --- /dev/null +++ b/include/sound/tas2770-tlv.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2770 Audio Smart Amplifier +// +// Copyright (C) 2025 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2770 hda driver implements for one, two, or even multiple +// TAS2770 chips. +// +// Author: Baojun Xu +// + +#ifndef __TAS2770_TLV_H__ +#define __TAS2770_TLV_H__ + +#define TAS2770_DVC_LEVEL TASDEVICE_REG(0x0, 0x0, 0x05) +#define TAS2770_AMP_LEVEL TASDEVICE_REG(0x0, 0x0, 0x03) + +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2770_dvc_tlv, -10000, 50, 0); +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2770_amp_tlv, 1100, 50, 0); + +#endif diff --git a/include/sound/tas2781-comlib-i2c.h b/include/sound/tas2781-comlib-i2c.h new file mode 100644 index 000000000..a1afa5c44 --- /dev/null +++ b/include/sound/tas2781-comlib-i2c.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2563/TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2025 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2563/TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2563/TAS2781 chips. +// +// Author: Shenghao Ding +// + +#ifndef __TAS2781_COMLIB_I2C_H__ +#define __TAS2781_COMLIB_I2C_H__ + +void tasdevice_reset(struct tasdevice_priv *tas_dev); +int tascodec_init(struct tasdevice_priv *tas_priv, void *codec, + struct module *module, + void (*cont)(const struct firmware *fw, void *context)); +struct tasdevice_priv *tasdevice_kzalloc(struct i2c_client *i2c); +int tasdevice_init(struct tasdevice_priv *tas_priv); +int tasdev_chn_switch(struct tasdevice_priv *tas_priv, + unsigned short chn); +int tasdevice_dev_update_bits( + struct tasdevice_priv *tasdevice, unsigned short chn, + unsigned int reg, unsigned int mask, unsigned int value); +int tasdevice_amp_putvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +int tasdevice_amp_getvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +int tasdevice_digital_getvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +int tasdevice_digital_putvol(struct tasdevice_priv *tas_priv, + struct snd_ctl_elem_value *ucontrol, struct soc_mixer_control *mc); +#endif /* __TAS2781_COMLIB_I2C_H__ */ diff --git a/include/sound/tas2781-dsp.h b/include/sound/tas2781-dsp.h new file mode 100644 index 000000000..e845687de --- /dev/null +++ b/include/sound/tas2781-dsp.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2025 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2781 chips. +// +// Author: Shenghao Ding +// Author: Kevin Lu +// + +#ifndef __TAS2781_DSP_H__ +#define __TAS2781_DSP_H__ + +#define MAIN_ALL_DEVICES 0x0d +#define MAIN_DEVICE_A 0x01 +#define MAIN_DEVICE_B 0x08 +#define MAIN_DEVICE_C 0x10 +#define MAIN_DEVICE_D 0x14 +#define COEFF_DEVICE_A 0x03 +#define COEFF_DEVICE_B 0x0a +#define COEFF_DEVICE_C 0x11 +#define COEFF_DEVICE_D 0x15 +#define PRE_DEVICE_A 0x04 +#define PRE_DEVICE_B 0x0b +#define PRE_DEVICE_C 0x12 +#define PRE_DEVICE_D 0x16 + +#define PPC3_VERSION_BASE 0x4100 +#define PPC3_VERSION_TAS2781_BASIC_MIN 0x14600 +#define PPC3_VERSION_TAS2781_ALPHA_MIN 0x4a00 +#define PPC3_VERSION_TAS2781_BETA_MIN 0x19400 +#define PPC3_VERSION_TAS5825_BASE 0x114200 +#define TASDEVICE_DEVICE_SUM 8 +#define TASDEVICE_CONFIG_SUM 64 + +#define TASDEVICE_MAX_CHANNELS 8 + +enum tasdevice_dsp_dev_idx { + TASDEVICE_DSP_TAS_2555 = 0, + TASDEVICE_DSP_TAS_2555_STEREO, + TASDEVICE_DSP_TAS_2557_MONO, + TASDEVICE_DSP_TAS_2557_DUAL_MONO, + TASDEVICE_DSP_TAS_2559, + TASDEVICE_DSP_TAS_2563, + TASDEVICE_DSP_TAS_2563_DUAL_MONO = 7, + TASDEVICE_DSP_TAS_2563_QUAD, + TASDEVICE_DSP_TAS_2563_21, + TASDEVICE_DSP_TAS_2781, + TASDEVICE_DSP_TAS_2781_DUAL_MONO, + TASDEVICE_DSP_TAS_2781_21, + TASDEVICE_DSP_TAS_2781_QUAD, + TASDEVICE_DSP_TAS_5825_MONO, + TASDEVICE_DSP_TAS_5825_DUAL, + TASDEVICE_DSP_TAS_MAX_DEVICE +}; + +struct tasdevice_fw_fixed_hdr { + unsigned int fwsize; + unsigned int ppcver; + unsigned int drv_ver; +}; + +struct tasdevice_dspfw_hdr { + struct tasdevice_fw_fixed_hdr fixed_hdr; + unsigned short device_family; + unsigned short device; + unsigned char ndev; +}; + +struct tasdev_blk { + int nr_retry; + unsigned int type; + unsigned char is_pchksum_present; + unsigned char pchksum; + unsigned char is_ychksum_present; + unsigned char ychksum; + unsigned int nr_cmds; + unsigned int blk_size; + unsigned int nr_subblocks; + /* fixed m68k compiling issue, storing the dev_idx as a member of block + * can reduce unnecessary timeand system resource comsumption of + * dev_idx mapping every time the block data writing to the dsp. + */ + unsigned char dev_idx; + unsigned char *data; +}; + +struct tasdevice_data { + char name[64]; + unsigned int nr_blk; + struct tasdev_blk *dev_blks; +}; + +struct tasdevice_prog { + unsigned int prog_size; + struct tasdevice_data dev_data; +}; + +struct tasdevice_config { + unsigned int cfg_size; + char name[64]; + struct tasdevice_data dev_data; +}; + +struct tasdevice_calibration { + struct tasdevice_data dev_data; +}; + +struct fct_param_address { + /* Thermal data for PG 1.0 device */ + unsigned char thr[3]; + /* Thermal data for PG 2.0 device */ + unsigned char thr2[3]; + /* Pilot tone enable flag, usually the sine wave */ + unsigned char plt_flg[3]; + /* Pilot tone gain for calibration */ + unsigned char sin_gn[3]; + /* Pilot tone gain for calibration */ + unsigned char sin_gn2[3]; + /* high 32-bit of real-time spk impedance */ + unsigned char r0_reg[3]; + /* check spk connection */ + unsigned char tf_reg[3]; + /* check spk resonant frequency */ + unsigned char a1_reg[3]; + /* check spk resonant frequency */ + unsigned char a2_reg[3]; +}; + +struct tasdevice_fw { + struct tasdevice_dspfw_hdr fw_hdr; + unsigned short nr_programs; + struct tasdevice_prog *programs; + unsigned short nr_configurations; + struct tasdevice_config *configs; + unsigned short nr_calibrations; + struct tasdevice_calibration *calibrations; + struct fct_param_address fct_par_addr; + struct device *dev; +}; + +enum tasdevice_fw_state { + /* Driver in startup mode, not load any firmware. */ + TASDEVICE_DSP_FW_PENDING, + /* DSP firmware in the system, but parsing error. */ + TASDEVICE_DSP_FW_FAIL, + /* + * Only RCA (Reconfigurable Architecture) firmware load + * successfully. + */ + TASDEVICE_RCA_FW_OK, + /* Both RCA and DSP firmware load successfully. */ + TASDEVICE_DSP_FW_ALL_OK, +}; + +enum tasdevice_bin_blk_type { + TASDEVICE_BIN_BLK_COEFF = 1, + TASDEVICE_BIN_BLK_POST_POWER_UP, + TASDEVICE_BIN_BLK_PRE_SHUTDOWN, + TASDEVICE_BIN_BLK_PRE_POWER_UP, + TASDEVICE_BIN_BLK_POST_SHUTDOWN +}; + +struct tasdevice_rca_hdr { + unsigned int img_sz; + unsigned int checksum; + unsigned int binary_version_num; + unsigned int drv_fw_version; + unsigned char plat_type; + unsigned char dev_family; + unsigned char reserve; + unsigned char ndev; + unsigned char devs[TASDEVICE_DEVICE_SUM]; + unsigned int nconfig; + unsigned int config_size[TASDEVICE_CONFIG_SUM]; +}; + +struct tasdev_blk_data { + unsigned char dev_idx; + unsigned char block_type; + unsigned short yram_checksum; + unsigned int block_size; + unsigned int n_subblks; + unsigned char *regdata; +}; + +struct tasdevice_config_info { + unsigned int nblocks; + unsigned int real_nblocks; + unsigned char active_dev; + struct tasdev_blk_data **blk_data; +}; + +struct tasdevice_rca { + struct tasdevice_rca_hdr fw_hdr; + int ncfgs; + struct tasdevice_config_info **cfg_info; + int profile_cfg_id; + /* + * Used among SmartAMP for PDM microphone recording or IV data + * capture. + */ + int capture_profile_id; + /* + * Since version 0x105, the keyword 'init' was introduced into the + * profile, which is used for chip initialization, particularly to + * store common settings for other non-initialization profiles. + * if (init_profile_id < 0) + * No init profile inside the RCA firmware. + */ + int init_profile_id; +}; + +void tasdevice_select_cfg_blk(void *context, int conf_no, + unsigned char block_type); +void tasdevice_config_info_remove(void *context); +void tasdevice_dsp_remove(void *context); +int tasdevice_dsp_parser(void *context); +int tasdevice_rca_parser(void *context, const struct firmware *fmw); +void tasdevice_dsp_remove(void *context); +void tasdevice_calbin_remove(void *context); +int tasdevice_select_tuningprm_cfg(void *context, int prm, + int cfg_no, int rca_conf_no); +int tasdevice_prmg_load(void *context, int prm_no); +void tasdevice_tuning_switch(void *context, int state, bool is_cap); +int tas2781_load_calibration(void *context, char *file_name, + unsigned short i); + +#endif diff --git a/include/sound/tas2781-tlv.h b/include/sound/tas2781-tlv.h new file mode 100644 index 000000000..273224df9 --- /dev/null +++ b/include/sound/tas2781-tlv.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2025 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2781 chips. +// +// Author: Shenghao Ding +// + +#ifndef __TAS2781_TLV_H__ +#define __TAS2781_TLV_H__ + +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2781_dvc_tlv, -10000, 50, 0); +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2781_amp_tlv, 1100, 50, 0); + +#endif diff --git a/include/sound/tas2781.h b/include/sound/tas2781.h new file mode 100644 index 000000000..b763da613 --- /dev/null +++ b/include/sound/tas2781.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2563/TAS2781 Audio Smart Amplifier +// +// Copyright (C) 2022 - 2026 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2563/TAS2781 driver implements a flexible and configurable +// algo coefficient setting for one, two, or even multiple +// TAS2563/TAS2781 chips. +// +// Author: Shenghao Ding +// Author: Kevin Lu +// Author: Baojun Xu +// + +#ifndef __TAS2781_H__ +#define __TAS2781_H__ + +#ifdef CONFIG_SND_SOC_TAS2781_ACOUST_I2C +#include +#endif + +#include "tas2781-dsp.h" + +/* version number */ +#define TAS2781_DRV_VER 1 +#define SMARTAMP_MODULE_NAME "tas2781" +#define TAS2781_GLOBAL_ADDR 0x40 +#define TAS2563_GLOBAL_ADDR 0x48 +#define TASDEVICE_RATES (SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_88200) + +#define TASDEVICE_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +#define TASDEVICE_CRC8_POLYNOMIAL 0x4d + +/* PAGE Control Register (available in page0 of each book) */ +#define TASDEVICE_PAGE_SELECT 0x00 +#define TASDEVICE_BOOKCTL_PAGE 0x00 +#define TASDEVICE_BOOKCTL_REG 127 +#define TASDEVICE_BOOK_ID(reg) (reg / (256 * 128)) +#define TASDEVICE_PAGE_ID(reg) ((reg % (256 * 128)) / 128) +#define TASDEVICE_PAGE_REG(reg) ((reg % (256 * 128)) % 128) +#define TASDEVICE_PGRG(reg) (reg % (256 * 128)) +#define TASDEVICE_REG(book, page, reg) (((book * 256 * 128) + \ + (page * 128)) + reg) + +/* Software Reset, compatble with new device (TAS5825). */ +#define TASDEVICE_REG_SWRESET TASDEVICE_REG(0x0, 0x0, 0x01) +#define TASDEVICE_REG_SWRESET_RESET BIT(0) + +#define TAS5825_REG_SWRESET_RESET (BIT(0) | BIT(4)) + +/* Checksum */ +#define TASDEVICE_CHECKSUM_REG TASDEVICE_REG(0x0, 0x0, 0x7e) + +/* XM_340 */ +#define TASDEVICE_XM_A1_REG TASDEVICE_REG(0x64, 0x02, 0x4c) +/* XM_341 */ +#define TASDEVICE_XM_A2_REG TASDEVICE_REG(0x64, 0x02, 0x64) + +/* Volume control */ +#define TAS2563_DVC_LVL TASDEVICE_REG(0x00, 0x02, 0x0c) +#define TAS2781_DVC_LVL TASDEVICE_REG(0x0, 0x0, 0x1a) +#define TAS2781_AMP_LEVEL TASDEVICE_REG(0x0, 0x0, 0x03) +#define TAS2781_AMP_LEVEL_MASK GENMASK(5, 1) + +#define TAS2563_IDLE TASDEVICE_REG(0x00, 0x00, 0x3e) +#define TAS2563_PRM_R0_REG TASDEVICE_REG(0x00, 0x0f, 0x34) + +#define TAS2563_RUNTIME_RE_REG_TF TASDEVICE_REG(0x64, 0x02, 0x70) +#define TAS2563_RUNTIME_RE_REG TASDEVICE_REG(0x64, 0x02, 0x48) + +#define TAS2563_PRM_ENFF_REG TASDEVICE_REG(0x00, 0x0d, 0x54) +#define TAS2563_PRM_DISTCK_REG TASDEVICE_REG(0x00, 0x0d, 0x58) +#define TAS2563_PRM_TE_SCTHR_REG TASDEVICE_REG(0x00, 0x0f, 0x60) +#define TAS2563_PRM_PLT_FLAG_REG TASDEVICE_REG(0x00, 0x0d, 0x74) +#define TAS2563_PRM_SINEGAIN_REG TASDEVICE_REG(0x00, 0x0d, 0x7c) +/* prm_Int_B0 */ +#define TAS2563_TE_TA1_REG TASDEVICE_REG(0x00, 0x10, 0x0c) +/* prm_Int_A1 */ +#define TAS2563_TE_TA1_AT_REG TASDEVICE_REG(0x00, 0x10, 0x10) +/* prm_TE_Beta */ +#define TAS2563_TE_TA2_REG TASDEVICE_REG(0x00, 0x0f, 0x64) +/* prm_TE_Beta1 */ +#define TAS2563_TE_AT_REG TASDEVICE_REG(0x00, 0x0f, 0x68) +/* prm_TE_1_Beta1 */ +#define TAS2563_TE_DT_REG TASDEVICE_REG(0x00, 0x0f, 0x70) + +#define TAS2781_PRM_INT_MASK_REG TASDEVICE_REG(0x00, 0x00, 0x3b) +#define TAS2781_PRM_CLK_CFG_REG TASDEVICE_REG(0x00, 0x00, 0x5c) +#define TAS2781_PRM_RSVD_REG TASDEVICE_REG(0x00, 0x01, 0x19) +#define TAS2781_PRM_TEST_57_REG TASDEVICE_REG(0x00, 0xfd, 0x39) +#define TAS2781_PRM_TEST_62_REG TASDEVICE_REG(0x00, 0xfd, 0x3e) +#define TAS2781_PRM_PVDD_UVLO_REG TASDEVICE_REG(0x00, 0x00, 0x71) +#define TAS2781_PRM_CHNL_0_REG TASDEVICE_REG(0x00, 0x00, 0x03) +#define TAS2781_PRM_NG_CFG0_REG TASDEVICE_REG(0x00, 0x00, 0x35) +#define TAS2781_PRM_IDLE_CH_DET_REG TASDEVICE_REG(0x00, 0x00, 0x66) +#define TAS2781_PRM_PLT_FLAG_REG TASDEVICE_REG(0x00, 0x14, 0x38) +#define TAS2781_PRM_SINEGAIN_REG TASDEVICE_REG(0x00, 0x14, 0x40) +#define TAS2781_PRM_SINEGAIN2_REG TASDEVICE_REG(0x00, 0x14, 0x44) + +#define TAS2781_TEST_UNLOCK_REG TASDEVICE_REG(0x00, 0xfd, 0x0d) +#define TAS2781_TEST_PAGE_UNLOCK 0x0d + +#define TAS2781_RUNTIME_LATCH_RE_REG TASDEVICE_REG(0x00, 0x00, 0x49) +#define TAS2781_RUNTIME_RE_REG_TF TASDEVICE_REG(0x64, 0x62, 0x48) +#define TAS2781_RUNTIME_RE_REG TASDEVICE_REG(0x64, 0x63, 0x44) + +enum audio_device { + TAS2020, + TAS2118, + TAS2120, + TAS2320, + TAS2563, + TAS2568, + TAS2570, + TAS2572, + TAS2573, + TAS2574, + TAS2781, + TAS5802, + TAS5806M, + TAS5806MD, + TAS5815, + TAS5822, + TAS5825, + TAS5827, + TAS5828, + TAS5830, + TAS5832, + TAS_OTHERS, +}; + +enum dspbin_type { + TASDEV_BASIC, + TASDEV_ALPHA, + TASDEV_BETA, +}; + +struct bulk_reg_val { + int reg; + unsigned char val[4]; + unsigned char val_len; + bool is_locked; +}; + +struct tasdevice { + struct bulk_reg_val *cali_data_backup; + struct bulk_reg_val alp_cali_bckp; + struct tasdevice_fw *cali_data_fmw; + void *cali_specific; + unsigned int dev_addr; + unsigned int err_code; + unsigned char cur_book; + short cur_prog; + short cur_conf; + bool is_loading; + bool is_loaderr; +}; + +struct cali_reg { + unsigned int r0_reg; + unsigned int r0_low_reg; + unsigned int invr0_reg; + unsigned int pow_reg; + unsigned int tlimit_reg; +}; + +struct calidata { + unsigned char *data; + unsigned long total_sz; + struct cali_reg cali_reg_array; + unsigned int cali_dat_sz_per_dev; +}; + +/* + * To enable CONFIG_SND_SOC_TAS2781_ACOUST_I2C will create a bridge to the + * acoustic tuning tool which can tune the chips' acoustic effect. Due to the + * whole directly exposing the registers, there exist some potential risks. So + * this define is invisible in Kconfig, anyone who wants to use acoustic tool + * have to edit the source manually. + */ +#ifdef CONFIG_SND_SOC_TAS2781_ACOUST_I2C +#define TASDEV_DATA_PAYLOAD_SIZE 128 +struct acoustic_data { + unsigned char len; + unsigned char id; + unsigned char addr; + unsigned char book; + unsigned char page; + unsigned char reg; + unsigned char data[TASDEV_DATA_PAYLOAD_SIZE]; +}; +#endif + +struct tasdevice_priv { + struct tasdevice tasdevice[TASDEVICE_MAX_CHANNELS]; + struct tasdevice_rca rcabin; + struct calidata cali_data; +#ifdef CONFIG_SND_SOC_TAS2781_ACOUST_I2C + struct acoustic_data acou_data; +#endif + struct tasdevice_fw *fmw; + struct gpio_desc *reset; + struct mutex codec_lock; + struct regmap *regmap; + struct device *dev; + + unsigned char cal_binaryname[TASDEVICE_MAX_CHANNELS][64]; + unsigned char crc8_lkp_tbl[CRC8_TABLE_SIZE]; + unsigned char coef_binaryname[64]; + unsigned char rca_binaryname[64]; + unsigned char dev_name[32]; + const unsigned char (*dvc_tlv_table)[4]; + const char *name_prefix; + unsigned char ndev; + unsigned int dspbin_typ; + unsigned int magic_num; + unsigned int chip_id; + unsigned int sysclk; + int speaker_id; + + int irq; + int cur_prog; + int cur_conf; + int fw_state; + int index; + void *client; + void *codec; + bool force_fwload_status; + bool playback_started; + bool isacpi; + bool isspi; + unsigned int global_addr; + + int (*fw_parse_variable_header)(struct tasdevice_priv *tas_priv, + const struct firmware *fmw, int offset); + int (*fw_parse_program_data)(struct tasdevice_priv *tas_priv, + struct tasdevice_fw *tas_fmw, + const struct firmware *fmw, int offset); + int (*fw_parse_configuration_data)(struct tasdevice_priv *tas_priv, + struct tasdevice_fw *tas_fmw, + const struct firmware *fmw, int offset); + int (*fw_parse_fct_param_address)(struct tasdevice_priv *tas_priv, + struct tasdevice_fw *tas_fmw, + const struct firmware *fmw, int offset); + int (*tasdevice_load_block)(struct tasdevice_priv *tas_priv, + struct tasdev_blk *block); + + int (*change_chn_book)(struct tasdevice_priv *tas_priv, + unsigned short chn, int book); + int (*update_bits)(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned int mask, + unsigned int value); + int (*dev_read)(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned int *value); + int (*dev_bulk_read)(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned char *p_data, + unsigned int n_length); +}; + +int tasdevice_dev_read(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned int *value); +int tasdevice_dev_bulk_read(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned char *p_data, + unsigned int n_length); +int tasdevice_dev_write(struct tasdevice_priv *tas_priv, + unsigned short chn, unsigned int reg, unsigned int value); +int tasdevice_dev_bulk_write( + struct tasdevice_priv *tas_priv, unsigned short chn, + unsigned int reg, unsigned char *p_data, unsigned int n_length); +void tasdevice_remove(struct tasdevice_priv *tas_priv); +#endif /* __TAS2781_H__ */ diff --git a/include/sound/tas2x20-tlv.h b/include/sound/tas2x20-tlv.h new file mode 100644 index 000000000..6e6bcec4a --- /dev/null +++ b/include/sound/tas2x20-tlv.h @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS2x20/TAS2118 Audio Smart Amplifier +// +// Copyright (C) 2025 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS2x20/TAS2118 hda driver implements for one, two, or even multiple +// TAS2x20/TAS2118 chips. +// +// Author: Baojun Xu +// + +#ifndef __TAS2X20_TLV_H__ +#define __TAS2X20_TLV_H__ + +#define TAS2X20_DVC_LEVEL TASDEVICE_REG(0x0, 0x2, 0x0c) +#define TAS2X20_AMP_LEVEL TASDEVICE_REG(0x0, 0x0, 0x07) + +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2x20_dvc_tlv, 1650, 50, 0); +static const __maybe_unused DECLARE_TLV_DB_SCALE(tas2x20_amp_tlv, 2100, 50, 0); + +/* pow(10, db/20) * pow(2,22) */ +static const __maybe_unused unsigned char tas2x20_dvc_table[][4] = { + { 0X00, 0X00, 0X0D, 0X00 }, /* -110.0db */ + { 0X00, 0X00, 0X0E, 0X00 }, /* -109.5db */ + { 0X00, 0X00, 0X0E, 0X00 }, /* -109.0db */ + { 0X00, 0X00, 0X0F, 0X00 }, /* -108.5db */ + { 0X00, 0X00, 0X10, 0X00 }, /* -108.0db */ + { 0X00, 0X00, 0X11, 0X00 }, /* -107.5db */ + { 0X00, 0X00, 0X12, 0X00 }, /* -107.0db */ + { 0X00, 0X00, 0X13, 0X00 }, /* -106.5db */ + { 0X00, 0X00, 0X15, 0X00 }, /* -106.0db */ + { 0X00, 0X00, 0X16, 0X00 }, /* -105.5db */ + { 0X00, 0X00, 0X17, 0X00 }, /* -105.0db */ + { 0X00, 0X00, 0X18, 0X00 }, /* -104.5db */ + { 0X00, 0X00, 0X1A, 0X00 }, /* -104.0db */ + { 0X00, 0X00, 0X1C, 0X00 }, /* -103.5db */ + { 0X00, 0X00, 0X1D, 0X00 }, /* -103.0db */ + { 0X00, 0X00, 0X1F, 0X00 }, /* -102.5db */ + { 0X00, 0X00, 0X21, 0X00 }, /* -102.0db */ + { 0X00, 0X00, 0X23, 0X00 }, /* -101.5db */ + { 0X00, 0X00, 0X25, 0X00 }, /* -101.0db */ + { 0X00, 0X00, 0X27, 0X00 }, /* -100.5db */ + { 0X00, 0X00, 0X29, 0X00 }, /* -100.0db */ + { 0X00, 0X00, 0X2C, 0X00 }, /* -99.5db */ + { 0X00, 0X00, 0X2F, 0X00 }, /* -99.0db */ + { 0X00, 0X00, 0X31, 0X00 }, /* -98.5db */ + { 0X00, 0X00, 0X34, 0X00 }, /* -98.0db */ + { 0X00, 0X00, 0X37, 0X00 }, /* -97.5db */ + { 0X00, 0X00, 0X3B, 0X00 }, /* -97.0db */ + { 0X00, 0X00, 0X3E, 0X00 }, /* -96.5db */ + { 0X00, 0X00, 0X42, 0X00 }, /* -96.0db */ + { 0X00, 0X00, 0X46, 0X00 }, /* -95.5db */ + { 0X00, 0X00, 0X4A, 0X00 }, /* -95.0db */ + { 0X00, 0X00, 0X4F, 0X00 }, /* -94.5db */ + { 0X00, 0X00, 0X53, 0X00 }, /* -94.0db */ + { 0X00, 0X00, 0X58, 0X00 }, /* -93.5db */ + { 0X00, 0X00, 0X5D, 0X00 }, /* -93.0db */ + { 0X00, 0X00, 0X63, 0X00 }, /* -92.5db */ + { 0X00, 0X00, 0X69, 0X00 }, /* -92.0db */ + { 0X00, 0X00, 0X6F, 0X00 }, /* -91.5db */ + { 0X00, 0X00, 0X76, 0X00 }, /* -91.0db */ + { 0X00, 0X00, 0X7D, 0X00 }, /* -90.5db */ + { 0X00, 0X00, 0X84, 0X00 }, /* -90.0db */ + { 0X00, 0X00, 0X8C, 0X00 }, /* -89.5db */ + { 0X00, 0X00, 0X94, 0X00 }, /* -89.0db */ + { 0X00, 0X00, 0X9D, 0X00 }, /* -88.5db */ + { 0X00, 0X00, 0XA6, 0X00 }, /* -88.0db */ + { 0X00, 0X00, 0XB0, 0X00 }, /* -87.5db */ + { 0X00, 0X00, 0XBB, 0X00 }, /* -87.0db */ + { 0X00, 0X00, 0XC6, 0X00 }, /* -86.5db */ + { 0X00, 0X00, 0XD2, 0X00 }, /* -86.0db */ + { 0X00, 0X00, 0XDE, 0X00 }, /* -85.5db */ + { 0X00, 0X00, 0XEB, 0X00 }, /* -85.0db */ + { 0X00, 0X00, 0XF9, 0X00 }, /* -84.5db */ + { 0X00, 0X01, 0X08, 0X00 }, /* -84.0db */ + { 0X00, 0X01, 0X18, 0X00 }, /* -83.5db */ + { 0X00, 0X01, 0X28, 0X00 }, /* -83.0db */ + { 0X00, 0X01, 0X3A, 0X00 }, /* -82.5db */ + { 0X00, 0X01, 0X4D, 0X00 }, /* -82.0db */ + { 0X00, 0X01, 0X60, 0X00 }, /* -81.5db */ + { 0X00, 0X01, 0X75, 0X00 }, /* -81.0db */ + { 0X00, 0X01, 0X8B, 0X00 }, /* -80.5db */ + { 0X00, 0X01, 0XA3, 0X00 }, /* -80.0db */ + { 0X00, 0X01, 0XBC, 0X00 }, /* -79.5db */ + { 0X00, 0X01, 0XD6, 0X00 }, /* -79.0db */ + { 0X00, 0X01, 0XF2, 0X00 }, /* -78.5db */ + { 0X00, 0X02, 0X10, 0X00 }, /* -78.0db */ + { 0X00, 0X02, 0X2F, 0X00 }, /* -77.5db */ + { 0X00, 0X02, 0X50, 0X00 }, /* -77.0db */ + { 0X00, 0X02, 0X73, 0X00 }, /* -76.5db */ + { 0X00, 0X02, 0X98, 0X00 }, /* -76.0db */ + { 0X00, 0X02, 0XC0, 0X00 }, /* -75.5db */ + { 0X00, 0X02, 0XE9, 0X00 }, /* -75.0db */ + { 0X00, 0X03, 0X16, 0X00 }, /* -74.5db */ + { 0X00, 0X03, 0X44, 0X00 }, /* -74.0db */ + { 0X00, 0X03, 0X76, 0X00 }, /* -73.5db */ + { 0X00, 0X03, 0XAA, 0X00 }, /* -73.0db */ + { 0X00, 0X03, 0XE2, 0X00 }, /* -72.5db */ + { 0X00, 0X04, 0X1D, 0X00 }, /* -72.0db */ + { 0X00, 0X04, 0X5B, 0X00 }, /* -71.5db */ + { 0X00, 0X04, 0X9E, 0X00 }, /* -71.0db */ + { 0X00, 0X04, 0XE4, 0X00 }, /* -70.5db */ + { 0X00, 0X05, 0X2E, 0X00 }, /* -70.0db */ + { 0X00, 0X05, 0X7C, 0X00 }, /* -69.5db */ + { 0X00, 0X05, 0XD0, 0X00 }, /* -69.0db */ + { 0X00, 0X06, 0X28, 0X00 }, /* -68.5db */ + { 0X00, 0X06, 0X85, 0X00 }, /* -68.0db */ + { 0X00, 0X06, 0XE8, 0X00 }, /* -67.5db */ + { 0X00, 0X07, 0X51, 0X00 }, /* -67.0db */ + { 0X00, 0X07, 0XC0, 0X00 }, /* -66.5db */ + { 0X00, 0X08, 0X36, 0X00 }, /* -66.0db */ + { 0X00, 0X08, 0XB2, 0X00 }, /* -65.5db */ + { 0X00, 0X09, 0X36, 0X00 }, /* -65.0db */ + { 0X00, 0X09, 0XC2, 0X00 }, /* -64.5db */ + { 0X00, 0X0A, 0X56, 0X00 }, /* -64.0db */ + { 0X00, 0X0A, 0XF3, 0X00 }, /* -63.5db */ + { 0X00, 0X0B, 0X99, 0X00 }, /* -63.0db */ + { 0X00, 0X0C, 0X49, 0X00 }, /* -62.5db */ + { 0X00, 0X0D, 0X03, 0X00 }, /* -62.0db */ + { 0X00, 0X0D, 0XC9, 0X00 }, /* -61.5db */ + { 0X00, 0X0E, 0X9A, 0X00 }, /* -61.0db */ + { 0X00, 0X0F, 0X77, 0X00 }, /* -60.5db */ + { 0X00, 0X10, 0X62, 0X00 }, /* -60.0db */ + { 0X00, 0X11, 0X5A, 0X00 }, /* -59.5db */ + { 0X00, 0X12, 0X62, 0X00 }, /* -59.0db */ + { 0X00, 0X13, 0X78, 0X00 }, /* -58.5db */ + { 0X00, 0X14, 0XA0, 0X00 }, /* -58.0db */ + { 0X00, 0X15, 0XD9, 0X00 }, /* -57.5db */ + { 0X00, 0X17, 0X24, 0X00 }, /* -57.0db */ + { 0X00, 0X18, 0X83, 0X00 }, /* -56.5db */ + { 0X00, 0X19, 0XF7, 0X00 }, /* -56.0db */ + { 0X00, 0X1B, 0X81, 0X00 }, /* -55.5db */ + { 0X00, 0X1D, 0X22, 0X00 }, /* -55.0db */ + { 0X00, 0X1E, 0XDC, 0X00 }, /* -54.5db */ + { 0X00, 0X20, 0XB0, 0X00 }, /* -54.0db */ + { 0X00, 0X22, 0XA0, 0X00 }, /* -53.5db */ + { 0X00, 0X24, 0XAD, 0X00 }, /* -53.0db */ + { 0X00, 0X26, 0XDA, 0X00 }, /* -52.5db */ + { 0X00, 0X29, 0X27, 0X00 }, /* -52.0db */ + { 0X00, 0X2B, 0X97, 0X00 }, /* -51.5db */ + { 0X00, 0X2E, 0X2D, 0X00 }, /* -51.0db */ + { 0X00, 0X30, 0XE9, 0X00 }, /* -50.5db */ + { 0X00, 0X33, 0XCF, 0X00 }, /* -50.0db */ + { 0X00, 0X36, 0XE1, 0X00 }, /* -49.5db */ + { 0X00, 0X3A, 0X21, 0X00 }, /* -49.0db */ + { 0X00, 0X3D, 0X93, 0X00 }, /* -48.5db */ + { 0X00, 0X41, 0X39, 0X00 }, /* -48.0db */ + { 0X00, 0X45, 0X17, 0X00 }, /* -47.5db */ + { 0X00, 0X49, 0X2F, 0X00 }, /* -47.0db */ + { 0X00, 0X4D, 0X85, 0X00 }, /* -46.5db */ + { 0X00, 0X52, 0X1D, 0X00 }, /* -46.0db */ + { 0X00, 0X56, 0XFA, 0X00 }, /* -45.5db */ + { 0X00, 0X5C, 0X22, 0X00 }, /* -45.0db */ + { 0X00, 0X61, 0X97, 0X00 }, /* -44.5db */ + { 0X00, 0X67, 0X60, 0X00 }, /* -44.0db */ + { 0X00, 0X6D, 0X80, 0X00 }, /* -43.5db */ + { 0X00, 0X73, 0XFD, 0X00 }, /* -43.0db */ + { 0X00, 0X7A, 0XDC, 0X00 }, /* -42.5db */ + { 0X00, 0X82, 0X24, 0X00 }, /* -42.0db */ + { 0X00, 0X89, 0XDA, 0X00 }, /* -41.5db */ + { 0X00, 0X92, 0X05, 0X00 }, /* -41.0db */ + { 0X00, 0X9A, 0XAC, 0X00 }, /* -40.5db */ + { 0X00, 0XA3, 0XD7, 0X00 }, /* -40.0db */ + { 0X00, 0XAD, 0X8C, 0X00 }, /* -39.5db */ + { 0X00, 0XB7, 0XD4, 0X00 }, /* -39.0db */ + { 0X00, 0XC2, 0XB9, 0X00 }, /* -38.5db */ + { 0X00, 0XCE, 0X43, 0X00 }, /* -38.0db */ + { 0X00, 0XDA, 0X7B, 0X00 }, /* -37.5db */ + { 0X00, 0XE7, 0X6E, 0X00 }, /* -37.0db */ + { 0X00, 0XF5, 0X24, 0X00 }, /* -36.5db */ + { 0X01, 0X03, 0XAB, 0X00 }, /* -36.0db */ + { 0X01, 0X13, 0X0E, 0X00 }, /* -35.5db */ + { 0X01, 0X23, 0X5A, 0X00 }, /* -35.0db */ + { 0X01, 0X34, 0X9D, 0X00 }, /* -34.5db */ + { 0X01, 0X46, 0XE7, 0X00 }, /* -34.0db */ + { 0X01, 0X5A, 0X46, 0X00 }, /* -33.5db */ + { 0X01, 0X6E, 0XCA, 0X00 }, /* -33.0db */ + { 0X01, 0X84, 0X86, 0X00 }, /* -32.5db */ + { 0X01, 0X9B, 0X8C, 0X00 }, /* -32.0db */ + { 0X01, 0XB3, 0XEE, 0X00 }, /* -31.5db */ + { 0X01, 0XCD, 0XC3, 0X00 }, /* -31.0db */ + { 0X01, 0XE9, 0X20, 0X00 }, /* -30.5db */ + { 0X02, 0X06, 0X1B, 0X00 }, /* -30.0db */ + { 0X02, 0X24, 0XCE, 0X00 }, /* -29.5db */ + { 0X02, 0X45, 0X53, 0X00 }, /* -29.0db */ + { 0X02, 0X67, 0XC5, 0X00 }, /* -28.5db */ + { 0X02, 0X8C, 0X42, 0X00 }, /* -28.0db */ + { 0X02, 0XB2, 0XE8, 0X00 }, /* -27.5db */ + { 0X02, 0XDB, 0XD8, 0X00 }, /* -27.0db */ + { 0X03, 0X07, 0X36, 0X00 }, /* -26.5db */ + { 0X03, 0X35, 0X25, 0X00 }, /* -26.0db */ + { 0X03, 0X65, 0XCD, 0X00 }, /* -25.5db */ + { 0X03, 0X99, 0X57, 0X00 }, /* -25.0db */ + { 0X03, 0XCF, 0XEE, 0X00 }, /* -24.5db */ + { 0X04, 0X09, 0XC2, 0X00 }, /* -24.0db */ + { 0X04, 0X47, 0X03, 0X00 }, /* -23.5db */ + { 0X04, 0X87, 0XE5, 0X00 }, /* -23.0db */ + { 0X04, 0XCC, 0XA0, 0X00 }, /* -22.5db */ + { 0X05, 0X15, 0X6D, 0X00 }, /* -22.0db */ + { 0X05, 0X62, 0X8A, 0X00 }, /* -21.5db */ + { 0X05, 0XB4, 0X39, 0X00 }, /* -21.0db */ + { 0X06, 0X0A, 0XBF, 0X00 }, /* -20.5db */ + { 0X06, 0X66, 0X66, 0X00 }, /* -20.0db */ + { 0X06, 0XC7, 0X7B, 0X00 }, /* -19.5db */ + { 0X07, 0X2E, 0X50, 0X00 }, /* -19.0db */ + { 0X07, 0X9B, 0X3D, 0X00 }, /* -18.5db */ + { 0X08, 0X0E, 0X9F, 0X00 }, /* -18.0db */ + { 0X08, 0X88, 0XD7, 0X00 }, /* -17.5db */ + { 0X09, 0X0A, 0X4D, 0X00 }, /* -17.0db */ + { 0X09, 0X93, 0X6E, 0X00 }, /* -16.5db */ + { 0X0A, 0X24, 0XB0, 0X00 }, /* -16.0db */ + { 0X0A, 0XBE, 0X8D, 0X00 }, /* -15.5db */ + { 0X0B, 0X61, 0X88, 0X00 }, /* -15.0db */ + { 0X0C, 0X0E, 0X2B, 0X00 }, /* -14.5db */ + { 0X0C, 0XC5, 0X09, 0X00 }, /* -14.0db */ + { 0X0D, 0X86, 0XBD, 0X00 }, /* -13.5db */ + { 0X0E, 0X53, 0XEB, 0X00 }, /* -13.0db */ + { 0X0F, 0X2D, 0X42, 0X00 }, /* -12.5db */ + { 0X10, 0X13, 0X79, 0X00 }, /* -12.0db */ + { 0X11, 0X07, 0X54, 0X00 }, /* -11.5db */ + { 0X12, 0X09, 0XA3, 0X00 }, /* -11.0db */ + { 0X13, 0X1B, 0X40, 0X00 }, /* -10.5db */ + { 0X14, 0X3D, 0X13, 0X00 }, /* -10.0db */ + { 0X15, 0X70, 0X12, 0X00 }, /* -9.5db */ + { 0X16, 0XB5, 0X43, 0X00 }, /* -9.0db */ + { 0X18, 0X0D, 0XB8, 0X00 }, /* -8.5db */ + { 0X19, 0X7A, 0X96, 0X00 }, /* -8.0db */ + { 0X1A, 0XFD, 0X13, 0X00 }, /* -7.5db */ + { 0X1C, 0X96, 0X76, 0X00 }, /* -7.0db */ + { 0X1E, 0X48, 0X1C, 0X00 }, /* -6.5db */ + { 0X20, 0X13, 0X73, 0X00 }, /* -6.0db */ + { 0X21, 0XFA, 0X02, 0X00 }, /* -5.5db */ + { 0X23, 0XFD, 0X66, 0X00 }, /* -5.0db */ + { 0X26, 0X1F, 0X54, 0X00 }, /* -4.5db */ + { 0X28, 0X61, 0X9A, 0X00 }, /* -4.0db */ + { 0X2A, 0XC6, 0X25, 0X00 }, /* -3.5db */ + { 0X2D, 0X4E, 0XFB, 0X00 }, /* -3.0db */ + { 0X2F, 0XFE, 0X44, 0X00 }, /* -2.5db */ + { 0X32, 0XD6, 0X46, 0X00 }, /* -2.0db */ + { 0X35, 0XD9, 0X6B, 0X00 }, /* -1.5db */ + { 0X39, 0X0A, 0X41, 0X00 }, /* -1.0db */ + { 0X3C, 0X6B, 0X7E, 0X00 }, /* -0.5db */ + { 0X40, 0X00, 0X00, 0X00 }, /* 0.0db */ + { 0X43, 0XCA, 0XD0, 0X00 }, /* 0.5db */ + { 0X47, 0XCF, 0X26, 0X00 }, /* 1.0db */ + { 0X4C, 0X10, 0X6B, 0X00 }, /* 1.5db */ + { 0X50, 0X92, 0X3B, 0X00 }, /* 2.0db */ + { 0X55, 0X58, 0X6A, 0X00 }, /* 2.5db */ + { 0X5A, 0X67, 0X03, 0X00 }, /* 3.0db */ + { 0X5F, 0XC2, 0X53, 0X00 }, /* 3.5db */ + { 0X65, 0X6E, 0XE3, 0X00 }, /* 4.0db */ + { 0X6B, 0X71, 0X86, 0X00 }, /* 4.5db */ + { 0X71, 0XCF, 0X54, 0X00 }, /* 5.0db */ + { 0X78, 0X8D, 0XB4, 0X00 }, /* 5.5db */ + { 0X7F, 0XB2, 0X61, 0X00 }, /* 6.0db */ +}; +#endif diff --git a/include/sound/tas5086.h b/include/sound/tas5086.h new file mode 100644 index 000000000..a0a1c380f --- /dev/null +++ b/include/sound/tas5086.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _SND_SOC_CODEC_TAS5086_H_ +#define _SND_SOC_CODEC_TAS5086_H_ + +#define TAS5086_CLK_IDX_MCLK 0 +#define TAS5086_CLK_IDX_SCLK 1 + +#endif /* _SND_SOC_CODEC_TAS5086_H_ */ diff --git a/include/sound/tas5825-tlv.h b/include/sound/tas5825-tlv.h new file mode 100644 index 000000000..95f2d3fad --- /dev/null +++ b/include/sound/tas5825-tlv.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// ALSA SoC Texas Instruments TAS5825 Audio Smart Amplifier +// +// Copyright (C) 2025 Texas Instruments Incorporated +// https://www.ti.com +// +// The TAS5825 hda driver implements for one or two TAS5825 chips. +// +// Author: Baojun Xu +// + +#ifndef __TAS5825_TLV_H__ +#define __TAS5825_TLV_H__ + +#define TAS5825_DVC_LEVEL TASDEVICE_REG(0x0, 0x0, 0x4c) +#define TAS5825_AMP_LEVEL TASDEVICE_REG(0x0, 0x0, 0x54) + +static const __maybe_unused DECLARE_TLV_DB_SCALE( + tas5825_dvc_tlv, -10300, 50, 0); +static const __maybe_unused DECLARE_TLV_DB_SCALE( + tas5825_amp_tlv, -1550, 50, 0); + +#endif diff --git a/include/sound/tea6330t.h b/include/sound/tea6330t.h new file mode 100644 index 000000000..3a34033d2 --- /dev/null +++ b/include/sound/tea6330t.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_TEA6330T_H +#define __SOUND_TEA6330T_H + +/* + * Routines for control of TEA6330T circuit. + * Sound fader control circuit for car radios. + */ + +#include /* generic i2c support */ + +int snd_tea6330t_detect(struct snd_i2c_bus *bus, int equalizer); +int snd_tea6330t_update_mixer(struct snd_card *card, struct snd_i2c_bus *bus, + int equalizer, int fader); +int snd_tea6330t_restore_mixer(struct snd_i2c_bus *bus); + +#endif /* __SOUND_TEA6330T_H */ diff --git a/include/sound/timer.h b/include/sound/timer.h new file mode 100644 index 000000000..e549eab71 --- /dev/null +++ b/include/sound/timer.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_TIMER_H +#define __SOUND_TIMER_H + +/* + * Timer abstract layer + * Copyright (c) by Jaroslav Kysela , + * Abramo Bagnara + */ + +#include +#include + +#define snd_timer_chip(timer) ((timer)->private_data) + +#define SNDRV_TIMER_DEVICES 16 + +#define SNDRV_TIMER_DEV_FLG_PCM 0x10000000 + +#define SNDRV_TIMER_HW_AUTO 0x00000001 /* auto trigger is supported */ +#define SNDRV_TIMER_HW_STOP 0x00000002 /* call stop before start */ +#define SNDRV_TIMER_HW_SLAVE 0x00000004 /* only slave timer (variable resolution) */ +#define SNDRV_TIMER_HW_FIRST 0x00000008 /* first tick can be incomplete */ +#define SNDRV_TIMER_HW_WORK 0x00000010 /* timer is called from work */ + +#define SNDRV_TIMER_IFLG_SLAVE 0x00000001 +#define SNDRV_TIMER_IFLG_RUNNING 0x00000002 +#define SNDRV_TIMER_IFLG_START 0x00000004 +#define SNDRV_TIMER_IFLG_AUTO 0x00000008 /* auto restart */ +#define SNDRV_TIMER_IFLG_FAST 0x00000010 /* fast callback (do not use work) */ +#define SNDRV_TIMER_IFLG_CALLBACK 0x00000020 /* timer callback is active */ +#define SNDRV_TIMER_IFLG_EXCLUSIVE 0x00000040 /* exclusive owner - no more instances */ +#define SNDRV_TIMER_IFLG_EARLY_EVENT 0x00000080 /* write early event to the poll queue */ + +#define SNDRV_TIMER_FLG_CHANGE 0x00000001 +#define SNDRV_TIMER_FLG_RESCHED 0x00000002 /* need reschedule */ + +struct snd_timer; + +struct snd_timer_hardware { + /* -- must be filled with low-level driver */ + unsigned int flags; /* various flags */ + unsigned long resolution; /* average timer resolution for one tick in nsec */ + unsigned long resolution_min; /* minimal resolution */ + unsigned long resolution_max; /* maximal resolution */ + unsigned long ticks; /* max timer ticks per interrupt */ + /* -- low-level functions -- */ + int (*open) (struct snd_timer * timer); + int (*close) (struct snd_timer * timer); + unsigned long (*c_resolution) (struct snd_timer * timer); + int (*start) (struct snd_timer * timer); + int (*stop) (struct snd_timer * timer); + int (*set_period) (struct snd_timer * timer, unsigned long period_num, unsigned long period_den); + int (*precise_resolution) (struct snd_timer * timer, unsigned long *num, unsigned long *den); +}; + +struct snd_timer { + int tmr_class; + struct snd_card *card; + struct module *module; + int tmr_device; + int tmr_subdevice; + char id[64]; + char name[80]; + unsigned int flags; + int running; /* running instances */ + unsigned long sticks; /* schedule ticks */ + void *private_data; + void (*private_free) (struct snd_timer *timer); + struct snd_timer_hardware hw; + spinlock_t lock; + struct list_head device_list; + struct list_head open_list_head; + struct list_head active_list_head; + struct list_head ack_list_head; + struct list_head sack_list_head; /* slow ack list head */ + struct work_struct task_work; + struct kref kref; + int max_instances; /* upper limit of timer instances */ + int num_instances; /* current number of timer instances */ +}; + +struct snd_timer_instance { + struct snd_timer *timer; + char *owner; + unsigned int flags; + void *private_data; + void (*private_free) (struct snd_timer_instance *ti); + void (*callback) (struct snd_timer_instance *timeri, + unsigned long ticks, unsigned long resolution); + void (*ccallback) (struct snd_timer_instance * timeri, + int event, + struct timespec64 * tstamp, + unsigned long resolution); + void (*disconnect)(struct snd_timer_instance *timeri); + void *callback_data; + unsigned long ticks; /* auto-load ticks when expired */ + unsigned long cticks; /* current ticks */ + unsigned long pticks; /* accumulated ticks for callback */ + unsigned long resolution; /* current resolution for work */ + unsigned long lost; /* lost ticks */ + int slave_class; + unsigned int slave_id; + struct list_head open_list; + struct list_head active_list; + struct list_head master_list; + struct list_head ack_list; + struct list_head slave_list_head; + struct list_head slave_active_head; + struct snd_timer_instance *master; +}; + +/* + * Registering + */ + +int snd_timer_new(struct snd_card *card, char *id, struct snd_timer_id *tid, struct snd_timer **rtimer); +void snd_timer_notify(struct snd_timer *timer, int event, struct timespec64 *tstamp); +int snd_timer_global_new(char *id, int device, struct snd_timer **rtimer); +int snd_timer_global_free(struct snd_timer *timer); +int snd_timer_global_register(struct snd_timer *timer); + +struct snd_timer_instance *snd_timer_instance_new(const char *owner); +void snd_timer_instance_free(struct snd_timer_instance *timeri); +int snd_timer_open(struct snd_timer_instance *timeri, struct snd_timer_id *tid, unsigned int slave_id); +void snd_timer_close(struct snd_timer_instance *timeri); +unsigned long snd_timer_resolution(struct snd_timer_instance *timeri); +int snd_timer_start(struct snd_timer_instance *timeri, unsigned int ticks); +int snd_timer_stop(struct snd_timer_instance *timeri); +int snd_timer_continue(struct snd_timer_instance *timeri); +int snd_timer_pause(struct snd_timer_instance *timeri); + +void snd_timer_interrupt(struct snd_timer *timer, unsigned long ticks_left); + +struct snd_timer *snd_timeri_timer_get(struct snd_timer_instance *timeri); +void snd_timeri_timer_put(struct snd_timer *timer); + +DEFINE_FREE(snd_timeri_timer, struct snd_timer *, if (_T) snd_timeri_timer_put(_T)) + +#endif /* __SOUND_TIMER_H */ diff --git a/include/sound/tlv.h b/include/sound/tlv.h new file mode 100644 index 000000000..5cff33a2d --- /dev/null +++ b/include/sound/tlv.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_TLV_H +#define __SOUND_TLV_H + +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 2006 by Jaroslav Kysela + */ + +#include + +/* For historical reasons, these macros are aliases to the ones in UAPI. */ +#define TLV_ITEM SNDRV_CTL_TLVD_ITEM +#define TLV_LENGTH SNDRV_CTL_TLVD_LENGTH + +#define TLV_CONTAINER_ITEM SNDRV_CTL_TLVD_CONTAINER_ITEM +#define DECLARE_TLV_CONTAINER SNDRV_CTL_TLVD_DECLARE_CONTAINER + +#define TLV_DB_SCALE_MASK SNDRV_CTL_TLVD_DB_SCALE_MASK +#define TLV_DB_SCALE_MUTE SNDRV_CTL_TLVD_DB_SCALE_MUTE +#define TLV_DB_SCALE_ITEM SNDRV_CTL_TLVD_DB_SCALE_ITEM +#define DECLARE_TLV_DB_SCALE SNDRV_CTL_TLVD_DECLARE_DB_SCALE + +#define TLV_DB_MINMAX_ITEM SNDRV_CTL_TLVD_DB_MINMAX_ITEM +#define TLV_DB_MINMAX_MUTE_ITEM SNDRV_CTL_TLVD_DB_MINMAX_MUTE_ITEM +#define DECLARE_TLV_DB_MINMAX SNDRV_CTL_TLVD_DECLARE_DB_MINMAX +#define DECLARE_TLV_DB_MINMAX_MUTE SNDRV_CTL_TLVD_DECLARE_DB_MINMAX_MUTE + +#define TLV_DB_LINEAR_ITEM SNDRV_CTL_TLVD_DB_LINEAR_ITEM +#define DECLARE_TLV_DB_LINEAR SNDRV_CTL_TLVD_DECLARE_DB_LINEAR + +#define TLV_DB_RANGE_ITEM SNDRV_CTL_TLVD_DB_RANGE_ITEM +#define DECLARE_TLV_DB_RANGE SNDRV_CTL_TLVD_DECLARE_DB_RANGE + +#define TLV_DB_GAIN_MUTE SNDRV_CTL_TLVD_DB_GAIN_MUTE + +/* + * The below assumes that each item TLV is 4 words like DB_SCALE or LINEAR. + * This is an old fasion and obsoleted by commit bf1d1c9b6179("ALSA: tlv: add + * DECLARE_TLV_DB_RANGE()"). + */ +#define TLV_DB_RANGE_HEAD(num) \ + SNDRV_CTL_TLVT_DB_RANGE, 6 * (num) * sizeof(unsigned int) + +#endif /* __SOUND_TLV_H */ diff --git a/include/sound/ump.h b/include/sound/ump.h new file mode 100644 index 000000000..73f97f88e --- /dev/null +++ b/include/sound/ump.h @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal MIDI Packet (UMP) Support + */ +#ifndef __SOUND_UMP_H +#define __SOUND_UMP_H + +#include + +struct snd_ump_endpoint; +struct snd_ump_block; +struct snd_ump_ops; +struct ump_cvt_to_ump; +struct snd_seq_ump_ops; + +struct snd_ump_group { + int group; /* group index (0-based) */ + unsigned int dir_bits; /* directions */ + bool active; /* activeness */ + bool valid; /* valid group (referred by blocks) */ + bool is_midi1; /* belongs to a MIDI1 FB */ + char name[64]; /* group name */ +}; + +struct snd_ump_endpoint { + struct snd_rawmidi core; /* raw UMP access */ + + struct snd_ump_endpoint_info info; + + const struct snd_ump_ops *ops; /* UMP ops set by the driver */ + struct snd_rawmidi_substream *substreams[2]; /* opened substreams */ + + void *private_data; + void (*private_free)(struct snd_ump_endpoint *ump); + + /* UMP Stream message processing */ + u32 stream_wait_for; /* expected stream message status */ + bool stream_finished; /* set when message has been processed */ + bool parsed; /* UMP / FB parse finished? */ + bool no_process_stream; /* suppress UMP stream messages handling */ + wait_queue_head_t stream_wait; + struct snd_rawmidi_file stream_rfile; + + struct list_head block_list; /* list of snd_ump_block objects */ + + /* intermediate buffer for UMP input */ + u32 input_buf[4]; + int input_buf_head; + int input_pending; + + struct mutex open_mutex; + + struct snd_ump_group groups[SNDRV_UMP_MAX_GROUPS]; /* table of groups */ + +#if IS_ENABLED(CONFIG_SND_UMP_LEGACY_RAWMIDI) + spinlock_t legacy_locks[2]; + struct snd_rawmidi *legacy_rmidi; + struct snd_rawmidi_substream *legacy_substreams[2][SNDRV_UMP_MAX_GROUPS]; + unsigned char legacy_mapping[SNDRV_UMP_MAX_GROUPS]; + + /* for legacy output; need to open the actual substream unlike input */ + int legacy_out_opens; + struct snd_rawmidi_file legacy_out_rfile; + struct ump_cvt_to_ump *out_cvts; +#endif + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) + struct snd_seq_device *seq_dev; + const struct snd_seq_ump_ops *seq_ops; + void *seq_client; +#endif +}; + +/* ops filled by UMP drivers */ +struct snd_ump_ops { + int (*open)(struct snd_ump_endpoint *ump, int dir); + void (*close)(struct snd_ump_endpoint *ump, int dir); + void (*trigger)(struct snd_ump_endpoint *ump, int dir, int up); + void (*drain)(struct snd_ump_endpoint *ump, int dir); +}; + +/* ops filled by sequencer binding */ +struct snd_seq_ump_ops { + void (*input_receive)(struct snd_ump_endpoint *ump, + const u32 *data, int words); + int (*notify_ep_change)(struct snd_ump_endpoint *ump); + int (*notify_fb_change)(struct snd_ump_endpoint *ump, + struct snd_ump_block *fb); + int (*switch_protocol)(struct snd_ump_endpoint *ump); +}; + +struct snd_ump_block { + struct snd_ump_block_info info; + struct snd_ump_endpoint *ump; + + void *private_data; + void (*private_free)(struct snd_ump_block *blk); + + struct list_head list; +}; + +#define rawmidi_to_ump(rmidi) container_of(rmidi, struct snd_ump_endpoint, core) + +int snd_ump_endpoint_new(struct snd_card *card, char *id, int device, + int output, int input, + struct snd_ump_endpoint **ump_ret); +int snd_ump_parse_endpoint(struct snd_ump_endpoint *ump); +int snd_ump_block_new(struct snd_ump_endpoint *ump, unsigned int blk, + unsigned int direction, unsigned int first_group, + unsigned int num_groups, struct snd_ump_block **blk_ret); +int snd_ump_receive(struct snd_ump_endpoint *ump, const u32 *buffer, int count); +int snd_ump_transmit(struct snd_ump_endpoint *ump, u32 *buffer, int count); + +#if IS_ENABLED(CONFIG_SND_UMP_LEGACY_RAWMIDI) +int snd_ump_attach_legacy_rawmidi(struct snd_ump_endpoint *ump, + char *id, int device); +#else +static inline int snd_ump_attach_legacy_rawmidi(struct snd_ump_endpoint *ump, + char *id, int device) +{ + return 0; +} +#endif + +int snd_ump_receive_ump_val(struct snd_ump_endpoint *ump, u32 val); +int snd_ump_switch_protocol(struct snd_ump_endpoint *ump, unsigned int protocol); +void snd_ump_update_group_attrs(struct snd_ump_endpoint *ump); + +/* + * Some definitions for UMP + */ + +/* MIDI 2.0 Message Type */ +enum { + UMP_MSG_TYPE_UTILITY = 0x00, + UMP_MSG_TYPE_SYSTEM = 0x01, + UMP_MSG_TYPE_MIDI1_CHANNEL_VOICE = 0x02, + UMP_MSG_TYPE_DATA = 0x03, + UMP_MSG_TYPE_MIDI2_CHANNEL_VOICE = 0x04, + UMP_MSG_TYPE_EXTENDED_DATA = 0x05, + UMP_MSG_TYPE_FLEX_DATA = 0x0d, + UMP_MSG_TYPE_STREAM = 0x0f, +}; + +/* MIDI 2.0 SysEx / Data Status; same values for both 7-bit and 8-bit SysEx */ +enum { + UMP_SYSEX_STATUS_SINGLE = 0, + UMP_SYSEX_STATUS_START = 1, + UMP_SYSEX_STATUS_CONTINUE = 2, + UMP_SYSEX_STATUS_END = 3, +}; + +/* UMP Utility Type Status (type 0x0) */ +enum { + UMP_UTILITY_MSG_STATUS_NOOP = 0x00, + UMP_UTILITY_MSG_STATUS_JR_CLOCK = 0x01, + UMP_UTILITY_MSG_STATUS_JR_TSTAMP = 0x02, + UMP_UTILITY_MSG_STATUS_DCTPQ = 0x03, + UMP_UTILITY_MSG_STATUS_DC = 0x04, +}; + +/* UMP Stream Message Status (type 0xf) */ +enum { + UMP_STREAM_MSG_STATUS_EP_DISCOVERY = 0x00, + UMP_STREAM_MSG_STATUS_EP_INFO = 0x01, + UMP_STREAM_MSG_STATUS_DEVICE_INFO = 0x02, + UMP_STREAM_MSG_STATUS_EP_NAME = 0x03, + UMP_STREAM_MSG_STATUS_PRODUCT_ID = 0x04, + UMP_STREAM_MSG_STATUS_STREAM_CFG_REQUEST = 0x05, + UMP_STREAM_MSG_STATUS_STREAM_CFG = 0x06, + UMP_STREAM_MSG_STATUS_FB_DISCOVERY = 0x10, + UMP_STREAM_MSG_STATUS_FB_INFO = 0x11, + UMP_STREAM_MSG_STATUS_FB_NAME = 0x12, + UMP_STREAM_MSG_STATUS_START_CLIP = 0x20, + UMP_STREAM_MSG_STATUS_END_CLIP = 0x21, +}; + +/* UMP Endpoint Discovery filter bitmap */ +enum { + UMP_STREAM_MSG_REQUEST_EP_INFO = (1U << 0), + UMP_STREAM_MSG_REQUEST_DEVICE_INFO = (1U << 1), + UMP_STREAM_MSG_REQUEST_EP_NAME = (1U << 2), + UMP_STREAM_MSG_REQUEST_PRODUCT_ID = (1U << 3), + UMP_STREAM_MSG_REQUEST_STREAM_CFG = (1U << 4), +}; + +/* UMP Function Block Discovery filter bitmap */ +enum { + UMP_STREAM_MSG_REQUEST_FB_INFO = (1U << 0), + UMP_STREAM_MSG_REQUEST_FB_NAME = (1U << 1), +}; + +/* UMP Endpoint Info capability bits (used for protocol request/notify, too) */ +enum { + UMP_STREAM_MSG_EP_INFO_CAP_TXJR = (1U << 0), /* Sending JRTS */ + UMP_STREAM_MSG_EP_INFO_CAP_RXJR = (1U << 1), /* Receiving JRTS */ + UMP_STREAM_MSG_EP_INFO_CAP_MIDI1 = (1U << 8), /* MIDI 1.0 */ + UMP_STREAM_MSG_EP_INFO_CAP_MIDI2 = (1U << 9), /* MIDI 2.0 */ +}; + +/* UMP EP / FB name string format; same as SysEx string handling */ +enum { + UMP_STREAM_MSG_FORMAT_SINGLE = 0, + UMP_STREAM_MSG_FORMAT_START = 1, + UMP_STREAM_MSG_FORMAT_CONTINUE = 2, + UMP_STREAM_MSG_FORMAT_END = 3, +}; + +/* + * Helpers for retrieving / filling bits from UMP + */ +/* get the message type (4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_type(u32 data) +{ + return data >> 28; +} + +/* get the group number (0-based, 4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_group(u32 data) +{ + return (data >> 24) & 0x0f; +} + +/* get the MIDI status code (4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_status_code(u32 data) +{ + return (data >> 20) & 0x0f; +} + +/* get the MIDI channel number (0-based, 4bit) from a UMP packet (header) */ +static inline unsigned char ump_message_channel(u32 data) +{ + return (data >> 16) & 0x0f; +} + +/* get the MIDI status + channel combo byte (8bit) from a UMP packet (header) */ +static inline unsigned char ump_message_status_channel(u32 data) +{ + return (data >> 16) & 0xff; +} + +/* compose a UMP packet (header) from type, group and status values */ +static inline u32 ump_compose(unsigned char type, unsigned char group, + unsigned char status, unsigned char channel) +{ + return ((u32)type << 28) | ((u32)group << 24) | ((u32)status << 20) | + ((u32)channel << 16); +} + +/* get SysEx message status (for both 7 and 8bits) from a UMP packet (header) */ +static inline unsigned char ump_sysex_message_status(u32 data) +{ + return (data >> 20) & 0xf; +} + +/* get SysEx message length (for both 7 and 8bits) from a UMP packet (header) */ +static inline unsigned char ump_sysex_message_length(u32 data) +{ + return (data >> 16) & 0xf; +} + +/* For Stream Messages */ +static inline unsigned char ump_stream_message_format(u32 data) +{ + return (data >> 26) & 0x03; +} + +static inline unsigned int ump_stream_message_status(u32 data) +{ + return (data >> 16) & 0x3ff; +} + +static inline u32 ump_stream_compose(unsigned char status, unsigned short form) +{ + return (UMP_MSG_TYPE_STREAM << 28) | ((u32)form << 26) | + ((u32)status << 16); +} + +#define ump_is_groupless_msg(type) \ + ((type) == UMP_MSG_TYPE_UTILITY || (type) == UMP_MSG_TYPE_STREAM) + +#endif /* __SOUND_UMP_H */ diff --git a/include/sound/ump_convert.h b/include/sound/ump_convert.h new file mode 100644 index 000000000..682499b87 --- /dev/null +++ b/include/sound/ump_convert.h @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#ifndef __SOUND_UMP_CONVERT_H +#define __SOUND_UMP_CONVERT_H + +#include + +/* context for converting from legacy control messages to UMP packet */ +struct ump_cvt_to_ump_bank { + bool rpn_set; + bool nrpn_set; + bool bank_set; + unsigned char cc_rpn_msb, cc_rpn_lsb; + unsigned char cc_nrpn_msb, cc_nrpn_lsb; + unsigned char cc_data_msb, cc_data_lsb; + unsigned char cc_bank_msb, cc_bank_lsb; + bool cc_data_msb_set, cc_data_lsb_set; +}; + +/* context for converting from MIDI1 byte stream to UMP packet */ +struct ump_cvt_to_ump { + /* MIDI1 intermediate buffer */ + unsigned char buf[6]; /* up to 6 bytes for SysEx */ + int len; + int cmd_bytes; + + /* UMP output packet */ + u32 ump[4]; + int ump_bytes; + + /* various status */ + unsigned int in_sysex; + struct ump_cvt_to_ump_bank bank[16]; /* per channel */ +}; + +int snd_ump_convert_from_ump(const u32 *data, unsigned char *dst, + unsigned char *group_ret); +void snd_ump_convert_to_ump(struct ump_cvt_to_ump *cvt, unsigned char group, + unsigned int protocol, unsigned char c); + +/* reset the converter context, called at each open to ump */ +static inline void snd_ump_convert_reset(struct ump_cvt_to_ump *ctx) +{ + memset(ctx, 0, sizeof(*ctx)); + +} + +#endif /* __SOUND_UMP_CONVERT_H */ diff --git a/include/sound/ump_msg.h b/include/sound/ump_msg.h new file mode 100644 index 000000000..9556b4755 --- /dev/null +++ b/include/sound/ump_msg.h @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Universal MIDI Packet (UMP): Message Definitions + */ +#ifndef __SOUND_UMP_MSG_H +#define __SOUND_UMP_MSG_H + +/* MIDI 1.0 / 2.0 Status Code (4bit) */ +enum { + UMP_MSG_STATUS_PER_NOTE_RCC = 0x0, + UMP_MSG_STATUS_PER_NOTE_ACC = 0x1, + UMP_MSG_STATUS_RPN = 0x2, + UMP_MSG_STATUS_NRPN = 0x3, + UMP_MSG_STATUS_RELATIVE_RPN = 0x4, + UMP_MSG_STATUS_RELATIVE_NRPN = 0x5, + UMP_MSG_STATUS_PER_NOTE_PITCH_BEND = 0x6, + UMP_MSG_STATUS_NOTE_OFF = 0x8, + UMP_MSG_STATUS_NOTE_ON = 0x9, + UMP_MSG_STATUS_POLY_PRESSURE = 0xa, + UMP_MSG_STATUS_CC = 0xb, + UMP_MSG_STATUS_PROGRAM = 0xc, + UMP_MSG_STATUS_CHANNEL_PRESSURE = 0xd, + UMP_MSG_STATUS_PITCH_BEND = 0xe, + UMP_MSG_STATUS_PER_NOTE_MGMT = 0xf, +}; + +/* MIDI 1.0 Channel Control (7bit) */ +enum { + UMP_CC_BANK_SELECT = 0, + UMP_CC_MODULATION = 1, + UMP_CC_BREATH = 2, + UMP_CC_FOOT = 4, + UMP_CC_PORTAMENTO_TIME = 5, + UMP_CC_DATA = 6, + UMP_CC_VOLUME = 7, + UMP_CC_BALANCE = 8, + UMP_CC_PAN = 10, + UMP_CC_EXPRESSION = 11, + UMP_CC_EFFECT_CONTROL_1 = 12, + UMP_CC_EFFECT_CONTROL_2 = 13, + UMP_CC_GP_1 = 16, + UMP_CC_GP_2 = 17, + UMP_CC_GP_3 = 18, + UMP_CC_GP_4 = 19, + UMP_CC_BANK_SELECT_LSB = 32, + UMP_CC_MODULATION_LSB = 33, + UMP_CC_BREATH_LSB = 34, + UMP_CC_FOOT_LSB = 36, + UMP_CC_PORTAMENTO_TIME_LSB = 37, + UMP_CC_DATA_LSB = 38, + UMP_CC_VOLUME_LSB = 39, + UMP_CC_BALANCE_LSB = 40, + UMP_CC_PAN_LSB = 42, + UMP_CC_EXPRESSION_LSB = 43, + UMP_CC_EFFECT1_LSB = 44, + UMP_CC_EFFECT2_LSB = 45, + UMP_CC_GP_1_LSB = 48, + UMP_CC_GP_2_LSB = 49, + UMP_CC_GP_3_LSB = 50, + UMP_CC_GP_4_LSB = 51, + UMP_CC_SUSTAIN = 64, + UMP_CC_PORTAMENTO_SWITCH = 65, + UMP_CC_SOSTENUTO = 66, + UMP_CC_SOFT_PEDAL = 67, + UMP_CC_LEGATO = 68, + UMP_CC_HOLD_2 = 69, + UMP_CC_SOUND_CONTROLLER_1 = 70, + UMP_CC_SOUND_CONTROLLER_2 = 71, + UMP_CC_SOUND_CONTROLLER_3 = 72, + UMP_CC_SOUND_CONTROLLER_4 = 73, + UMP_CC_SOUND_CONTROLLER_5 = 74, + UMP_CC_SOUND_CONTROLLER_6 = 75, + UMP_CC_SOUND_CONTROLLER_7 = 76, + UMP_CC_SOUND_CONTROLLER_8 = 77, + UMP_CC_SOUND_CONTROLLER_9 = 78, + UMP_CC_SOUND_CONTROLLER_10 = 79, + UMP_CC_GP_5 = 80, + UMP_CC_GP_6 = 81, + UMP_CC_GP_7 = 82, + UMP_CC_GP_8 = 83, + UMP_CC_PORTAMENTO_CONTROL = 84, + UMP_CC_EFFECT_1 = 91, + UMP_CC_EFFECT_2 = 92, + UMP_CC_EFFECT_3 = 93, + UMP_CC_EFFECT_4 = 94, + UMP_CC_EFFECT_5 = 95, + UMP_CC_DATA_INC = 96, + UMP_CC_DATA_DEC = 97, + UMP_CC_NRPN_LSB = 98, + UMP_CC_NRPN_MSB = 99, + UMP_CC_RPN_LSB = 100, + UMP_CC_RPN_MSB = 101, + UMP_CC_ALL_SOUND_OFF = 120, + UMP_CC_RESET_ALL = 121, + UMP_CC_LOCAL_CONTROL = 122, + UMP_CC_ALL_NOTES_OFF = 123, + UMP_CC_OMNI_OFF = 124, + UMP_CC_OMNI_ON = 125, + UMP_CC_POLY_OFF = 126, + UMP_CC_POLY_ON = 127, +}; + +/* MIDI 1.0 / 2.0 System Messages (0xfx) */ +enum { + UMP_SYSTEM_STATUS_MIDI_TIME_CODE = 0xf1, + UMP_SYSTEM_STATUS_SONG_POSITION = 0xf2, + UMP_SYSTEM_STATUS_SONG_SELECT = 0xf3, + UMP_SYSTEM_STATUS_TUNE_REQUEST = 0xf6, + UMP_SYSTEM_STATUS_TIMING_CLOCK = 0xf8, + UMP_SYSTEM_STATUS_START = 0xfa, + UMP_SYSTEM_STATUS_CONTINUE = 0xfb, + UMP_SYSTEM_STATUS_STOP = 0xfc, + UMP_SYSTEM_STATUS_ACTIVE_SENSING = 0xfe, + UMP_SYSTEM_STATUS_RESET = 0xff, +}; + +/* MIDI 1.0 Realtime and SysEx status messages (0xfx) */ +enum { + UMP_MIDI1_MSG_REALTIME = 0xf0, /* mask */ + UMP_MIDI1_MSG_SYSEX_START = 0xf0, + UMP_MIDI1_MSG_SYSEX_END = 0xf7, +}; + +/* + * UMP Message Definitions + */ + +/* MIDI 1.0 Note Off / Note On (32bit) */ +struct snd_ump_midi1_msg_note { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 velocity:8; +#else + u32 velocity:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Poly Pressure (32bit) */ +struct snd_ump_midi1_msg_paf { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 data:8; +#else + u32 data:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Control Change (32bit) */ +struct snd_ump_midi1_msg_cc { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 index:8; + u32 data:8; +#else + u32 data:8; + u32 index:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Program Change (32bit) */ +struct snd_ump_midi1_msg_program { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 program:8; + u32 reserved:8; +#else + u32 reserved:8; + u32 program:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Channel Pressure (32bit) */ +struct snd_ump_midi1_msg_caf { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 data:8; + u32 reserved:8; +#else + u32 reserved:8; + u32 data:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 Pitch Bend (32bit) */ +struct snd_ump_midi1_msg_pitchbend { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 data_lsb:8; + u32 data_msb:8; +#else + u32 data_msb:8; + u32 data_lsb:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* System Common and Real Time messages (32bit); no channel field */ +struct snd_ump_system_msg { +#ifdef __BIG_ENDIAN_BITFIELD + u32 type:4; + u32 group:4; + u32 status:8; + u32 parm1:8; + u32 parm2:8; +#else + u32 parm2:8; + u32 parm1:8; + u32 status:8; + u32 group:4; + u32 type:4; +#endif +} __packed; + +/* MIDI 1.0 UMP CVM (32bit) */ +union snd_ump_midi1_msg { + struct snd_ump_midi1_msg_note note; + struct snd_ump_midi1_msg_paf paf; + struct snd_ump_midi1_msg_cc cc; + struct snd_ump_midi1_msg_program pg; + struct snd_ump_midi1_msg_caf caf; + struct snd_ump_midi1_msg_pitchbend pb; + struct snd_ump_system_msg system; + u32 raw; +}; + +/* MIDI 2.0 Note Off / Note On (64bit) */ +struct snd_ump_midi2_msg_note { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 attribute_type:8; + /* 1 */ + u32 velocity:16; + u32 attribute_data:16; +#else + /* 0 */ + u32 attribute_type:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 attribute_data:16; + u32 velocity:16; +#endif +} __packed; + +/* MIDI 2.0 Poly Pressure (64bit) */ +struct snd_ump_midi2_msg_paf { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 reserved:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Per-Note Controller (64bit) */ +struct snd_ump_midi2_msg_pernote_cc { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 index:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 index:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Per-Note Management (64bit) */ +struct snd_ump_midi2_msg_pernote_mgmt { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 flags:8; + /* 1 */ + u32 reserved; +#else + /* 0 */ + u32 flags:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 reserved; +#endif +} __packed; + +/* MIDI 2.0 Control Change (64bit) */ +struct snd_ump_midi2_msg_cc { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 index:8; + u32 reserved:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:8; + u32 index:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Registered Controller (RPN) / Assignable Controller (NRPN) (64bit) */ +struct snd_ump_midi2_msg_rpn { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 bank:8; + u32 index:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 index:8; + u32 bank:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Program Change (64bit) */ +struct snd_ump_midi2_msg_program { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 reserved:15; + u32 bank_valid:1; + /* 1 */ + u32 program:8; + u32 reserved2:8; + u32 bank_msb:8; + u32 bank_lsb:8; +#else + /* 0 */ + u32 bank_valid:1; + u32 reserved:15; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 bank_lsb:8; + u32 bank_msb:8; + u32 reserved2:8; + u32 program:8; +#endif +} __packed; + +/* MIDI 2.0 Channel Pressure (64bit) */ +struct snd_ump_midi2_msg_caf { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 reserved:16; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:16; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Pitch Bend (64bit) */ +struct snd_ump_midi2_msg_pitchbend { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 reserved:16; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:16; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 Per-Note Pitch Bend (64bit) */ +struct snd_ump_midi2_msg_pernote_pitchbend { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 group:4; + u32 status:4; + u32 channel:4; + u32 note:8; + u32 reserved:8; + /* 1 */ + u32 data; +#else + /* 0 */ + u32 reserved:8; + u32 note:8; + u32 channel:4; + u32 status:4; + u32 group:4; + u32 type:4; + /* 1 */ + u32 data; +#endif +} __packed; + +/* MIDI 2.0 UMP CVM (64bit) */ +union snd_ump_midi2_msg { + struct snd_ump_midi2_msg_note note; + struct snd_ump_midi2_msg_paf paf; + struct snd_ump_midi2_msg_pernote_cc pernote_cc; + struct snd_ump_midi2_msg_pernote_mgmt pernote_mgmt; + struct snd_ump_midi2_msg_cc cc; + struct snd_ump_midi2_msg_rpn rpn; + struct snd_ump_midi2_msg_program pg; + struct snd_ump_midi2_msg_caf caf; + struct snd_ump_midi2_msg_pitchbend pb; + struct snd_ump_midi2_msg_pernote_pitchbend pernote_pb; + u32 raw[2]; +}; + +/* UMP Stream Message: Endpoint Discovery (128bit) */ +struct snd_ump_stream_msg_ep_discovery { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 ump_version_major:8; + u32 ump_version_minor:8; + /* 1 */ + u32 reserved:24; + u32 filter_bitmap:8; + /* 2-3 */ + u32 reserved2[2]; +#else + /* 0 */ + u32 ump_version_minor:8; + u32 ump_version_major:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 filter_bitmap:8; + u32 reserved:24; + /* 2-3 */ + u32 reserved2[2]; +#endif +} __packed; + +/* UMP Stream Message: Endpoint Info Notification (128bit) */ +struct snd_ump_stream_msg_ep_info { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 ump_version_major:8; + u32 ump_version_minor:8; + /* 1 */ + u32 static_function_block:1; + u32 num_function_blocks:7; + u32 reserved:8; + u32 protocol:8; + u32 reserved2:6; + u32 jrts:2; + /* 2-3 */ + u32 reserved3[2]; +#else + /* 0 */ + u32 ump_version_minor:8; + u32 ump_version_major:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 jrts:2; + u32 reserved2:6; + u32 protocol:8; + u32 reserved:8; + u32 num_function_blocks:7; + u32 static_function_block:1; + /* 2-3 */ + u32 reserved3[2]; +#endif +} __packed; + +/* UMP Stream Message: Device Info Notification (128bit) */ +struct snd_ump_stream_msg_device_info { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 reserved:16; + /* 1 */ + u32 manufacture_id; + /* 2 */ + u8 family_lsb; + u8 family_msb; + u8 model_lsb; + u8 model_msb; + /* 3 */ + u32 sw_revision; +#else + /* 0 */ + u32 reserved:16; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 manufacture_id; + /* 2 */ + u8 model_msb; + u8 model_lsb; + u8 family_msb; + u8 family_lsb; + /* 3 */ + u32 sw_revision; +#endif +} __packed; + +/* UMP Stream Message: Stream Config Request / Notification (128bit) */ +struct snd_ump_stream_msg_stream_cfg { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 protocol:8; + u32 reserved:6; + u32 jrts:2; + /* 1-3 */ + u32 reserved2[3]; +#else + /* 0 */ + u32 jrts:2; + u32 reserved:6; + u32 protocol:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1-3 */ + u32 reserved2[3]; +#endif +} __packed; + +/* UMP Stream Message: Function Block Discovery (128bit) */ +struct snd_ump_stream_msg_fb_discovery { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 function_block_id:8; + u32 filter:8; + /* 1-3 */ + u32 reserved[3]; +#else + /* 0 */ + u32 filter:8; + u32 function_block_id:8; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1-3 */ + u32 reserved[3]; +#endif +} __packed; + +/* UMP Stream Message: Function Block Info Notification (128bit) */ +struct snd_ump_stream_msg_fb_info { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u32 type:4; + u32 format:2; + u32 status:10; + u32 active:1; + u32 function_block_id:7; + u32 reserved:2; + u32 ui_hint:2; + u32 midi_10:2; + u32 direction:2; + /* 1 */ + u32 first_group:8; + u32 num_groups:8; + u32 midi_ci_version:8; + u32 sysex8_streams:8; + /* 2-3 */ + u32 reserved2[2]; +#else + /* 0 */ + u32 direction:2; + u32 midi_10:2; + u32 ui_hint:2; + u32 reserved:2; + u32 function_block_id:7; + u32 active:1; + u32 status:10; + u32 format:2; + u32 type:4; + /* 1 */ + u32 sysex8_streams:8; + u32 midi_ci_version:8; + u32 num_groups:8; + u32 first_group:8; + /* 2-3 */ + u32 reserved2[2]; +#endif +} __packed; + +/* UMP Stream Message: Function Block Name Notification (128bit) */ +struct snd_ump_stream_msg_fb_name { +#ifdef __BIG_ENDIAN_BITFIELD + /* 0 */ + u16 type:4; + u16 format:2; + u16 status:10; + u8 function_block_id; + u8 name0; + /* 1-3 */ + u8 name[12]; +#else + /* 0 */ + u8 name0; + u8 function_block_id; + u16 status:10; + u16 format:2; + u16 type:4; + /* 1-3 */ + u8 name[12]; // FIXME: byte order +#endif +} __packed; + +/* MIDI 2.0 Stream Messages (128bit) */ +union snd_ump_stream_msg { + struct snd_ump_stream_msg_ep_discovery ep_discovery; + struct snd_ump_stream_msg_ep_info ep_info; + struct snd_ump_stream_msg_device_info device_info; + struct snd_ump_stream_msg_stream_cfg stream_cfg; + struct snd_ump_stream_msg_fb_discovery fb_discovery; + struct snd_ump_stream_msg_fb_info fb_info; + struct snd_ump_stream_msg_fb_name fb_name; + u32 raw[4]; +}; + +#endif /* __SOUND_UMP_MSG_H */ diff --git a/include/sound/util_mem.h b/include/sound/util_mem.h new file mode 100644 index 000000000..01310e089 --- /dev/null +++ b/include/sound/util_mem.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_UTIL_MEM_H +#define __SOUND_UTIL_MEM_H + +#include +/* + * Copyright (C) 2000 Takashi Iwai + * + * Generic memory management routines for soundcard memory allocation + */ + +/* + * memory block + */ +struct snd_util_memblk { + unsigned int size; /* size of this block */ + unsigned int offset; /* zero-offset of this block */ + struct list_head list; /* link */ +}; + +#define snd_util_memblk_argptr(blk) (void*)((char*)(blk) + sizeof(struct snd_util_memblk)) + +/* + * memory management information + */ +struct snd_util_memhdr { + unsigned int size; /* size of whole data */ + struct list_head block; /* block linked-list header */ + int nblocks; /* # of allocated blocks */ + unsigned int used; /* used memory size */ + int block_extra_size; /* extra data size of chunk */ + struct mutex block_mutex; /* lock */ +}; + +/* + * prototypes + */ +struct snd_util_memhdr *snd_util_memhdr_new(int memsize); +void snd_util_memhdr_free(struct snd_util_memhdr *hdr); +struct snd_util_memblk *snd_util_mem_alloc(struct snd_util_memhdr *hdr, int size); +int snd_util_mem_free(struct snd_util_memhdr *hdr, struct snd_util_memblk *blk); +int snd_util_mem_avail(struct snd_util_memhdr *hdr); + +/* functions without mutex */ +struct snd_util_memblk *__snd_util_mem_alloc(struct snd_util_memhdr *hdr, int size); +void __snd_util_mem_free(struct snd_util_memhdr *hdr, struct snd_util_memblk *blk); +struct snd_util_memblk *__snd_util_memblk_new(struct snd_util_memhdr *hdr, + unsigned int units, + struct list_head *prev); + +#endif /* __SOUND_UTIL_MEM_H */ diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h new file mode 100644 index 000000000..ca87fa6a8 --- /dev/null +++ b/include/sound/vx_core.h @@ -0,0 +1,535 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Driver for Digigram VX soundcards + * + * Hardware core part + * + * Copyright (c) 2002 by Takashi Iwai + */ + +#ifndef __SOUND_VX_COMMON_H +#define __SOUND_VX_COMMON_H + +#include +#include +#include + +struct firmware; +struct device; + +#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */ + +/* + */ +#define SIZE_MAX_CMD 0x10 +#define SIZE_MAX_STATUS 0x10 + +struct vx_rmh { + u16 LgCmd; /* length of the command to send (WORDs) */ + u16 LgStat; /* length of the status received (WORDs) */ + u32 Cmd[SIZE_MAX_CMD]; + u32 Stat[SIZE_MAX_STATUS]; + u16 DspStat; /* status type, RMP_SSIZE_XXX */ +}; + +typedef u64 pcx_time_t; + +#define VX_MAX_PIPES 16 +#define VX_MAX_PERIODS 32 +#define VX_MAX_CODECS 2 + +struct vx_ibl_info { + int size; /* the current IBL size (0 = query) in bytes */ + int max_size; /* max. IBL size in bytes */ + int min_size; /* min. IBL size in bytes */ + int granularity; /* granularity */ +}; + +struct vx_pipe { + int number; + unsigned int is_capture: 1; + unsigned int data_mode: 1; + unsigned int running: 1; + unsigned int prepared: 1; + int channels; + unsigned int differed_type; + pcx_time_t pcx_time; + struct snd_pcm_substream *substream; + + int hbuf_size; /* H-buffer size in bytes */ + int buffer_bytes; /* the ALSA pcm buffer size in bytes */ + int period_bytes; /* the ALSA pcm period size in bytes */ + int hw_ptr; /* the current hardware pointer in bytes */ + int position; /* the current position in frames (playback only) */ + int transferred; /* the transferred size (per period) in frames */ + int align; /* size of alignment */ + u64 cur_count; /* current sample position (for playback) */ + + unsigned int references; /* an output pipe may be used for monitoring and/or playback */ + struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/ +}; + +struct vx_core; + +struct snd_vx_ops { + /* low-level i/o */ + unsigned char (*in8)(struct vx_core *chip, int reg); + unsigned int (*in32)(struct vx_core *chip, int reg); + void (*out8)(struct vx_core *chip, int reg, unsigned char val); + void (*out32)(struct vx_core *chip, int reg, unsigned int val); + /* irq */ + int (*test_and_ack)(struct vx_core *chip); + void (*validate_irq)(struct vx_core *chip, int enable); + /* codec */ + void (*write_codec)(struct vx_core *chip, int codec, unsigned int data); + void (*akm_write)(struct vx_core *chip, int reg, unsigned int data); + void (*reset_codec)(struct vx_core *chip); + void (*change_audio_source)(struct vx_core *chip, int src); + void (*set_clock_source)(struct vx_core *chp, int src); + /* chip init */ + int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw); + void (*reset_dsp)(struct vx_core *chip); + void (*reset_board)(struct vx_core *chip, int cold_reset); + int (*add_controls)(struct vx_core *chip); + /* pcm */ + void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count); + void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count); +}; + +struct snd_vx_hardware { + const char *name; + int type; /* VX_TYPE_XXX */ + + /* hardware specs */ + unsigned int num_codecs; + unsigned int num_ins; + unsigned int num_outs; + unsigned int output_level_max; + const unsigned int *output_level_db_scale; +}; + +/* hwdep id string */ +#define SND_VX_HWDEP_ID "VX Loader" + +/* hardware type */ +enum { + /* VX222 PCI */ + VX_TYPE_BOARD, /* old VX222 PCI */ + VX_TYPE_V2, /* VX222 V2 PCI */ + VX_TYPE_MIC, /* VX222 Mic PCI */ + /* VX-pocket */ + VX_TYPE_VXPOCKET, /* VXpocket V2 */ + VX_TYPE_VXP440, /* VXpocket 440 */ + VX_TYPE_NUMS +}; + +/* chip status */ +enum { + VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */ + VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */ + VX_STAT_CHIP_INIT = (1 << 2), /* all operational */ + VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */ + VX_STAT_IS_STALE = (1 << 15) /* device is stale */ +}; + +/* min/max values for analog output for old codecs */ +#define VX_ANALOG_OUT_LEVEL_MAX 0xe3 + +struct vx_core { + /* ALSA stuff */ + struct snd_card *card; + struct snd_pcm *pcm[VX_MAX_CODECS]; + int type; /* VX_TYPE_XXX */ + + int irq; + /* ports are defined externally */ + + /* low-level functions */ + const struct snd_vx_hardware *hw; + const struct snd_vx_ops *ops; + + struct mutex lock; + + unsigned int chip_status; + unsigned int pcm_running; + + struct snd_hwdep *hwdep; + + struct vx_rmh irq_rmh; /* RMH used in interrupts */ + + unsigned int audio_info; /* see VX_AUDIO_INFO */ + unsigned int audio_ins; + unsigned int audio_outs; + struct vx_pipe **playback_pipes; + struct vx_pipe **capture_pipes; + + /* clock and audio sources */ + unsigned int audio_source; /* current audio input source */ + unsigned int audio_source_target; + unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */ + unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */ + unsigned int freq; /* current frequency */ + unsigned int freq_detected; /* detected frequency from digital in */ + unsigned int uer_detected; /* VX_UER_MODE_XXX */ + unsigned int uer_bits; /* IEC958 status bits */ + struct vx_ibl_info ibl; /* IBL information */ + + /* mixer setting */ + int output_level[VX_MAX_CODECS][2]; /* analog output level */ + int audio_gain[2][4]; /* digital audio level (playback/capture) */ + unsigned char audio_active[4]; /* mute/unmute on digital playback */ + int audio_monitor[4]; /* playback hw-monitor level */ + unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */ + + struct mutex mixer_mutex; + + const struct firmware *firmware[4]; /* loaded firmware data */ +}; + + +/* + * constructor + */ +struct vx_core *snd_vx_create(struct snd_card *card, + const struct snd_vx_hardware *hw, + const struct snd_vx_ops *ops, int extra_size); +int snd_vx_setup_firmware(struct vx_core *chip); +int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp); +int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp); +int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp); + +void snd_vx_free_firmware(struct vx_core *chip); + +/* + * interrupt handler; exported for pcmcia + */ +irqreturn_t snd_vx_irq_handler(int irq, void *dev); +irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev); + +/* + * lowlevel functions + */ +static inline int vx_test_and_ack(struct vx_core *chip) +{ + return chip->ops->test_and_ack(chip); +} + +static inline void vx_validate_irq(struct vx_core *chip, int enable) +{ + chip->ops->validate_irq(chip, enable); +} + +static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg) +{ + return chip->ops->in8(chip, reg); +} + +static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg) +{ + return chip->ops->in32(chip, reg); +} + +static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val) +{ + chip->ops->out8(chip, reg, val); +} + +static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val) +{ + chip->ops->out32(chip, reg, val); +} + +#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg) +#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) +#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg) +#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) + +static inline void vx_reset_dsp(struct vx_core *chip) +{ + chip->ops->reset_dsp(chip); +} + +int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh); +int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh); +int vx_send_rih(struct vx_core *chip, int cmd); +int vx_send_rih_nolock(struct vx_core *chip, int cmd); + +void vx_reset_codec(struct vx_core *chip, int cold_reset); + +/* + * check the bit on the specified register + * returns zero if a bit matches, or a negative error code. + * exported for vxpocket driver + */ +int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time); +#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) +#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200) +#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL) + + +/* + * pseudo-DMA transfer + */ +static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count) +{ + chip->ops->dma_write(chip, runtime, pipe, count); +} + +static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count) +{ + chip->ops->dma_read(chip, runtime, pipe, count); +} + + + +/* error with hardware code, + * the return value is -(VX_ERR_MASK | actual-hw-error-code) + */ +#define VX_ERR_MASK 0x1000000 +#define vx_get_error(err) (-(err) & ~VX_ERR_MASK) + + +/* + * pcm stuff + */ +int snd_vx_pcm_new(struct vx_core *chip); +void vx_pcm_update_intr(struct vx_core *chip, unsigned int events); + +/* + * mixer stuff + */ +int snd_vx_mixer_new(struct vx_core *chip); +void vx_toggle_dac_mute(struct vx_core *chip, int mute); +int vx_sync_audio_source(struct vx_core *chip); +int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active); + +/* + * IEC958 & clock stuff + */ +void vx_set_iec958_status(struct vx_core *chip, unsigned int bits); +int vx_set_clock(struct vx_core *chip, unsigned int freq); +void vx_set_internal_clock(struct vx_core *chip, unsigned int freq); +int vx_change_frequency(struct vx_core *chip); + + +/* + * PM + */ +int snd_vx_suspend(struct vx_core *card); +int snd_vx_resume(struct vx_core *card); + +/* + * hardware constants + */ + +#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD) +#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET) + +/* audio input source */ +enum { + VX_AUDIO_SRC_DIGITAL, + VX_AUDIO_SRC_LINE, + VX_AUDIO_SRC_MIC +}; + +/* clock source */ +enum { + INTERNAL_QUARTZ, + UER_SYNC +}; + +/* clock mode */ +enum { + VX_CLOCK_MODE_AUTO, /* depending on the current audio source */ + VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */ + VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */ +}; + +/* SPDIF/UER type */ +enum { + VX_UER_MODE_CONSUMER, + VX_UER_MODE_PROFESSIONAL, + VX_UER_MODE_NOT_PRESENT, +}; + +/* register indices */ +enum { + VX_ICR, + VX_CVR, + VX_ISR, + VX_IVR, + VX_RXH, + VX_TXH = VX_RXH, + VX_RXM, + VX_TXM = VX_RXM, + VX_RXL, + VX_TXL = VX_RXL, + VX_DMA, + VX_CDSP, + VX_RFREQ, + VX_RUER_V2, + VX_GAIN, + VX_DATA = VX_GAIN, + VX_MEMIRQ, + VX_ACQ, + VX_BIT0, + VX_BIT1, + VX_MIC0, + VX_MIC1, + VX_MIC2, + VX_MIC3, + VX_PLX0, + VX_PLX1, + VX_PLX2, + + VX_LOFREQ, // V2: ACQ, VP: RFREQ + VX_HIFREQ, // V2: BIT0, VP: RUER_V2 + VX_CSUER, // V2: BIT1, VP: BIT0 + VX_RUER, // V2: RUER_V2, VP: BIT1 + + VX_REG_MAX, + + /* aliases for VX board */ + VX_RESET_DMA = VX_ISR, + VX_CFG = VX_RFREQ, + VX_STATUS = VX_MEMIRQ, + VX_SELMIC = VX_MIC0, + VX_COMPOT = VX_MIC1, + VX_SCOMPR = VX_MIC2, + VX_GLIMIT = VX_MIC3, + VX_INTCSR = VX_PLX0, + VX_CNTRL = VX_PLX1, + VX_GPIOC = VX_PLX2, + + /* aliases for VXPOCKET board */ + VX_MICRO = VX_MEMIRQ, + VX_CODEC2 = VX_MEMIRQ, + VX_DIALOG = VX_ACQ, + +}; + +/* RMH status type */ +enum { + RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */ + RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ + RMH_SSIZE_MASK = 2, /* status size given in bitmask */ +}; + + +/* bits for ICR register */ +#define ICR_HF1 0x10 +#define ICR_HF0 0x08 +#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */ +#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */ + +/* bits for CVR register */ +#define CVR_HC 0x80 + +/* bits for ISR register */ +#define ISR_HF3 0x10 +#define ISR_HF2 0x08 +#define ISR_CHK 0x10 +#define ISR_ERR 0x08 +#define ISR_TX_READY 0x04 +#define ISR_TX_EMPTY 0x02 +#define ISR_RX_FULL 0x01 + +/* Constants used to access the DATA register */ +#define VX_DATA_CODEC_MASK 0x80 +#define VX_DATA_XICOR_MASK 0x80 + +/* Constants used to access the CSUER register (both for VX2 and VXP) */ +#define VX_SUER_FREQ_MASK 0x0c +#define VX_SUER_FREQ_32KHz_MASK 0x0c +#define VX_SUER_FREQ_44KHz_MASK 0x00 +#define VX_SUER_FREQ_48KHz_MASK 0x04 +#define VX_SUER_DATA_PRESENT_MASK 0x02 +#define VX_SUER_CLOCK_PRESENT_MASK 0x01 + +#define VX_CUER_HH_BITC_SEL_MASK 0x08 +#define VX_CUER_MH_BITC_SEL_MASK 0x04 +#define VX_CUER_ML_BITC_SEL_MASK 0x02 +#define VX_CUER_LL_BITC_SEL_MASK 0x01 + +#define XX_UER_CBITS_OFFSET_MASK 0x1f + + +/* bits for audio_info */ +#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */ +#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */ +#define VX_AUDIO_INFO_MPEG1 (1<<5) +#define VX_AUDIO_INFO_MPEG2 (1<<6) +#define VX_AUDIO_INFO_LINEAR_8 (1<<7) +#define VX_AUDIO_INFO_LINEAR_16 (1<<8) +#define VX_AUDIO_INFO_LINEAR_24 (1<<9) + +/* DSP Interrupt Request values */ +#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */ +/* call with vx_send_irq_dsp() */ +#define IRQ_MESS_WRITE_END 0x30 +#define IRQ_MESS_WRITE_NEXT 0x32 +#define IRQ_MESS_READ_NEXT 0x34 +#define IRQ_MESS_READ_END 0x36 +#define IRQ_MESSAGE 0x38 +#define IRQ_RESET_CHK 0x3A +#define IRQ_CONNECT_STREAM_NEXT 0x26 +#define IRQ_CONNECT_STREAM_END 0x28 +#define IRQ_PAUSE_START_CONNECT 0x2A +#define IRQ_END_CONNECTION 0x2C + +/* Is there async. events pending ( IT Source Test ) */ +#define ASYNC_EVENTS_PENDING 0x008000 +#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate +#define NOTIF_EVENTS_PENDING 0x002000 +#define TIME_CODE_EVENT_PENDING 0x001000 +#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800 +#define END_OF_BUFFER_EVENTS_PENDING 0x000400 +#define FATAL_DSP_ERROR 0xff0000 + +/* Stream Format Header Defines */ +#define HEADER_FMT_BASE 0xFED00000 +#define HEADER_FMT_MONO 0x000000C0 +#define HEADER_FMT_INTEL 0x00008000 +#define HEADER_FMT_16BITS 0x00002000 +#define HEADER_FMT_24BITS 0x00004000 +#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/ +#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/ + +/* Constants used to access the Codec */ +#define XX_CODEC_SELECTOR 0x20 +/* codec commands */ +#define XX_CODEC_ADC_CONTROL_REGISTER 0x01 +#define XX_CODEC_DAC_CONTROL_REGISTER 0x02 +#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03 +#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04 +#define XX_CODEC_PORT_MODE_REGISTER 0x05 +#define XX_CODEC_STATUS_REPORT_REGISTER 0x06 +#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07 + +/* + * Audio-level control values + */ +#define CVAL_M110DB 0x000 /* -110dB */ +#define CVAL_M99DB 0x02C +#define CVAL_M21DB 0x163 +#define CVAL_M18DB 0x16F +#define CVAL_M10DB 0x18F +#define CVAL_0DB 0x1B7 +#define CVAL_18DB 0x1FF /* +18dB */ +#define CVAL_MAX 0x1FF + +#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000 +#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000 +#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000 +#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01 +#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02 +#define VALID_AUDIO_IO_MUTE_LEVEL 0x04 +#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08 +#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10 + + +#endif /* __SOUND_VX_COMMON_H */ diff --git a/include/sound/wavefront.h b/include/sound/wavefront.h new file mode 100644 index 000000000..ef6f46acc --- /dev/null +++ b/include/sound/wavefront.h @@ -0,0 +1,631 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_WAVEFRONT_H__ +#define __SOUND_WAVEFRONT_H__ + +/* + * Driver for Turtle Beach Wavefront cards (Maui,Tropez,Tropez+) + * + * Copyright (c) by Paul Barton-Davis + */ + +#ifndef NUM_MIDIKEYS +#define NUM_MIDIKEYS 128 +#endif /* NUM_MIDIKEYS */ + +#ifndef NUM_MIDICHANNELS +#define NUM_MIDICHANNELS 16 +#endif /* NUM_MIDICHANNELS */ + +/* Pseudo-commands not part of the WaveFront command set. + These are used for various driver controls and direct + hardware control. + */ + +#define WFC_DEBUG_DRIVER 0 +#define WFC_FX_IOCTL 1 +#define WFC_PATCH_STATUS 2 +#define WFC_PROGRAM_STATUS 3 +#define WFC_SAMPLE_STATUS 4 +#define WFC_DISABLE_INTERRUPTS 5 +#define WFC_ENABLE_INTERRUPTS 6 +#define WFC_INTERRUPT_STATUS 7 +#define WFC_ROMSAMPLES_RDONLY 8 +#define WFC_IDENTIFY_SLOT_TYPE 9 + +/* Wavefront synth commands + */ + +#define WFC_DOWNLOAD_SAMPLE 0x80 +#define WFC_DOWNLOAD_BLOCK 0x81 +#define WFC_DOWNLOAD_MULTISAMPLE 0x82 +#define WFC_DOWNLOAD_SAMPLE_ALIAS 0x83 +#define WFC_DELETE_SAMPLE 0x84 +#define WFC_REPORT_FREE_MEMORY 0x85 +#define WFC_DOWNLOAD_PATCH 0x86 +#define WFC_DOWNLOAD_PROGRAM 0x87 +#define WFC_SET_SYNTHVOL 0x89 +#define WFC_SET_NVOICES 0x8B +#define WFC_DOWNLOAD_DRUM 0x90 +#define WFC_GET_SYNTHVOL 0x92 +#define WFC_GET_NVOICES 0x94 +#define WFC_DISABLE_CHANNEL 0x9A +#define WFC_ENABLE_CHANNEL 0x9B +#define WFC_MISYNTH_OFF 0x9D +#define WFC_MISYNTH_ON 0x9E +#define WFC_FIRMWARE_VERSION 0x9F +#define WFC_GET_NSAMPLES 0xA0 +#define WFC_DISABLE_DRUM_PROGRAM 0xA2 +#define WFC_UPLOAD_PATCH 0xA3 +#define WFC_UPLOAD_PROGRAM 0xA4 +#define WFC_SET_TUNING 0xA6 +#define WFC_GET_TUNING 0xA7 +#define WFC_VMIDI_ON 0xA8 +#define WFC_VMIDI_OFF 0xA9 +#define WFC_MIDI_STATUS 0xAA +#define WFC_GET_CHANNEL_STATUS 0xAB +#define WFC_DOWNLOAD_SAMPLE_HEADER 0xAC +#define WFC_UPLOAD_SAMPLE_HEADER 0xAD +#define WFC_UPLOAD_MULTISAMPLE 0xAE +#define WFC_UPLOAD_SAMPLE_ALIAS 0xAF +#define WFC_IDENTIFY_SAMPLE_TYPE 0xB0 +#define WFC_DOWNLOAD_EDRUM_PROGRAM 0xB1 +#define WFC_UPLOAD_EDRUM_PROGRAM 0xB2 +#define WFC_SET_EDRUM_CHANNEL 0xB3 +#define WFC_INSTOUT_LEVELS 0xB4 +#define WFC_PEAKOUT_LEVELS 0xB5 +#define WFC_REPORT_CHANNEL_PROGRAMS 0xB6 +#define WFC_HARDWARE_VERSION 0xCF +#define WFC_UPLOAD_SAMPLE_PARAMS 0xD7 +#define WFC_DOWNLOAD_OS 0xF1 +#define WFC_NOOP 0xFF + +#define WF_MAX_SAMPLE 512 +#define WF_MAX_PATCH 256 +#define WF_MAX_PROGRAM 128 + +#define WF_SECTION_MAX 44 /* longest OS section length */ + +/* # of bytes we send to the board when sending it various kinds of + substantive data, such as samples, patches and programs. +*/ + +#define WF_PROGRAM_BYTES 32 +#define WF_PATCH_BYTES 132 +#define WF_SAMPLE_BYTES 27 +#define WF_SAMPLE_HDR_BYTES 25 +#define WF_ALIAS_BYTES 25 +#define WF_DRUM_BYTES 9 +#define WF_MSAMPLE_BYTES 259 /* (MIDI_KEYS * 2) + 3 */ + +#define WF_ACK 0x80 +#define WF_DMA_ACK 0x81 + +/* OR-values for MIDI status bits */ + +#define WF_MIDI_VIRTUAL_ENABLED 0x1 +#define WF_MIDI_VIRTUAL_IS_EXTERNAL 0x2 +#define WF_MIDI_IN_TO_SYNTH_DISABLED 0x4 + +/* slot indexes for struct address_info: makes code a little more mnemonic */ + +#define WF_SYNTH_SLOT 0 +#define WF_INTERNAL_MIDI_SLOT 1 +#define WF_EXTERNAL_MIDI_SLOT 2 + +/* Magic MIDI bytes used to switch I/O streams on the ICS2115 MPU401 + emulation. Note these NEVER show up in output from the device and + should NEVER be used in input unless Virtual MIDI mode has been + disabled. If they do show up as input, the results are unpredictable. +*/ + +#define WF_EXTERNAL_SWITCH 0xFD +#define WF_INTERNAL_SWITCH 0xF9 + +/* Debugging flags */ + +#define WF_DEBUG_CMD 0x1 +#define WF_DEBUG_DATA 0x2 +#define WF_DEBUG_LOAD_PATCH 0x4 +#define WF_DEBUG_IO 0x8 + +/* WavePatch file format stuff */ + +#define WF_WAVEPATCH_VERSION 120; /* Current version number (1.2) */ +#define WF_MAX_COMMENT 64 /* Comment length */ +#define WF_NUM_LAYERS 4 +#define WF_NAME_LENGTH 32 +#define WF_SOURCE_LENGTH 260 + +#define BankFileID "Bank" +#define DrumkitFileID "DrumKit" +#define ProgramFileID "Program" + +struct wf_envelope +{ + u8 attack_time:7; + u8 Unused1:1; + + u8 decay1_time:7; + u8 Unused2:1; + + u8 decay2_time:7; + u8 Unused3:1; + + u8 sustain_time:7; + u8 Unused4:1; + + u8 release_time:7; + u8 Unused5:1; + + u8 release2_time:7; + u8 Unused6:1; + + s8 attack_level; + s8 decay1_level; + s8 decay2_level; + s8 sustain_level; + s8 release_level; + + u8 attack_velocity:7; + u8 Unused7:1; + + u8 volume_velocity:7; + u8 Unused8:1; + + u8 keyboard_scaling:7; + u8 Unused9:1; +}; +typedef struct wf_envelope wavefront_envelope; + +struct wf_lfo +{ + u8 sample_number; + + u8 frequency:7; + u8 Unused1:1; + + u8 am_src:4; + u8 fm_src:4; + + s8 fm_amount; + s8 am_amount; + s8 start_level; + s8 end_level; + + u8 ramp_delay:7; + u8 wave_restart:1; /* for LFO2 only */ + + u8 ramp_time:7; + u8 Unused2:1; +}; +typedef struct wf_lfo wavefront_lfo; + +struct wf_patch +{ + s16 frequency_bias; /* ** THIS IS IN MOTOROLA FORMAT!! ** */ + + u8 amplitude_bias:7; + u8 Unused1:1; + + u8 portamento:7; + u8 Unused2:1; + + u8 sample_number; + + u8 pitch_bend:4; + u8 sample_msb:1; + u8 Unused3:3; + + u8 mono:1; + u8 retrigger:1; + u8 nohold:1; + u8 restart:1; + u8 filterconfig:2; /* SDK says "not used" */ + u8 reuse:1; + u8 reset_lfo:1; + + u8 fm_src2:4; + u8 fm_src1:4; + + s8 fm_amount1; + s8 fm_amount2; + + u8 am_src:4; + u8 Unused4:4; + + s8 am_amount; + + u8 fc1_mode:4; + u8 fc2_mode:4; + + s8 fc1_mod_amount; + s8 fc1_keyboard_scaling; + s8 fc1_bias; + s8 fc2_mod_amount; + s8 fc2_keyboard_scaling; + s8 fc2_bias; + + u8 randomizer:7; + u8 Unused5:1; + + struct wf_envelope envelope1; + struct wf_envelope envelope2; + struct wf_lfo lfo1; + struct wf_lfo lfo2; +}; +typedef struct wf_patch wavefront_patch; + +struct wf_layer +{ + u8 patch_number; + + u8 mix_level:7; + u8 mute:1; + + u8 split_point:7; + u8 play_below:1; + + u8 pan_mod_src:2; + u8 pan_or_mod:1; + u8 pan:4; + u8 split_type:1; +}; +typedef struct wf_layer wavefront_layer; + +struct wf_program +{ + struct wf_layer layer[WF_NUM_LAYERS]; +}; +typedef struct wf_program wavefront_program; + +struct wf_sample_offset +{ + s32 Fraction:4; + s32 Integer:20; + s32 Unused:8; +}; +typedef struct wf_sample_offset wavefront_sample_offset; + +/* Sample slot types */ + +#define WF_ST_SAMPLE 0 +#define WF_ST_MULTISAMPLE 1 +#define WF_ST_ALIAS 2 +#define WF_ST_EMPTY 3 + +/* pseudo's */ + +#define WF_ST_DRUM 4 +#define WF_ST_PROGRAM 5 +#define WF_ST_PATCH 6 +#define WF_ST_SAMPLEHDR 7 + +#define WF_ST_MASK 0xf + +/* Flags for slot status. These occupy the upper bits of the same byte + as a sample type. +*/ + +#define WF_SLOT_USED 0x80 /* XXX don't rely on this being accurate */ +#define WF_SLOT_FILLED 0x40 +#define WF_SLOT_ROM 0x20 + +#define WF_SLOT_MASK 0xf0 + +/* channel constants */ + +#define WF_CH_MONO 0 +#define WF_CH_LEFT 1 +#define WF_CH_RIGHT 2 + +/* Sample formats */ + +#define LINEAR_16BIT 0 +#define WHITE_NOISE 1 +#define LINEAR_8BIT 2 +#define MULAW_8BIT 3 + +#define WF_SAMPLE_IS_8BIT(smpl) ((smpl)->SampleResolution&2) + + +/* + + Because most/all of the sample data we pass in via pointers has + never been copied (just mmap-ed into user space straight from the + disk), it would be nice to allow handling of multi-channel sample + data without forcing user-level extraction of the relevant bytes. + + So, we need a way of specifying which channel to use (the WaveFront + only handles mono samples in a given slot), and the only way to do + this without using some struct other than wavefront_sample as the + interface is the awful hack of using the unused bits in a + wavefront_sample: + + Val Meaning + --- ------- + 0 no channel selection (use channel 1, sample is MONO) + 1 use first channel, and skip one + 2 use second channel, and skip one + 3 use third channel, and skip two + 4 use fourth channel, skip three + 5 use fifth channel, skip four + 6 use six channel, skip five + + + This can handle up to 4 channels, and anyone downloading >4 channels + of sample data just to select one of them needs to find some tools + like sox ... + + NOTE: values 0, 1 and 2 correspond to WF_CH_* above. This is + important. + +*/ + +#define WF_SET_CHANNEL(samp,chn) \ + (samp)->Unused1 = chn & 0x1; \ + (samp)->Unused2 = chn & 0x2; \ + (samp)->Unused3 = chn & 0x4 + +#define WF_GET_CHANNEL(samp) \ + (((samp)->Unused3 << 2)|((samp)->Unused2<<1)|(samp)->Unused1) + +typedef struct wf_sample { + struct wf_sample_offset sampleStartOffset; + struct wf_sample_offset loopStartOffset; + struct wf_sample_offset loopEndOffset; + struct wf_sample_offset sampleEndOffset; + s16 FrequencyBias; + u8 SampleResolution:2; /* sample_format */ + u8 Unused1:1; + u8 Loop:1; + u8 Bidirectional:1; + u8 Unused2:1; + u8 Reverse:1; + u8 Unused3:1; +} wavefront_sample; + +typedef struct wf_multisample { + s16 NumberOfSamples; /* log2 of the number of samples */ + s16 SampleNumber[NUM_MIDIKEYS]; +} wavefront_multisample; + +typedef struct wf_alias { + s16 OriginalSample; + + struct wf_sample_offset sampleStartOffset; + struct wf_sample_offset loopStartOffset; + struct wf_sample_offset sampleEndOffset; + struct wf_sample_offset loopEndOffset; + + s16 FrequencyBias; + + u8 SampleResolution:2; + u8 Unused1:1; + u8 Loop:1; + u8 Bidirectional:1; + u8 Unused2:1; + u8 Reverse:1; + u8 Unused3:1; + + /* This structure is meant to be padded only to 16 bits on their + original. Of course, whoever wrote their documentation didn't + realize that sizeof(struct) can be >= + sum(sizeof(struct-fields)) and so thought that giving a C level + description of the structs used in WavePatch files was + sufficient. I suppose it was, as long as you remember the + standard 16->32 bit issues. + */ + + u8 sixteen_bit_padding; +} __packed wavefront_alias; + +typedef struct wf_drum { + u8 PatchNumber; + u8 MixLevel:7; + u8 Unmute:1; + u8 Group:4; + u8 Unused1:4; + u8 PanModSource:2; + u8 PanModulated:1; + u8 PanAmount:4; + u8 Unused2:1; +} wavefront_drum; + +typedef struct wf_drumkit { + struct wf_drum drum[NUM_MIDIKEYS]; +} wavefront_drumkit; + +typedef struct wf_channel_programs { + u8 Program[NUM_MIDICHANNELS]; +} wavefront_channel_programs; + +/* How to get MIDI channel status from the data returned by + a WFC_GET_CHANNEL_STATUS command (a struct wf_channel_programs) +*/ + +#define WF_CHANNEL_STATUS(ch,wcp) (wcp)[(ch/7)] & (1<<((ch)%7)) + +typedef union wf_any { + wavefront_sample s; + wavefront_multisample ms; + wavefront_alias a; + wavefront_program pr; + wavefront_patch p; + wavefront_drum d; +} wavefront_any; + +/* Hannu Solvainen hoped that his "patch_info" struct in soundcard.h + might work for other wave-table based patch loading situations. + Alas, his fears were correct. The WaveFront doesn't even come with + just "patches", but several different kind of structures that + control the sound generation process. + */ + +typedef struct wf_patch_info { + + /* the first two fields are used by the OSS "patch loading" interface + only, and are unused by the current user-level library. + */ + + s16 key; /* Use WAVEFRONT_PATCH here */ + u16 devno; /* fill in when sending */ + u8 subkey; /* WF_ST_{SAMPLE,ALIAS,etc.} */ + +#define WAVEFRONT_FIND_FREE_SAMPLE_SLOT 999 + + u16 number; /* patch/sample/prog number */ + + u32 size; /* size of any data included in + one of the fields in `hdrptr', or + as `dataptr'. + + NOTE: for actual samples, this is + the size of the *SELECTED CHANNEL* + even if more data is actually available. + + So, a stereo sample (2 channels) of + 6000 bytes total has `size' = 3000. + + See the macros and comments for + WF_{GET,SET}_CHANNEL above. + + */ + wavefront_any __user *hdrptr; /* user-space ptr to hdr bytes */ + u16 __user *dataptr; /* actual sample data */ + + wavefront_any hdr; /* kernel-space copy of hdr bytes */ +} wavefront_patch_info; + +/* The maximum number of bytes we will ever move to or from user space + in response to a WFC_* command. This obviously doesn't cover + actual sample data. +*/ + +#define WF_MAX_READ sizeof(wavefront_multisample) +#define WF_MAX_WRITE sizeof(wavefront_multisample) + +/* + This allows us to execute any WF command except the download/upload + ones, which are handled differently due to copyin/copyout issues as + well as data-nybbling to/from the card. + */ + +typedef struct wavefront_control { + int cmd; /* WFC_* */ + char status; /* return status to user-space */ + unsigned char rbuf[WF_MAX_READ]; /* bytes read from card */ + unsigned char wbuf[WF_MAX_WRITE]; /* bytes written to card */ +} wavefront_control; + +#define WFCTL_WFCMD 0x1 +#define WFCTL_LOAD_SPP 0x2 + +/* Modulator table */ + +#define WF_MOD_LFO1 0 +#define WF_MOD_LFO2 1 +#define WF_MOD_ENV1 2 +#define WF_MOD_ENV2 3 +#define WF_MOD_KEYBOARD 4 +#define WF_MOD_LOGKEY 5 +#define WF_MOD_VELOCITY 6 +#define WF_MOD_LOGVEL 7 +#define WF_MOD_RANDOM 8 +#define WF_MOD_PRESSURE 9 +#define WF_MOD_MOD_WHEEL 10 +#define WF_MOD_1 WF_MOD_MOD_WHEEL +#define WF_MOD_BREATH 11 +#define WF_MOD_2 WF_MOD_BREATH +#define WF_MOD_FOOT 12 +#define WF_MOD_4 WF_MOD_FOOT +#define WF_MOD_VOLUME 13 +#define WF_MOD_7 WF_MOD_VOLUME +#define WF_MOD_PAN 14 +#define WF_MOD_10 WF_MOD_PAN +#define WF_MOD_EXPR 15 +#define WF_MOD_11 WF_MOD_EXPR + +/* FX-related material */ + +typedef struct wf_fx_info { + int request; /* see list below */ + long data[4]; /* we don't need much */ +} wavefront_fx_info; + +/* support for each of these will be forthcoming once I or someone + else has figured out which of the addresses on page 6 and page 7 of + the YSS225 control each parameter. Incidentally, these come from + the Windows driver interface, but again, Turtle Beach didn't + document the API to use them. +*/ + +#define WFFX_SETOUTGAIN 0 +#define WFFX_SETSTEREOOUTGAIN 1 +#define WFFX_SETREVERBIN1GAIN 2 +#define WFFX_SETREVERBIN2GAIN 3 +#define WFFX_SETREVERBIN3GAIN 4 +#define WFFX_SETCHORUSINPORT 5 +#define WFFX_SETREVERBIN1PORT 6 +#define WFFX_SETREVERBIN2PORT 7 +#define WFFX_SETREVERBIN3PORT 8 +#define WFFX_SETEFFECTPORT 9 +#define WFFX_SETAUXPORT 10 +#define WFFX_SETREVERBTYPE 11 +#define WFFX_SETREVERBDELAY 12 +#define WFFX_SETCHORUSLFO 13 +#define WFFX_SETCHORUSPMD 14 +#define WFFX_SETCHORUSAMD 15 +#define WFFX_SETEFFECT 16 +#define WFFX_SETBASEALL 17 +#define WFFX_SETREVERBALL 18 +#define WFFX_SETCHORUSALL 20 +#define WFFX_SETREVERBDEF 22 +#define WFFX_SETCHORUSDEF 23 +#define WFFX_DELAYSETINGAIN 24 +#define WFFX_DELAYSETFBGAIN 25 +#define WFFX_DELAYSETFBLPF 26 +#define WFFX_DELAYSETGAIN 27 +#define WFFX_DELAYSETTIME 28 +#define WFFX_DELAYSETFBTIME 29 +#define WFFX_DELAYSETALL 30 +#define WFFX_DELAYSETDEF 32 +#define WFFX_SDELAYSETINGAIN 33 +#define WFFX_SDELAYSETFBGAIN 34 +#define WFFX_SDELAYSETFBLPF 35 +#define WFFX_SDELAYSETGAIN 36 +#define WFFX_SDELAYSETTIME 37 +#define WFFX_SDELAYSETFBTIME 38 +#define WFFX_SDELAYSETALL 39 +#define WFFX_SDELAYSETDEF 41 +#define WFFX_DEQSETINGAIN 42 +#define WFFX_DEQSETFILTER 43 +#define WFFX_DEQSETALL 44 +#define WFFX_DEQSETDEF 46 +#define WFFX_MUTE 47 +#define WFFX_FLANGESETBALANCE 48 +#define WFFX_FLANGESETDELAY 49 +#define WFFX_FLANGESETDWFFX_TH 50 +#define WFFX_FLANGESETFBGAIN 51 +#define WFFX_FLANGESETINGAIN 52 +#define WFFX_FLANGESETLFO 53 +#define WFFX_FLANGESETALL 54 +#define WFFX_FLANGESETDEF 56 +#define WFFX_PITCHSETSHIFT 57 +#define WFFX_PITCHSETBALANCE 58 +#define WFFX_PITCHSETALL 59 +#define WFFX_PITCHSETDEF 61 +#define WFFX_SRSSETINGAIN 62 +#define WFFX_SRSSETSPACE 63 +#define WFFX_SRSSETCENTER 64 +#define WFFX_SRSSETGAIN 65 +#define WFFX_SRSSETMODE 66 +#define WFFX_SRSSETDEF 68 + +/* Allow direct user-space control over FX memory/coefficient data. + In theory this could be used to download the FX microprogram, + but it would be a little slower, and involve some weird code. + */ + +#define WFFX_MEMSET 69 + +#endif /* __SOUND_WAVEFRONT_H__ */ diff --git a/include/sound/wm0010.h b/include/sound/wm0010.h new file mode 100644 index 000000000..14ff9056c --- /dev/null +++ b/include/sound/wm0010.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * wm0010.h -- Platform data for WM0010 DSP Driver + * + * Copyright 2012 Wolfson Microelectronics PLC. + * + * Author: Dimitris Papastamos + */ + +#ifndef WM0010_PDATA_H +#define WM0010_PDATA_H + +struct wm0010_pdata { + int irq_flags; +}; + +#endif diff --git a/include/sound/wm2000.h b/include/sound/wm2000.h new file mode 100644 index 000000000..affd11073 --- /dev/null +++ b/include/sound/wm2000.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm2000.h -- Platform data for WM2000 + * + * Copyright 2010 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM2000_H +#define __LINUX_SND_WM2000_H + +struct wm2000_platform_data { + /** Filename for system-specific image to download to device. */ + const char *download_file; + + /** Disable speech clarity enhancement, for use when an + * external algorithm is used. */ + unsigned int speech_enh_disable:1; +}; + +#endif diff --git a/include/sound/wm2200.h b/include/sound/wm2200.h new file mode 100644 index 000000000..2e4913ee2 --- /dev/null +++ b/include/sound/wm2200.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm2200.h -- Platform data for WM2200 + * + * Copyright 2012 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM2200_H +#define __LINUX_SND_WM2200_H + +#define WM2200_GPIO_SET 0x10000 +#define WM2200_MAX_MICBIAS 2 + +enum wm2200_in_mode { + WM2200_IN_SE = 0, + WM2200_IN_DIFF = 1, + WM2200_IN_DMIC = 2, +}; + +enum wm2200_dmic_sup { + WM2200_DMIC_SUP_MICVDD = 0, + WM2200_DMIC_SUP_MICBIAS1 = 1, + WM2200_DMIC_SUP_MICBIAS2 = 2, +}; + +enum wm2200_mbias_lvl { + WM2200_MBIAS_LVL_1V5 = 1, + WM2200_MBIAS_LVL_1V8 = 2, + WM2200_MBIAS_LVL_1V9 = 3, + WM2200_MBIAS_LVL_2V0 = 4, + WM2200_MBIAS_LVL_2V2 = 5, + WM2200_MBIAS_LVL_2V4 = 6, + WM2200_MBIAS_LVL_2V5 = 7, + WM2200_MBIAS_LVL_2V6 = 8, +}; + +struct wm2200_micbias { + enum wm2200_mbias_lvl mb_lvl; /** Regulated voltage */ + unsigned int discharge:1; /** Actively discharge */ + unsigned int fast_start:1; /** Enable aggressive startup ramp rate */ + unsigned int bypass:1; /** Use bypass mode */ +}; + +struct wm2200_pdata { + int irq_flags; + + int gpio_defaults[4]; + + enum wm2200_in_mode in_mode[3]; + enum wm2200_dmic_sup dmic_sup[3]; + + /** MICBIAS configurations */ + struct wm2200_micbias micbias[WM2200_MAX_MICBIAS]; +}; + +#endif diff --git a/include/sound/wm5100.h b/include/sound/wm5100.h new file mode 100644 index 000000000..1c48090fd --- /dev/null +++ b/include/sound/wm5100.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm5100.h -- Platform data for WM5100 + * + * Copyright 2011 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM5100_H +#define __LINUX_SND_WM5100_H + +enum wm5100_in_mode { + WM5100_IN_SE = 0, + WM5100_IN_DIFF = 1, + WM5100_IN_DMIC = 2, +}; + +enum wm5100_dmic_sup { + WM5100_DMIC_SUP_MICVDD = 0, + WM5100_DMIC_SUP_MICBIAS1 = 1, + WM5100_DMIC_SUP_MICBIAS2 = 2, + WM5100_DMIC_SUP_MICBIAS3 = 3, +}; + +enum wm5100_micdet_bias { + WM5100_MICDET_MICBIAS1 = 0, + WM5100_MICDET_MICBIAS2 = 1, + WM5100_MICDET_MICBIAS3 = 2, +}; + +struct wm5100_jack_mode { + enum wm5100_micdet_bias bias; + int hp_pol; + int micd_src; +}; + +#define WM5100_GPIO_SET 0x10000 + +struct wm5100_pdata { + int irq_flags; + + struct wm5100_jack_mode jack_modes[2]; + + /* Input pin mode selection */ + enum wm5100_in_mode in_mode[4]; + + /* DMIC supply selection */ + enum wm5100_dmic_sup dmic_sup[4]; + + int gpio_defaults[6]; +}; + +#endif diff --git a/include/sound/wm8903.h b/include/sound/wm8903.h new file mode 100644 index 000000000..3e9af639e --- /dev/null +++ b/include/sound/wm8903.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm8903.h -- Platform data for WM8903 + * + * Copyright 2010 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM8903_H +#define __LINUX_SND_WM8903_H + +/* + * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of + * zero in platform data means "don't touch this pin". + */ +#define WM8903_GPIO_CONFIG_ZERO 0x8000 + +/* + * R6 (0x06) - Mic Bias Control 0 + */ +#define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */ +#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */ +#define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */ +#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ +#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ +#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ +#define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ +#define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ +#define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ +#define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ +#define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ +#define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ +#define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ +#define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ + +/* + * WM8903_GPn_FN values + * + * See datasheets for list of valid values per pin + */ +#define WM8903_GPn_FN_GPIO_OUTPUT 0 +#define WM8903_GPn_FN_BCLK 1 +#define WM8903_GPn_FN_IRQ_OUTPT 2 +#define WM8903_GPn_FN_GPIO_INPUT 3 +#define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT 4 +#define WM8903_GPn_FN_MICBIAS_SHORT_DETECT 5 +#define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT 6 +#define WM8903_GPn_FN_FLL_LOCK_OUTPUT 8 +#define WM8903_GPn_FN_FLL_CLOCK_OUTPUT 9 + +/* + * R116 (0x74) - GPIO Control 1 + */ +#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ +#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ +#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ +#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ +#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ +#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ +#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ +#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ +#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ +#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ +#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ +#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ +#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ +#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ +#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ +#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ +#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ +#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ +#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ +#define WM8903_GP1_PD 0x0008 /* GP1_PD */ +#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ +#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ +#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ +#define WM8903_GP1_PU 0x0004 /* GP1_PU */ +#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ +#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ +#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ +#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ +#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ +#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ +#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ +#define WM8903_GP1_DB 0x0001 /* GP1_DB */ +#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ +#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ +#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ + +/* + * R117 (0x75) - GPIO Control 2 + */ +#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ +#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ +#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ +#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ +#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ +#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ +#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ +#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ +#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ +#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ +#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ +#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ +#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ +#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ +#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ +#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ +#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ +#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ +#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ +#define WM8903_GP2_PD 0x0008 /* GP2_PD */ +#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ +#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ +#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ +#define WM8903_GP2_PU 0x0004 /* GP2_PU */ +#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ +#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ +#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ +#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ +#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ +#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ +#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ +#define WM8903_GP2_DB 0x0001 /* GP2_DB */ +#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ +#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ +#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ + +/* + * R118 (0x76) - GPIO Control 3 + */ +#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ +#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ +#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ +#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ +#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ +#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ +#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ +#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ +#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ +#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ +#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ +#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ +#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ +#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ +#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ +#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ +#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ +#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ +#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ +#define WM8903_GP3_PD 0x0008 /* GP3_PD */ +#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ +#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ +#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ +#define WM8903_GP3_PU 0x0004 /* GP3_PU */ +#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ +#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ +#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ +#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ +#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ +#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ +#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ +#define WM8903_GP3_DB 0x0001 /* GP3_DB */ +#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ +#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ +#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ + +/* + * R119 (0x77) - GPIO Control 4 + */ +#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ +#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ +#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ +#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ +#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ +#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ +#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ +#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ +#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ +#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ +#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ +#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ +#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ +#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ +#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ +#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ +#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ +#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ +#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ +#define WM8903_GP4_PD 0x0008 /* GP4_PD */ +#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ +#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ +#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ +#define WM8903_GP4_PU 0x0004 /* GP4_PU */ +#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ +#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ +#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ +#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ +#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ +#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ +#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ +#define WM8903_GP4_DB 0x0001 /* GP4_DB */ +#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ +#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ +#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ + +/* + * R120 (0x78) - GPIO Control 5 + */ +#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ +#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ +#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ +#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ +#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ +#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ +#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ +#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ +#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ +#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ +#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ +#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ +#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ +#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ +#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ +#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ +#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ +#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ +#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ +#define WM8903_GP5_PD 0x0008 /* GP5_PD */ +#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ +#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ +#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ +#define WM8903_GP5_PU 0x0004 /* GP5_PU */ +#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ +#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ +#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ +#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ +#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ +#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ +#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ +#define WM8903_GP5_DB 0x0001 /* GP5_DB */ +#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ +#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ +#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ + +#define WM8903_NUM_GPIO 5 + +struct wm8903_platform_data { + bool irq_active_low; /* Set if IRQ active low, default high */ + + /* Default register value for R6 (Mic bias), used to configure + * microphone detection. In conjunction with gpio_cfg this + * can be used to route the microphone status signals out onto + * the GPIOs for use with snd_soc_jack_add_gpios(). + */ + u16 micdet_cfg; + + int micdet_delay; /* Delay after microphone detection (ms) */ + + int gpio_base; + u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */ +}; + +#endif diff --git a/include/sound/wm8904.h b/include/sound/wm8904.h new file mode 100644 index 000000000..151a05b13 --- /dev/null +++ b/include/sound/wm8904.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for WM8904 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + */ + +#ifndef __MFD_WM8994_PDATA_H__ +#define __MFD_WM8994_PDATA_H__ + +/* Used to enable configuration of a GPIO to all zeros */ +#define WM8904_GPIO_NO_CONFIG 0x8000 + +/* + * R6 (0x06) - Mic Bias Control 0 + */ +#define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */ +#define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */ +#define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */ +#define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ +#define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ +#define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ +#define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */ +#define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ +#define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ +#define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ +#define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ +#define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ +#define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ +#define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ + +/* + * R7 (0x07) - Mic Bias Control 1 + */ +#define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */ +#define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */ +#define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */ + + +/* + * R121 (0x79) - GPIO Control 1 + */ +#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */ +#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ +#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ +#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ +#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */ +#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ +#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ +#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ +#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ +#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ +#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ + +/* + * R122 (0x7A) - GPIO Control 2 + */ +#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */ +#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */ +#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */ +#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ +#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */ +#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */ +#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */ +#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ +#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */ +#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */ +#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */ + +/* + * R123 (0x7B) - GPIO Control 3 + */ +#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */ +#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ +#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ +#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ +#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */ +#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ +#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ +#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ +#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ +#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ +#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ + +/* + * R124 (0x7C) - GPIO Control 4 + */ +#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */ +#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */ +#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */ +#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */ +#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */ +#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */ +#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */ +#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */ +#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */ +#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */ + +#define WM8904_MIC_REGS 2 +#define WM8904_GPIO_REGS 4 +#define WM8904_DRC_REGS 4 +#define WM8904_EQ_REGS 24 + +/* + * DRC configurations are specified with a label and a set of register + * values to write (the enable bits will be ignored). At runtime an + * enumerated control will be presented for each DRC block allowing + * the user to choose the configuration to use. + * + * Configurations may be generated by hand or by using the DRC control + * panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/ + * for details. + */ +struct wm8904_drc_cfg { + const char *name; + u16 regs[WM8904_DRC_REGS]; +}; + +/* + * ReTune Mobile configurations are specified with a label, sample + * rate and set of values to write (the enable bits will be ignored). + * + * Configurations are expected to be generated using the ReTune Mobile + * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/ + */ +struct wm8904_retune_mobile_cfg { + const char *name; + unsigned int rate; + u16 regs[WM8904_EQ_REGS]; +}; + +struct wm8904_pdata { + int num_drc_cfgs; + struct wm8904_drc_cfg *drc_cfgs; + + int num_retune_mobile_cfgs; + struct wm8904_retune_mobile_cfg *retune_mobile_cfgs; + + bool in1l_as_dmicdat1; + bool in1r_as_dmicdat2; + + u32 gpio_cfg[WM8904_GPIO_REGS]; + u32 mic_cfg[WM8904_MIC_REGS]; +}; + +#endif diff --git a/include/sound/wm8955.h b/include/sound/wm8955.h new file mode 100644 index 000000000..62c5fa1e1 --- /dev/null +++ b/include/sound/wm8955.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for WM8955 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown + */ + +#ifndef __WM8955_PDATA_H__ +#define __WM8955_PDATA_H__ + +struct wm8955_pdata { + /* Configure LOUT2/ROUT2 to drive a speaker */ + unsigned int out2_speaker:1; + + /* Configure MONOIN+/- in differential mode */ + unsigned int monoin_diff:1; +}; + +#endif diff --git a/include/sound/wm8960.h b/include/sound/wm8960.h new file mode 100644 index 000000000..275fd5b20 --- /dev/null +++ b/include/sound/wm8960.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wm8960.h -- WM8960 Soc Audio driver platform data + */ + +#ifndef _WM8960_PDATA_H +#define _WM8960_PDATA_H + +#define WM8960_DRES_400R 0 +#define WM8960_DRES_200R 1 +#define WM8960_DRES_600R 2 +#define WM8960_DRES_150R 3 +#define WM8960_DRES_MAX 3 + +struct wm8960_data { + bool capless; /* Headphone outputs configured in capless mode */ + + bool shared_lrclk; /* DAC and ADC LRCLKs are wired together */ + + /* + * Setup for headphone detection + * + * hp_cfg[0]: HPSEL[1:0] of R48 (Additional Control 4) + * hp_cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2). + * hp_cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1). + */ + u32 hp_cfg[3]; + + /* + * Setup for gpio configuration + * + * gpio_cfg[0]: ALRCGPIO of R9 (Audio interface) + * gpio_cfg[1]: {GPIOPOL:GPIOSEL[2:0]} of R48 (Additional Control 4). + */ + u32 gpio_cfg[2]; +}; + +#endif diff --git a/include/sound/wm8962.h b/include/sound/wm8962.h new file mode 100644 index 000000000..f77722573 --- /dev/null +++ b/include/sound/wm8962.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wm8962.h -- WM8962 Soc Audio driver platform data + */ + +#ifndef _WM8962_PDATA_H +#define _WM8962_PDATA_H + +#define WM8962_MAX_GPIO 6 + +/* Use to set GPIO default values to zero */ +#define WM8962_GPIO_SET 0x10000 + +#define WM8962_GPIO_FN_CLKOUT 0 +#define WM8962_GPIO_FN_LOGIC 1 +#define WM8962_GPIO_FN_SDOUT 2 +#define WM8962_GPIO_FN_IRQ 3 +#define WM8962_GPIO_FN_THERMAL 4 +#define WM8962_GPIO_FN_PLL2_LOCK 6 +#define WM8962_GPIO_FN_PLL3_LOCK 7 +#define WM8962_GPIO_FN_FLL_LOCK 9 +#define WM8962_GPIO_FN_DRC_ACT 10 +#define WM8962_GPIO_FN_WSEQ_DONE 11 +#define WM8962_GPIO_FN_ALC_NG_ACT 12 +#define WM8962_GPIO_FN_ALC_PEAK_LIMIT 13 +#define WM8962_GPIO_FN_ALC_SATURATION 14 +#define WM8962_GPIO_FN_ALC_LEVEL_THR 15 +#define WM8962_GPIO_FN_ALC_LEVEL_LOCK 16 +#define WM8962_GPIO_FN_FIFO_ERR 17 +#define WM8962_GPIO_FN_OPCLK 18 +#define WM8962_GPIO_FN_DMICCLK 19 +#define WM8962_GPIO_FN_DMICDAT 20 +#define WM8962_GPIO_FN_MICD 21 +#define WM8962_GPIO_FN_MICSCD 22 + +struct wm8962_pdata { + struct clk *mclk; + int gpio_base; + u32 gpio_init[WM8962_MAX_GPIO]; + + /* Setup for microphone detection, raw value to be written to + * R48(0x30) - only microphone related bits will be updated. + * Detection may be enabled here for use with signals brought + * out on the GPIOs. */ + u32 mic_cfg; + + bool irq_active_low; + + bool spk_mono; /* Speaker outputs tied together as mono */ + + /** + * This flag should be set if one or both IN4 inputs is wired + * in a DC measurement configuration. + */ + bool in4_dc_measure; +}; + +#endif diff --git a/include/sound/wm8993.h b/include/sound/wm8993.h new file mode 100644 index 000000000..8cf9de85d --- /dev/null +++ b/include/sound/wm8993.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm8993.h -- Platform data for WM8993 + * + * Copyright 2009 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM8993_H +#define __LINUX_SND_WM8993_H + +/* Note that EQ1 only contains the enable/disable bit so will be + ignored but is included for simplicity. + */ +struct wm8993_retune_mobile_setting { + const char *name; + unsigned int rate; + u16 config[24]; +}; + +struct wm8993_platform_data { + struct wm8993_retune_mobile_setting *retune_configs; + int num_retune_configs; + + /* LINEOUT can be differential or single ended */ + unsigned int lineout1_diff:1; + unsigned int lineout2_diff:1; + + /* Common mode feedback */ + unsigned int lineout1fb:1; + unsigned int lineout2fb:1; + + /* Delay to add for microphones to stabalise after power up */ + int micbias1_delay; + int micbias2_delay; + + /* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */ + unsigned int micbias1_lvl:1; + unsigned int micbias2_lvl:1; + + /* Jack detect threshold levels, see datasheet for values */ + unsigned int jd_scthr:2; + unsigned int jd_thr:2; +}; + +#endif diff --git a/include/sound/wm8996.h b/include/sound/wm8996.h new file mode 100644 index 000000000..342abeef2 --- /dev/null +++ b/include/sound/wm8996.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm8996.h -- Platform data for WM8996 + * + * Copyright 2011 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM8996_H +#define __LINUX_SND_WM8996_H + +enum wm8996_inmode { + WM8996_DIFFERRENTIAL_1 = 0, /* IN1xP - IN1xN */ + WM8996_INVERTING = 1, /* IN1xN */ + WM8996_NON_INVERTING = 2, /* IN1xP */ + WM8996_DIFFERENTIAL_2 = 3, /* IN2xP - IN2xP */ +}; + +/** + * ReTune Mobile configurations are specified with a label, sample + * rate and set of values to write (the enable bits will be ignored). + * + * Configurations are expected to be generated using the ReTune Mobile + * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/ + */ +struct wm8996_retune_mobile_config { + const char *name; + int rate; + u16 regs[20]; +}; + +#define WM8996_SET_DEFAULT 0x10000 + +struct wm8996_pdata { + int irq_flags; /** Set IRQ trigger flags; default active low */ + + int micdet_def; /** Default MICDET_SRC/HP1FB_SRC/MICD_BIAS */ + + enum wm8996_inmode inl_mode; + enum wm8996_inmode inr_mode; + + u32 spkmute_seq; /** Value for register 0x802 */ + + u32 gpio_default[5]; + + int num_retune_mobile_cfgs; + struct wm8996_retune_mobile_config *retune_mobile_cfgs; +}; + +#endif diff --git a/include/sound/wm9081.h b/include/sound/wm9081.h new file mode 100644 index 000000000..2fd4bec8a --- /dev/null +++ b/include/sound/wm9081.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm9081.h -- Platform data for WM9081 + * + * Copyright 2009 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM_9081_H +#define __LINUX_SND_WM_9081_H + +struct wm9081_retune_mobile_setting { + const char *name; + unsigned int rate; + u16 config[20]; +}; + +struct wm9081_pdata { + bool irq_high; /* IRQ is active high */ + bool irq_cmos; /* IRQ is in CMOS mode */ + + struct wm9081_retune_mobile_setting *retune_configs; + int num_retune_configs; +}; + +#endif diff --git a/include/sound/wm9090.h b/include/sound/wm9090.h new file mode 100644 index 000000000..0dd2c9397 --- /dev/null +++ b/include/sound/wm9090.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm9090.h -- Platform data for WM9090 + * + * Copyright 2009, 2010 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM9090_H +#define __LINUX_SND_WM9090_H + +struct wm9090_platform_data { + /* Line inputs 1 & 2 can optionally be differential */ + unsigned int lin1_diff:1; + unsigned int lin2_diff:1; + + /* AGC configuration. This is intended to protect the speaker + * against overdriving and will therefore depend on the + * hardware setup with incorrect runtime configuration + * potentially causing hardware damage. + */ + unsigned int agc_ena:1; + u16 agc[3]; +}; + +#endif diff --git a/include/sound/wss.h b/include/sound/wss.h new file mode 100644 index 000000000..4bdbb8c57 --- /dev/null +++ b/include/sound/wss.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_WSS_H +#define __SOUND_WSS_H + +/* + * Copyright (c) by Jaroslav Kysela + * Definitions for CS4231 & InterWave chips & compatible chips + */ + +#include +#include +#include + +#include + +/* defines for codec.mode */ + +#define WSS_MODE_NONE 0x0000 +#define WSS_MODE_PLAY 0x0001 +#define WSS_MODE_RECORD 0x0002 +#define WSS_MODE_TIMER 0x0004 +#define WSS_MODE_OPEN (WSS_MODE_PLAY|WSS_MODE_RECORD|WSS_MODE_TIMER) + +/* defines for codec.hardware */ + +#define WSS_HW_DETECT 0x0000 /* let CS4231 driver detect chip */ +#define WSS_HW_DETECT3 0x0001 /* allow mode 3 */ +#define WSS_HW_TYPE_MASK 0xff00 /* type mask */ +#define WSS_HW_CS4231_MASK 0x0100 /* CS4231 serie */ +#define WSS_HW_CS4231 0x0100 /* CS4231 chip */ +#define WSS_HW_CS4231A 0x0101 /* CS4231A chip */ +#define WSS_HW_AD1845 0x0102 /* AD1845 chip */ +#define WSS_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */ +#define WSS_HW_CS4232 0x0200 /* CS4232 */ +#define WSS_HW_CS4232A 0x0201 /* CS4232A */ +#define WSS_HW_CS4236 0x0202 /* CS4236 */ +#define WSS_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */ +#define WSS_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */ +#define WSS_HW_CS4236B 0x0401 /* CS4236B */ +#define WSS_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */ +#define WSS_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */ +#define WSS_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */ +#define WSS_HW_AD1848_MASK 0x0800 /* AD1848 serie (half duplex) */ +#define WSS_HW_AD1847 0x0801 /* AD1847 chip */ +#define WSS_HW_AD1848 0x0802 /* AD1848 chip */ +#define WSS_HW_CS4248 0x0803 /* CS4248 chip */ +#define WSS_HW_CMI8330 0x0804 /* CMI8330 chip */ +#define WSS_HW_THINKPAD 0x0805 /* Thinkpad 360/750/755 */ +/* compatible, but clones */ +#define WSS_HW_INTERWAVE 0x1000 /* InterWave chip */ +#define WSS_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */ +#define WSS_HW_OPTI93X 0x1102 /* Opti 930/931/933 */ + +/* defines for codec.hwshare */ +#define WSS_HWSHARE_IRQ (1<<0) +#define WSS_HWSHARE_DMA1 (1<<1) +#define WSS_HWSHARE_DMA2 (1<<2) + +/* IBM Thinkpad specific stuff */ +#define AD1848_THINKPAD_CTL_PORT1 0x15e8 +#define AD1848_THINKPAD_CTL_PORT2 0x15e9 +#define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02 + +struct snd_wss { + unsigned long port; /* base i/o port */ + struct resource *res_port; + unsigned long cport; /* control base i/o port (CS4236) */ + struct resource *res_cport; + int irq; /* IRQ line */ + int dma1; /* playback DMA */ + int dma2; /* record DMA */ + unsigned short version; /* version of CODEC chip */ + unsigned short mode; /* see to WSS_MODE_XXXX */ + unsigned short hardware; /* see to WSS_HW_XXXX */ + unsigned short hwshare; /* shared resources */ + unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit */ + /* daughter board) or dma1 == dma2 */ + ebus_flag:1, /* SPARC: EBUS present */ + thinkpad_flag:1; /* Thinkpad CS4248 needs extra help */ + + struct snd_card *card; + struct snd_pcm *pcm; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + struct snd_timer *timer; + + unsigned char image[32]; /* registers image */ + unsigned char eimage[32]; /* extended registers image */ + unsigned char cimage[16]; /* control registers image */ + int mce_bit; + int calibrate_mute; + int sw_3d_bit; + unsigned int p_dma_size; + unsigned int c_dma_size; + + spinlock_t reg_lock; + struct mutex mce_mutex; + struct mutex open_mutex; + + int (*rate_constraint) (struct snd_pcm_runtime *runtime); + void (*set_playback_format) (struct snd_wss *chip, + struct snd_pcm_hw_params *hw_params, + unsigned char pdfr); + void (*set_capture_format) (struct snd_wss *chip, + struct snd_pcm_hw_params *hw_params, + unsigned char cdfr); + void (*trigger) (struct snd_wss *chip, unsigned int what, int start); +#ifdef CONFIG_PM + void (*suspend) (struct snd_wss *chip); + void (*resume) (struct snd_wss *chip); +#endif + void *dma_private_data; + int (*claim_dma) (struct snd_wss *chip, + void *dma_private_data, int dma); + int (*release_dma) (struct snd_wss *chip, + void *dma_private_data, int dma); +}; + +/* exported functions */ + +void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val); +unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg); +void snd_cs4236_ext_out(struct snd_wss *chip, + unsigned char reg, unsigned char val); +unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg); +void snd_wss_mce_up(struct snd_wss *chip); +void snd_wss_mce_down(struct snd_wss *chip); + +void snd_wss_overrange(struct snd_wss *chip); + +irqreturn_t snd_wss_interrupt(int irq, void *dev_id); + +const char *snd_wss_chip_id(struct snd_wss *chip); + +int snd_wss_create(struct snd_card *card, + unsigned long port, + unsigned long cport, + int irq, int dma1, int dma2, + unsigned short hardware, + unsigned short hwshare, + struct snd_wss **rchip); +int snd_wss_pcm(struct snd_wss *chip, int device); +int snd_wss_timer(struct snd_wss *chip, int device); +int snd_wss_mixer(struct snd_wss *chip); + +const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction); + +int snd_cs4236_create(struct snd_card *card, + unsigned long port, + unsigned long cport, + int irq, int dma1, int dma2, + unsigned short hardware, + unsigned short hwshare, + struct snd_wss **rchip); +int snd_cs4236_pcm(struct snd_wss *chip, int device); +int snd_cs4236_mixer(struct snd_wss *chip); + +/* + * mixer library + */ + +#define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_single, \ + .get = snd_wss_get_single, \ + .put = snd_wss_put_single, \ + .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } + +int snd_wss_info_single(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_wss_get_single(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_wss_put_single(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define WSS_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_double, \ + .get = snd_wss_get_double, \ + .put = snd_wss_put_double, \ + .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \ + (shift_right << 19) | (mask << 24) | (invert << 22) } + +#define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_single, \ + .get = snd_wss_get_single, \ + .put = snd_wss_put_single, \ + .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ + .tlv = { .p = (xtlv) } } + +#define WSS_DOUBLE_TLV(xname, xindex, left_reg, right_reg, \ + shift_left, shift_right, mask, invert, xtlv) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_double, \ + .get = snd_wss_get_double, \ + .put = snd_wss_put_double, \ + .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \ + (shift_right << 19) | (mask << 24) | (invert << 22), \ + .tlv = { .p = (xtlv) } } + + +int snd_wss_info_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_wss_get_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_wss_put_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#endif /* __SOUND_WSS_H */ -- cgit v1.3.1