From cf9610f9116d55c5a66ef9f1faecacabd93a9322 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Mon, 24 Aug 2026 08:46:03 -0700 Subject: Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ... --- drivers/video/fbdev/bt455.h | 90 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 drivers/video/fbdev/bt455.h (limited to 'drivers/video/fbdev/bt455.h') diff --git a/drivers/video/fbdev/bt455.h b/drivers/video/fbdev/bt455.h new file mode 100644 index 000000000..dd1404b40 --- /dev/null +++ b/drivers/video/fbdev/bt455.h @@ -0,0 +1,90 @@ +/* + * linux/drivers/video/bt455.h + * + * Copyright 2003 Thiemo Seufer + * Copyright 2016 Maciej W. Rozycki + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + */ +#include + +/* + * Bt455 byte-wide registers, 32-bit aligned. + */ +struct bt455_regs { + volatile u8 addr_cmap; + u8 pad0[3]; + volatile u8 addr_cmap_data; + u8 pad1[3]; + volatile u8 addr_clr; + u8 pad2[3]; + volatile u8 addr_ovly; + u8 pad3[3]; +}; + +static inline void bt455_select_reg(struct bt455_regs *regs, int ir) +{ + mb(); + regs->addr_cmap = ir & 0x0f; +} + +static inline void bt455_reset_reg(struct bt455_regs *regs) +{ + mb(); + regs->addr_clr = 0; +} + +/* + * Read/write to a Bt455 color map register. + */ +static inline void bt455_read_cmap_next(struct bt455_regs *regs, u8 *grey) +{ + mb(); + regs->addr_cmap_data; + rmb(); + *grey = regs->addr_cmap_data & 0xf; + rmb(); + regs->addr_cmap_data; +} + +static inline void bt455_write_cmap_next(struct bt455_regs *regs, u8 grey) +{ + wmb(); + regs->addr_cmap_data = 0x0; + wmb(); + regs->addr_cmap_data = grey & 0xf; + wmb(); + regs->addr_cmap_data = 0x0; +} + +static inline void bt455_write_ovly_next(struct bt455_regs *regs, u8 grey) +{ + wmb(); + regs->addr_ovly = 0x0; + wmb(); + regs->addr_ovly = grey & 0xf; + wmb(); + regs->addr_ovly = 0x0; +} + +static inline void bt455_read_cmap_entry(struct bt455_regs *regs, + int cr, u8 *grey) +{ + bt455_select_reg(regs, cr); + bt455_read_cmap_next(regs, grey); +} + +static inline void bt455_write_cmap_entry(struct bt455_regs *regs, + int cr, u8 grey) +{ + bt455_select_reg(regs, cr); + bt455_write_cmap_next(regs, grey); +} + +static inline void bt455_write_ovly_entry(struct bt455_regs *regs, u8 grey) +{ + bt455_reset_reg(regs); + bt455_write_ovly_next(regs, grey); +} -- cgit v1.3.1