From 27600805e62f800bacf990354632eae4e487d34c Mon Sep 17 00:00:00 2001 From: Yazen Ghannam Date: Thu, 3 Sep 2026 10:43:25 -0500 Subject: x86/amd_node: Fix PCI device reference counting in amd_smn_init() The local "root" pointer is a temporary variable used during the device search. Therefore, refcount related to the search iterators should be cleaned up after the search is complete. Use the __free() cleanup macro to ensure the refcount is decremented when the temporary pointer goes out of scope. Additionally, increment the refcount when caching a root pointer. This ensures the in-use refcount is separate from the temporary search refcounting. Finally, drop the redundant "root = NULL" before the second search loop. The pci_get_class() iterator always decrements the refcount of its "from" argument, so the first loop can only fall through with "root" already NULL. Fixes: 0a4b61d9c2e4 ("x86/amd_node: Fix AMD root device caching") Closes: https://sashiko.dev/#/patchset/20260806160159.230453-1-jason.andryuk%40amd.com Reported-by: Sashiko Assisted-by: LLM Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Mario Limonciello (AMD) Cc: Link: https://patch.msgid.link/20260903154325.74343-1-yazen.ghannam@amd.com --- drivers/soc/tegra/Kconfig | 198 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 drivers/soc/tegra/Kconfig (limited to 'drivers/soc/tegra/Kconfig') diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig new file mode 100644 index 000000000..8b6fdb9ad --- /dev/null +++ b/drivers/soc/tegra/Kconfig @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: GPL-2.0-only +if ARCH_TEGRA + +# 32-bit ARM SoCs +if ARM + +config ARCH_TEGRA_2x_SOC + bool "Enable support for Tegra20 family" + default ARCH_TEGRA + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARM_ERRATA_720789 + select ARM_ERRATA_754327 if SMP + select ARM_ERRATA_764369 if SMP + select PINCTRL_TEGRA20 + select PL310_ERRATA_727915 if CACHE_L2X0 + select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_FLOWCTRL + select SOC_TEGRA_PMC + select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR + select TEGRA_TIMER + help + Support for NVIDIA Tegra AP20 and T20 processors, based on the + ARM CortexA9MP CPU and the ARM PL310 L2 cache controller + +config ARCH_TEGRA_3x_SOC + bool "Enable support for Tegra30 family" + default ARCH_TEGRA + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 if SMP + select PINCTRL_TEGRA30 + select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_FLOWCTRL + select SOC_TEGRA_PMC + select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR + select TEGRA_TIMER + help + Support for NVIDIA Tegra T30 processor family, based on the + ARM CortexA9MP CPU and the ARM PL310 L2 cache controller + +config ARCH_TEGRA_114_SOC + bool "Enable support for Tegra114 family" + default ARCH_TEGRA + select ARM_ERRATA_798181 if SMP + select HAVE_ARM_ARCH_TIMER + select PINCTRL_TEGRA114 + select SOC_TEGRA_FLOWCTRL + select SOC_TEGRA_PMC + select TEGRA_TIMER + help + Support for NVIDIA Tegra T114 processor family, based on the + ARM CortexA15MP CPU + +config ARCH_TEGRA_124_SOC + bool "Enable support for Tegra124 family" + default ARCH_TEGRA + select HAVE_ARM_ARCH_TIMER + select PINCTRL_TEGRA124 + select SOC_TEGRA_FLOWCTRL + select SOC_TEGRA_PMC + select TEGRA_TIMER + help + Support for NVIDIA Tegra T124 processor family, based on the + ARM CortexA15MP CPU + +endif + +# 64-bit ARM SoCs +if ARM64 + +config ARCH_TEGRA_132_SOC + bool "NVIDIA Tegra132 SoC" + default ARCH_TEGRA + select PINCTRL_TEGRA124 + select SOC_TEGRA_FLOWCTRL + select SOC_TEGRA_PMC + help + Enable support for NVIDIA Tegra132 SoC, based on the Denver + ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, + but contains an NVIDIA Denver CPU complex in place of + Tegra124's "4+1" Cortex-A15 CPU complex. + +config ARCH_TEGRA_210_SOC + bool "NVIDIA Tegra210 SoC" + default ARCH_TEGRA + select PINCTRL_TEGRA210 + select SOC_TEGRA_FLOWCTRL + select SOC_TEGRA_PMC + select TEGRA_TIMER + help + Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, + the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 + cores in a switched configuration. It features a GPU of the Maxwell + architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 + and providing 256 CUDA cores. It supports hardware-accelerated en- + and decoding of various video standards including H.265, H.264 and + VP8 at 4K resolution and up to 60 fps. + + Besides the multimedia features it also comes with a variety of I/O + controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to + name only a few. + +config ARCH_TEGRA_186_SOC + bool "NVIDIA Tegra186 SoC" + default ARCH_TEGRA + depends on !CPU_BIG_ENDIAN + select PINCTRL_TEGRA186 + select MAILBOX + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a + combination of Denver and Cortex-A57 CPU cores and a GPU based on + the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU + used for audio processing, hardware video encoders/decoders with + multi-format support, ISP for image capture processing and BPMP for + power management. + +config ARCH_TEGRA_194_SOC + bool "NVIDIA Tegra194 SoC" + default ARCH_TEGRA + depends on !CPU_BIG_ENDIAN + select MAILBOX + select PINCTRL_TEGRA194 + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra194 SoC. + +config ARCH_TEGRA_234_SOC + bool "NVIDIA Tegra234 SoC" + default ARCH_TEGRA + depends on !CPU_BIG_ENDIAN + select MAILBOX + select PINCTRL_TEGRA234 + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra234 SoC. + +config ARCH_TEGRA_238_SOC + bool "NVIDIA Tegra238 SoC" + default ARCH_TEGRA + depends on !CPU_BIG_ENDIAN + select MAILBOX + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra238 SoC. + +config ARCH_TEGRA_241_SOC + bool "NVIDIA Tegra241 SoC" + default ARCH_TEGRA + help + Enable support for the NVIDIA Tegra241 SoC. + +config ARCH_TEGRA_264_SOC + bool "NVIDIA Tegra264 SoC" + default ARCH_TEGRA + depends on !CPU_BIG_ENDIAN + select MAILBOX + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra264 SoC. + +endif +endif + +config SOC_TEGRA_FUSE + def_bool y + depends on ARCH_TEGRA + select SOC_BUS + +config SOC_TEGRA_FLOWCTRL + bool + +config SOC_TEGRA_PMC + bool + depends on PM + select GENERIC_PINCONF + select IRQ_DOMAIN_HIERARCHY + select PM_OPP + select PM_GENERIC_DOMAINS + select REGMAP + +config SOC_TEGRA20_VOLTAGE_COUPLER + bool "Voltage scaling support for Tegra20 SoCs" + depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST + depends on REGULATOR + +config SOC_TEGRA30_VOLTAGE_COUPLER + bool "Voltage scaling support for Tegra30 SoCs" + depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST + depends on REGULATOR + +config SOC_TEGRA_CBB + tristate "Tegra driver to handle error from CBB" + depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC + default y + help + Support for handling error from Tegra Control Backbone(CBB). + This driver handles the errors from CBB and prints debug + information about the failed transactions. -- cgit v1.3.1