From f4cdf7ca9a1fdcca413157df19753f388a5a224e Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 19 Aug 2026 10:09:22 -0700 Subject: Merge tag 'media/v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - v4l2-core: added ISP statistics support and per-block validation - v4l2-core: Allow unknown HDR10 white point and luminance - New camera sensors: Sony IMX678 and IMX471m, Himax HM1092 IR sensor - New codec: Milos: VPU v2.0 codec support - isp driver: gained support for Dreamchip RPPX1 ISP framework - vsp1 driver: gained support for RZ/T2H and RZ/N2H - Novalake driver: gained CVS support for new NVL hardware - dvb-core: fix feed leak on failed DMX_ADD_PID - several driver fixes, cleanups and minor improvements * tag 'media/v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (308 commits) media: ipu-bridge: check all DMI entries when overriding sensor rotation media: v4l2-async: avoid deleting unlinked ASC entry on link error media: rzg2l-cru: Align bytesperline to hardware DMA stride requirement media: intel/ipu6: fix async notifier cleanup leak on parse error media: staging/ipu7: fix async notifier UAF on probe error path media: amd: isp4: fix self-deadlock in isp4sd_pwron_and_init() error path media: amd: isp4: release partial allocations in isp4if_alloc_fw_gpumem() media: rcar-isp: Fix VSPX reference leaks media: rcar-isp: Release ISPCORE resources media: i2c: imx415: Release runtime PM reference on VBLANK error media: i2c: imx415: Return test pattern write errors media: renesas: vsp1: Declare index variables in for loop statement media: renesas: vsp1: Make reset control optional to support platforms without a reset line media: dt-bindings: media: renesas,vsp1: Document RZ/T2H and RZ/N2H SoCs media: dt-bindings: media: renesas,fcp: Document RZ/T2H and RZ/N2H SoCs media: nxp: imx8-isi: Add additional 32-bit RGB format support media: nxp: imx8-isi: Add 16-bit raw Bayer format support media: nxp: imx8-isi: Implement per-stream reference counting for multiplexed streams media: nxp: imx8-isi: Use BIT_ULL() for 64-bit stream masks media: nxp: imx8-isi: Correct color map between V4L2 and ISI ... --- drivers/pinctrl/sunplus/sppctl.h | 170 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 drivers/pinctrl/sunplus/sppctl.h (limited to 'drivers/pinctrl/sunplus/sppctl.h') diff --git a/drivers/pinctrl/sunplus/sppctl.h b/drivers/pinctrl/sunplus/sppctl.h new file mode 100644 index 000000000..6210f2200 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#ifndef __SPPCTL_H__ +#define __SPPCTL_H__ + +#include +#include +#include +#include +#include +#include + +#define SPPCTL_MODULE_NAME "sppctl_sp7021" + +#define SPPCTL_GPIO_OFF_FIRST 0x00 +#define SPPCTL_GPIO_OFF_MASTER 0x00 +#define SPPCTL_GPIO_OFF_OE 0x20 +#define SPPCTL_GPIO_OFF_OUT 0x40 +#define SPPCTL_GPIO_OFF_IN 0x60 +#define SPPCTL_GPIO_OFF_IINV 0x80 +#define SPPCTL_GPIO_OFF_OINV 0xa0 +#define SPPCTL_GPIO_OFF_OD 0xc0 + +#define SPPCTL_FULLY_PINMUX_MASK_MASK GENMASK(22, 16) +#define SPPCTL_FULLY_PINMUX_SEL_MASK GENMASK(6, 0) +#define SPPCTL_FULLY_PINMUX_UPPER_SHIFT 8 + +/* + * Mask-fields and control-fields of MOON registers of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + */ +#define SPPCTL_MOON_REG_MASK_SHIFT 16 +#define SPPCTL_SET_MOON_REG_BIT(bit) (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit)) +#define SPPCTL_CLR_MOON_REG_BIT(bit) BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) + +#define SPPCTL_IOP_CONFIGS 0xff + +#define FNCE(n, r, o, bo, bl, g) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = (g), \ + .gnum = ARRAY_SIZE(g), \ +} + +#define FNCN(n, r, o, bo, bl) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = NULL, \ + .gnum = 0, \ +} + +#define EGRP(n, v, p) { \ + .name = n, \ + .gval = (v), \ + .pins = (p), \ + .pnum = ARRAY_SIZE(p), \ +} + +/** + * enum mux_first_reg - Define modes of access of FIRST register + * @mux_f_mux: Set the corresponding pin to a fully-pinmux pin + * @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin + * @mux_f_keep: Don't change (keep intact) + */ +enum mux_first_reg { + mux_f_mux = 0, + mux_f_gpio = 1, + mux_f_keep = 2, +}; + +/** + * enum mux_master_reg - Define modes of access of MASTER register + * @mux_m_iop: Set the corresponding pin to an IO processor (IOP) pin + * @mux_m_gpio: Set the corresponding pin to a digital GPIO pin + * @mux_m_keep: Don't change (keep intact) + */ +enum mux_master_reg { + mux_m_iop = 0, + mux_m_gpio = 1, + mux_m_keep = 2, +}; + +/** + * enum pinmux_type - Define types of pinmux pins + * @pinmux_type_fpmx: A fully-pinmux pin + * @pinmux_type_grp: A group-pinmux pin + */ +enum pinmux_type { + pinmux_type_fpmx, + pinmux_type_grp, +}; + +/** + * struct grp2fp_map - A map storing indexes + * @f_idx: an index to function table + * @g_idx: an index to group table + */ +struct grp2fp_map { + u16 f_idx; + u16 g_idx; +}; + +struct sppctl_gpio_chip; + +struct sppctl_pdata { + void __iomem *moon2_base; /* MOON2 */ + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* FIRST */ + void __iomem *moon1_base; /* MOON1 */ + + struct pinctrl_desc pctl_desc; + struct pinctrl_dev *pctl_dev; + struct pinctrl_gpio_range pctl_grange; + struct sppctl_gpio_chip *spp_gchip; + + char const **unq_grps; + size_t unq_grps_sz; + struct grp2fp_map *g2fp_maps; +}; + +struct sppctl_grp { + const char * const name; + const u8 gval; /* group number */ + const unsigned * const pins; /* list of pins */ + const unsigned int pnum; /* number of pins */ +}; + +struct sppctl_func { + const char * const name; + const enum pinmux_type type; /* function type */ + const u8 roff; /* register offset */ + const u8 boff; /* bit offset */ + const u8 blen; /* bit length */ + const struct sppctl_grp * const grps; /* list of groups */ + const unsigned int gnum; /* number of groups */ +}; + +extern const struct sppctl_func sppctl_list_funcs[]; +extern const char * const sppctl_pmux_list_s[]; +extern const char * const sppctl_gpio_list_s[]; +extern const struct pinctrl_pin_desc sppctl_pins_all[]; +extern const unsigned int sppctl_pins_gpio[]; + +extern const size_t sppctl_list_funcs_sz; +extern const size_t sppctl_pmux_list_sz; +extern const size_t sppctl_gpio_list_sz; +extern const size_t sppctl_pins_all_sz; + +#endif -- cgit v1.3.1