From a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255 Mon Sep 17 00:00:00 2001 From: Jinke Han Date: Tue, 8 Sep 2026 15:37:42 +0800 Subject: x86/kprobes: Fix crash when probing CS CALL instructions When using eBPF to probe CS CALL instructions within a function, a crash can be triggered. The eBPF tool probes offset 257 of the __hrtimer_run_queues() function: <__hrtimer_run_queues+249>: nopl 0x0(%rax,%rax,1) <__hrtimer_run_queues+254>: mov %r14,%rdi <__hrtimer_run_queues+257>: cs call <__x86_indirect_thunk_r12> <__hrtimer_run_queues+263>: mov %eax,%r12d <__hrtimer_run_queues+266>: xchg %ax,%ax <__hrtimer_run_queues+268>: mov %r13,%rdi Which triggers this crash: BUG: unable to handle page fault for address: 00000000000f41c9 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP NOPTI CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: P RIP: 0010:__hrtimer_run_queues+0x106/0x230 Note that __hrtimer_run_queues+0x106 is __hrtimer_run_queues+262, which is at the 6th byte of the above CS CALL instruction. Since the CS CALL instruction occupies 6 bytes, the exception occurred in the middle of that call instruction. The root cause is that when using eBPF tools to probe in the middle of a function, a kprobe with INT3 is used as the underlying implementation. During single-step emulation of the original CALL instruction, int3_emulate_call() assumes that the probed CALL instruction is 5 bytes long. However, the actual CS-prefixed CALL instruction occupies 6 bytes, so it constructs an incorrect exception return address. When the CPU returns from the kprobe handler, the next instruction to be executed is at the address of the last byte of that CS CALL instruction. Coincidentally, starting from that address, the CPU fetches and decodes a completely different instruction, which ultimately triggers a kernel crash. Fix the issue by using the actual instruction length obtained from the instruction decoder when constructing the exception return address, rather than relying on the hardcoded CALL_INSN_SIZE macro. [ mingo: Refined the changelog ] Fixes: 6256e668b7af ("x86/kprobes: Use int3 instead of debug trap for single-step") Suggested-by: Masami Hiramatsu (Google) Signed-off-by: Jinke Han Signed-off-by: Ingo Molnar Reviewed-by: Masami Hiramatsu (Google) Acked-by: Yafang Shao Acked-by: Borislav Petkov Cc: Peter Zijlstra Link: https://patch.msgid.link/20260908073742.GA10517@didi-ThinkCentre-M920t-N000 --- drivers/pinctrl/intel/Kconfig | 175 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 drivers/pinctrl/intel/Kconfig (limited to 'drivers/pinctrl/intel/Kconfig') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig new file mode 100644 index 000000000..04c3a5b58 --- /dev/null +++ b/drivers/pinctrl/intel/Kconfig @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: GPL-2.0 +# Intel pin control drivers +menu "Intel pinctrl drivers" + depends on (ACPI && X86) || COMPILE_TEST + +config PINCTRL_BAYTRAIL + bool "Intel Baytrail GPIO pin control" + select PINCTRL_INTEL + help + driver for memory mapped GPIO functionality on Intel Baytrail + platforms. Supports 3 banks with 102, 28 and 44 gpios. + Most pins are usually muxed to some other functionality by firmware, + so only a small amount is available for gpio use. + + Requires ACPI device enumeration code to set up a platform device. + +config PINCTRL_CHERRYVIEW + tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" + select PINCTRL_INTEL + help + Cherryview/Braswell pinctrl driver provides an interface that + allows configuring of SoC pins and using them as GPIOs. + +config PINCTRL_LYNXPOINT + tristate "Intel Lynxpoint pinctrl and GPIO driver" + select PINCTRL_INTEL + help + Lynxpoint is the PCH of Intel Haswell. This pinctrl driver + provides an interface that allows configuring of PCH pins and + using them as GPIOs. + +config PINCTRL_INTEL + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + +config PINCTRL_INTEL_PLATFORM + tristate "Intel pinctrl and GPIO platform driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel PCH pins and using them as GPIOs. Currently the following + Intel SoCs / platforms require this to be functional: + - Lunar Lake + - Nova Lake + - Panther Lake + +config PINCTRL_ALDERLAKE + tristate "Intel Alder Lake pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + PCH pins of the following platforms and using them as GPIOs: + - Alder Lake HX, N, and S + - Raptor Lake HX, E, and S + - Twin Lake + +config PINCTRL_BROXTON + tristate "Intel Broxton pinctrl and GPIO driver" + select PINCTRL_INTEL + help + Broxton pinctrl driver provides an interface that allows + configuring of SoC pins and using them as GPIOs. + +config PINCTRL_CANNONLAKE + tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Cannon Lake PCH pins and using them as GPIOs. + +config PINCTRL_CEDARFORK + tristate "Intel Cedar Fork pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Cedar Fork PCH pins and using them as GPIOs. + +config PINCTRL_DENVERTON + tristate "Intel Denverton pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Denverton SoC pins and using them as GPIOs. + +config PINCTRL_ELKHARTLAKE + tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Elkhart Lake SoC pins and using them as GPIOs. + +config PINCTRL_EMMITSBURG + tristate "Intel Emmitsburg pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Emmitsburg pins and using them as GPIOs. + +config PINCTRL_GEMINILAKE + tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Gemini Lake SoC pins and using them as GPIOs. + +config PINCTRL_ICELAKE + tristate "Intel Ice Lake PCH pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Ice Lake PCH pins and using them as GPIOs. + +config PINCTRL_JASPERLAKE + tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Jasper Lake PCH pins and using them as GPIOs. + +config PINCTRL_LAKEFIELD + tristate "Intel Lakefield SoC pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Lakefield SoC pins and using them as GPIOs. + +config PINCTRL_LEWISBURG + tristate "Intel Lewisburg pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Lewisburg pins and using them as GPIOs. + +config PINCTRL_METEORLAKE + tristate "Intel Meteor Lake pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + SoC pins of the following platforms and using them as GPIOs: + - Arrow Lake (all variants) + - Meteor Lake (all variants) + +config PINCTRL_METEORPOINT + tristate "Intel Meteor Point pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + PCH pins of the following platforms and using them as GPIOs: + - Arrow Lake HX and S + +config PINCTRL_SUNRISEPOINT + tristate "Intel Sunrisepoint pinctrl and GPIO driver" + select PINCTRL_INTEL + help + Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver + provides an interface that allows configuring of PCH pins and + using them as GPIOs. + +config PINCTRL_TIGERLAKE + tristate "Intel Tiger Lake pinctrl and GPIO driver" + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + PCH pins of the following platforms and using them as GPIOs: + - Alder Lake H, P, PS, and U + - Raptor Lake H, P, PS, PX, and U + - Rocket Lake S + - Tiger Lake (all variants) + +source "drivers/pinctrl/intel/Kconfig.tng" +endmenu -- cgit v1.3.1