From 9f0346dcbea363787186c94ef94dd01aaa215afa Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 5 Sep 2026 11:59:05 -0700 Subject: Merge tag 'driver-core-7.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core Pull driver core fixes from Danilo Krummrich: - Fix kernfs listxattr() not returning security xattr names (e.g. SELinux labels) when the kernfs node has no allocated kernfs_iattrs - Fix silent truncation of IRQ vector indices in the Rust PCI abstractions - Don't select OF from DRIVER_PE_KUNIT_TEST; skip the test when OF is disabled instead of silently enabling extra kernel functionality - Russ Weight is retiring from kernel development; update the Firmware Loader sysfs contact to the driver-core mailing list, add a CREDITS entry for Firmware Upload, and update MAINTAINERS accordingly * tag 'driver-core-7.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core: MAINTAINERS: Remove Russ Weight from Firmware Loader CREDITS: Add CREDITS entry for Firmware Upload firmware_loader: Change contact for sysfs nodes rust: pci: reject IRQ vector indices that do not fit in u32 kernfs: preserve security xattrs without allocating iattrs drivers: base: test: DRIVER_PE_KUNIT_TEST should not select OF --- drivers/pinctrl/aspeed/Kconfig | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 drivers/pinctrl/aspeed/Kconfig (limited to 'drivers/pinctrl/aspeed/Kconfig') diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig new file mode 100644 index 000000000..8e1d4da08 --- /dev/null +++ b/drivers/pinctrl/aspeed/Kconfig @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_ASPEED + bool + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select MFD_SYSCON + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + +config PINCTRL_ASPEED_G4 + bool "Aspeed G4 SoC pin control" + depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 4th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G6 + bool "Aspeed G6 SoC pin control" + depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 6th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G7_SOC0 + bool "Aspeed G7 SoC pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for the SoC0 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. + +config PINCTRL_ASPEED_G7_SOC1 + bool "Aspeed G7 SoC1 pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select MFD_SYSCON + select PINMUX + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to enable pin controller support for the SoC1 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. -- cgit v1.3.1