From 4617721c502b2ddaa4e324e86da4997edf738fa5 Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Wed, 2 Sep 2026 09:55:01 -0400 Subject: ftrace: Synchronize the initialization of ftrace_ops There's some internal state that ftrace_ops needs to have set, but since it can be declared outside of the ftrace.c code, it calls ftrace_ops_init() on the ops in every global function. The issue is that if two tasks call it on the same ops at the same time it is possible to have the initialization of one corrupt the initialization of the other call. Create a ops_mutex to use to synchronize every initialization of the ftrace_ops. The mutex is taken within checking the ftrace_ops flag that states it was initializied but the flag is checked again after the mutex has been taken. Checking first outside the mutex allows it to shortcut having to take the mutex. But then the check needs to be done again after the mute is taken in case of races. Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260902095501.6b59af20@gandalf.local.home Fixes: f04f24fb7e48d ("ftrace, kprobes: Fix a deadlock on ftrace_regex_lock") Reported-by: sashiko-bot@kernel.org Close: https://lore.kernel.org/all/20260829025528.49A831F000E9@smtp.kernel.org/ Signed-off-by: Steven Rostedt --- drivers/pinctrl/aspeed/Kconfig | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 drivers/pinctrl/aspeed/Kconfig (limited to 'drivers/pinctrl/aspeed/Kconfig') diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig new file mode 100644 index 000000000..8e1d4da08 --- /dev/null +++ b/drivers/pinctrl/aspeed/Kconfig @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_ASPEED + bool + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select MFD_SYSCON + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + +config PINCTRL_ASPEED_G4 + bool "Aspeed G4 SoC pin control" + depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 4th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G6 + bool "Aspeed G6 SoC pin control" + depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 6th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G7_SOC0 + bool "Aspeed G7 SoC pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for the SoC0 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. + +config PINCTRL_ASPEED_G7_SOC1 + bool "Aspeed G7 SoC1 pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select MFD_SYSCON + select PINMUX + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to enable pin controller support for the SoC1 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. -- cgit v1.3.1