From 2bc6b218717b9d08f466f88209251d54bc09b207 Mon Sep 17 00:00:00 2001 From: Fuad Tabba Date: Tue, 22 Sep 2026 19:14:30 +0100 Subject: arm64/boot: Disable trapping of PMZR_EL0 writes to EL2 __init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2. PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a write from EL0 reaches the trap and takes the host down without a panic message. Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9 bits. Fixes: 858c7bfcb35e1 ("arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9") Cc: stable@vger.kernel.org Signed-off-by: Fuad Tabba Reviewed-by: Anshuman Khandual Reviewed-by: Oliver Upton Signed-off-by: Will Deacon --- drivers/phy/Makefile | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 drivers/phy/Makefile (limited to 'drivers/phy/Makefile') diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile new file mode 100644 index 000000000..d7aa516bc --- /dev/null +++ b/drivers/phy/Makefile @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the phy drivers. +# + +obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o +obj-$(CONFIG_PHY_COMMON_PROPS_TEST) += phy-common-props-test.o +obj-$(CONFIG_GENERIC_PHY) += phy-core.o +obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o +obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o +obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o +obj-$(CONFIG_PHY_ECONET_PCIE) += phy-econet-pcie.o +obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o +obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o +obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o +obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o +obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o +obj-$(CONFIG_PHY_NXP_TJA1145) += phy-nxp-tja1145.o +obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o +obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o +obj-$(CONFIG_PHY_XGENE) += phy-xgene.o + +obj-$(CONFIG_GENERIC_PHY) += allwinner/ \ + amlogic/ \ + apple/ \ + axiado/ \ + broadcom/ \ + cadence/ \ + canaan/ \ + eswin/ \ + freescale/ \ + hisilicon/ \ + ingenic/ \ + intel/ \ + lantiq/ \ + marvell/ \ + mediatek/ \ + microchip/ \ + motorola/ \ + mscc/ \ + nuvoton/ \ + qualcomm/ \ + ralink/ \ + realtek/ \ + renesas/ \ + rockchip/ \ + samsung/ \ + socionext/ \ + sophgo/ \ + spacemit/ \ + st/ \ + starfive/ \ + sunplus/ \ + tegra/ \ + ti/ \ + xilinx/ -- cgit v1.3.1