From a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255 Mon Sep 17 00:00:00 2001 From: Jinke Han Date: Tue, 8 Sep 2026 15:37:42 +0800 Subject: x86/kprobes: Fix crash when probing CS CALL instructions When using eBPF to probe CS CALL instructions within a function, a crash can be triggered. The eBPF tool probes offset 257 of the __hrtimer_run_queues() function: <__hrtimer_run_queues+249>: nopl 0x0(%rax,%rax,1) <__hrtimer_run_queues+254>: mov %r14,%rdi <__hrtimer_run_queues+257>: cs call <__x86_indirect_thunk_r12> <__hrtimer_run_queues+263>: mov %eax,%r12d <__hrtimer_run_queues+266>: xchg %ax,%ax <__hrtimer_run_queues+268>: mov %r13,%rdi Which triggers this crash: BUG: unable to handle page fault for address: 00000000000f41c9 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP NOPTI CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: P RIP: 0010:__hrtimer_run_queues+0x106/0x230 Note that __hrtimer_run_queues+0x106 is __hrtimer_run_queues+262, which is at the 6th byte of the above CS CALL instruction. Since the CS CALL instruction occupies 6 bytes, the exception occurred in the middle of that call instruction. The root cause is that when using eBPF tools to probe in the middle of a function, a kprobe with INT3 is used as the underlying implementation. During single-step emulation of the original CALL instruction, int3_emulate_call() assumes that the probed CALL instruction is 5 bytes long. However, the actual CS-prefixed CALL instruction occupies 6 bytes, so it constructs an incorrect exception return address. When the CPU returns from the kprobe handler, the next instruction to be executed is at the address of the last byte of that CS CALL instruction. Coincidentally, starting from that address, the CPU fetches and decodes a completely different instruction, which ultimately triggers a kernel crash. Fix the issue by using the actual instruction length obtained from the instruction decoder when constructing the exception return address, rather than relying on the hardcoded CALL_INSN_SIZE macro. [ mingo: Refined the changelog ] Fixes: 6256e668b7af ("x86/kprobes: Use int3 instead of debug trap for single-step") Suggested-by: Masami Hiramatsu (Google) Signed-off-by: Jinke Han Signed-off-by: Ingo Molnar Reviewed-by: Masami Hiramatsu (Google) Acked-by: Yafang Shao Acked-by: Borislav Petkov Cc: Peter Zijlstra Link: https://patch.msgid.link/20260908073742.GA10517@didi-ThinkCentre-M920t-N000 --- drivers/mfd/vx855.c | 123 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 drivers/mfd/vx855.c (limited to 'drivers/mfd/vx855.c') diff --git a/drivers/mfd/vx855.c b/drivers/mfd/vx855.c new file mode 100644 index 000000000..985f81c17 --- /dev/null +++ b/drivers/mfd/vx855.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Linux multi-function-device driver (MFD) for the integrated peripherals + * of the VIA VX855 chipset + * + * Copyright (C) 2009 VIA Technologies, Inc. + * Copyright (C) 2010 One Laptop per Child + * Author: Harald Welte + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +/* offset into pci config space indicating the 16bit register containing + * the power management IO space base */ +#define VX855_CFG_PMIO_OFFSET 0x88 + +/* ACPI I/O Space registers */ +#define VX855_PMIO_ACPI 0x00 +#define VX855_PMIO_ACPI_LEN 0x0b + +/* Processor Power Management */ +#define VX855_PMIO_PPM 0x10 +#define VX855_PMIO_PPM_LEN 0x08 + +/* General Purpose Power Management */ +#define VX855_PMIO_GPPM 0x20 +#define VX855_PMIO_R_GPI 0x48 +#define VX855_PMIO_R_GPO 0x4c +#define VX855_PMIO_GPPM_LEN 0x33 + +#define VSPIC_MMIO_SIZE 0x1000 + +static struct resource vx855_gpio_resources[] = { + { + .flags = IORESOURCE_IO, + }, + { + .flags = IORESOURCE_IO, + }, +}; + +static const struct mfd_cell vx855_cells[] = { + { + .name = "vx855_gpio", + .num_resources = ARRAY_SIZE(vx855_gpio_resources), + .resources = vx855_gpio_resources, + + /* we must ignore resource conflicts, for reasons outlined in + * the vx855_gpio driver */ + .ignore_resource_conflicts = true, + }, +}; + +static int vx855_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + int ret; + u16 gpio_io_offset; + + ret = pci_enable_device(pdev); + if (ret) + return -ENODEV; + + pci_read_config_word(pdev, VX855_CFG_PMIO_OFFSET, &gpio_io_offset); + if (!gpio_io_offset) { + dev_warn(&pdev->dev, + "BIOS did not assign PMIO base offset?!?\n"); + ret = -ENODEV; + goto out; + } + + /* mask out the lowest seven bits, as they are always zero, but + * hardware returns them as 0x01 */ + gpio_io_offset &= 0xff80; + + /* As the region identified here includes many non-GPIO things, we + * only work with the specific registers that concern us. */ + vx855_gpio_resources[0].start = gpio_io_offset + VX855_PMIO_R_GPI; + vx855_gpio_resources[0].end = vx855_gpio_resources[0].start + 3; + vx855_gpio_resources[1].start = gpio_io_offset + VX855_PMIO_R_GPO; + vx855_gpio_resources[1].end = vx855_gpio_resources[1].start + 3; + + ret = mfd_add_devices(&pdev->dev, -1, vx855_cells, ARRAY_SIZE(vx855_cells), + NULL, 0, NULL); + + /* we always return -ENODEV here in order to enable other + * drivers like old, not-yet-platform_device ported i2c-viapro */ + return -ENODEV; +out: + pci_disable_device(pdev); + return ret; +} + +static void vx855_remove(struct pci_dev *pdev) +{ + mfd_remove_devices(&pdev->dev); + pci_disable_device(pdev); +} + +static const struct pci_device_id vx855_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) }, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, vx855_pci_tbl); + +static struct pci_driver vx855_pci_driver = { + .name = "vx855", + .id_table = vx855_pci_tbl, + .probe = vx855_probe, + .remove = vx855_remove, +}; + +module_pci_driver(vx855_pci_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Harald Welte "); +MODULE_DESCRIPTION("Driver for the VIA VX855 chipset"); -- cgit v1.3.1