From a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255 Mon Sep 17 00:00:00 2001 From: Jinke Han Date: Tue, 8 Sep 2026 15:37:42 +0800 Subject: x86/kprobes: Fix crash when probing CS CALL instructions When using eBPF to probe CS CALL instructions within a function, a crash can be triggered. The eBPF tool probes offset 257 of the __hrtimer_run_queues() function: <__hrtimer_run_queues+249>: nopl 0x0(%rax,%rax,1) <__hrtimer_run_queues+254>: mov %r14,%rdi <__hrtimer_run_queues+257>: cs call <__x86_indirect_thunk_r12> <__hrtimer_run_queues+263>: mov %eax,%r12d <__hrtimer_run_queues+266>: xchg %ax,%ax <__hrtimer_run_queues+268>: mov %r13,%rdi Which triggers this crash: BUG: unable to handle page fault for address: 00000000000f41c9 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP NOPTI CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: P RIP: 0010:__hrtimer_run_queues+0x106/0x230 Note that __hrtimer_run_queues+0x106 is __hrtimer_run_queues+262, which is at the 6th byte of the above CS CALL instruction. Since the CS CALL instruction occupies 6 bytes, the exception occurred in the middle of that call instruction. The root cause is that when using eBPF tools to probe in the middle of a function, a kprobe with INT3 is used as the underlying implementation. During single-step emulation of the original CALL instruction, int3_emulate_call() assumes that the probed CALL instruction is 5 bytes long. However, the actual CS-prefixed CALL instruction occupies 6 bytes, so it constructs an incorrect exception return address. When the CPU returns from the kprobe handler, the next instruction to be executed is at the address of the last byte of that CS CALL instruction. Coincidentally, starting from that address, the CPU fetches and decodes a completely different instruction, which ultimately triggers a kernel crash. Fix the issue by using the actual instruction length obtained from the instruction decoder when constructing the exception return address, rather than relying on the hardcoded CALL_INSN_SIZE macro. [ mingo: Refined the changelog ] Fixes: 6256e668b7af ("x86/kprobes: Use int3 instead of debug trap for single-step") Suggested-by: Masami Hiramatsu (Google) Signed-off-by: Jinke Han Signed-off-by: Ingo Molnar Reviewed-by: Masami Hiramatsu (Google) Acked-by: Yafang Shao Acked-by: Borislav Petkov Cc: Peter Zijlstra Link: https://patch.msgid.link/20260908073742.GA10517@didi-ThinkCentre-M920t-N000 --- drivers/gpu/drm/mgag200/Kconfig | 24 + drivers/gpu/drm/mgag200/Makefile | 19 + drivers/gpu/drm/mgag200/mgag200_bmc.c | 92 ++++ drivers/gpu/drm/mgag200/mgag200_ddc.c | 178 +++++++ drivers/gpu/drm/mgag200/mgag200_ddc.h | 11 + drivers/gpu/drm/mgag200/mgag200_drv.c | 315 +++++++++++ drivers/gpu/drm/mgag200/mgag200_drv.h | 439 ++++++++++++++++ drivers/gpu/drm/mgag200/mgag200_g200.c | 408 +++++++++++++++ drivers/gpu/drm/mgag200/mgag200_g200eh.c | 280 ++++++++++ drivers/gpu/drm/mgag200/mgag200_g200eh3.c | 185 +++++++ drivers/gpu/drm/mgag200/mgag200_g200eh5.c | 205 ++++++++ drivers/gpu/drm/mgag200/mgag200_g200er.c | 313 +++++++++++ drivers/gpu/drm/mgag200/mgag200_g200ev.c | 318 ++++++++++++ drivers/gpu/drm/mgag200/mgag200_g200ew3.c | 203 ++++++++ drivers/gpu/drm/mgag200/mgag200_g200se.c | 525 +++++++++++++++++++ drivers/gpu/drm/mgag200/mgag200_g200wb.c | 327 ++++++++++++ drivers/gpu/drm/mgag200/mgag200_mode.c | 831 ++++++++++++++++++++++++++++++ drivers/gpu/drm/mgag200/mgag200_reg.h | 699 +++++++++++++++++++++++++ drivers/gpu/drm/mgag200/mgag200_vga.c | 73 +++ drivers/gpu/drm/mgag200/mgag200_vga_bmc.c | 157 ++++++ 20 files changed, 5602 insertions(+) create mode 100644 drivers/gpu/drm/mgag200/Kconfig create mode 100644 drivers/gpu/drm/mgag200/Makefile create mode 100644 drivers/gpu/drm/mgag200/mgag200_bmc.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_ddc.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_ddc.h create mode 100644 drivers/gpu/drm/mgag200/mgag200_drv.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_drv.h create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh3.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200eh5.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200er.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200ev.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200ew3.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200se.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_g200wb.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_mode.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_reg.h create mode 100644 drivers/gpu/drm/mgag200/mgag200_vga.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_vga_bmc.c (limited to 'drivers/gpu/drm/mgag200') diff --git a/drivers/gpu/drm/mgag200/Kconfig b/drivers/gpu/drm/mgag200/Kconfig new file mode 100644 index 000000000..a962ae564 --- /dev/null +++ b/drivers/gpu/drm/mgag200/Kconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_MGAG200 + tristate "Matrox G200" + depends on DRM && PCI + select DRM_CLIENT_SELECTION + select DRM_GEM_SHMEM_HELPER + select DRM_KMS_HELPER + select I2C + select I2C_ALGOBIT + help + This is a KMS driver for Matrox G200 chips. It supports the original + MGA G200 desktop chips and the server variants. It requires 0.3.0 + of the modesetting userspace driver, and a version of mga driver + that will fail on KMS enabled devices. + +config DRM_MGAG200_DISABLE_WRITECOMBINE + bool "Disable Write Combine mapping of VRAM" + depends on DRM_MGAG200 && PREEMPT_RT + help + The VRAM of the G200 is mapped with Write-Combine to improve + performances. This can interfere with real-time tasks; even if they + are running on other CPU cores than the graphics output. + Enable this option only if you run realtime tasks on a server with a + Matrox G200. diff --git a/drivers/gpu/drm/mgag200/Makefile b/drivers/gpu/drm/mgag200/Makefile new file mode 100644 index 000000000..94f063c87 --- /dev/null +++ b/drivers/gpu/drm/mgag200/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only +mgag200-y := \ + mgag200_bmc.o \ + mgag200_ddc.o \ + mgag200_drv.o \ + mgag200_g200.o \ + mgag200_g200eh.o \ + mgag200_g200eh3.o \ + mgag200_g200eh5.o \ + mgag200_g200er.o \ + mgag200_g200ev.o \ + mgag200_g200ew3.o \ + mgag200_g200se.o \ + mgag200_g200wb.o \ + mgag200_mode.o \ + mgag200_vga_bmc.o \ + mgag200_vga.o + +obj-$(CONFIG_DRM_MGAG200) += mgag200.o diff --git a/drivers/gpu/drm/mgag200/mgag200_bmc.c b/drivers/gpu/drm/mgag200/mgag200_bmc.c new file mode 100644 index 000000000..bbdeb791c --- /dev/null +++ b/drivers/gpu/drm/mgag200/mgag200_bmc.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include + +#include +#include +#include +#include + +#include "mgag200_drv.h" + +void mgag200_bmc_stop_scanout(struct mga_device *mdev) +{ + u8 tmp; + int ret; + + /* + * 1 - The first step is to inform the BMC of an upcoming mode + * change. We are putting the misc<0> to output. + */ + + WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); + tmp = RREG8(DAC_DATA); + tmp |= 0x10; + WREG_DAC(MGA1064_GEN_IO_CTL, tmp); + + /* we are putting a 1 on the misc<0> line */ + WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); + tmp = RREG8(DAC_DATA); + tmp |= 0x10; + WREG_DAC(MGA1064_GEN_IO_DATA, tmp); + + /* + * 2- Second step to mask any further scan request. This is + * done by asserting the remfreqmsk bit (XSPAREREG<7>) + */ + + WREG8(DAC_INDEX, MGA1064_SPAREREG); + tmp = RREG8(DAC_DATA); + tmp |= 0x80; + WREG_DAC(MGA1064_SPAREREG, tmp); + + /* + * 3a- The third step is to verify if there is an active scan. + * We are waiting for a 0 on remhsyncsts (). + */ + ret = read_poll_timeout(RREG_DAC, tmp, !(tmp & 0x1), + 1000, 300000, false, + MGA1064_SPAREREG); + if (ret == -ETIMEDOUT) + return; + + /* + * 3b- This step occurs only if the remote BMC is actually + * scanning. We are waiting for the end of the frame which is + * a 1 on remvsyncsts (XSPAREREG<1>) + */ + (void)read_poll_timeout(RREG_DAC, tmp, (tmp & 0x2), + 1000, 300000, false, + MGA1064_SPAREREG); +} + +void mgag200_bmc_start_scanout(struct mga_device *mdev) +{ + u8 tmp; + + /* Assert rstlvl2 */ + WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); + tmp = RREG8(DAC_DATA); + tmp |= 0x8; + WREG8(DAC_DATA, tmp); + + udelay(10); + + /* Deassert rstlvl2 */ + tmp &= ~0x08; + WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); + WREG8(DAC_DATA, tmp); + + /* Remove mask of scan request */ + WREG8(DAC_INDEX, MGA1064_SPAREREG); + tmp = RREG8(DAC_DATA); + tmp &= ~0x80; + WREG8(DAC_DATA, tmp); + + /* Put back a 0 on the misc<0> line */ + WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); + tmp = RREG8(DAC_DATA); + tmp &= ~0x10; + WREG_DAC(MGA1064_GEN_IO_DATA, tmp); +} diff --git a/drivers/gpu/drm/mgag200/mgag200_ddc.c b/drivers/gpu/drm/mgag200/mgag200_ddc.c new file mode 100644 index 000000000..c31673eaa --- /dev/null +++ b/drivers/gpu/drm/mgag200/mgag200_ddc.c @@ -0,0 +1,178 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: Dave Airlie + */ + +#include +#include +#include + +#include + +#include "mgag200_ddc.h" +#include "mgag200_drv.h" + +struct mgag200_ddc { + struct mga_device *mdev; + + int data; + int clock; + + struct i2c_algo_bit_data bit; + struct i2c_adapter adapter; +}; + +static int mga_i2c_read_gpio(struct mga_device *mdev) +{ + WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); + return RREG8(DAC_DATA); +} + +static void mga_i2c_set_gpio(struct mga_device *mdev, int mask, int val) +{ + int tmp; + + WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); + tmp = (RREG8(DAC_DATA) & mask) | val; + WREG_DAC(MGA1064_GEN_IO_CTL, tmp); + WREG_DAC(MGA1064_GEN_IO_DATA, 0); +} + +static inline void mga_i2c_set(struct mga_device *mdev, int mask, int state) +{ + if (state) + state = 0; + else + state = mask; + mga_i2c_set_gpio(mdev, ~mask, state); +} + +static void mgag200_ddc_algo_bit_data_setsda(void *data, int state) +{ + struct mgag200_ddc *ddc = data; + + mga_i2c_set(ddc->mdev, ddc->data, state); +} + +static void mgag200_ddc_algo_bit_data_setscl(void *data, int state) +{ + struct mgag200_ddc *ddc = data; + + mga_i2c_set(ddc->mdev, ddc->clock, state); +} + +static int mgag200_ddc_algo_bit_data_getsda(void *data) +{ + struct mgag200_ddc *ddc = data; + + return (mga_i2c_read_gpio(ddc->mdev) & ddc->data) ? 1 : 0; +} + +static int mgag200_ddc_algo_bit_data_getscl(void *data) +{ + struct mgag200_ddc *ddc = data; + + return (mga_i2c_read_gpio(ddc->mdev) & ddc->clock) ? 1 : 0; +} + +static int mgag200_ddc_algo_bit_data_pre_xfer(struct i2c_adapter *adapter) +{ + struct mgag200_ddc *ddc = i2c_get_adapdata(adapter); + struct mga_device *mdev = ddc->mdev; + + /* + * Protect access to I/O registers from concurrent modesetting + * by acquiring the I/O-register lock. + */ + mutex_lock(&mdev->rmmio_lock); + + return 0; +} + +static void mgag200_ddc_algo_bit_data_post_xfer(struct i2c_adapter *adapter) +{ + struct mgag200_ddc *ddc = i2c_get_adapdata(adapter); + struct mga_device *mdev = ddc->mdev; + + mutex_unlock(&mdev->rmmio_lock); +} + +static void mgag200_ddc_release(struct drm_device *dev, void *res) +{ + struct mgag200_ddc *ddc = res; + + i2c_del_adapter(&ddc->adapter); +} + +struct i2c_adapter *mgag200_ddc_create(struct mga_device *mdev) +{ + struct drm_device *dev = &mdev->base; + const struct mgag200_device_info *info = mdev->info; + struct mgag200_ddc *ddc; + struct i2c_algo_bit_data *bit; + struct i2c_adapter *adapter; + int ret; + + ddc = drmm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL); + if (!ddc) + return ERR_PTR(-ENOMEM); + + WREG_DAC(MGA1064_GEN_IO_CTL2, 1); + WREG_DAC(MGA1064_GEN_IO_DATA, 0xff); + WREG_DAC(MGA1064_GEN_IO_CTL, 0); + + ddc->mdev = mdev; + ddc->data = BIT(info->i2c.data_bit); + ddc->clock = BIT(info->i2c.clock_bit); + + bit = &ddc->bit; + bit->data = ddc; + bit->setsda = mgag200_ddc_algo_bit_data_setsda; + bit->setscl = mgag200_ddc_algo_bit_data_setscl; + bit->getsda = mgag200_ddc_algo_bit_data_getsda; + bit->getscl = mgag200_ddc_algo_bit_data_getscl; + bit->pre_xfer = mgag200_ddc_algo_bit_data_pre_xfer; + bit->post_xfer = mgag200_ddc_algo_bit_data_post_xfer; + bit->udelay = 10; + bit->timeout = usecs_to_jiffies(2200); + + adapter = &ddc->adapter; + adapter->owner = THIS_MODULE; + adapter->algo_data = bit; + adapter->dev.parent = dev->dev; + snprintf(adapter->name, sizeof(adapter->name), "Matrox DDC bus"); + i2c_set_adapdata(adapter, ddc); + + ret = i2c_bit_add_bus(adapter); + if (ret) + return ERR_PTR(ret); + + ret = drmm_add_action_or_reset(dev, mgag200_ddc_release, ddc); + if (ret) + return ERR_PTR(ret); + + return adapter; +} diff --git a/drivers/gpu/drm/mgag200/mgag200_ddc.h b/drivers/gpu/drm/mgag200/mgag200_ddc.h new file mode 100644 index 000000000..fa21d197c --- /dev/null +++ b/drivers/gpu/drm/mgag200/mgag200_ddc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MGAG200_DDC_H__ +#define __MGAG200_DDC_H__ + +struct i2c_adapter; +struct mga_device; + +struct i2c_adapter *mgag200_ddc_create(struct mga_device *mdev); + +#endif diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c new file mode 100644 index 000000000..dfae58122 --- /dev/null +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2012 Red Hat + * + * Authors: Matthew Garrett + * Dave Airlie + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mgag200_drv.h" + +static int mgag200_modeset = -1; +MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); +module_param_named(modeset, mgag200_modeset, int, 0400); + +int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2) +{ + struct device *dev = &pdev->dev; + int err; + + err = pci_write_config_dword(pdev, PCI_MGA_OPTION, option); + if (err != PCIBIOS_SUCCESSFUL) { + dev_err(dev, "pci_write_config_dword(PCI_MGA_OPTION) failed: %d\n", err); + return pcibios_err_to_errno(err); + } + + err = pci_write_config_dword(pdev, PCI_MGA_OPTION2, option2); + if (err != PCIBIOS_SUCCESSFUL) { + dev_err(dev, "pci_write_config_dword(PCI_MGA_OPTION2) failed: %d\n", err); + return pcibios_err_to_errno(err); + } + + return 0; +} + +resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size) +{ + int offset; + int orig; + int test1, test2; + int orig1, orig2; + size_t vram_size; + + /* Probe */ + orig = ioread16(mem); + iowrite16(0, mem); + + vram_size = size; + + for (offset = 0x100000; offset < vram_size; offset += 0x4000) { + orig1 = ioread8(mem + offset); + orig2 = ioread8(mem + offset + 0x100); + + iowrite16(0xaa55, mem + offset); + iowrite16(0xaa55, mem + offset + 0x100); + + test1 = ioread16(mem + offset); + test2 = ioread16(mem); + + iowrite16(orig1, mem + offset); + iowrite16(orig2, mem + offset + 0x100); + + if (test1 != 0xaa55) + break; + + if (test2) + break; + } + + iowrite16(orig, mem); + + return offset - 65536; +} + +/* + * DRM driver + */ + +DEFINE_DRM_GEM_FOPS(mgag200_driver_fops); + +static const struct drm_driver mgag200_driver = { + .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, + .fops = &mgag200_driver_fops, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .major = DRIVER_MAJOR, + .minor = DRIVER_MINOR, + .patchlevel = DRIVER_PATCHLEVEL, + DRM_GEM_SHMEM_DRIVER_OPS, + DRM_FBDEV_SHMEM_DRIVER_OPS, +}; + +/* + * DRM device + */ + +resource_size_t mgag200_device_probe_vram(struct mga_device *mdev) +{ + return mgag200_probe_vram(mdev->vram, resource_size(mdev->vram_res)); +} + +int mgag200_device_preinit(struct mga_device *mdev) +{ + struct drm_device *dev = &mdev->base; + struct pci_dev *pdev = to_pci_dev(dev->dev); + resource_size_t start, len; + struct resource *res; + + /* BAR 1 contains registers */ + + start = pci_resource_start(pdev, 1); + len = pci_resource_len(pdev, 1); + + res = devm_request_mem_region(dev->dev, start, len, "mgadrmfb_mmio"); + if (!res) { + drm_err(dev, "devm_request_mem_region(MMIO) failed\n"); + return -ENXIO; + } + mdev->rmmio_res = res; + + mdev->rmmio = pcim_iomap(pdev, 1, 0); + if (!mdev->rmmio) + return -ENOMEM; + + /* BAR 0 is VRAM */ + + start = pci_resource_start(pdev, 0); + len = pci_resource_len(pdev, 0); + + res = devm_request_mem_region(dev->dev, start, len, "mgadrmfb_vram"); + if (!res) { + drm_err(dev, "devm_request_mem_region(VRAM) failed\n"); + return -ENXIO; + } + mdev->vram_res = res; + +#if defined(CONFIG_DRM_MGAG200_DISABLE_WRITECOMBINE) + mdev->vram = devm_ioremap(dev->dev, res->start, resource_size(res)); + if (!mdev->vram) + return -ENOMEM; +#else + mdev->vram = devm_ioremap_wc(dev->dev, res->start, resource_size(res)); + if (!mdev->vram) + return -ENOMEM; + + /* Don't fail on errors, but performance might be reduced. */ + devm_arch_phys_wc_add(dev->dev, res->start, resource_size(res)); +#endif + + return 0; +} + +int mgag200_device_init(struct mga_device *mdev, + const struct mgag200_device_info *info, + const struct mgag200_device_funcs *funcs) +{ + struct drm_device *dev = &mdev->base; + u8 crtcext3, misc; + int ret; + + mdev->info = info; + mdev->funcs = funcs; + + ret = drmm_mutex_init(dev, &mdev->rmmio_lock); + if (ret) + return ret; + + mutex_lock(&mdev->rmmio_lock); + + RREG_ECRT(0x03, crtcext3); + crtcext3 |= MGAREG_CRTCEXT3_MGAMODE; + WREG_ECRT(0x03, crtcext3); + + WREG_ECRT(0x04, 0x00); + + misc = RREG8(MGA_MISC_IN); + misc |= MGAREG_MISC_RAMMAPEN | + MGAREG_MISC_HIGH_PG_SEL; + WREG8(MGA_MISC_OUT, misc); + + mutex_unlock(&mdev->rmmio_lock); + + WREG32(MGAREG_IEN, 0); + + return 0; +} + +/* + * PCI driver + */ + +static const struct pci_device_id mgag200_pciidlist[] = { + { PCI_VDEVICE(MATROX, 0x0520), .driver_data = G200_PCI }, + { PCI_VDEVICE(MATROX, 0x0521), .driver_data = G200_AGP }, + { PCI_VDEVICE(MATROX, 0x0522), .driver_data = G200_SE_A }, + { PCI_VDEVICE(MATROX, 0x0524), .driver_data = G200_SE_B }, + { PCI_VDEVICE(MATROX, 0x0530), .driver_data = G200_EV }, + { PCI_VDEVICE(MATROX, 0x0532), .driver_data = G200_WB }, + { PCI_VDEVICE(MATROX, 0x0533), .driver_data = G200_EH }, + { PCI_VDEVICE(MATROX, 0x0534), .driver_data = G200_ER }, + { PCI_VDEVICE(MATROX, 0x0536), .driver_data = G200_EW3 }, + { PCI_VDEVICE(MATROX, 0x0538), .driver_data = G200_EH3 }, + { PCI_VDEVICE(MATROX, 0x053a), .driver_data = G200_EH5 }, + { } +}; + +MODULE_DEVICE_TABLE(pci, mgag200_pciidlist); + +static int +mgag200_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + enum mga_type type = (enum mga_type)ent->driver_data; + struct mga_device *mdev; + struct drm_device *dev; + int ret; + + ret = aperture_remove_conflicting_pci_devices(pdev, mgag200_driver.name); + if (ret) + return ret; + + ret = pcim_enable_device(pdev); + if (ret) + return ret; + + switch (type) { + case G200_PCI: + case G200_AGP: + mdev = mgag200_g200_device_create(pdev, &mgag200_driver); + break; + case G200_SE_A: + case G200_SE_B: + mdev = mgag200_g200se_device_create(pdev, &mgag200_driver, type); + break; + case G200_WB: + mdev = mgag200_g200wb_device_create(pdev, &mgag200_driver); + break; + case G200_EV: + mdev = mgag200_g200ev_device_create(pdev, &mgag200_driver); + break; + case G200_EH: + mdev = mgag200_g200eh_device_create(pdev, &mgag200_driver); + break; + case G200_EH3: + mdev = mgag200_g200eh3_device_create(pdev, &mgag200_driver); + break; + case G200_EH5: + mdev = mgag200_g200eh5_device_create(pdev, &mgag200_driver); + break; + case G200_ER: + mdev = mgag200_g200er_device_create(pdev, &mgag200_driver); + break; + case G200_EW3: + mdev = mgag200_g200ew3_device_create(pdev, &mgag200_driver); + break; + default: + dev_err(&pdev->dev, "Device type %d is unsupported\n", type); + return -ENODEV; + } + if (IS_ERR(mdev)) + return PTR_ERR(mdev); + dev = &mdev->base; + + ret = drm_dev_register(dev, 0); + if (ret) + return ret; + + /* + * FIXME: A 24-bit color depth does not work with 24 bpp on + * G200ER. Force 32 bpp. + */ + drm_client_setup_with_fourcc(dev, DRM_FORMAT_XRGB8888); + + return 0; +} + +static void mgag200_pci_remove(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + + drm_dev_unregister(dev); + drm_atomic_helper_shutdown(dev); +} + +static void mgag200_pci_shutdown(struct pci_dev *pdev) +{ + drm_atomic_helper_shutdown(pci_get_drvdata(pdev)); +} + +static struct pci_driver mgag200_pci_driver = { + .name = DRIVER_NAME, + .id_table = mgag200_pciidlist, + .probe = mgag200_pci_probe, + .remove = mgag200_pci_remove, + .shutdown = mgag200_pci_shutdown, +}; + +drm_module_pci_driver_if_modeset(mgag200_pci_driver, mgag200_modeset); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h new file mode 100644 index 000000000..3732c6235 --- /dev/null +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2010 Matt Turner. + * Copyright 2012 Red Hat + * + * Authors: Matthew Garrett + * Matt Turner + * Dave Airlie + */ +#ifndef __MGAG200_DRV_H__ +#define __MGAG200_DRV_H__ + +#include