From 78004e9a87f240df03e2f73120d291763c32e0a7 Mon Sep 17 00:00:00 2001 From: Ali Ahmet Memis Date: Fri, 21 Aug 2026 01:45:27 +0000 Subject: openrisc: fix arbitrary kernel memory access via or1k_atomic syscall sys_or1k_atomic() (syscall 244 in the "or1k" ABI) takes two user pointers, v1 and v2, and swaps the words they point to in hand-written assembly. l.lwz r29,0(r4) l.lwz r27,0(r5) l.sw 0(r4),r27 l.sw 0(r5),r29 The pointers are not checked with access_ok(). The four memory accesses also have no exception table entries. A caller passes a kernel address as either pointer, and the syscall reads from and writes to it directly. This gives an unprivileged process a kernel read/write primitive. It overwrites kernel data such as the sys_call_table, gaining code execution in kernel context. Check both pointers before entering the critical section. Add fixups for the four memory accesses so faults on valid but unmapped user addresses return -EFAULT. [shorne@gmail.com: fix comment style] Fixes: 9d02a4283e9c ("OpenRISC: Boot code") Cc: stable@vger.kernel.org Signed-off-by: Ali Ahmet Memis Signed-off-by: Stafford Horne --- drivers/clk/sprd/gate.h | 168 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 drivers/clk/sprd/gate.h (limited to 'drivers/clk/sprd/gate.h') diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h new file mode 100644 index 000000000..775519eb1 --- /dev/null +++ b/drivers/clk/sprd/gate.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// +// Spreadtrum gate clock driver +// +// Copyright (C) 2017 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#ifndef _SPRD_GATE_H_ +#define _SPRD_GATE_H_ + +#include "common.h" + +struct sprd_gate { + u32 enable_mask; + u16 flags; + u16 sc_offset; + u16 udelay; + + struct sprd_clk_common common; +}; + +/* + * sprd_gate->flags is used for: + * CLK_GATE_SET_TO_DISABLE BIT(0) + * CLK_GATE_HIWORD_MASK BIT(1) + * CLK_GATE_BIG_ENDIAN BIT(2) + * so we define new flags from BIT(3) + */ +#define SPRD_GATE_NON_AON BIT(3) /* not always powered on, check before read */ + +#define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay, _ops, _fn) \ + struct sprd_gate _struct = { \ + .enable_mask = _enable_mask, \ + .sc_offset = _sc_offset, \ + .flags = _gate_flags, \ + .udelay = _udelay, \ + .common = { \ + .regmap = NULL, \ + .reg = _reg, \ + .hw.init = _fn(_name, _parent, \ + _ops, _flags), \ + } \ + } + +#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay, _ops) \ + SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay, _ops, CLK_HW_INIT) + +#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ + _enable_mask, _flags, _gate_flags, _ops) \ + SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, 0, _ops) + +#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ + _enable_mask, _flags, _gate_flags) \ + SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ + _enable_mask, _flags, _gate_flags, \ + &sprd_sc_gate_ops) + +#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ + _enable_mask, _flags, _gate_flags) \ + SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \ + _enable_mask, _flags, _gate_flags, \ + &sprd_gate_ops) + +#define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ + _enable_mask, _flags, _gate_flags, \ + _udelay) \ + SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay, \ + &sprd_pll_sc_gate_ops) + + +#define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, \ + _flags, _gate_flags, \ + _udelay, _ops) \ + SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay, _ops, \ + CLK_HW_INIT_HW) + +#define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _ops) \ + SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, \ + _flags, _gate_flags, 0, _ops) + +#define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags) \ + SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, &sprd_sc_gate_ops) + +#define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ + _enable_mask, _flags, _gate_flags) \ + SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, 0, \ + _enable_mask, _flags, _gate_flags, \ + &sprd_gate_ops) + +#define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay) \ + SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, \ + _flags, _gate_flags, _udelay, \ + &sprd_pll_sc_gate_ops) + +#define SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \ + _reg, _sc_offset, \ + _enable_mask, _flags, \ + _gate_flags, _udelay, _ops) \ + SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay, _ops, \ + CLK_HW_INIT_FW_NAME) + +#define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _ops) \ + SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \ + _reg, _sc_offset, \ + _enable_mask, _flags, \ + _gate_flags, 0, _ops) + +#define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags) \ + SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, &sprd_sc_gate_ops) + +#define SPRD_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \ + _enable_mask, _flags, _gate_flags) \ + SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, 0, \ + _enable_mask, _flags, _gate_flags, \ + &sprd_gate_ops) + +#define SPRD_PLL_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \ + _sc_offset, _enable_mask, _flags, \ + _gate_flags, _udelay) \ + SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \ + _reg, _sc_offset, \ + _enable_mask, _flags, \ + _gate_flags, _udelay, \ + &sprd_pll_sc_gate_ops) + +static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw) +{ + struct sprd_clk_common *common = hw_to_sprd_clk_common(hw); + + return container_of(common, struct sprd_gate, common); +} + +extern const struct clk_ops sprd_gate_ops; +extern const struct clk_ops sprd_sc_gate_ops; +extern const struct clk_ops sprd_pll_sc_gate_ops; + +#endif /* _SPRD_GATE_H_ */ -- cgit v1.3.1