From e1c13aed4a1641550e8c9518c96f016e1d52d09b Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Tue, 11 Aug 2026 16:46:47 +0800 Subject: dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible Add the Qualcomm Maili SoC compatible string for the CPU bandwidth monitor (BWMONv4). This falls back to the sdm845-bwmon compatible, consistent with the existing pattern used by other recent SoCs such as sm8750 and kaanapali. Signed-off-by: Yijie Yang Acked-by: Krzysztof Kozlowski Reviewed-by: Jingyi Wang Link: https://patch.msgid.link/20260811-bwmon-v2-1-80f7f150ab9e@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) --- drivers/acpi/reboot.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 drivers/acpi/reboot.c (limited to 'drivers/acpi/reboot.c') diff --git a/drivers/acpi/reboot.c b/drivers/acpi/reboot.c new file mode 100644 index 000000000..b79b7c99c --- /dev/null +++ b/drivers/acpi/reboot.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "ACPI: " fmt + +#include +#include +#include +#include + +#ifdef CONFIG_PCI +static void acpi_pci_reboot(struct acpi_generic_address *rr, u8 reset_value) +{ + unsigned int devfn; + struct pci_bus *bus0; + + /* The reset register can only live on bus 0. */ + bus0 = pci_find_bus(0, 0); + if (!bus0) + return; + /* Form PCI device/function pair. */ + devfn = PCI_DEVFN((rr->address >> 32) & 0xffff, + (rr->address >> 16) & 0xffff); + pr_debug("Resetting with ACPI PCI RESET_REG.\n"); + /* Write the value that resets us. */ + pci_bus_write_config_byte(bus0, devfn, + (rr->address & 0xffff), reset_value); +} +#else +static inline void acpi_pci_reboot(struct acpi_generic_address *rr, + u8 reset_value) +{ + pr_warn_once("PCI configuration space access is not supported\n"); +} +#endif + +void acpi_reboot(void) +{ + struct acpi_generic_address *rr; + u8 reset_value; + + if (acpi_disabled) + return; + + rr = &acpi_gbl_FADT.reset_register; + + /* ACPI reset register was only introduced with v2 of the FADT */ + + if (acpi_gbl_FADT.header.revision < 2) + return; + + /* Is the reset register supported? The spec says we should be + * checking the bit width and bit offset, but Windows ignores + * these fields */ + if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER)) + return; + + reset_value = acpi_gbl_FADT.reset_value; + + /* The reset register can only exist in I/O, Memory or PCI config space + * on a device on bus 0. */ + switch (rr->space_id) { + case ACPI_ADR_SPACE_PCI_CONFIG: + acpi_pci_reboot(rr, reset_value); + break; + + case ACPI_ADR_SPACE_SYSTEM_MEMORY: + case ACPI_ADR_SPACE_SYSTEM_IO: + pr_debug("ACPI MEMORY or I/O RESET_REG.\n"); + acpi_reset(); + break; + } + + /* + * Some platforms do not shut down immediately after writing to the + * ACPI reset register, and this results in racing with the + * subsequent reboot mechanism. + * + * The 15ms delay has been found to be long enough for the system + * to reboot on the affected platforms. + */ + mdelay(15); +} -- cgit v1.3.1