From a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255 Mon Sep 17 00:00:00 2001 From: Jinke Han Date: Tue, 8 Sep 2026 15:37:42 +0800 Subject: x86/kprobes: Fix crash when probing CS CALL instructions When using eBPF to probe CS CALL instructions within a function, a crash can be triggered. The eBPF tool probes offset 257 of the __hrtimer_run_queues() function: <__hrtimer_run_queues+249>: nopl 0x0(%rax,%rax,1) <__hrtimer_run_queues+254>: mov %r14,%rdi <__hrtimer_run_queues+257>: cs call <__x86_indirect_thunk_r12> <__hrtimer_run_queues+263>: mov %eax,%r12d <__hrtimer_run_queues+266>: xchg %ax,%ax <__hrtimer_run_queues+268>: mov %r13,%rdi Which triggers this crash: BUG: unable to handle page fault for address: 00000000000f41c9 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP NOPTI CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: P RIP: 0010:__hrtimer_run_queues+0x106/0x230 Note that __hrtimer_run_queues+0x106 is __hrtimer_run_queues+262, which is at the 6th byte of the above CS CALL instruction. Since the CS CALL instruction occupies 6 bytes, the exception occurred in the middle of that call instruction. The root cause is that when using eBPF tools to probe in the middle of a function, a kprobe with INT3 is used as the underlying implementation. During single-step emulation of the original CALL instruction, int3_emulate_call() assumes that the probed CALL instruction is 5 bytes long. However, the actual CS-prefixed CALL instruction occupies 6 bytes, so it constructs an incorrect exception return address. When the CPU returns from the kprobe handler, the next instruction to be executed is at the address of the last byte of that CS CALL instruction. Coincidentally, starting from that address, the CPU fetches and decodes a completely different instruction, which ultimately triggers a kernel crash. Fix the issue by using the actual instruction length obtained from the instruction decoder when constructing the exception return address, rather than relying on the hardcoded CALL_INSN_SIZE macro. [ mingo: Refined the changelog ] Fixes: 6256e668b7af ("x86/kprobes: Use int3 instead of debug trap for single-step") Suggested-by: Masami Hiramatsu (Google) Signed-off-by: Jinke Han Signed-off-by: Ingo Molnar Reviewed-by: Masami Hiramatsu (Google) Acked-by: Yafang Shao Acked-by: Borislav Petkov Cc: Peter Zijlstra Link: https://patch.msgid.link/20260908073742.GA10517@didi-ThinkCentre-M920t-N000 --- arch/sh/Kbuild | 8 + arch/sh/Kconfig | 768 ++++++++++ arch/sh/Kconfig.cpu | 100 ++ arch/sh/Kconfig.debug | 89 ++ arch/sh/Makefile | 193 +++ arch/sh/boards/Kconfig | 400 ++++++ arch/sh/boards/Makefile | 38 + arch/sh/boards/board-apsh4a3a.c | 182 +++ arch/sh/boards/board-apsh4ad0a.c | 132 ++ arch/sh/boards/board-edosk7705.c | 79 + arch/sh/boards/board-edosk7760.c | 178 +++ arch/sh/boards/board-espt.c | 105 ++ arch/sh/boards/board-magicpanelr2.c | 391 +++++ arch/sh/boards/board-polaris.c | 156 ++ arch/sh/boards/board-secureedge5410.c | 75 + arch/sh/boards/board-sh2007.c | 146 ++ arch/sh/boards/board-sh7757lcr.c | 604 ++++++++ arch/sh/boards/board-sh7785lcr.c | 384 +++++ arch/sh/boards/board-shmin.c | 35 + arch/sh/boards/board-titan.c | 21 + arch/sh/boards/board-urquell.c | 218 +++ arch/sh/boards/mach-ap325rxa/Makefile | 3 + arch/sh/boards/mach-ap325rxa/sdram.S | 66 + arch/sh/boards/mach-ap325rxa/setup.c | 574 ++++++++ arch/sh/boards/mach-dreamcast/Makefile | 7 + arch/sh/boards/mach-dreamcast/irq.c | 155 ++ arch/sh/boards/mach-dreamcast/rtc.c | 96 ++ arch/sh/boards/mach-dreamcast/setup.c | 42 + arch/sh/boards/mach-ecovec24/Makefile | 10 + arch/sh/boards/mach-ecovec24/sdram.S | 108 ++ arch/sh/boards/mach-ecovec24/setup.c | 1520 ++++++++++++++++++++ arch/sh/boards/mach-highlander/Kconfig | 27 + arch/sh/boards/mach-highlander/Makefile | 12 + arch/sh/boards/mach-highlander/irq-r7780mp.c | 71 + arch/sh/boards/mach-highlander/irq-r7780rp.c | 64 + arch/sh/boards/mach-highlander/irq-r7785rp.c | 83 ++ arch/sh/boards/mach-highlander/pinmux-r7785rp.c | 18 + arch/sh/boards/mach-highlander/psw.c | 119 ++ arch/sh/boards/mach-highlander/setup.c | 416 ++++++ arch/sh/boards/mach-hp6xx/Makefile | 8 + arch/sh/boards/mach-hp6xx/hp6xx_apm.c | 109 ++ arch/sh/boards/mach-hp6xx/pm.c | 156 ++ arch/sh/boards/mach-hp6xx/pm_wakeup.S | 39 + arch/sh/boards/mach-hp6xx/setup.c | 172 +++ arch/sh/boards/mach-kfr2r09/Makefile | 5 + arch/sh/boards/mach-kfr2r09/lcd_wqvga.c | 275 ++++ arch/sh/boards/mach-kfr2r09/sdram.S | 77 + arch/sh/boards/mach-kfr2r09/setup.c | 649 +++++++++ arch/sh/boards/mach-landisk/Makefile | 6 + arch/sh/boards/mach-landisk/gio.c | 164 +++ arch/sh/boards/mach-landisk/irq.c | 63 + arch/sh/boards/mach-landisk/psw.c | 140 ++ arch/sh/boards/mach-landisk/setup.c | 102 ++ arch/sh/boards/mach-lboxre2/Makefile | 6 + arch/sh/boards/mach-lboxre2/irq.c | 27 + arch/sh/boards/mach-lboxre2/setup.c | 79 + arch/sh/boards/mach-migor/Kconfig | 16 + arch/sh/boards/mach-migor/Makefile | 3 + arch/sh/boards/mach-migor/lcd_qvga.c | 163 +++ arch/sh/boards/mach-migor/sdram.S | 66 + arch/sh/boards/mach-migor/setup.c | 649 +++++++++ arch/sh/boards/mach-r2d/Kconfig | 24 + arch/sh/boards/mach-r2d/Makefile | 6 + arch/sh/boards/mach-r2d/irq.c | 156 ++ arch/sh/boards/mach-r2d/setup.c | 305 ++++ arch/sh/boards/mach-rsk/Kconfig | 32 + arch/sh/boards/mach-rsk/Makefile | 5 + arch/sh/boards/mach-rsk/devices-rsk7203.c | 137 ++ arch/sh/boards/mach-rsk/devices-rsk7264.c | 55 + arch/sh/boards/mach-rsk/devices-rsk7269.c | 56 + arch/sh/boards/mach-rsk/setup.c | 84 ++ arch/sh/boards/mach-sdk7780/Kconfig | 17 + arch/sh/boards/mach-sdk7780/Makefile | 6 + arch/sh/boards/mach-sdk7780/irq.c | 43 + arch/sh/boards/mach-sdk7780/setup.c | 96 ++ arch/sh/boards/mach-sdk7786/Makefile | 5 + arch/sh/boards/mach-sdk7786/fpga.c | 69 + arch/sh/boards/mach-sdk7786/gpio.c | 46 + arch/sh/boards/mach-sdk7786/irq.c | 45 + arch/sh/boards/mach-sdk7786/nmi.c | 80 ++ arch/sh/boards/mach-sdk7786/setup.c | 266 ++++ arch/sh/boards/mach-sdk7786/sram.c | 69 + arch/sh/boards/mach-se/7206/Makefile | 6 + arch/sh/boards/mach-se/7206/irq.c | 151 ++ arch/sh/boards/mach-se/7206/setup.c | 96 ++ arch/sh/boards/mach-se/7343/Makefile | 6 + arch/sh/boards/mach-se/7343/irq.c | 124 ++ arch/sh/boards/mach-se/7343/setup.c | 182 +++ arch/sh/boards/mach-se/770x/Makefile | 6 + arch/sh/boards/mach-se/770x/irq.c | 109 ++ arch/sh/boards/mach-se/770x/setup.c | 205 +++ arch/sh/boards/mach-se/7721/Makefile | 2 + arch/sh/boards/mach-se/7721/irq.c | 42 + arch/sh/boards/mach-se/7721/setup.c | 92 ++ arch/sh/boards/mach-se/7722/Makefile | 11 + arch/sh/boards/mach-se/7722/irq.c | 116 ++ arch/sh/boards/mach-se/7722/setup.c | 190 +++ arch/sh/boards/mach-se/7724/Makefile | 11 + arch/sh/boards/mach-se/7724/irq.c | 143 ++ arch/sh/boards/mach-se/7724/sdram.S | 128 ++ arch/sh/boards/mach-se/7724/setup.c | 984 +++++++++++++ arch/sh/boards/mach-se/7751/Makefile | 6 + arch/sh/boards/mach-se/7751/irq.c | 51 + arch/sh/boards/mach-se/7751/setup.c | 60 + arch/sh/boards/mach-se/7780/Makefile | 11 + arch/sh/boards/mach-se/7780/irq.c | 65 + arch/sh/boards/mach-se/7780/setup.c | 111 ++ arch/sh/boards/mach-se/Makefile | 11 + arch/sh/boards/mach-se/board-se7619.c | 27 + arch/sh/boards/mach-sh03/Makefile | 7 + arch/sh/boards/mach-sh03/rtc.c | 143 ++ arch/sh/boards/mach-sh03/setup.c | 97 ++ arch/sh/boards/mach-sh7763rdp/Makefile | 2 + arch/sh/boards/mach-sh7763rdp/irq.c | 42 + arch/sh/boards/mach-sh7763rdp/setup.c | 213 +++ arch/sh/boards/mach-x3proto/Makefile | 4 + arch/sh/boards/mach-x3proto/gpio.c | 136 ++ arch/sh/boards/mach-x3proto/ilsel.c | 156 ++ arch/sh/boards/mach-x3proto/setup.c | 270 ++++ arch/sh/boards/of-generic.c | 174 +++ arch/sh/boot/.gitignore | 5 + arch/sh/boot/Makefile | 115 ++ arch/sh/boot/compressed/.gitignore | 2 + arch/sh/boot/compressed/Makefile | 57 + arch/sh/boot/compressed/ashiftrt.S | 2 + arch/sh/boot/compressed/ashldi3.c | 2 + arch/sh/boot/compressed/ashlsi3.S | 2 + arch/sh/boot/compressed/ashrsi3.S | 2 + arch/sh/boot/compressed/head_32.S | 126 ++ arch/sh/boot/compressed/head_64.S | 159 ++ arch/sh/boot/compressed/lshrsi3.S | 2 + arch/sh/boot/compressed/misc.c | 141 ++ arch/sh/boot/compressed/misc.h | 9 + arch/sh/boot/compressed/vmlinux.scr | 10 + arch/sh/boot/dts/Makefile | 2 + arch/sh/boot/dts/j2_mimas_v2.dts | 97 ++ arch/sh/boot/romimage/Makefile | 30 + arch/sh/boot/romimage/head.S | 85 ++ arch/sh/boot/romimage/mmcif-sh7724.c | 78 + arch/sh/boot/romimage/vmlinux.scr | 8 + arch/sh/cchips/Kconfig | 46 + arch/sh/cchips/hd6446x/Makefile | 4 + arch/sh/cchips/hd6446x/hd64461.c | 112 ++ arch/sh/configs/ap325rxa_defconfig | 99 ++ arch/sh/configs/apsh4a3a_defconfig | 89 ++ arch/sh/configs/apsh4ad0a_defconfig | 118 ++ arch/sh/configs/dreamcast_defconfig | 67 + arch/sh/configs/ecovec24-romimage_defconfig | 57 + arch/sh/configs/ecovec24_defconfig | 126 ++ arch/sh/configs/edosk7705_defconfig | 35 + arch/sh/configs/edosk7760_defconfig | 111 ++ arch/sh/configs/espt_defconfig | 110 ++ arch/sh/configs/hp6xx_defconfig | 55 + arch/sh/configs/j2_defconfig | 42 + arch/sh/configs/kfr2r09-romimage_defconfig | 51 + arch/sh/configs/kfr2r09_defconfig | 81 ++ arch/sh/configs/landisk_defconfig | 110 ++ arch/sh/configs/lboxre2_defconfig | 58 + arch/sh/configs/magicpanelr2_defconfig | 87 ++ arch/sh/configs/migor_defconfig | 88 ++ arch/sh/configs/polaris_defconfig | 82 ++ arch/sh/configs/r7780mp_defconfig | 104 ++ arch/sh/configs/r7785rp_defconfig | 102 ++ arch/sh/configs/rsk7201_defconfig | 63 + arch/sh/configs/rsk7203_defconfig | 121 ++ arch/sh/configs/rsk7264_defconfig | 70 + arch/sh/configs/rsk7269_defconfig | 55 + arch/sh/configs/rts7751r2d1_defconfig | 86 ++ arch/sh/configs/rts7751r2dplus_defconfig | 91 ++ arch/sh/configs/sdk7780_defconfig | 136 ++ arch/sh/configs/sdk7786_defconfig | 213 +++ arch/sh/configs/se7206_defconfig | 102 ++ arch/sh/configs/se7343_defconfig | 92 ++ arch/sh/configs/se7619_defconfig | 43 + arch/sh/configs/se7705_defconfig | 53 + arch/sh/configs/se7712_defconfig | 95 ++ arch/sh/configs/se7721_defconfig | 122 ++ arch/sh/configs/se7722_defconfig | 55 + arch/sh/configs/se7724_defconfig | 125 ++ arch/sh/configs/se7750_defconfig | 54 + arch/sh/configs/se7751_defconfig | 44 + arch/sh/configs/se7780_defconfig | 101 ++ arch/sh/configs/secureedge5410_defconfig | 53 + arch/sh/configs/sh03_defconfig | 122 ++ arch/sh/configs/sh2007_defconfig | 191 +++ arch/sh/configs/sh7710voipgw_defconfig | 53 + arch/sh/configs/sh7724_generic_defconfig | 41 + arch/sh/configs/sh7757lcr_defconfig | 83 ++ arch/sh/configs/sh7763rdp_defconfig | 112 ++ arch/sh/configs/sh7770_generic_defconfig | 43 + arch/sh/configs/sh7785lcr_32bit_defconfig | 146 ++ arch/sh/configs/sh7785lcr_defconfig | 112 ++ arch/sh/configs/shmin_defconfig | 51 + arch/sh/configs/shx3_defconfig | 99 ++ arch/sh/configs/titan_defconfig | 262 ++++ arch/sh/configs/ul2_defconfig | 81 ++ arch/sh/configs/urquell_defconfig | 142 ++ arch/sh/drivers/Kconfig | 20 + arch/sh/drivers/Makefile | 10 + arch/sh/drivers/dma/Kconfig | 76 + arch/sh/drivers/dma/Makefile | 9 + arch/sh/drivers/dma/dma-api.c | 274 ++++ arch/sh/drivers/dma/dma-g2.c | 197 +++ arch/sh/drivers/dma/dma-pvr2.c | 102 ++ arch/sh/drivers/dma/dma-sh.c | 425 ++++++ arch/sh/drivers/dma/dma-sysfs.c | 170 +++ arch/sh/drivers/dma/dmabrg.c | 195 +++ arch/sh/drivers/heartbeat.c | 152 ++ arch/sh/drivers/pci/Makefile | 27 + arch/sh/drivers/pci/common.c | 160 +++ arch/sh/drivers/pci/fixups-dreamcast.c | 84 ++ arch/sh/drivers/pci/fixups-landisk.c | 57 + arch/sh/drivers/pci/fixups-r7780rp.c | 18 + arch/sh/drivers/pci/fixups-rts7751r2d.c | 64 + arch/sh/drivers/pci/fixups-sdk7780.c | 40 + arch/sh/drivers/pci/fixups-sdk7786.c | 64 + arch/sh/drivers/pci/fixups-se7751.c | 113 ++ arch/sh/drivers/pci/fixups-sh03.c | 33 + arch/sh/drivers/pci/fixups-snapgear.c | 37 + arch/sh/drivers/pci/fixups-titan.c | 36 + arch/sh/drivers/pci/ops-dreamcast.c | 79 + arch/sh/drivers/pci/ops-sh4.c | 105 ++ arch/sh/drivers/pci/ops-sh7786.c | 168 +++ arch/sh/drivers/pci/pci-dreamcast.c | 97 ++ arch/sh/drivers/pci/pci-sh4.h | 182 +++ arch/sh/drivers/pci/pci-sh7751.c | 179 +++ arch/sh/drivers/pci/pci-sh7751.h | 126 ++ arch/sh/drivers/pci/pci-sh7780.c | 407 ++++++ arch/sh/drivers/pci/pci-sh7780.h | 43 + arch/sh/drivers/pci/pci.c | 302 ++++ arch/sh/drivers/pci/pcie-sh7786.c | 607 ++++++++ arch/sh/drivers/pci/pcie-sh7786.h | 577 ++++++++ arch/sh/drivers/platform_early.c | 336 +++++ arch/sh/drivers/push-switch.c | 135 ++ arch/sh/include/asm/Kbuild | 7 + arch/sh/include/asm/adc.h | 12 + arch/sh/include/asm/addrspace.h | 63 + arch/sh/include/asm/alignment.h | 22 + arch/sh/include/asm/asm-offsets.h | 2 + arch/sh/include/asm/atomic-grb.h | 95 ++ arch/sh/include/asm/atomic-irq.h | 81 ++ arch/sh/include/asm/atomic-llsc.h | 97 ++ arch/sh/include/asm/atomic.h | 35 + arch/sh/include/asm/barrier.h | 45 + arch/sh/include/asm/bitops-cas.h | 94 ++ arch/sh/include/asm/bitops-grb.h | 173 +++ arch/sh/include/asm/bitops-llsc.h | 147 ++ arch/sh/include/asm/bitops-op32.h | 143 ++ arch/sh/include/asm/bitops.h | 72 + arch/sh/include/asm/bl_bit.h | 2 + arch/sh/include/asm/bl_bit_32.h | 34 + arch/sh/include/asm/bug.h | 121 ++ arch/sh/include/asm/cache.h | 52 + arch/sh/include/asm/cache_insns.h | 2 + arch/sh/include/asm/cache_insns_32.h | 22 + arch/sh/include/asm/cacheflush.h | 126 ++ arch/sh/include/asm/cachetype.h | 9 + arch/sh/include/asm/checksum.h | 2 + arch/sh/include/asm/checksum_32.h | 204 +++ arch/sh/include/asm/clock.h | 17 + arch/sh/include/asm/cmpxchg-cas.h | 25 + arch/sh/include/asm/cmpxchg-grb.h | 95 ++ arch/sh/include/asm/cmpxchg-irq.h | 54 + arch/sh/include/asm/cmpxchg-llsc.h | 53 + arch/sh/include/asm/cmpxchg-xchg.h | 50 + arch/sh/include/asm/cmpxchg.h | 86 ++ arch/sh/include/asm/device.h | 17 + arch/sh/include/asm/dma-register.h | 50 + arch/sh/include/asm/dma.h | 133 ++ arch/sh/include/asm/dmabrg.h | 24 + arch/sh/include/asm/dwarf.h | 417 ++++++ arch/sh/include/asm/elf.h | 211 +++ arch/sh/include/asm/entry-macros.S | 123 ++ arch/sh/include/asm/extable.h | 7 + arch/sh/include/asm/fixmap.h | 86 ++ arch/sh/include/asm/flat.h | 33 + arch/sh/include/asm/fpu.h | 72 + arch/sh/include/asm/freq.h | 12 + arch/sh/include/asm/ftrace.h | 58 + arch/sh/include/asm/futex-cas.h | 35 + arch/sh/include/asm/futex-irq.h | 25 + arch/sh/include/asm/futex-llsc.h | 42 + arch/sh/include/asm/futex.h | 72 + arch/sh/include/asm/hardirq.h | 11 + arch/sh/include/asm/hd64461.h | 252 ++++ arch/sh/include/asm/heartbeat.h | 19 + arch/sh/include/asm/hugetlb.h | 23 + arch/sh/include/asm/hw_breakpoint.h | 72 + arch/sh/include/asm/hw_irq.h | 36 + arch/sh/include/asm/i2c-sh7760.h | 21 + arch/sh/include/asm/io.h | 291 ++++ arch/sh/include/asm/io_generic.h | 19 + arch/sh/include/asm/io_noioport.h | 79 + arch/sh/include/asm/io_trapped.h | 59 + arch/sh/include/asm/irq.h | 51 + arch/sh/include/asm/irqflags.h | 10 + arch/sh/include/asm/kdebug.h | 19 + arch/sh/include/asm/kexec.h | 72 + arch/sh/include/asm/kgdb.h | 38 + arch/sh/include/asm/kprobes.h | 55 + arch/sh/include/asm/linkage.h | 8 + arch/sh/include/asm/machvec.h | 36 + arch/sh/include/asm/mmiowb.h | 12 + arch/sh/include/asm/mmu.h | 107 ++ arch/sh/include/asm/mmu_context.h | 178 +++ arch/sh/include/asm/mmu_context_32.h | 51 + arch/sh/include/asm/mmzone.h | 42 + arch/sh/include/asm/module.h | 14 + arch/sh/include/asm/page.h | 163 +++ arch/sh/include/asm/pci.h | 91 ++ arch/sh/include/asm/perf_event.h | 30 + arch/sh/include/asm/pgalloc.h | 38 + arch/sh/include/asm/pgtable-2level.h | 24 + arch/sh/include/asm/pgtable-3level.h | 59 + arch/sh/include/asm/pgtable.h | 145 ++ arch/sh/include/asm/pgtable_32.h | 482 +++++++ arch/sh/include/asm/platform_early.h | 61 + arch/sh/include/asm/posix_types.h | 2 + arch/sh/include/asm/processor.h | 175 +++ arch/sh/include/asm/processor_32.h | 203 +++ arch/sh/include/asm/ptrace.h | 139 ++ arch/sh/include/asm/ptrace_32.h | 14 + arch/sh/include/asm/push-switch.h | 32 + arch/sh/include/asm/reboot.h | 22 + arch/sh/include/asm/romimage-macros.h | 74 + arch/sh/include/asm/rtc.h | 13 + arch/sh/include/asm/seccomp.h | 21 + arch/sh/include/asm/sections.h | 12 + arch/sh/include/asm/setup.h | 27 + arch/sh/include/asm/sfp-machine.h | 80 ++ arch/sh/include/asm/sh7760fb.h | 198 +++ arch/sh/include/asm/sh_bios.h | 28 + arch/sh/include/asm/shmparam.h | 19 + arch/sh/include/asm/siu.h | 20 + arch/sh/include/asm/smc37c93x.h | 191 +++ arch/sh/include/asm/smp-ops.h | 53 + arch/sh/include/asm/smp.h | 83 ++ arch/sh/include/asm/sparsemem.h | 12 + arch/sh/include/asm/spi.h | 14 + arch/sh/include/asm/spinlock-cas.h | 89 ++ arch/sh/include/asm/spinlock-llsc.h | 198 +++ arch/sh/include/asm/spinlock.h | 19 + arch/sh/include/asm/spinlock_types.h | 22 + arch/sh/include/asm/sram.h | 39 + arch/sh/include/asm/stackprotector.h | 21 + arch/sh/include/asm/stacktrace.h | 21 + arch/sh/include/asm/string.h | 2 + arch/sh/include/asm/string_32.h | 102 ++ arch/sh/include/asm/suspend.h | 97 ++ arch/sh/include/asm/switch_to.h | 7 + arch/sh/include/asm/switch_to_32.h | 131 ++ arch/sh/include/asm/syscall.h | 9 + arch/sh/include/asm/syscall_32.h | 93 ++ arch/sh/include/asm/syscalls.h | 15 + arch/sh/include/asm/syscalls_32.h | 27 + arch/sh/include/asm/thread_info.h | 168 +++ arch/sh/include/asm/tlb.h | 33 + arch/sh/include/asm/tlbflush.h | 52 + arch/sh/include/asm/topology.h | 28 + arch/sh/include/asm/traps.h | 18 + arch/sh/include/asm/traps_32.h | 64 + arch/sh/include/asm/types.h | 16 + arch/sh/include/asm/uaccess.h | 132 ++ arch/sh/include/asm/uaccess_32.h | 227 +++ arch/sh/include/asm/uncached.h | 59 + arch/sh/include/asm/unistd.h | 33 + arch/sh/include/asm/unwinder.h | 32 + arch/sh/include/asm/user.h | 55 + arch/sh/include/asm/vermagic.h | 30 + arch/sh/include/asm/vmalloc.h | 4 + arch/sh/include/asm/vmlinux.lds.h | 18 + arch/sh/include/asm/watchdog.h | 159 ++ arch/sh/include/asm/word-at-a-time.h | 56 + arch/sh/include/cpu-common/cpu/addrspace.h | 16 + arch/sh/include/cpu-common/cpu/mmu_context.h | 13 + arch/sh/include/cpu-common/cpu/pfc.h | 18 + arch/sh/include/cpu-common/cpu/rtc.h | 9 + arch/sh/include/cpu-common/cpu/sigcontext.h | 18 + arch/sh/include/cpu-common/cpu/timer.h | 7 + arch/sh/include/cpu-sh2/cpu/cache.h | 40 + arch/sh/include/cpu-sh2/cpu/freq.h | 15 + arch/sh/include/cpu-sh2/cpu/watchdog.h | 66 + arch/sh/include/cpu-sh2a/cpu/addrspace.h | 11 + arch/sh/include/cpu-sh2a/cpu/cache.h | 40 + arch/sh/include/cpu-sh2a/cpu/freq.h | 13 + arch/sh/include/cpu-sh2a/cpu/rtc.h | 9 + arch/sh/include/cpu-sh2a/cpu/sh7203.h | 144 ++ arch/sh/include/cpu-sh2a/cpu/sh7264.h | 169 +++ arch/sh/include/cpu-sh2a/cpu/sh7269.h | 213 +++ arch/sh/include/cpu-sh2a/cpu/watchdog.h | 2 + arch/sh/include/cpu-sh3/cpu/adc.h | 29 + arch/sh/include/cpu-sh3/cpu/cache.h | 40 + arch/sh/include/cpu-sh3/cpu/dac.h | 44 + arch/sh/include/cpu-sh3/cpu/dma-register.h | 38 + arch/sh/include/cpu-sh3/cpu/dma.h | 19 + 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SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ boards/ +obj-$(CONFIG_SH_FPU_EMU) += math-emu/ + +obj-$(CONFIG_HD6446X_SERIES) += cchips/hd6446x/ + +# for cleaning +subdir- += boot diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig new file mode 100644 index 000000000..d60f1d5a9 --- /dev/null +++ b/arch/sh/Kconfig @@ -0,0 +1,768 @@ +# SPDX-License-Identifier: GPL-2.0 +config SUPERH + def_bool y + select ARCH_32BIT_OFF_T + select ARCH_HAS_CPU_CACHE_ALIASING + select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) + select ARCH_HAS_BINFMT_FLAT if !MMU + select ARCH_HAS_CPU_FINALIZE_INIT + select ARCH_HAS_CURRENT_STACK_POINTER + select ARCH_HAS_GIGANTIC_PAGE + select ARCH_HAS_GCOV_PROFILE_ALL + select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST + select ARCH_HIBERNATION_POSSIBLE if MMU + select ARCH_MIGHT_HAVE_PC_PARPORT + select ARCH_WANT_IPC_PARSE_VERSION + select ARCH_NEED_CMPXCHG_1_EMU + select CPU_NO_EFFICIENT_FFS + select DMA_DECLARE_COHERENT + select GENERIC_ATOMIC64 + select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST + select GENERIC_IDLE_POLL_SETUP + select GENERIC_IRQ_SHOW + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + select GENERIC_PCI_IOMAP if PCI + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select GUP_GET_PXX_LOW_HIGH if X2TLB + select HAS_IOPORT if HAS_IOPORT_MAP + select GENERIC_IOREMAP if MMU + select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_KGDB + select HAVE_ARCH_SECCOMP_FILTER + select HAVE_ARCH_TRACEHOOK + select HAVE_DEBUG_BUGVERBOSE + select HAVE_DEBUG_KMEMLEAK + select HAVE_DYNAMIC_FTRACE + select HAVE_GUP_FAST if MMU + select HAVE_FUNCTION_GRAPH_TRACER + select HAVE_FUNCTION_TRACER + select HAVE_HW_BREAKPOINT + select HAVE_IOREMAP_PROT if MMU && !X2TLB + select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZMA + select HAVE_KERNEL_LZO + select HAVE_KERNEL_XZ + select HAVE_KPROBES + select HAVE_KRETPROBES + select HAVE_MIXED_BREAKPOINTS_REGS + select HAVE_MOD_ARCH_SPECIFIC if DWARF_UNWINDER + select HAVE_NMI + select HAVE_PATA_PLATFORM + select HAVE_PERF_EVENTS + select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_UID16 + select HAVE_SOFTIRQ_ON_OWN_STACK if IRQSTACKS + select HAVE_STACKPROTECTOR + select HAVE_SYSCALL_TRACEPOINTS + select IRQ_FORCED_THREADING + select LOCK_MM_AND_FIND_VMA + select MODULES_USE_ELF_RELA + select NEED_SG_DMA_LENGTH + select NO_DMA if !MMU && !DMA_COHERENT + select NO_GENERIC_PCI_IOPORT_MAP if PCI + select OLD_SIGACTION + select OLD_SIGSUSPEND + select PCI_DOMAINS if PCI + select PERF_EVENTS + select PERF_USE_VMALLOC + select RTC_LIB + select SPARSE_IRQ + select TRACE_IRQFLAGS_SUPPORT + help + The SuperH is a RISC processor targeted for use in embedded systems + and consumer electronics; it was also used in the Sega Dreamcast + gaming console. The SuperH port has a home page at + . + +config GENERIC_BUG + def_bool y + depends on BUG + +config GENERIC_HWEIGHT + def_bool y + +config GENERIC_CALIBRATE_DELAY + bool + +config GENERIC_LOCKBREAK + def_bool y + depends on SMP && PREEMPTION + +config ARCH_SUSPEND_POSSIBLE + def_bool n + +config ARCH_HIBERNATION_POSSIBLE + def_bool n + +config SYS_SUPPORTS_APM_EMULATION + bool + select ARCH_SUSPEND_POSSIBLE + +config SYS_SUPPORTS_SMP + bool + +config SYS_SUPPORTS_NUMA + bool + +config STACKTRACE_SUPPORT + def_bool y + +config LOCKDEP_SUPPORT + def_bool y + +config ARCH_HAS_ILOG2_U32 + def_bool n + +config ARCH_HAS_ILOG2_U64 + def_bool n + +config NO_IOPORT_MAP + def_bool !PCI + depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE && \ + !SH_DREAMCAST + +config IO_TRAPPED + bool + +config SWAP_IO_SPACE + bool + +config DMA_COHERENT + bool + +config DMA_NONCOHERENT + def_bool !NO_DMA && !DMA_COHERENT + select ARCH_HAS_DMA_PREP_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select DMA_DIRECT_REMAP + +config PGTABLE_LEVELS + default 3 if X2TLB + default 2 + +menu "System type" + +# +# Processor families +# +config CPU_SH2 + bool + select SH_INTC + +config CPU_SH2A + bool + select CPU_SH2 + select UNCACHED_MAPPING + +config CPU_J2 + bool + select CPU_SH2 + select OF + select OF_EARLY_FLATTREE + +config CPU_SH3 + bool + select CPU_HAS_INTEVT + select CPU_HAS_SR_RB + select SH_INTC + select SYS_SUPPORTS_SH_TMU + +config CPU_SH4 + bool + select ARCH_SUPPORTS_HUGETLBFS if MMU + select CPU_HAS_INTEVT + select CPU_HAS_SR_RB + select CPU_HAS_FPU if !CPU_SH4AL_DSP + select SH_INTC + select SYS_SUPPORTS_SH_TMU + +config CPU_SH4A + bool + select CPU_SH4 + +config CPU_SH4AL_DSP + bool + select CPU_SH4A + select CPU_HAS_DSP + +config CPU_SHX2 + bool + +config CPU_SHX3 + bool + select DMA_COHERENT + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_NUMA + +config ARCH_SHMOBILE + bool + select ARCH_SUSPEND_POSSIBLE + select PM + +config CPU_HAS_PMU + depends on CPU_SH4 || CPU_SH4A + default y + bool + +choice + prompt "Processor sub-type selection" + +# +# Processor subtypes +# + +# SH-2 Processor Support + +config CPU_SUBTYPE_SH7619 + bool "Support SH7619 processor" + select CPU_SH2 + select SYS_SUPPORTS_SH_CMT + +config CPU_SUBTYPE_J2 + bool "Support J2 processor" + select CPU_J2 + select SYS_SUPPORTS_SMP + select GENERIC_CLOCKEVENTS_BROADCAST if SMP + +# SH-2A Processor Support + +config CPU_SUBTYPE_SH7201 + bool "Support SH7201 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_SH_MTU2 + +config CPU_SUBTYPE_SH7203 + bool "Support SH7203 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 + select PINCTRL + +config CPU_SUBTYPE_SH7206 + bool "Support SH7206 processor" + select CPU_SH2A + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 + +config CPU_SUBTYPE_SH7263 + bool "Support SH7263 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 + +config CPU_SUBTYPE_SH7264 + bool "Support SH7264 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 + select PINCTRL + +config CPU_SUBTYPE_SH7269 + bool "Support SH7269 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 + select PINCTRL + +config CPU_SUBTYPE_MXG + bool "Support MX-G processor" + select CPU_SH2A + select SYS_SUPPORTS_SH_MTU2 + help + Select MX-G if running on an R8A03022BG part. + +# SH-3 Processor Support + +config CPU_SUBTYPE_SH7705 + bool "Support SH7705 processor" + select CPU_SH3 + +config CPU_SUBTYPE_SH7706 + bool "Support SH7706 processor" + select CPU_SH3 + help + Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. + +config CPU_SUBTYPE_SH7707 + bool "Support SH7707 processor" + select CPU_SH3 + help + Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. + +config CPU_SUBTYPE_SH7708 + bool "Support SH7708 processor" + select CPU_SH3 + help + Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or + if you have a 100 Mhz SH-3 HD6417708R CPU. + +config CPU_SUBTYPE_SH7709 + bool "Support SH7709 processor" + select CPU_SH3 + help + Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. + +config CPU_SUBTYPE_SH7710 + bool "Support SH7710 processor" + select CPU_SH3 + select CPU_HAS_DSP + help + Select SH7710 if you have a SH3-DSP SH7710 CPU. + +config CPU_SUBTYPE_SH7712 + bool "Support SH7712 processor" + select CPU_SH3 + select CPU_HAS_DSP + help + Select SH7712 if you have a SH3-DSP SH7712 CPU. + +config CPU_SUBTYPE_SH7720 + bool "Support SH7720 processor" + select CPU_SH3 + select CPU_HAS_DSP + select SYS_SUPPORTS_SH_CMT + select USB_OHCI_SH if USB_OHCI_HCD + select PINCTRL + help + Select SH7720 if you have a SH3-DSP SH7720 CPU. + +config CPU_SUBTYPE_SH7721 + bool "Support SH7721 processor" + select CPU_SH3 + select CPU_HAS_DSP + select SYS_SUPPORTS_SH_CMT + select USB_OHCI_SH if USB_OHCI_HCD + help + Select SH7721 if you have a SH3-DSP SH7721 CPU. + +# SH-4 Processor Support + +config CPU_SUBTYPE_SH7750 + bool "Support SH7750 processor" + select CPU_SH4 + help + Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. + +config CPU_SUBTYPE_SH7091 + bool "Support SH7091 processor" + select CPU_SH4 + help + Select SH7091 if you have an SH-4 based Sega device (such as + the Dreamcast, Naomi, and Naomi 2). + +config CPU_SUBTYPE_SH7750R + bool "Support SH7750R processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH7750S + bool "Support SH7750S processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH7751 + bool "Support SH7751 processor" + select CPU_SH4 + help + Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, + or if you have a HD6417751R CPU. + +config CPU_SUBTYPE_SH7751R + bool "Support SH7751R processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH7760 + bool "Support SH7760 processor" + select CPU_SH4 + +# SH-4A Processor Support + +config CPU_SUBTYPE_SH7723 + bool "Support SH7723 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_SH_CMT + select PINCTRL + help + Select SH7723 if you have an SH-MobileR2 CPU. + +config CPU_SUBTYPE_SH7724 + bool "Support SH7724 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_SH_CMT + select PINCTRL + help + Select SH7724 if you have an SH-MobileR2R CPU. + +config CPU_SUBTYPE_SH7734 + bool "Support SH7734 processor" + select CPU_SH4A + select CPU_SHX2 + select PINCTRL + help + Select SH7734 if you have a SH4A SH7734 CPU. + +config CPU_SUBTYPE_SH7757 + bool "Support SH7757 processor" + select CPU_SH4A + select CPU_SHX2 + select PINCTRL + help + Select SH7757 if you have a SH4A SH7757 CPU. + +config CPU_SUBTYPE_SH7763 + bool "Support SH7763 processor" + select CPU_SH4A + select USB_OHCI_SH if USB_OHCI_HCD + help + Select SH7763 if you have a SH4A SH7763(R5S77631) CPU. + +config CPU_SUBTYPE_SH7770 + bool "Support SH7770 processor" + select CPU_SH4A + +config CPU_SUBTYPE_SH7780 + bool "Support SH7780 processor" + select CPU_SH4A + +config CPU_SUBTYPE_SH7785 + bool "Support SH7785 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_NUMA + select PINCTRL + +config CPU_SUBTYPE_SH7786 + bool "Support SH7786 processor" + select CPU_SH4A + select CPU_SHX3 + select CPU_HAS_PTEAEX + select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select USB_OHCI_SH if USB_OHCI_HCD + select USB_EHCI_SH if USB_EHCI_HCD + select PINCTRL + +config CPU_SUBTYPE_SHX3 + bool "Support SH-X3 processor" + select CPU_SH4A + select CPU_SHX3 + select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select GPIOLIB + select GPIOLIB_LEGACY + select PINCTRL + +# SH4AL-DSP Processor Support + +config CPU_SUBTYPE_SH7343 + bool "Support SH7343 processor" + select CPU_SH4AL_DSP + select ARCH_SHMOBILE + select SYS_SUPPORTS_SH_CMT + +config CPU_SUBTYPE_SH7722 + bool "Support SH7722 processor" + select CPU_SH4AL_DSP + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_SH_CMT + select PINCTRL + +config CPU_SUBTYPE_SH7366 + bool "Support SH7366 processor" + select CPU_SH4AL_DSP + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_SH_CMT + +endchoice + +source "arch/sh/mm/Kconfig" + +source "arch/sh/Kconfig.cpu" + +source "arch/sh/boards/Kconfig" + +menu "Timer and clock configuration" + +config SH_PCLK_FREQ + int "Peripheral clock frequency (in Hz)" + depends on SH_CLK_CPG_LEGACY + default "31250000" if CPU_SUBTYPE_SH7619 + default "33333333" if CPU_SUBTYPE_SH7770 || \ + CPU_SUBTYPE_SH7760 || \ + CPU_SUBTYPE_SH7705 || \ + CPU_SUBTYPE_SH7203 || \ + CPU_SUBTYPE_SH7206 || \ + CPU_SUBTYPE_SH7263 || \ + CPU_SUBTYPE_MXG + default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R + default "50000000" + help + This option is used to specify the peripheral clock frequency. + This is necessary for determining the reference clock value on + platforms lacking an RTC. + +config SH_CLK_CPG + def_bool y + +config SH_CLK_CPG_LEGACY + depends on SH_CLK_CPG + def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ + !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ + !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \ + !CPU_SUBTYPE_SH7269 + +endmenu + +menu "CPU Frequency scaling" +source "drivers/cpufreq/Kconfig" +endmenu + +source "arch/sh/drivers/Kconfig" + +endmenu + +menu "Kernel features" + +source "kernel/Kconfig.hz" + +config ARCH_SUPPORTS_KEXEC + def_bool MMU + +config ARCH_SUPPORTS_CRASH_DUMP + def_bool BROKEN_ON_SMP + +config ARCH_DEFAULT_CRASH_DUMP + def_bool y + +config ARCH_SUPPORTS_KEXEC_JUMP + def_bool y + +config PHYSICAL_START + hex "Physical address where the kernel is loaded" if (EXPERT || CRASH_DUMP) + default MEMORY_START + help + This gives the physical address where the kernel is loaded + and is ordinarily the same as MEMORY_START. + + Different values are primarily used in the case of kexec on panic + where the fail safe kernel needs to run at a different address + than the panic-ed kernel. + +config SMP + bool "Symmetric multi-processing support" + depends on SYS_SUPPORTS_SMP + help + This enables support for systems with more than one CPU. If you have + a system with only one CPU, say N. If you have a system with more + than one CPU, say Y. + + If you say N here, the kernel will run on uni- and multiprocessor + machines, but will use only one CPU of a multiprocessor machine. If + you say Y here, the kernel will run on many, but not all, + uniprocessor machines. On a uniprocessor machine, the kernel + will run faster if you say N here. + + People using multiprocessor machines who say Y here should also say + Y to "Enhanced Real Time Clock Support", below. + + See also and the SMP-HOWTO + available at . + + If you don't know what to do here, say N. + +config NR_CPUS + int "Maximum number of CPUs (2-32)" + range 2 32 + depends on SMP + default "4" if CPU_SUBTYPE_SHX3 + default "2" + help + This allows you to specify the maximum number of CPUs which this + kernel will support. The maximum supported value is 32 and the + minimum value which makes sense is 2. + + This is purely to save memory - each supported CPU adds + approximately eight kilobytes to the kernel image. + +config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" + depends on SMP + help + Say Y here to experiment with turning CPUs off and on. CPUs + can be controlled through /sys/devices/system/cpu. + +config GUSA + def_bool y + depends on !SMP + help + This enables support for gUSA (general UserSpace Atomicity). + This is the default implementation for both UP and non-ll/sc + CPUs, and is used by the libc, amongst others. + + For additional information, design information can be found + in . + + This should only be disabled for special cases where alternate + atomicity implementations exist. + +config GUSA_RB + bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)" + depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A) + help + Enabling this option will allow the kernel to implement some + atomic operations using a software implementation of load-locked/ + store-conditional (LLSC). On machines which do not have hardware + LLSC, this should be more efficient than the other alternative of + disabling interrupts around the atomic sequence. + +config HW_PERF_EVENTS + bool "Enable hardware performance counter support for perf events" + depends on PERF_EVENTS && CPU_HAS_PMU + default y + help + Enable hardware performance counter support for perf events. If + disabled, perf events will use software events only. + +source "drivers/sh/Kconfig" + +endmenu + +menu "Boot options" + +config BUILTIN_DTB + bool "Use builtin DTB" + default n + depends on SH_DEVICE_TREE + select GENERIC_BUILTIN_DTB + help + Link a device tree blob for particular hardware into the kernel, + suppressing use of the DTB pointer provided by the bootloader. + This option should only be used with legacy bootloaders that are + not capable of providing a DTB to the kernel, or for experimental + hardware without stable device tree bindings. + +config BUILTIN_DTB_NAME + string "Source file for builtin DTB" + default "" + depends on BUILTIN_DTB + help + Base name (without suffix, relative to arch/sh/boot/dts) for the + a DTS file that will be used to produce the DTB linked into the + kernel. + +config ZERO_PAGE_OFFSET + hex + default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ + SH_7751_SOLUTION_ENGINE + default "0x00004000" if PAGE_SIZE_16KB || SH_SH03 + default "0x00002000" if PAGE_SIZE_8KB + default "0x00001000" + help + This sets the default offset of zero page. + +config BOOT_LINK_OFFSET + hex + default "0x00210000" if SH_SHMIN + default "0x00810000" if SH_7780_SOLUTION_ENGINE + default "0x009e0000" if SH_TITAN + default "0x01800000" if SH_SDK7780 + default "0x02000000" if SH_EDOSK7760 + default "0x00800000" + help + This option allows you to set the link address offset of the zImage. + This can be useful if you are on a board which has a small amount of + memory. + +config ENTRY_OFFSET + hex + default "0x00001000" if PAGE_SIZE_4KB + default "0x00002000" if PAGE_SIZE_8KB + default "0x00004000" if PAGE_SIZE_16KB + default "0x00010000" if PAGE_SIZE_64KB + default "0x00000000" + +config ROMIMAGE_MMCIF + bool "Include MMCIF loader in romImage (EXPERIMENTAL)" + depends on CPU_SUBTYPE_SH7724 + help + Say Y here to include experimental MMCIF loading code in + romImage. With this enabled it is possible to write the romImage + kernel image to an MMC card and boot the kernel straight from + the reset vector. At reset the processor Mask ROM will load the + first part of the romImage which in turn loads the rest the kernel + image to RAM using the MMCIF hardware block. + +choice + prompt "Kernel command line" + default CMDLINE_OVERWRITE + help + Setting this option allows the kernel command line arguments + to be set. + +config CMDLINE_OVERWRITE + bool "Overwrite bootloader kernel arguments" + help + Given string will overwrite any arguments passed in by + a bootloader. + +config CMDLINE_EXTEND + bool "Extend bootloader kernel arguments" + help + Given string will be concatenated with arguments passed in + by a bootloader. + +config CMDLINE_FROM_BOOTLOADER + bool "Use bootloader kernel arguments" + help + Uses the command-line options passed by the boot loader. + +endchoice + +config CMDLINE + string "Kernel command line arguments string" + depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND + default "console=ttySC1,115200" + +endmenu + +menu "Bus options" + +config MAPLE + bool "Maple Bus support" + depends on SH_DREAMCAST + help + The Maple Bus is SEGA's serial communication bus for peripherals + on the Dreamcast. Without this bus support you won't be able to + get your Dreamcast keyboard etc to work, so most users + probably want to say 'Y' here, unless you are only using the + Dreamcast with a serial line terminal or a remote network + connection. + +endmenu + +menu "Power management options (EXPERIMENTAL)" + +source "kernel/power/Kconfig" + +source "drivers/cpuidle/Kconfig" + +endmenu diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu new file mode 100644 index 000000000..336c54369 --- /dev/null +++ b/arch/sh/Kconfig.cpu @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0 +menu "Processor features" + +choice + prompt "Endianness selection" + default CPU_LITTLE_ENDIAN + help + Some SuperH machines can be configured for either little or big + endian byte order. These modes require different kernels. + +config CPU_LITTLE_ENDIAN + bool "Little Endian" + +config CPU_BIG_ENDIAN + bool "Big Endian" + +endchoice + +config SH_FPU + def_bool y + prompt "FPU support" + depends on CPU_HAS_FPU + help + Selecting this option will enable support for SH processors that + have FPU units (ie, SH77xx). + + This option must be set in order to enable the FPU. + +config SH_FPU_EMU + def_bool n + prompt "FPU emulation support" + depends on !SH_FPU + help + Selecting this option will enable support for software FPU emulation. + Most SH-3 users will want to say Y here, whereas most SH-4 users will + want to say N. + +config SH_DSP + def_bool y + prompt "DSP support" + depends on CPU_HAS_DSP + help + Selecting this option will enable support for SH processors that + have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP). + + This option must be set in order to enable the DSP. + +config SH_ADC + def_bool y + prompt "ADC support" + depends on CPU_SH3 + help + Selecting this option will allow the Linux kernel to use SH3 on-chip + ADC module. + + If unsure, say N. + +config SH_STORE_QUEUES + bool "Support for Store Queues" + depends on CPU_SH4 + help + Selecting this option will enable an in-kernel API for manipulating + the store queues integrated in the SH-4 processors. + +config SPECULATIVE_EXECUTION + bool "Speculative subroutine return" + depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786 + help + This enables support for a speculative instruction fetch for + subroutine return. There are various pitfalls associated with + this, as outlined in the SH7780 hardware manual. + + If unsure, say N. + +config CPU_HAS_INTEVT + bool + +config CPU_HAS_IPR_IRQ + bool + +config CPU_HAS_SR_RB + bool + help + This will enable the use of SR.RB register bank usage. Processors + that are lacking this bit must have another method in place for + accomplishing what is taken care of by the banked registers. + + See for further + information on SR.RB and register banking in the kernel in general. + +config CPU_HAS_PTEAEX + bool + +config CPU_HAS_DSP + bool + +config CPU_HAS_FPU + bool + +endmenu diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug new file mode 100644 index 000000000..8bcd6c143 --- /dev/null +++ b/arch/sh/Kconfig.debug @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0 + +config SH_STANDARD_BIOS + bool "Use LinuxSH standard BIOS" + help + Say Y here if your target has the gdb-sh-stub + package from www.m17n.org (or any conforming standard LinuxSH BIOS) + in FLASH or EPROM. The kernel will use standard BIOS calls during + boot for various housekeeping tasks (including calls to read and + write characters to a system console, get a MAC address from an + on-board Ethernet interface, and shut down the hardware). Note this + does not work with machines with an existing operating system in + mask ROM and no flash (WindowsCE machines fall in this category). + If unsure, say N. + +config STACK_DEBUG + bool "Check for stack overflows" + depends on DEBUG_KERNEL && PRINTK + help + This option will cause messages to be printed if free stack space + drops below a certain limit. Saying Y here will add overhead to + every function call and will therefore incur a major + performance hit. Most users should say N. + +config EARLY_PRINTK + bool "Early printk" + depends on SH_STANDARD_BIOS + help + Say Y here to redirect kernel printk messages to the serial port + used by the SH-IPL bootloader, starting very early in the boot + process and ending when the kernel's serial console is initialised. + This option is only useful while porting the kernel to a new machine, + when the kernel may crash or hang before the serial console is + initialised. If unsure, say N. + +config 4KSTACKS + bool "Use 4Kb for kernel stacks instead of 8Kb" + depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB + help + If you say Y here the kernel will use a 4Kb stacksize for the + kernel stack attached to each process/thread. This facilitates + running more threads on a system and also reduces the pressure + on the VM subsystem for higher order allocations. This option + will also use IRQ stacks to compensate for the reduced stackspace. + +config IRQSTACKS + bool "Use separate kernel stacks when processing interrupts" + depends on DEBUG_KERNEL && BROKEN + help + If you say Y here the kernel will use separate kernel stacks + for handling hard and soft interrupts. This can help avoid + overflowing the process kernel stacks. + +config DUMP_CODE + bool "Show disassembly of nearby code in register dumps" + depends on DEBUG_KERNEL + default y if DEBUG_BUGVERBOSE + default n + help + This prints out a code trace of the instructions leading up to + the faulting instruction as a debugging aid. As this does grow + the kernel in size a bit, most users will want to say N here. + + Those looking for more verbose debugging output should say Y. + +config DWARF_UNWINDER + bool "Enable the DWARF unwinder for stacktraces" + depends on DEBUG_KERNEL + select FRAME_POINTER + default n + help + Enabling this option will make stacktraces more accurate, at + the cost of an increase in overall kernel size. + +config SH_NO_BSS_INIT + bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)" + depends on DEBUG_KERNEL + default n + help + If running in painfully slow environments, such as an RTL + simulation or from remote memory via SHdebug, where the memory + can already be guaranteed to ber zeroed on boot, say Y. + + For all other cases, say N. If this option seems perplexing, or + you aren't sure, say N. + +config MCOUNT + def_bool y + depends on STACK_DEBUG || FUNCTION_TRACER diff --git a/arch/sh/Makefile b/arch/sh/Makefile new file mode 100644 index 000000000..7b420424b --- /dev/null +++ b/arch/sh/Makefile @@ -0,0 +1,193 @@ +# +# arch/sh/Makefile +# +# Copyright (C) 1999 Kaz Kojima +# Copyright (C) 2002 - 2008 Paul Mundt +# Copyright (C) 2002 M. R. Brown +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +ifdef cross_compiling + ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE := $(call cc-cross-prefix, sh-linux- sh-linux-gnu- sh-unknown-linux-gnu-) + endif +endif + +KBUILD_DEFCONFIG := shx3_defconfig + +isa-y := any +isa-$(CONFIG_SH_DSP) := sh +isa-$(CONFIG_CPU_SH2) := sh2 +isa-$(CONFIG_CPU_SH2A) := sh2a +isa-$(CONFIG_CPU_SH3) := sh3 +isa-$(CONFIG_CPU_SH4) := sh4 +isa-$(CONFIG_CPU_SH4A) := sh4a +isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al + +isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp +isa-y := $(isa-y)-up + +cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,) +cflags-$(CONFIG_CPU_J2) += $(call cc-option,-mj2,) +cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \ + $(call cc-option,-m2a-nofpu,) \ + $(call cc-option,-m4-nofpu,) +cflags-$(CONFIG_CPU_SH3) := $(call cc-option,-m3,) +cflags-$(CONFIG_CPU_SH4) := $(call cc-option,-m4,) \ + $(call cc-option,-mno-implicit-fp,-m4-nofpu) +cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \ + $(call cc-option,-m4a-nofpu,) +cflags-$(CONFIG_CPU_SH4AL_DSP) += $(call cc-option,-m4al,) + +ifeq ($(cflags-y),) +# +# In the case where we are stuck with a compiler that has been uselessly +# restricted to a particular ISA, a favourite default of newer GCCs when +# extensive multilib targets are not provided, ensure we get the best fit +# regarding FP generation. This is intentionally stupid (albeit many +# orders of magnitude less than GCC's default behaviour), as anything +# with a large number of multilib targets better have been built +# correctly for the target in mind. +# +cflags-y += $(shell $(CC) $(KBUILD_CFLAGS) -print-multi-lib | \ + grep nofpu | sed q | sed -e 's/^/-/;s/;.*$$//') +# At this point, anything goes. +isaflags-y := $(call as-option,-Wa$(comma)-isa=any,) +else +# +# -Wa,-isa= tuning implies -Wa,-dsp for the versions of binutils that +# support it, while -Wa,-dsp by itself limits the range of usable opcodes +# on certain CPU subtypes. Try the ISA variant first, and if that fails, +# fall back on -Wa,-dsp for the old binutils versions. Even without DSP +# opcodes, we always want the best ISA tuning the version of binutils +# will provide. +# +isaflags-y := $(call as-option,-Wa$(comma)-isa=$(isa-y),) + +isaflags-$(CONFIG_SH_DSP) := \ + $(call as-option,-Wa$(comma)-isa=$(isa-y),-Wa$(comma)-dsp) +endif + +cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb +cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml + +cflags-y += $(call cc-option,-mno-fdpic) +cflags-y += $(isaflags-y) -ffreestanding + +OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \ + -R .stab -R .stabstr -S + +# Give the various platforms the opportunity to set default image types +defaultimage-y := zImage +defaultimage-$(CONFIG_SH_SH7785LCR) := uImage +defaultimage-$(CONFIG_SH_RSK) := uImage +defaultimage-$(CONFIG_SH_URQUELL) := uImage +defaultimage-$(CONFIG_SH_MIGOR) := uImage +defaultimage-$(CONFIG_SH_AP325RXA) := uImage +defaultimage-$(CONFIG_SH_SH7757LCR) := uImage +defaultimage-$(CONFIG_SH_7724_SOLUTION_ENGINE) := uImage +defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux +defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux + +# Set some sensible Kbuild defaults +boot := arch/sh/boot +KBUILD_IMAGE := $(boot)/$(defaultimage-y) + +# +# Choosing incompatible machines durings configuration will result in +# error messages during linking. +# +UTS_MACHINE := sh +LDFLAGS_vmlinux += -e _stext + +ifdef CONFIG_CPU_LITTLE_ENDIAN +ld_bfd := elf32-sh-linux +LDFLAGS_vmlinux += --defsym jiffies=jiffies_64 --oformat $(ld_bfd) +KBUILD_LDFLAGS += -EL +else +ld_bfd := elf32-shbig-linux +LDFLAGS_vmlinux += --defsym jiffies=jiffies_64+4 --oformat $(ld_bfd) +KBUILD_LDFLAGS += -EB +endif + +export ld_bfd + +# Mach groups +machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se +machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast +machdir-$(CONFIG_SH_SH03) += mach-sh03 +machdir-$(CONFIG_SH_MIGOR) += mach-migor +machdir-$(CONFIG_SH_KFR2R09) += mach-kfr2r09 +machdir-$(CONFIG_SH_ECOVEC) += mach-ecovec24 +machdir-$(CONFIG_SH_SDK7786) += mach-sdk7786 +machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto +machdir-$(CONFIG_SH_LANDISK) += mach-landisk +machdir-y += mach-common + +# +# CPU header paths +# +# These are ordered by optimization level. A CPU family that is a subset +# of another (ie, SH-2A / SH-2), is picked up first, with increasing +# levels of genericness if nothing more suitable is situated in the +# hierarchy. +# +# As an example, in order of preference, SH-2A > SH-2 > common definitions. +# +cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a +cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2 +cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3 +cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a +cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4 +cpuincdir-y += cpu-common # Must be last + +drivers-y += arch/sh/drivers/ + +KBUILD_CPPFLAGS += $(addprefix -I $(srctree)/arch/sh/include/, $(cpuincdir-y) $(machdir-y)) +KBUILD_CFLAGS += -pipe $(cflags-y) +KBUILD_AFLAGS += $(cflags-y) + +ifeq ($(CONFIG_MCOUNT),y) + KBUILD_CFLAGS += -pg +endif + +ifeq ($(CONFIG_DWARF_UNWINDER),y) + KBUILD_CFLAGS += -fasynchronous-unwind-tables +endif + +libs-y := arch/sh/lib/ $(libs-y) + +BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \ + uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \ + romImage +PHONY += $(BOOT_TARGETS) + +all: $(notdir $(KBUILD_IMAGE)) + +$(BOOT_TARGETS): vmlinux + $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + +compressed: zImage + +archprepare: + $(Q)$(MAKE) $(build)=arch/sh/tools include/generated/machtypes.h + +archheaders: + $(Q)$(MAKE) $(build)=arch/sh/kernel/syscalls all + +define archhelp + @echo ' zImage - Compressed kernel image' + @echo ' romImage - Compressed ROM image, if supported' + @echo ' vmlinux.srec - Create an ELF S-record' + @echo ' vmlinux.bin - Create an uncompressed binary image' + @echo '* uImage - Alias to bootable U-Boot image' + @echo ' uImage.srec - Create an S-record for U-Boot' + @echo ' uImage.bin - Kernel-only image for U-Boot (bin)' + @echo '* uImage.gz - Kernel-only image for U-Boot (gzip)' + @echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)' + @echo ' uImage.lzma - Kernel-only image for U-Boot (lzma)' + @echo ' uImage.xz - Kernel-only image for U-Boot (xz)' + @echo ' uImage.lzo - Kernel-only image for U-Boot (lzo)' +endef diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig new file mode 100644 index 000000000..d89b74177 --- /dev/null +++ b/arch/sh/boards/Kconfig @@ -0,0 +1,400 @@ +# SPDX-License-Identifier: GPL-2.0 +menu "Board support" + +config SOLUTION_ENGINE + bool + +config SH_ALPHA_BOARD + bool + +config SH_CUSTOM_CLK + def_bool y + depends on !SH_DEVICE_TREE + select HAVE_LEGACY_CLK + +config SH_DEVICE_TREE + bool + select OF + select OF_EARLY_FLATTREE + select TIMER_OF + select COMMON_CLK + select GENERIC_CALIBRATE_DELAY + +config SH_JCORE_SOC + bool "J-Core SoC" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT + select JCORE_AIC + depends on CPU_J2 + help + Select this option to include drivers core components of the + J-Core SoC, including interrupt controllers and timers. + +config SH_SOLUTION_ENGINE + bool "SolutionEngine" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \ + CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R + help + Select SolutionEngine if configuring for a Hitachi SH7705, SH7709, + SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board. + +config SH_7206_SOLUTION_ENGINE + bool "SolutionEngine7206" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7206 + help + Select 7206 SolutionEngine if configuring for a Hitachi SH7206 + evaluation board. + +config SH_7619_SOLUTION_ENGINE + bool "SolutionEngine7619" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7619 + help + Select 7619 SolutionEngine if configuring for a Hitachi SH7619 + evaluation board. + +config SH_7721_SOLUTION_ENGINE + bool "SolutionEngine7721" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7721 + help + Select 7721 SolutionEngine if configuring for a Hitachi SH7721 + evaluation board. + +config SH_7722_SOLUTION_ENGINE + bool "SolutionEngine7722" + select SOLUTION_ENGINE + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + depends on CPU_SUBTYPE_SH7722 + help + Select 7722 SolutionEngine if configuring for a Hitachi SH772 + evaluation board. + +config SH_7724_SOLUTION_ENGINE + bool "SolutionEngine7724" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7724 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + imply SND_SOC_AK4642 if SND_SIMPLE_CARD + help + Select 7724 SolutionEngine if configuring for a Hitachi SH7724 + evaluation board. + +config SH_7751_SOLUTION_ENGINE + bool "SolutionEngine7751" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7751 + help + Select 7751 SolutionEngine if configuring for a Hitachi SH7751 + evaluation board. + +config SH_7780_SOLUTION_ENGINE + bool "SolutionEngine7780" + select SOLUTION_ENGINE + select HAVE_PCI + depends on CPU_SUBTYPE_SH7780 + help + Select 7780 SolutionEngine if configuring for a Renesas SH7780 + evaluation board. + +config SH_7343_SOLUTION_ENGINE + bool "SolutionEngine7343" + select SOLUTION_ENGINE + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + depends on CPU_SUBTYPE_SH7343 + help + Select 7343 SolutionEngine if configuring for a Hitachi + SH7343 (SH-Mobile 3AS) evaluation board. + +config SH_HP6XX + bool "HP6XX" + select SYS_SUPPORTS_APM_EMULATION + select HD6446X_SERIES + depends on CPU_SUBTYPE_SH7709 + help + Select HP6XX if configuring for a HP jornada HP6xx. + More information (hardware only) at + . + +config SH_DREAMCAST + bool "Dreamcast" + select HAVE_PCI + depends on CPU_SUBTYPE_SH7091 + help + Select Dreamcast if configuring for a SEGA Dreamcast. + More information at + +config SH_SH03 + bool "Interface CTP/PCI-SH03" + depends on CPU_SUBTYPE_SH7751 + select CPU_HAS_IPR_IRQ + select HAVE_PCI + help + CTP/PCI-SH03 is a CPU module computer that is produced + by Interface Corporation. + More information at + +config SH_SECUREEDGE5410 + bool "SecureEdge5410" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select HAVE_PCI + help + Select SecureEdge5410 if configuring for a SnapGear SH board. + This includes both the OEM SecureEdge products as well as the + SME product line. + +config SH_RTS7751R2D + bool "RTS7751R2D" + depends on CPU_SUBTYPE_SH7751R + select HAVE_PCI + select IO_TRAPPED if MMU + help + Select RTS7751R2D if configuring for a Renesas Technology + Sales SH-Graphics board. + +config SH_RSK + bool "Renesas Starter Kit" + depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \ + CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269 + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select this option if configuring for any of the RSK+ MCU + evaluation platforms. + +config SH_SDK7780 + bool "SDK7780R3" + depends on CPU_SUBTYPE_SH7780 + select HAVE_PCI + help + Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3 + evaluation board. + +config SH_SDK7786 + bool "SDK7786" + depends on CPU_SUBTYPE_SH7786 + select HAVE_PCI + select NO_IOPORT_MAP if !PCI + select HAVE_SRAM_POOL + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select SDK7786 if configuring for a Renesas Technology Europe + SH7786-65nm board. + +config SH_HIGHLANDER + bool "Highlander" + depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 + select HAVE_PCI + select IO_TRAPPED if MMU + +config SH_SH7757LCR + bool "SH7757LCR" + depends on CPU_SUBTYPE_SH7757 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + +config SH_SH7785LCR + bool "SH7785LCR" + depends on CPU_SUBTYPE_SH7785 + select HAVE_PCI + +config SH_SH7785LCR_29BIT_PHYSMAPS + bool "SH7785LCR 29bit physmaps" + depends on SH_SH7785LCR && 29BIT + default y + help + This board has 2 physical memory maps. It can be changed with + DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, + you can access all on-board device in 29bit address mode. + +config SH_SH7785LCR_PT + bool "SH7785LCR prototype board on 32-bit MMU mode" + depends on SH_SH7785LCR && 32BIT + default n + help + If you use prototype board, this option is enabled. + +config SH_URQUELL + bool "Urquell" + depends on CPU_SUBTYPE_SH7786 + select GPIOLIB + select GPIOLIB_LEGACY + select HAVE_PCI + select NO_IOPORT_MAP if !PCI + +config SH_MIGOR + bool "Migo-R" + depends on CPU_SUBTYPE_SH7722 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select Migo-R if configuring for the SH7722 Migo-R platform + by Renesas System Solutions Asia Pte. Ltd. + +config SH_AP325RXA + bool "AP-325RXA" + depends on CPU_SUBTYPE_SH7723 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Renesas "AP-325RXA" support. + Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" + +config SH_KFR2R09 + bool "KFR2R09" + depends on CPU_SUBTYPE_SH7724 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + "Kit For R2R for 2009" support. + +config SH_ECOVEC + bool "EcoVec" + depends on CPU_SUBTYPE_SH7724 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + imply SND_SOC_DA7210 if SND_SIMPLE_CARD + help + Renesas "R0P7724LC0011/21RL (EcoVec)" support. + +config SH_SH7763RDP + bool "SH7763RDP" + depends on CPU_SUBTYPE_SH7763 + help + Select SH7763RDP if configuring for a Renesas SH7763 + evaluation board. + +config SH_ESPT + bool "ESPT" + depends on CPU_SUBTYPE_SH7763 + help + Select ESPT if configuring for a Renesas SH7763 + with gigabit ether evaluation board. + +config SH_EDOSK7705 + bool "EDOSK7705" + depends on CPU_SUBTYPE_SH7705 + +config SH_EDOSK7760 + bool "EDOSK7760" + depends on CPU_SUBTYPE_SH7760 + help + Select if configuring for a Renesas EDOSK7760 + evaluation board. + +config SH_LANDISK + bool "LANDISK" + depends on CPU_SUBTYPE_SH7751R + select HAVE_PCI + help + I-O DATA DEVICE, INC. "LANDISK Series" support. + +config SH_TITAN + bool "TITAN" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select HAVE_PCI + help + Select Titan if you are configuring for a Nimble Microsystems + NetEngine NP51R. + +config SH_SHMIN + bool "SHMIN" + depends on CPU_SUBTYPE_SH7706 + select CPU_HAS_IPR_IRQ + help + Select SHMIN if configuring for the SHMIN board. + +config SH_LBOX_RE2 + bool "L-BOX RE2" + depends on CPU_SUBTYPE_SH7751R + select HAVE_PCI + help + Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2. + +config SH_X3PROTO + bool "SH-X3 Prototype board" + depends on CPU_SUBTYPE_SHX3 + select NO_IOPORT_MAP if !PCI + select IRQ_DOMAIN + +config SH_MAGIC_PANEL_R2 + bool "Magic Panel R2" + depends on CPU_SUBTYPE_SH7720 + select GPIOLIB + select GPIOLIB_LEGACY + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select Magic Panel R2 if configuring for Magic Panel R2. + +config SH_POLARIS + bool "SMSC Polaris" + select CPU_HAS_IPR_IRQ + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7709 + help + Select if configuring for an SMSC Polaris development board + +config SH_SH2007 + bool "SH-2007 board" + select NO_IOPORT_MAP + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7780 + help + SH-2007 is a single-board computer based around SH7780 chip + intended for embedded applications. + It has an Ethernet interface (SMC9118), direct connected + Compact Flash socket, two serial ports and PC-104 bus. + +config SH_APSH4A3A + bool "AP-SH4A-3A" + select SH_ALPHA_BOARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7785 + help + Select AP-SH4A-3A if configuring for an ALPHAPROJECT AP-SH4A-3A. + +config SH_APSH4AD0A + bool "AP-SH4AD-0A" + select SH_ALPHA_BOARD + select HAVE_PCI + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7786 + help + Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. + +source "arch/sh/boards/mach-r2d/Kconfig" +source "arch/sh/boards/mach-highlander/Kconfig" +source "arch/sh/boards/mach-sdk7780/Kconfig" +source "arch/sh/boards/mach-migor/Kconfig" +source "arch/sh/boards/mach-rsk/Kconfig" + +if SH_MAGIC_PANEL_R2 + +menu "Magic Panel R2 options" + +config SH_MAGIC_PANEL_R2_VERSION + int "Magic Panel R2 Version" + default "3" + help + Set the version of the Magic Panel R2 + +endmenu + +endif + +endmenu diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile new file mode 100644 index 000000000..fbbc350ca --- /dev/null +++ b/arch/sh/boards/Makefile @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Specific board support, not covered by a mach group. +# +obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o +obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o +obj-$(CONFIG_SH_SH2007) += board-sh2007.o +obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o +obj-$(CONFIG_SH_URQUELL) += board-urquell.o +obj-$(CONFIG_SH_SHMIN) += board-shmin.o +obj-$(CONFIG_SH_EDOSK7705) += board-edosk7705.o +obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o +obj-$(CONFIG_SH_ESPT) += board-espt.o +obj-$(CONFIG_SH_POLARIS) += board-polaris.o +obj-$(CONFIG_SH_TITAN) += board-titan.o +obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o +obj-$(CONFIG_SH_APSH4A3A) += board-apsh4a3a.o +obj-$(CONFIG_SH_APSH4AD0A) += board-apsh4ad0a.o + +obj-$(CONFIG_SH_DEVICE_TREE) += of-generic.o + +obj-$(CONFIG_SOLUTION_ENGINE) += mach-se/ +obj-$(CONFIG_SH_HP6XX) += mach-hp6xx/ +obj-$(CONFIG_SH_DREAMCAST) += mach-dreamcast/ +obj-$(CONFIG_SH_SH03) += mach-sh03/ +obj-$(CONFIG_SH_RTS7751R2D) += mach-r2d/ +obj-$(CONFIG_SH_HIGHLANDER) += mach-highlander/ +obj-$(CONFIG_SH_MIGOR) += mach-migor/ +obj-$(CONFIG_SH_AP325RXA) += mach-ap325rxa/ +obj-$(CONFIG_SH_KFR2R09) += mach-kfr2r09/ +obj-$(CONFIG_SH_ECOVEC) += mach-ecovec24/ +obj-$(CONFIG_SH_SDK7780) += mach-sdk7780/ +obj-$(CONFIG_SH_SDK7786) += mach-sdk7786/ +obj-$(CONFIG_SH_X3PROTO) += mach-x3proto/ +obj-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp/ +obj-$(CONFIG_SH_LANDISK) += mach-landisk/ +obj-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2/ +obj-$(CONFIG_SH_RSK) += mach-rsk/ diff --git a/arch/sh/boards/board-apsh4a3a.c b/arch/sh/boards/board-apsh4a3a.c new file mode 100644 index 000000000..abf19a947 --- /dev/null +++ b/arch/sh/boards/board-apsh4a3a.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ALPHAPROJECT AP-SH4A-3A Support. + * + * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd. + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x01000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0xA4000000, + .end = 0xA4000000 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x200), + .end = evt2irq(0x200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *apsh4a3a_devices[] __initdata = { + &nor_flash_device, + &smsc911x_device, +}; + +static int __init apsh4a3a_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(apsh4a3a_devices, + ARRAY_SIZE(apsh4a3a_devices)); +} +device_initcall(apsh4a3a_devices_setup); + +static int apsh4a3a_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333000); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init apsh4a3a_setup(char **cmdline_p) +{ + printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n"); +} + +static void __init apsh4a3a_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); +} + +/* Return the board specific boot mode pin configuration */ +static int apsh4a3a_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of SW1 and SW2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value &= ~MODE_PIN0; /* Clock Mode 16 */ + value &= ~MODE_PIN1; + value &= ~MODE_PIN2; + value &= ~MODE_PIN3; + value |= MODE_PIN4; + value &= ~MODE_PIN5; /* 16-bit Area0 bus width */ + value |= MODE_PIN6; /* Area 0 SRAM interface */ + value |= MODE_PIN7; + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN10; /* Crystal resonator */ + value |= MODE_PIN11; /* Display Unit */ + value |= MODE_PIN12; + value &= ~MODE_PIN13; /* 29-bit address mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_apsh4a3a __initmv = { + .mv_name = "AP-SH4A-3A", + .mv_setup = apsh4a3a_setup, + .mv_clk_init = apsh4a3a_clk_init, + .mv_init_irq = apsh4a3a_init_irq, + .mv_mode_pins = apsh4a3a_mode_pins, +}; diff --git a/arch/sh/boards/board-apsh4ad0a.c b/arch/sh/boards/board-apsh4ad0a.c new file mode 100644 index 000000000..fa031a16c --- /dev/null +++ b/arch/sh/boards/board-apsh4ad0a.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ALPHAPROJECT AP-SH4AD-0A Support. + * + * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd. + * Copyright (C) 2010 Matt Fleming + * Copyright (C) 2010 Paul Mundt + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0xA4000000, + .end = 0xA4000000 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x200), + .end = evt2irq(0x200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *apsh4ad0a_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init apsh4ad0a_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(apsh4ad0a_devices, + ARRAY_SIZE(apsh4ad0a_devices)); +} +device_initcall(apsh4ad0a_devices_setup); + +static int apsh4ad0a_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of SW1 and SW2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode 3 */ + value |= MODE_PIN1; + value &= ~MODE_PIN2; + value &= ~MODE_PIN3; + value &= ~MODE_PIN4; /* 16-bit Area0 bus width */ + value |= MODE_PIN5; + value |= MODE_PIN6; + value |= MODE_PIN7; /* Normal mode */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Crystal resonator */ + value &= ~MODE_PIN10; /* 29-bit address mode */ + value &= ~MODE_PIN11; /* PCI-E Root port */ + value &= ~MODE_PIN12; /* 4 lane + 1 lane */ + value |= MODE_PIN13; /* AUD Enable */ + value &= ~MODE_PIN14; /* Normal Operation */ + + return value; +} + +static int apsh4ad0a_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333000); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init apsh4ad0a_setup(char **cmdline_p) +{ + pr_info("Alpha Project AP-SH4AD-0A support:\n"); +} + +static void __init apsh4ad0a_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_apsh4ad0a __initmv = { + .mv_name = "AP-SH4AD-0A", + .mv_setup = apsh4ad0a_setup, + .mv_mode_pins = apsh4ad0a_mode_pins, + .mv_clk_init = apsh4ad0a_clk_init, + .mv_init_irq = apsh4ad0a_init_irq, +}; diff --git a/arch/sh/boards/board-edosk7705.c b/arch/sh/boards/board-edosk7705.c new file mode 100644 index 000000000..0de7d603d --- /dev/null +++ b/arch/sh/boards/board-edosk7705.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/boards/renesas/edosk7705/setup.c + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine Support. + * + * Modified for edosk7705 development + * board by S. Dunn, 2003. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMC_IOBASE 0xA2000000 +#define SMC_IO_OFFSET 0x300 +#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) + +#define ETHERNET_IRQ evt2irq(0x320) + +static void __init sh_edosk7705_init_irq(void) +{ + make_imask_irq(ETHERNET_IRQ); +} + +/* eth initialization functions */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC_IOADDR, + .end = SMC_IOADDR + SZ_32 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ETHERNET_IRQ, + .end = ETHERNET_IRQ, + .flags = IORESOURCE_IRQ , + } +}; + +static struct platform_device smc91x_dev = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res, + + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* platform init code */ +static struct platform_device *edosk7705_devices[] __initdata = { + &smc91x_dev, +}; + +static int __init init_edosk7705_devices(void) +{ + return platform_add_devices(edosk7705_devices, + ARRAY_SIZE(edosk7705_devices)); +} +device_initcall(init_edosk7705_devices); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_edosk7705 __initmv = { + .mv_name = "EDOSK7705", + .mv_init_irq = sh_edosk7705_init_irq, +}; diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c new file mode 100644 index 000000000..7569d85c5 --- /dev/null +++ b/arch/sh/boards/board-edosk7760.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas Europe EDOSK7760 Board Support + * + * Copyright (C) 2008 SPES Societa' Progettazione Elettronica e Software Ltd. + * Author: Luca Santini + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Bus state controller registers for CS4 area */ +#define BSC_CS4BCR 0xA4FD0010 +#define BSC_CS4WCR 0xA4FD0030 + +#define SMC_IOBASE 0xA2000000 +#define SMC_IO_OFFSET 0x300 +#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) + +/* NOR flash */ +static struct mtd_partition edosk7760_nor_flash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + }, { + .name = "fs", + .offset = MTDPART_OFS_APPEND, + .size = (26 << 20), + }, { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data edosk7760_nor_flash_data = { + .width = 4, + .parts = edosk7760_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(edosk7760_nor_flash_partitions), +}; + +static struct resource edosk7760_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x00000000 + SZ_32M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device edosk7760_nor_flash_device = { + .name = "physmap-flash", + .resource = edosk7760_nor_flash_resources, + .num_resources = ARRAY_SIZE(edosk7760_nor_flash_resources), + .dev = { + .platform_data = &edosk7760_nor_flash_data, + }, +}; + +/* i2c initialization functions */ +static struct sh7760_i2c_platdata i2c_pd = { + .speed_khz = 400, +}; + +static struct resource sh7760_i2c1_res[] = { + { + .start = SH7760_I2C1_MMIO, + .end = SH7760_I2C1_MMIOEND, + .flags = IORESOURCE_MEM, + },{ + .start = evt2irq(0x9e0), + .end = evt2irq(0x9e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh7760_i2c1_dev = { + .dev = { + .platform_data = &i2c_pd, + }, + + .name = SH7760_I2C_DEVNAME, + .id = 1, + .resource = sh7760_i2c1_res, + .num_resources = ARRAY_SIZE(sh7760_i2c1_res), +}; + +static struct resource sh7760_i2c0_res[] = { + { + .start = SH7760_I2C0_MMIO, + .end = SH7760_I2C0_MMIOEND, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x9c0), + .end = evt2irq(0x9c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh7760_i2c0_dev = { + .dev = { + .platform_data = &i2c_pd, + }, + .name = SH7760_I2C_DEVNAME, + .id = 0, + .resource = sh7760_i2c0_res, + .num_resources = ARRAY_SIZE(sh7760_i2c0_res), +}; + +/* eth initialization functions */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC_IOADDR, + .end = SMC_IOADDR + SZ_32 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x2a0), + .end = evt2irq(0x2a0), + .flags = IORESOURCE_IRQ , + } +}; + +static struct platform_device smc91x_dev = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res, + + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* platform init code */ +static struct platform_device *edosk7760_devices[] __initdata = { + &smc91x_dev, + &edosk7760_nor_flash_device, + &sh7760_i2c0_dev, + &sh7760_i2c1_dev, +}; + +static int __init init_edosk7760_devices(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); + + return platform_add_devices(edosk7760_devices, + ARRAY_SIZE(edosk7760_devices)); +} +device_initcall(init_edosk7760_devices); + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_edosk7760 __initmv = { + .mv_name = "EDOSK7760", +}; diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c new file mode 100644 index 000000000..6e784b5cf --- /dev/null +++ b/arch/sh/boards/board-espt.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Data Technology Inc. ESPT-GIGA board support + * + * Copyright (C) 2008, 2009 Renesas Solutions Corp. + * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NOR Flash */ +static struct mtd_partition espt_nor_flash_partitions[] = { + { + .name = "U-Boot", + .offset = 0, + .size = (2 * SZ_128K), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "Linux-Kernel", + .offset = MTDPART_OFS_APPEND, + .size = (20 * SZ_128K), + }, { + .name = "Root Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data espt_nor_flash_data = { + .width = 2, + .parts = espt_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(espt_nor_flash_partitions), +}; + +static struct resource espt_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0, + .end = SZ_8M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device espt_nor_flash_device = { + .name = "physmap-flash", + .resource = espt_nor_flash_resources, + .num_resources = ARRAY_SIZE(espt_nor_flash_resources), + .dev = { + .platform_data = &espt_nor_flash_data, + }, +}; + +/* SH-Ether */ +static struct resource sh_eth_resources[] = { + { + .start = 0xFEE00800, /* use eth1 */ + .end = 0xFEE00F7C - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 0xFEE01800, /* TSU */ + .end = 0xFEE01FFF, + .flags = IORESOURCE_MEM, + }, { + + .start = evt2irq(0x920), /* irq number */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7763_eth_pdata = { + .phy = 0, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device espt_eth_device = { + .name = "sh7763-gether", + .resource = sh_eth_resources, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .dev = { + .platform_data = &sh7763_eth_pdata, + }, +}; + +static struct platform_device *espt_devices[] __initdata = { + &espt_nor_flash_device, + &espt_eth_device, +}; + +static int __init espt_devices_setup(void) +{ + return platform_add_devices(espt_devices, + ARRAY_SIZE(espt_devices)); +} +device_initcall(espt_devices_setup); + +static struct sh_machine_vector mv_espt __initmv = { + .mv_name = "ESPT-GIGA", +}; diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c new file mode 100644 index 000000000..3f14118a1 --- /dev/null +++ b/arch/sh/boards/board-magicpanelr2.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/arch/sh/boards/magicpanel/setup.c + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * Magic Panel Release 2 board setup + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) + +/* Wait until reset finished. Timeout is 100ms. */ +static int __init ethernet_reset_finished(void) +{ + int i; + + if (LAN9115_READY) + return 1; + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (LAN9115_READY) + return 1; + } + + return 0; +} + +static void __init reset_ethernet(void) +{ + /* PMDR: LAN_RESET=on */ + CLRBITS_OUTB(0x10, PORT_PMDR); + + udelay(200); + + /* PMDR: LAN_RESET=off */ + SETBITS_OUTB(0x10, PORT_PMDR); +} + +static void __init setup_chip_select(void) +{ + /* CS2: LAN (0x08000000 - 0x0bffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x36db0400, CS2BCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x000003c0, CS2WCR); + + /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS4BCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x00100981, CS4WCR); + + /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS5ABCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x00100981, CS5AWCR); + + /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS5BBCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x00100981, CS5BWCR); + + /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS6ABCR); + /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ + __raw_writel(0x001009C1, CS6AWCR); +} + +static void __init setup_port_multiplexing(void) +{ + /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); + * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); + */ + __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ + + /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); + * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); + */ + __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ + + /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); + * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; + */ + __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ + + /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); + * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); + */ + __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ + + /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; + * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; + */ + __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ + + /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; + * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); + */ + __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ + + /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); + * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); + */ + __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ + + /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); + * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; + */ + __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ + + /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; + * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; + */ + __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ + + /* K7 (x); K6 (x); K5 (x); K4 (x); + * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) + */ + __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ + + /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; + * L3 TCK; L2 (x); L1 (x); L0 (x); + */ + __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ + + /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); + * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); + * M1 CS5B(CAN3_CS); M0 GPI+(nc); + */ + __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ + + /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, + * LAN_RESET=off, BUZZER=off, LCD_BL=off + */ +#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 + __raw_writeb(0x30, PORT_PMDR); +#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 + __raw_writeb(0xF0, PORT_PMDR); +#else +#error Unknown revision of PLATFORM_MP_R2 +#endif + + /* P7 (x); P6 (x); P5 (x); + * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); + * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) + */ + __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ + __raw_writeb(0x10, PORT_PPDR); + + /* R7 A25; R6 A24; R5 A23; R4 A22; + * R3 A21; R2 A20; R1 A19; R0 A0; + */ + gpio_request(GPIO_FN_A25, NULL); + gpio_request(GPIO_FN_A24, NULL); + gpio_request(GPIO_FN_A23, NULL); + gpio_request(GPIO_FN_A22, NULL); + gpio_request(GPIO_FN_A21, NULL); + gpio_request(GPIO_FN_A20, NULL); + gpio_request(GPIO_FN_A19, NULL); + gpio_request(GPIO_FN_A0, NULL); + + /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); + * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; + */ + __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ + + /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; + * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) + */ + __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ + + /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); + * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; + */ + __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ + + /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); + * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); + */ + __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ +} + +static void __init mpr2_setup(char **cmdline_p) +{ + /* set Pin Select Register A: + * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, + * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND + */ + __raw_writew(0xAABC, PORT_PSELA); + /* set Pin Select Register B: + * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, + * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved + */ + __raw_writew(0x3C00, PORT_PSELB); + /* set Pin Select Register C: + * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved + */ + __raw_writew(0x0000, PORT_PSELC); + /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, + * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved + */ + __raw_writew(0x0000, PORT_PSELD); + /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ + __raw_writew(0x0101, PORT_UTRCTL); + /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ + __raw_writew(0xA5C0, PORT_UCLKCR_W); + + setup_chip_select(); + + setup_port_multiplexing(); + + reset_ethernet(); + + printk(KERN_INFO "Magic Panel Release 2 A.%i\n", + CONFIG_SH_MAGIC_PANEL_R2_VERSION); + + if (ethernet_reset_finished() == 0) + printk(KERN_WARNING "Ethernet not ready\n"); +} + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0xa8000000, + .end = 0xabffffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x660), + .end = evt2irq(0x660), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct heartbeat_data heartbeat_data = { + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct mtd_partition mpr2_partitions[] = { + /* Reserved for bootloader, read-only */ + { + .name = "Bootloader", + .offset = 0x00000000UL, + .size = MPR2_MTD_BOOTLOADER_SIZE, + .mask_flags = MTD_WRITEABLE, + }, + /* Reserved for kernel image */ + { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = MPR2_MTD_KERNEL_SIZE, + }, + /* Rest is used for Flash FS */ + { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .parts = mpr2_partitions, + .nr_parts = ARRAY_SIZE(mpr2_partitions), + .width = 2, +}; + +static struct resource flash_resource = { + .start = 0x00000000, + .end = 0x2000000UL, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +/* + * Add all resources to the platform_device + */ + +static struct platform_device *mpr2_devices[] __initdata = { + &heartbeat_device, + &smsc911x_device, + &flash_device, +}; + + +static int __init mpr2_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); +} +device_initcall(mpr2_devices_setup); + +/* + * Initialize IRQ setting + */ +static void __init init_mpr2_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ + + irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ + irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ + irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ + irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ + irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ + irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ + + intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ + intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ + intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ + intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ +} + +/* + * The Machine Vector + */ + +static struct sh_machine_vector mv_mpr2 __initmv = { + .mv_name = "mpr2", + .mv_setup = mpr2_setup, + .mv_init_irq = init_mpr2_IRQ, +}; diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c new file mode 100644 index 000000000..3de7bac01 --- /dev/null +++ b/arch/sh/boards/board-polaris.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * June 2006 Steve Glendinning + * + * Polaris-specific resource declaration + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BCR2 (0xFFFFFF62) +#define WCR2 (0xFFFFFF66) +#define AREA5_WAIT_CTRL (0x1C00) +#define WAIT_STATES_10 (0x7) + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = PA_EXT5, + .end = PA_EXT5 + 0x1fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = IRQ0_IRQ, + .end = IRQ0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), +}; + +static struct resource heartbeat_resource = { + .start = PORT_PCDR, + .end = PORT_PCDR, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct platform_device *polaris_devices[] __initdata = { + &smsc911x_device, + &heartbeat_device, +}; + +static int __init polaris_initialise(void) +{ + u16 wcr, bcr_mask; + + printk(KERN_INFO "Configuring Polaris external bus\n"); + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + /* Configure area 5 with 2 wait states */ + wcr = __raw_readw(WCR2); + wcr &= (~AREA5_WAIT_CTRL); + wcr |= (WAIT_STATES_10 << 10); + __raw_writew(wcr, WCR2); + + /* Configure area 5 for 32-bit access */ + bcr_mask = __raw_readw(BCR2); + bcr_mask |= 1 << 10; + __raw_writew(bcr_mask, BCR2); + + return platform_add_devices(polaris_devices, + ARRAY_SIZE(polaris_devices)); +} +arch_initcall(polaris_initialise); + +static struct ipr_data ipr_irq_table[] = { + /* External IRQs */ + { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */ + { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */ +}; + +static unsigned long ipr_offsets[] = { + INTC_IPRC +}; + +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + .chip = { + .name = "sh7709-ext", + }, +}; + +static void __init init_polaris_irq(void) +{ + /* Disable all interrupts */ + __raw_writew(0, BCR_ILCRA); + __raw_writew(0, BCR_ILCRB); + __raw_writew(0, BCR_ILCRC); + __raw_writew(0, BCR_ILCRD); + __raw_writew(0, BCR_ILCRE); + __raw_writew(0, BCR_ILCRF); + __raw_writew(0, BCR_ILCRG); + + register_ipr_controller(&ipr_irq_desc); +} + +static struct sh_machine_vector mv_polaris __initmv = { + .mv_name = "Polaris", + .mv_init_irq = init_polaris_irq, +}; diff --git a/arch/sh/boards/board-secureedge5410.c b/arch/sh/boards/board-secureedge5410.c new file mode 100644 index 000000000..603a82325 --- /dev/null +++ b/arch/sh/boards/board-secureedge5410.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2002 David McCullough + * Copyright (C) 2003 Paul Mundt + * + * Based on files with the following comments: + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned short secureedge5410_ioport; + +/* + * EraseConfig handling functions + */ +static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) +{ + printk("SnapGear: erase switch interrupt!\n"); + + return IRQ_HANDLED; +} + +static int __init eraseconfig_init(void) +{ + unsigned int irq = evt2irq(0x240); + + printk("SnapGear: EraseConfig init\n"); + + /* Setup "EraseConfig" switch on external IRQ 0 */ + if (request_irq(irq, eraseconfig_interrupt, 0, "Erase Config", NULL)) + printk("SnapGear: failed to register IRQ%d for Reset witch\n", + irq); + else + printk("SnapGear: registered EraseConfig switch on IRQ%d\n", + irq); + return 0; +} +device_initcall(eraseconfig_init); + +/* + * Initialize IRQ setting + * + * IRL0 = erase switch + * IRL1 = eth0 + * IRL2 = eth1 + * IRL3 = crypto + */ +static void __init init_snapgear_IRQ(void) +{ + printk("Setup SnapGear IRQ/IPR ...\n"); + /* enable individual interrupt mode for externals */ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_snapgear __initmv = { + .mv_name = "SnapGear SecureEdge5410", + .mv_init_irq = init_snapgear_IRQ, +}; diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c new file mode 100644 index 000000000..6ea85e480 --- /dev/null +++ b/arch/sh/boards/board-sh2007.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SH-2007 board support. + * + * Copyright (C) 2003, 2004 SUGIOKA Toshinobu + * Copyright (C) 2010 Hitoshi Mitake + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), + REGULATOR_SUPPLY("vddvario", "smsc911x.1"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.1"), +}; + +struct smsc911x_platform_config smc911x_info = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct resource smsc9118_0_resources[] = { + [0] = { + .start = SMC0_BASE, + .end = SMC0_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource smsc9118_1_resources[] = { + [0] = { + .start = SMC1_BASE, + .end = SMC1_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x280), + .end = evt2irq(0x280), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smsc9118_0_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc9118_0_resources), + .resource = smsc9118_0_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct platform_device smsc9118_1_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(smsc9118_1_resources), + .resource = smsc9118_1_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct resource cf_resources[] = { + [0] = { + .start = CF_BASE + CF_OFFSET, + .end = CF_BASE + CF_OFFSET + 0x0f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CF_BASE + CF_OFFSET + 0x206, + .end = CF_BASE + CF_OFFSET + 0x20f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x2c0), + .end = evt2irq(0x2c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_device = { + .name = "pata_platform", + .id = 0, + .num_resources = ARRAY_SIZE(cf_resources), + .resource = cf_resources, +}; + +static struct platform_device *sh2007_devices[] __initdata = { + &smsc9118_0_device, + &smsc9118_1_device, + &cf_device, +}; + +static int __init sh2007_io_init(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices)); + return 0; +} +subsys_initcall(sh2007_io_init); + +static void __init sh2007_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * Initialize the board + */ +static void __init sh2007_setup(char **cmdline_p) +{ + pr_info("SH-2007 Setup..."); + + /* setup wait control registers for area 5 */ + __raw_writel(CS5BCR_D, CS5BCR); + __raw_writel(CS5WCR_D, CS5WCR); + __raw_writel(CS5PCR_D, CS5PCR); + + pr_cont(" done.\n"); +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_sh2007 __initmv = { + .mv_setup = sh2007_setup, + .mv_name = "sh2007", + .mv_init_irq = sh2007_init_irq, +}; diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c new file mode 100644 index 000000000..6d18f59ef --- /dev/null +++ b/arch/sh/boards/board-sh7757lcr.c @@ -0,0 +1,604 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R0P7757LC0012RL Support. + * + * Copyright (C) 2009 - 2010 Renesas Solutions Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct resource heartbeat_resource = { + .start = 0xffec005c, /* PUDR */ + .end = 0xffec005c, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* Fast Ethernet */ +#define GBECONT 0xffc10100 +#define GBECONT_RMII1 BIT(17) +#define GBECONT_RMII0 BIT(16) +static void sh7757_eth_set_mdio_gate(void *addr) +{ + if (((unsigned long)addr & 0x00000fff) < 0x0800) + writel(readl(GBECONT) | GBECONT_RMII0, GBECONT); + else + writel(readl(GBECONT) | GBECONT_RMII1, GBECONT); +} + +static struct resource sh_eth0_resources[] = { + { + .start = 0xfef00000, + .end = 0xfef001ff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth0_pdata = { + .phy = 1, + .set_mdio_gate = sh7757_eth_set_mdio_gate, +}; + +static struct platform_device sh7757_eth0_device = { + .name = "sh7757-ether", + .resource = sh_eth0_resources, + .id = 0, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .dev = { + .platform_data = &sh7757_eth0_pdata, + }, +}; + +static struct resource sh_eth1_resources[] = { + { + .start = 0xfef00800, + .end = 0xfef009ff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth1_pdata = { + .phy = 1, + .set_mdio_gate = sh7757_eth_set_mdio_gate, +}; + +static struct platform_device sh7757_eth1_device = { + .name = "sh7757-ether", + .resource = sh_eth1_resources, + .id = 1, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .dev = { + .platform_data = &sh7757_eth1_pdata, + }, +}; + +static void sh7757_eth_giga_set_mdio_gate(void *addr) +{ + if (((unsigned long)addr & 0x00000fff) < 0x0800) { + gpio_set_value(GPIO_PTT4, 1); + writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT); + } else { + gpio_set_value(GPIO_PTT4, 0); + writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT); + } +} + +static struct resource sh_eth_giga0_resources[] = { + { + .start = 0xfee00000, + .end = 0xfee007ff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x2960), + .end = evt2irq(0x2960), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { + .phy = 18, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga0_device = { + .name = "sh7757-gether", + .resource = sh_eth_giga0_resources, + .id = 2, + .num_resources = ARRAY_SIZE(sh_eth_giga0_resources), + .dev = { + .platform_data = &sh7757_eth_giga0_pdata, + }, +}; + +static struct resource sh_eth_giga1_resources[] = { + { + .start = 0xfee00800, + .end = 0xfee00fff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x2980), + .end = evt2irq(0x2980), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { + .phy = 19, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga1_device = { + .name = "sh7757-gether", + .resource = sh_eth_giga1_resources, + .id = 3, + .num_resources = ARRAY_SIZE(sh_eth_giga1_resources), + .dev = { + .platform_data = &sh7757_eth_giga1_pdata, + }, +}; + +/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +}; + +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .start = 0xffcb0000, + .end = 0xffcb00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1c60), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = evt2irq(0x1c80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0x0f, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_NONREMOVABLE, + .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, + .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, + .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + +/* SDHI0 */ +static struct tmio_mmc_data sdhi_info = { + .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX, + .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX, + .capabilities = MMC_CAP_SD_HIGHSPEED, +}; + +static struct resource sdhi_resources[] = { + [0] = { + .start = 0xffe50000, + .end = 0xffe500ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi_resources), + .resource = sdhi_resources, + .id = 0, + .dev = { + .platform_data = &sdhi_info, + }, +}; + +static int usbhs0_get_id(struct platform_device *pdev) +{ + return USBHS_GADGET; +} + +static struct renesas_usbhs_platform_info usb0_data = { + .platform_callback = { + .get_id = usbhs0_get_id, + }, + .driver_param = { + .buswait_bwait = 5, + } +}; + +static struct resource usb0_resources[] = { + [0] = { + .start = 0xfe450000, + .end = 0xfe4501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x840), + .end = evt2irq(0x840), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb0_device = { + .name = "renesas_usbhs", + .id = 0, + .dev = { + .platform_data = &usb0_data, + }, + .num_resources = ARRAY_SIZE(usb0_resources), + .resource = usb0_resources, +}; + +static struct platform_device *sh7757lcr_devices[] __initdata = { + &heartbeat_device, + &sh7757_eth0_device, + &sh7757_eth1_device, + &sh7757_eth_giga0_device, + &sh7757_eth_giga1_device, + &sh_mmcif_device, + &sdhi_device, + &usb0_device, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .type = "m25px64", +}; + +static struct spi_board_info spi_board_info[] = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &spi_flash_data, + }, +}; + +static int __init sh7757lcr_devices_setup(void) +{ + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + /* RGMII (PTA) */ + gpio_request(GPIO_FN_ET0_MDC, NULL); + gpio_request(GPIO_FN_ET0_MDIO, NULL); + gpio_request(GPIO_FN_ET1_MDC, NULL); + gpio_request(GPIO_FN_ET1_MDIO, NULL); + + /* ONFI (PTB, PTZ) */ + gpio_request(GPIO_FN_ON_NRE, NULL); + gpio_request(GPIO_FN_ON_NWE, NULL); + gpio_request(GPIO_FN_ON_NWP, NULL); + gpio_request(GPIO_FN_ON_NCE0, NULL); + gpio_request(GPIO_FN_ON_R_B0, NULL); + gpio_request(GPIO_FN_ON_ALE, NULL); + gpio_request(GPIO_FN_ON_CLE, NULL); + + gpio_request(GPIO_FN_ON_DQ7, NULL); + gpio_request(GPIO_FN_ON_DQ6, NULL); + gpio_request(GPIO_FN_ON_DQ5, NULL); + gpio_request(GPIO_FN_ON_DQ4, NULL); + gpio_request(GPIO_FN_ON_DQ3, NULL); + gpio_request(GPIO_FN_ON_DQ2, NULL); + gpio_request(GPIO_FN_ON_DQ1, NULL); + gpio_request(GPIO_FN_ON_DQ0, NULL); + + /* IRQ8 to 0 (PTB, PTC) */ + gpio_request(GPIO_FN_IRQ8, NULL); + gpio_request(GPIO_FN_IRQ7, NULL); + gpio_request(GPIO_FN_IRQ6, NULL); + gpio_request(GPIO_FN_IRQ5, NULL); + gpio_request(GPIO_FN_IRQ4, NULL); + gpio_request(GPIO_FN_IRQ3, NULL); + gpio_request(GPIO_FN_IRQ2, NULL); + gpio_request(GPIO_FN_IRQ1, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + /* SPI0 (PTD) */ + gpio_request(GPIO_FN_SP0_MOSI, NULL); + gpio_request(GPIO_FN_SP0_MISO, NULL); + gpio_request(GPIO_FN_SP0_SCK, NULL); + gpio_request(GPIO_FN_SP0_SCK_FB, NULL); + gpio_request(GPIO_FN_SP0_SS0, NULL); + gpio_request(GPIO_FN_SP0_SS1, NULL); + gpio_request(GPIO_FN_SP0_SS2, NULL); + gpio_request(GPIO_FN_SP0_SS3, NULL); + + /* RMII 0/1 (PTE, PTF) */ + gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII0_TXD1, NULL); + gpio_request(GPIO_FN_RMII0_TXD0, NULL); + gpio_request(GPIO_FN_RMII0_TXEN, NULL); + gpio_request(GPIO_FN_RMII0_REFCLK, NULL); + gpio_request(GPIO_FN_RMII0_RXD1, NULL); + gpio_request(GPIO_FN_RMII0_RXD0, NULL); + gpio_request(GPIO_FN_RMII0_RX_ER, NULL); + gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII1_TXD1, NULL); + gpio_request(GPIO_FN_RMII1_TXD0, NULL); + gpio_request(GPIO_FN_RMII1_TXEN, NULL); + gpio_request(GPIO_FN_RMII1_REFCLK, NULL); + gpio_request(GPIO_FN_RMII1_RXD1, NULL); + gpio_request(GPIO_FN_RMII1_RXD0, NULL); + gpio_request(GPIO_FN_RMII1_RX_ER, NULL); + + /* eMMC (PTG) */ + gpio_request(GPIO_FN_MMCCLK, NULL); + gpio_request(GPIO_FN_MMCCMD, NULL); + gpio_request(GPIO_FN_MMCDAT7, NULL); + gpio_request(GPIO_FN_MMCDAT6, NULL); + gpio_request(GPIO_FN_MMCDAT5, NULL); + gpio_request(GPIO_FN_MMCDAT4, NULL); + gpio_request(GPIO_FN_MMCDAT3, NULL); + gpio_request(GPIO_FN_MMCDAT2, NULL); + gpio_request(GPIO_FN_MMCDAT1, NULL); + gpio_request(GPIO_FN_MMCDAT0, NULL); + + /* LPC (PTG, PTH, PTQ, PTU) */ + gpio_request(GPIO_FN_SERIRQ, NULL); + gpio_request(GPIO_FN_LPCPD, NULL); + gpio_request(GPIO_FN_LDRQ, NULL); + gpio_request(GPIO_FN_WP, NULL); + gpio_request(GPIO_FN_FMS0, NULL); + gpio_request(GPIO_FN_LAD3, NULL); + gpio_request(GPIO_FN_LAD2, NULL); + gpio_request(GPIO_FN_LAD1, NULL); + gpio_request(GPIO_FN_LAD0, NULL); + gpio_request(GPIO_FN_LFRAME, NULL); + gpio_request(GPIO_FN_LRESET, NULL); + gpio_request(GPIO_FN_LCLK, NULL); + gpio_request(GPIO_FN_LGPIO7, NULL); + gpio_request(GPIO_FN_LGPIO6, NULL); + gpio_request(GPIO_FN_LGPIO5, NULL); + gpio_request(GPIO_FN_LGPIO4, NULL); + + /* SPI1 (PTH) */ + gpio_request(GPIO_FN_SP1_MOSI, NULL); + gpio_request(GPIO_FN_SP1_MISO, NULL); + gpio_request(GPIO_FN_SP1_SCK, NULL); + gpio_request(GPIO_FN_SP1_SCK_FB, NULL); + gpio_request(GPIO_FN_SP1_SS0, NULL); + gpio_request(GPIO_FN_SP1_SS1, NULL); + + /* SDHI (PTI) */ + gpio_request(GPIO_FN_SD_WP, NULL); + gpio_request(GPIO_FN_SD_CD, NULL); + gpio_request(GPIO_FN_SD_CLK, NULL); + gpio_request(GPIO_FN_SD_CMD, NULL); + gpio_request(GPIO_FN_SD_D3, NULL); + gpio_request(GPIO_FN_SD_D2, NULL); + gpio_request(GPIO_FN_SD_D1, NULL); + gpio_request(GPIO_FN_SD_D0, NULL); + + /* SCIF3/4 (PTJ, PTW) */ + gpio_request(GPIO_FN_RTS3, NULL); + gpio_request(GPIO_FN_CTS3, NULL); + gpio_request(GPIO_FN_TXD3, NULL); + gpio_request(GPIO_FN_RXD3, NULL); + gpio_request(GPIO_FN_RTS4, NULL); + gpio_request(GPIO_FN_RXD4, NULL); + gpio_request(GPIO_FN_TXD4, NULL); + gpio_request(GPIO_FN_CTS4, NULL); + + /* SERMUX (PTK, PTL, PTO, PTV) */ + gpio_request(GPIO_FN_COM2_TXD, NULL); + gpio_request(GPIO_FN_COM2_RXD, NULL); + gpio_request(GPIO_FN_COM2_RTS, NULL); + gpio_request(GPIO_FN_COM2_CTS, NULL); + gpio_request(GPIO_FN_COM2_DTR, NULL); + gpio_request(GPIO_FN_COM2_DSR, NULL); + gpio_request(GPIO_FN_COM2_DCD, NULL); + gpio_request(GPIO_FN_COM2_RI, NULL); + gpio_request(GPIO_FN_RAC_RXD, NULL); + gpio_request(GPIO_FN_RAC_RTS, NULL); + gpio_request(GPIO_FN_RAC_CTS, NULL); + gpio_request(GPIO_FN_RAC_DTR, NULL); + gpio_request(GPIO_FN_RAC_DSR, NULL); + gpio_request(GPIO_FN_RAC_DCD, NULL); + gpio_request(GPIO_FN_RAC_TXD, NULL); + gpio_request(GPIO_FN_COM1_TXD, NULL); + gpio_request(GPIO_FN_COM1_RXD, NULL); + gpio_request(GPIO_FN_COM1_RTS, NULL); + gpio_request(GPIO_FN_COM1_CTS, NULL); + + writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ + + /* IIC (PTM, PTR, PTS) */ + gpio_request(GPIO_FN_SDA7, NULL); + gpio_request(GPIO_FN_SCL7, NULL); + gpio_request(GPIO_FN_SDA6, NULL); + gpio_request(GPIO_FN_SCL6, NULL); + gpio_request(GPIO_FN_SDA5, NULL); + gpio_request(GPIO_FN_SCL5, NULL); + gpio_request(GPIO_FN_SDA4, NULL); + gpio_request(GPIO_FN_SCL4, NULL); + gpio_request(GPIO_FN_SDA3, NULL); + gpio_request(GPIO_FN_SCL3, NULL); + gpio_request(GPIO_FN_SDA2, NULL); + gpio_request(GPIO_FN_SCL2, NULL); + gpio_request(GPIO_FN_SDA1, NULL); + gpio_request(GPIO_FN_SCL1, NULL); + gpio_request(GPIO_FN_SDA0, NULL); + gpio_request(GPIO_FN_SCL0, NULL); + + /* USB (PTN) */ + gpio_request(GPIO_FN_VBUS_EN, NULL); + gpio_request(GPIO_FN_VBUS_OC, NULL); + + /* SGPIO1/0 (PTN, PTO) */ + gpio_request(GPIO_FN_SGPIO1_CLK, NULL); + gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO1_DI, NULL); + gpio_request(GPIO_FN_SGPIO1_DO, NULL); + gpio_request(GPIO_FN_SGPIO0_CLK, NULL); + gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO0_DI, NULL); + gpio_request(GPIO_FN_SGPIO0_DO, NULL); + + /* WDT (PTN) */ + gpio_request(GPIO_FN_SUB_CLKIN, NULL); + + /* System (PTT) */ + gpio_request(GPIO_FN_STATUS1, NULL); + gpio_request(GPIO_FN_STATUS0, NULL); + + /* PWMX (PTT) */ + gpio_request(GPIO_FN_PWMX1, NULL); + gpio_request(GPIO_FN_PWMX0, NULL); + + /* R-SPI (PTV) */ + gpio_request(GPIO_FN_R_SPI_MOSI, NULL); + gpio_request(GPIO_FN_R_SPI_MISO, NULL); + gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); + gpio_request(GPIO_FN_R_SPI_SSL0, NULL); + gpio_request(GPIO_FN_R_SPI_SSL1, NULL); + + /* EVC (PTV, PTW) */ + gpio_request(GPIO_FN_EVENT7, NULL); + gpio_request(GPIO_FN_EVENT6, NULL); + gpio_request(GPIO_FN_EVENT5, NULL); + gpio_request(GPIO_FN_EVENT4, NULL); + gpio_request(GPIO_FN_EVENT3, NULL); + gpio_request(GPIO_FN_EVENT2, NULL); + gpio_request(GPIO_FN_EVENT1, NULL); + gpio_request(GPIO_FN_EVENT0, NULL); + + /* LED for heartbeat */ + gpio_request(GPIO_PTU3, NULL); + gpio_direction_output(GPIO_PTU3, 1); + gpio_request(GPIO_PTU2, NULL); + gpio_direction_output(GPIO_PTU2, 1); + gpio_request(GPIO_PTU1, NULL); + gpio_direction_output(GPIO_PTU1, 1); + gpio_request(GPIO_PTU0, NULL); + gpio_direction_output(GPIO_PTU0, 1); + + /* control for MDIO of Gigabit Ethernet */ + gpio_request(GPIO_PTT4, NULL); + gpio_direction_output(GPIO_PTT4, 1); + + /* control for eMMC */ + gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ + gpio_direction_output(GPIO_PTT7, 0); + gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ + gpio_direction_output(GPIO_PTT6, 0); + gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ + gpio_direction_output(GPIO_PTT5, 1); + + /* register SPI device information */ + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + + /* General platform */ + return platform_add_devices(sh7757lcr_devices, + ARRAY_SIZE(sh7757lcr_devices)); +} +arch_initcall(sh7757lcr_devices_setup); + +/* Initialize IRQ setting */ +static void __init init_sh7757lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* Initialize the board */ +static void __init sh7757lcr_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); +} + +static int sh7757lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S3 (Low active). + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode: 1 */ + + return value; +} + +/* The Machine Vector */ +static struct sh_machine_vector mv_sh7757lcr __initmv = { + .mv_name = "SH7757LCR", + .mv_setup = sh7757lcr_setup, + .mv_init_irq = init_sh7757lcr_IRQ, + .mv_mode_pins = sh7757lcr_mode_pins, +}; + diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c new file mode 100644 index 000000000..25c4968f0 --- /dev/null +++ b/arch/sh/boards/board-sh7785lcr.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas Technology Corp. R0P7785LC0011RL Support. + * + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * NOTE: This board has 2 physical memory maps. + * Please look at include/asm-sh/sh7785lcr.h or hardware manual. + */ +static struct resource heartbeat_resource = { + .start = PLD_LEDCR, + .end = PLD_LEDCR, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct r8a66597_platdata r8a66597_data = { + .xtal = R8A66597_PLATDATA_XTAL_12MHZ, + .vif = 1, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .start = R8A66597_ADDR, + .end = R8A66597_ADDR + R8A66597_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct resource sm501_resources[] = { + [0] = { + .start = SM107_MEM_ADDR, + .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SM107_REG_ADDR, + .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x340), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fb_videomode sm501_default_mode_crt = { + .pixclock = 35714, /* 28MHz */ + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}; + +static struct fb_videomode sm501_default_mode_pnl = { + .pixclock = 40000, /* 25MHz */ + .xres = 640, + .yres = 480, + .left_margin = 2, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = 0, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_pnl, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_PANEL_NO_VBIASEN, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_crt, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT, +}; + +static struct sm501_platdata_fb sm501_fb_pdata = { + .fb_route = SM501_FB_OWN, + .fb_crt = &sm501_pdata_fbsub_crt, + .fb_pnl = &sm501_pdata_fbsub_pnl, +}; + +static struct sm501_initdata sm501_initdata = { + .gpio_high = { + .set = 0x00001fe0, + .mask = 0x0, + }, + .devices = 0, + .mclk = 84 * 1000000, + .m1xclk = 112 * 1000000, +}; + +static struct sm501_platdata sm501_platform_data = { + .init = &sm501_initdata, + .fb = &sm501_fb_pdata, +}; + +static struct platform_device sm501_device = { + .name = "sm501", + .id = -1, + .dev = { + .platform_data = &sm501_platform_data, + }, + .num_resources = ARRAY_SIZE(sm501_resources), + .resource = sm501_resources, +}; + +static struct resource i2c_proto_resources[] = { + [0] = { + .start = PCA9564_PROTO_32BIT_ADDR, + .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = evt2irq(0x380), + .end = evt2irq(0x380), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c_resources[] = { + [0] = { + .start = PCA9564_ADDR, + .end = PCA9564_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = evt2irq(0x380), + .end = evt2irq(0x380), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct gpiod_lookup_table i2c_gpio_table = { + .dev_id = "i2c.0", + .table = { + GPIO_LOOKUP("pfc-sh7757", 0, "reset-gpios", GPIO_ACTIVE_LOW), + { }, + }, +}; + +static struct i2c_pca9564_pf_platform_data i2c_platform_data = { + .i2c_clock_speed = I2C_PCA_CON_330kHz, + .timeout = HZ, +}; + +static struct platform_device i2c_device = { + .name = "i2c-pca-platform", + .id = -1, + .dev = { + .platform_data = &i2c_platform_data, + }, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources, +}; + +static struct platform_device *sh7785lcr_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &r8a66597_usb_host_device, + &sm501_device, + &i2c_device, +}; + +static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; + +static int __init sh7785lcr_devices_setup(void) +{ + i2c_register_board_info(0, sh7785lcr_i2c_devices, + ARRAY_SIZE(sh7785lcr_i2c_devices)); + + if (mach_is_sh7785lcr_pt()) { + i2c_device.resource = i2c_proto_resources; + i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources); + } + + gpiod_add_lookup_table(&i2c_gpio_table); + return platform_add_devices(sh7785lcr_devices, + ARRAY_SIZE(sh7785lcr_devices)); +} +device_initcall(sh7785lcr_devices_setup); + +/* Initialize IRQ setting */ +static void __init init_sh7785lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +static int sh7785lcr_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + +static void sh7785lcr_power_off(void) +{ + unsigned char *p; + + p = ioremap(PLD_POFCR, PLD_POFCR + 1); + if (!p) { + printk(KERN_ERR "%s: ioremap error.\n", __func__); + return; + } + *p = 0x01; + iounmap(p); + set_bl_bit(); + while (1) + cpu_relax(); +} + +/* Initialize the board */ +static void __init sh7785lcr_setup(char **cmdline_p) +{ + void __iomem *sm501_reg; + + printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); + + pm_power_off = sh7785lcr_power_off; + + /* sm501 DRAM configuration */ + sm501_reg = ioremap(SM107_REG_ADDR, SM501_DRAM_CONTROL); + if (!sm501_reg) { + printk(KERN_ERR "%s: ioremap error.\n", __func__); + return; + } + + writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL); + iounmap(sm501_reg); +} + +/* Return the board specific boot mode pin configuration */ +static int sh7785lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S1 and S2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN4; /* Clock Mode 16 */ + value |= MODE_PIN5; /* 32-bit Area0 bus width */ + value |= MODE_PIN6; /* 32-bit Area0 bus width */ + value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sh7785lcr __initmv = { + .mv_name = "SH7785LCR", + .mv_setup = sh7785lcr_setup, + .mv_clk_init = sh7785lcr_clk_init, + .mv_init_irq = init_sh7785lcr_IRQ, + .mv_mode_pins = sh7785lcr_mode_pins, +}; + diff --git a/arch/sh/boards/board-shmin.c b/arch/sh/boards/board-shmin.c new file mode 100644 index 000000000..83296c0b7 --- /dev/null +++ b/arch/sh/boards/board-shmin.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/boards/shmin/setup.c + * + * Copyright (C) 2006 Takashi YOSHII + * + * SHMIN Support. + */ +#include +#include +#include +#include +#include +#include + +#define PFC_PHCR 0xa400010eUL +#define INTC_ICR1 0xa4000010UL + +static void __init init_shmin_irq(void) +{ + __raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ + __raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +static void __init shmin_setup(char **cmdline_p) +{ + __set_io_port_base(SHMIN_IO_BASE); +} + +static struct sh_machine_vector mv_shmin __initmv = { + .mv_name = "SHMIN", + .mv_setup = shmin_setup, + .mv_init_irq = init_shmin_irq, +}; diff --git a/arch/sh/boards/board-titan.c b/arch/sh/boards/board-titan.c new file mode 100644 index 000000000..074a848d8 --- /dev/null +++ b/arch/sh/boards/board-titan.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/boards/titan/setup.c - Setup for Titan + * + * Copyright (C) 2006 Jamie Lenehan + */ +#include +#include +#include +#include + +static void __init init_titan_irq(void) +{ + /* enable individual interrupt mode for externals */ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +static struct sh_machine_vector mv_titan __initmv = { + .mv_name = "Titan", + .mv_init_irq = init_titan_irq, +}; diff --git a/arch/sh/boards/board-urquell.c b/arch/sh/boards/board-urquell.c new file mode 100644 index 000000000..1f73c04d3 --- /dev/null +++ b/arch/sh/boards/board-urquell.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas Technology Corp. SH7786 Urquell Support. + * + * Copyright (C) 2008 Kuninori Morimoto + * Copyright (C) 2009, 2010 Paul Mundt + * + * Based on board-sh7785lcr.c + * Copyright (C) 2008 Yoshihiro Shimoda + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * bit 1234 5678 + *---------------------------- + * SW1 0101 0010 -> Pck 33MHz version + * (1101 0010) Pck 66MHz version + * SW2 0x1x xxxx -> little endian + * 29bit mode + * SW47 0001 1000 -> CS0 : on-board flash + * CS1 : SRAM, registers, LAN, PCMCIA + * 38400 bps for SCIF1 + * + * Address + * 0x00000000 - 0x04000000 (CS0) Nor Flash + * 0x04000000 - 0x04200000 (CS1) SRAM + * 0x05000000 - 0x05800000 (CS1) on board register + * 0x05800000 - 0x06000000 (CS1) LAN91C111 + * 0x06000000 - 0x06400000 (CS1) PCMCIA + * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 + * 0x10000000 - 0x14000000 (CS4) PCIe + * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM + * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM + * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash + * 0x1C000000 - (CS7) SH7786 Control register + */ + +/* HeartBeat */ +static struct resource heartbeat_resource = { + .start = BOARDREG(SLEDR), + .end = BOARDREG(SLEDR), + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* LAN91C111 */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "SMC91C111" , + .start = 0x05800300, + .end = 0x0580030f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x360), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* Nor Flash */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct platform_device *urquell_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, + &nor_flash_device, +}; + +static int __init urquell_devices_setup(void) +{ + /* USB */ + gpio_request(GPIO_FN_USB_OVC0, NULL); + gpio_request(GPIO_FN_USB_PENC0, NULL); + + /* enable LAN */ + __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, + UBOARDREG(IRL2MSKR)); + + return platform_add_devices(urquell_devices, + ARRAY_SIZE(urquell_devices)); +} +device_initcall(urquell_devices_setup); + +static void urquell_power_off(void) +{ + __raw_writew(0xa5a5, UBOARDREG(SRSTR)); +} + +static void __init urquell_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); +} + +static int urquell_mode_pins(void) +{ + return __raw_readw(UBOARDREG(MDSWMR)); +} + +static int urquell_clk_init(void) +{ + struct clk *clk; + int ret; + + /* + * Only handle the EXTAL case, anyone interfacing a crystal + * resonator will need to provide their own input clock. + */ + if (test_mode_pin(MODE_PIN9)) + return -EINVAL; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init urquell_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n"); + + pm_power_off = urquell_power_off; + + register_smp_ops(&shx3_smp_ops); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_urquell __initmv = { + .mv_name = "Urquell", + .mv_setup = urquell_setup, + .mv_init_irq = urquell_init_irq, + .mv_mode_pins = urquell_mode_pins, + .mv_clk_init = urquell_clk_init, +}; diff --git a/arch/sh/boards/mach-ap325rxa/Makefile b/arch/sh/boards/mach-ap325rxa/Makefile new file mode 100644 index 000000000..dba5d0c20 --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y := setup.o sdram.o + diff --git a/arch/sh/boards/mach-ap325rxa/sdram.S b/arch/sh/boards/mach-ap325rxa/sdram.S new file mode 100644 index 000000000..541c82cc3 --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/sdram.S @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * AP325RXA sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + */ + +#include +#include +#include +#include +#include +#include + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(ap325rxa_sdram_enter_start) + + /* SBSC: disable power down and put in self-refresh mode */ + mov.l 1f, r4 + mov.l 2f, r1 + mov.l @r4, r2 + or r1, r2 + mov.l 3f, r3 + and r3, r2 + mov.l r2, @r4 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +2: .long 0x00000400 +3: .long 0xffff7fff +ENTRY(ap325rxa_sdram_enter_end) + + .balign 4 +ENTRY(ap325rxa_sdram_leave_start) + + /* SBSC: set auto-refresh mode */ + mov.l 1f, r4 + mov.l @r4, r0 + mov.l 4f, r1 + and r1, r0 + mov.l r0, @r4 + mov.l 6f, r4 + mov.l 8f, r0 + mov.l @r4, r1 + mov #-1, r4 + add r4, r1 + or r1, r0 + mov.l 7f, r1 + mov.l r0, @r1 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +4: .long 0xfffffbff +6: .long 0xfe40001c /* RTCOR */ +7: .long 0xfe400018 /* RTCNT */ +8: .long 0xa55a0000 +ENTRY(ap325rxa_sdram_leave_end) diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c new file mode 100644 index 000000000..17c3f568d --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/setup.c @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas - AP-325RXA + * (Compatible with Algo System ., LTD. - AP-320A) + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Author : Yusuke Goda + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include