From a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255 Mon Sep 17 00:00:00 2001 From: Jinke Han Date: Tue, 8 Sep 2026 15:37:42 +0800 Subject: x86/kprobes: Fix crash when probing CS CALL instructions When using eBPF to probe CS CALL instructions within a function, a crash can be triggered. The eBPF tool probes offset 257 of the __hrtimer_run_queues() function: <__hrtimer_run_queues+249>: nopl 0x0(%rax,%rax,1) <__hrtimer_run_queues+254>: mov %r14,%rdi <__hrtimer_run_queues+257>: cs call <__x86_indirect_thunk_r12> <__hrtimer_run_queues+263>: mov %eax,%r12d <__hrtimer_run_queues+266>: xchg %ax,%ax <__hrtimer_run_queues+268>: mov %r13,%rdi Which triggers this crash: BUG: unable to handle page fault for address: 00000000000f41c9 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP NOPTI CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: P RIP: 0010:__hrtimer_run_queues+0x106/0x230 Note that __hrtimer_run_queues+0x106 is __hrtimer_run_queues+262, which is at the 6th byte of the above CS CALL instruction. Since the CS CALL instruction occupies 6 bytes, the exception occurred in the middle of that call instruction. The root cause is that when using eBPF tools to probe in the middle of a function, a kprobe with INT3 is used as the underlying implementation. During single-step emulation of the original CALL instruction, int3_emulate_call() assumes that the probed CALL instruction is 5 bytes long. However, the actual CS-prefixed CALL instruction occupies 6 bytes, so it constructs an incorrect exception return address. When the CPU returns from the kprobe handler, the next instruction to be executed is at the address of the last byte of that CS CALL instruction. Coincidentally, starting from that address, the CPU fetches and decodes a completely different instruction, which ultimately triggers a kernel crash. Fix the issue by using the actual instruction length obtained from the instruction decoder when constructing the exception return address, rather than relying on the hardcoded CALL_INSN_SIZE macro. [ mingo: Refined the changelog ] Fixes: 6256e668b7af ("x86/kprobes: Use int3 instead of debug trap for single-step") Suggested-by: Masami Hiramatsu (Google) Signed-off-by: Jinke Han Signed-off-by: Ingo Molnar Reviewed-by: Masami Hiramatsu (Google) Acked-by: Yafang Shao Acked-by: Borislav Petkov Cc: Peter Zijlstra Link: https://patch.msgid.link/20260908073742.GA10517@didi-ThinkCentre-M920t-N000 --- arch/sh/cchips/Kconfig | 46 ++++++++++++++++ arch/sh/cchips/hd6446x/Makefile | 4 ++ arch/sh/cchips/hd6446x/hd64461.c | 112 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 arch/sh/cchips/Kconfig create mode 100644 arch/sh/cchips/hd6446x/Makefile create mode 100644 arch/sh/cchips/hd6446x/hd64461.c (limited to 'arch/sh/cchips') diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig new file mode 100644 index 000000000..9659a0bc5 --- /dev/null +++ b/arch/sh/cchips/Kconfig @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 +menu "Companion Chips" + +config HD6446X_SERIES + bool + +choice + prompt "HD6446x options" + depends on HD6446X_SERIES + default HD64461 + +config HD64461 + bool "Hitachi HD64461 companion chip support" + help + The Hitachi HD64461 provides an interface for + the SH7709 CPU, supporting a LCD controller, + CRT color controller, IrDA up to 4 Mbps, and a + PCMCIA controller supporting 2 slots. + + More information is available at + . + + Say Y if you want support for the HD64461. + Otherwise, say N. + +endchoice + +# These will also be split into the Kconfig's below +config HD64461_IRQ + int "HD64461 IRQ" + depends on HD64461 + default "52" + help + The default setting of the HD64461 IRQ is 52. + + Do not change this unless you know what you are doing. + +config HD64461_ENABLER + bool "HD64461 PCMCIA enabler" + depends on HD64461 + help + Say Y here if you want to enable PCMCIA support + via the HD64461 companion chip. + Otherwise, say N. + +endmenu diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile new file mode 100644 index 000000000..6673e0abe --- /dev/null +++ b/arch/sh/cchips/hd6446x/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_HD64461) += hd64461.o + +ccflags-y := -Werror diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c new file mode 100644 index 000000000..81764882d --- /dev/null +++ b/arch/sh/cchips/hd6446x/hd64461.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2000 YAEGASHI Takeshi + * Hitachi HD64461 companion chip support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* This belongs in cpu specific */ +#define INTC_ICR1 0xA4140010UL + +static void hd64461_mask_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + unsigned short nimr; + unsigned short mask = 1 << (irq - HD64461_IRQBASE); + + nimr = __raw_readw(HD64461_NIMR); + nimr |= mask; + __raw_writew(nimr, HD64461_NIMR); +} + +static void hd64461_unmask_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + unsigned short nimr; + unsigned short mask = 1 << (irq - HD64461_IRQBASE); + + nimr = __raw_readw(HD64461_NIMR); + nimr &= ~mask; + __raw_writew(nimr, HD64461_NIMR); +} + +static void hd64461_mask_and_ack_irq(struct irq_data *data) +{ + hd64461_mask_irq(data); + +#ifdef CONFIG_HD64461_ENABLER + if (data->irq == HD64461_IRQBASE + 13) + __raw_writeb(0x00, HD64461_PCC1CSCR); +#endif +} + +static struct irq_chip hd64461_irq_chip = { + .name = "HD64461-IRQ", + .irq_mask = hd64461_mask_irq, + .irq_mask_ack = hd64461_mask_and_ack_irq, + .irq_unmask = hd64461_unmask_irq, +}; + +static void hd64461_irq_demux(struct irq_desc *desc) +{ + unsigned short intv = __raw_readw(HD64461_NIRR); + unsigned int ext_irq = HD64461_IRQBASE; + + intv &= (1 << HD64461_IRQ_NUM) - 1; + + for (; intv; intv >>= 1, ext_irq++) { + if (!(intv & 1)) + continue; + + generic_handle_irq(ext_irq); + } +} + +static int __init setup_hd64461(void) +{ + int irq_base, i; + + printk(KERN_INFO + "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n", + HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE, + HD64461_IRQBASE + 15); + +/* Should be at processor specific part.. */ +#if defined(CONFIG_CPU_SUBTYPE_SH7709) + __raw_writew(0x2240, INTC_ICR1); +#endif + __raw_writew(0xffff, HD64461_NIMR); + + irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1); + if (IS_ERR_VALUE(irq_base)) { + pr_err("%s: failed hooking irqs for HD64461\n", __func__); + return irq_base; + } + + for (i = 0; i < 16; i++) + irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip, + handle_level_irq); + + irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); + irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); + +#ifdef CONFIG_HD64461_ENABLER + printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); + __raw_writeb(0x4c, HD64461_PCC1CSCIER); + __raw_writeb(0x00, HD64461_PCC1CSCR); +#endif + + return 0; +} + +module_init(setup_hd64461); -- cgit v1.3.1