From 2bd30b8dc75b823dd7bbef9d7bc68e1fd7ecee5c Mon Sep 17 00:00:00 2001 From: Sang-Heon Jeon Date: Mon, 24 Aug 2026 01:18:14 +0900 Subject: coccinelle: alloc_cast: drop removed allocators - pci_alloc_consistent() and pci_zalloc_consistent() were removed by commit 7968778914e5 ("PCI: Remove the deprecated "pci-dma-compat.h" API") - kmem_alloc() was removed by commit f078d4ea8276 ("xfs: convert kmem_alloc() to kmalloc()") - kmem_zalloc() was removed by commit 10634530f7ba ("xfs: convert kmem_zalloc() to kzalloc()") - kmem_zone_alloc() and kmem_zone_zalloc() were removed by commit bae633a4a283 ("xfs: remove xfs_zone_{alloc,zalloc} helpers") So drop them from the rules. No functional change. Signed-off-by: Sang-Heon Jeon Signed-off-by: Julia Lawall --- arch/mips/ralink/clk.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/mips/ralink/clk.c (limited to 'arch/mips/ralink/clk.c') diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c new file mode 100644 index 000000000..5c1eb46ef --- /dev/null +++ b/arch/mips/ralink/clk.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * + * Copyright (C) 2011 Gabor Juhos + * Copyright (C) 2013 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" + +static const char *clk_cpu(int *idx) +{ + switch (ralink_soc) { + case RT2880_SOC: + *idx = 1; + return "ralink,rt2880-sysc"; + case RT3883_SOC: + *idx = 1; + return "ralink,rt3883-sysc"; + case RT305X_SOC_RT3050: + *idx = 1; + return "ralink,rt3050-sysc"; + case RT305X_SOC_RT3052: + *idx = 1; + return "ralink,rt3052-sysc"; + case RT305X_SOC_RT3350: + *idx = 1; + return "ralink,rt3350-sysc"; + case RT305X_SOC_RT3352: + *idx = 1; + return "ralink,rt3352-sysc"; + case RT305X_SOC_RT5350: + *idx = 1; + return "ralink,rt5350-sysc"; + case MT762X_SOC_MT7620A: + *idx = 2; + return "ralink,mt7620-sysc"; + case MT762X_SOC_MT7620N: + *idx = 2; + return "ralink,mt7620-sysc"; + case MT762X_SOC_MT7628AN: + *idx = 1; + return "ralink,mt7628-sysc"; + case MT762X_SOC_MT7688: + *idx = 1; + return "ralink,mt7688-sysc"; + default: + *idx = -1; + return "invalid"; + } +} + +void __init plat_time_init(void) +{ + struct of_phandle_args clkspec; + const char *compatible; + struct clk *clk; + int cpu_clk_idx; + + ralink_of_remap(); + + compatible = clk_cpu(&cpu_clk_idx); + if (cpu_clk_idx == -1) + panic("unable to get CPU clock index"); + + of_clk_init(NULL); + clkspec.np = of_find_compatible_node(NULL, NULL, compatible); + clkspec.args_count = 1; + clkspec.args[0] = cpu_clk_idx; + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); + mips_hpt_frequency = clk_get_rate(clk) / 2; + clk_put(clk); + timer_probe(); +} -- cgit v1.3.1