From 6668ed271eaefaa63e686bdfbedaeb7b8e492722 Mon Sep 17 00:00:00 2001 From: Kumar Kartikeya Dwivedi Date: Fri, 4 Sep 2026 10:43:19 +0200 Subject: selftests/bpf: Reject graph kptr use after RCU unlock Add a sleepable verifier test that loads a graph-node local kptr in an explicit RCU read-side critical section, then passes its node to bpf_rbtree_remove() after the section ends. Before the verifier fix, the stale NON_OWN_REF flag makes the node look like a live borrowed reference and the program is accepted. After the fix, the pointer is demoted without NON_OWN_REF and the graph kfunc argument is rejected. Also exercise a graph kptr loaded while a spin lock provides implicit RCU protection. The pointer must be invalidated when the lock is released, which guards the required ordering between non-owning-reference invalidation and RCU demotion. Update the existing fault-protected load test state description. The post-unlock pointer no longer carries NON_OWN_REF, but remains readable because the load is rewritten to use BPF_PROBE_MEM. Signed-off-by: Kumar Kartikeya Dwivedi Link: https://lore.kernel.org/r/20260904084325.52250-7-memxor@gmail.com Signed-off-by: Alexei Starovoitov --- arch/mips/ralink/Kconfig | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 arch/mips/ralink/Kconfig (limited to 'arch/mips/ralink/Kconfig') diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig new file mode 100644 index 000000000..910d059ec --- /dev/null +++ b/arch/mips/ralink/Kconfig @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +if RALINK + +config RALINK_ILL_ACC + bool + depends on SOC_RT305X + default y + +config IRQ_INTC + bool + default y + depends on !SOC_MT7621 + +choice + prompt "Ralink SoC selection" + default SOC_RT305X + help + Select Ralink MIPS SoC type. + + config SOC_RT288X + bool "RT288x" + select MIPS_AUTO_PFN_OFFSET + select MIPS_L1_CACHE_SHIFT_4 + select HAVE_PCI + select SOC_BUS + + config SOC_RT305X + bool "RT305x" + select SOC_BUS + + config SOC_RT3883 + bool "RT3883" + select HAVE_PCI + select SOC_BUS + + config SOC_MT7620 + bool "MT7620/8" + select CPU_MIPSR2_IRQ_VI + select HAVE_PCI + select SOC_BUS + + config SOC_MT7621 + bool "MT7621" + select MIPS_CPU_SCACHE + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_MIPS_CPS + select SYS_SUPPORTS_HIGHMEM + select MIPS_GIC + select CLKSRC_MIPS_GIC + select HAVE_PCI + select PCI_DRIVERS_GENERIC + select SOC_BUS + select PINCTRL + + help + The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc + dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII. +endchoice + +choice + prompt "Devicetree selection" + depends on !SOC_MT7621 + default DTB_RT_NONE + help + Select the devicetree. + + config DTB_RT_NONE + bool "None" + + config DTB_RT2880_EVAL + bool "RT2880 eval kit" + depends on SOC_RT288X + select BUILTIN_DTB + + config DTB_RT305X_EVAL + bool "RT305x eval kit" + depends on SOC_RT305X + select BUILTIN_DTB + + config DTB_RT3883_EVAL + bool "RT3883 eval kit" + depends on SOC_RT3883 + select BUILTIN_DTB + + config DTB_MT7620A_EVAL + bool "MT7620A eval kit" + depends on SOC_MT7620 + select BUILTIN_DTB + + config DTB_OMEGA2P + bool "Onion Omega2+" + depends on SOC_MT7620 + select BUILTIN_DTB + + config DTB_VOCORE2 + bool "VoCore2" + depends on SOC_MT7620 + select BUILTIN_DTB + +endchoice + +endif -- cgit v1.3.1