From 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d Mon Sep 17 00:00:00 2001
From: Kees Cook <kees+treewide@kernel.org>
Date: Wed, 2 Sep 2026 15:31:14 -0700
Subject: treewide: refresh kmalloc_obj() conversions

This is another run of the Coccinelle script for converting kmalloc()
family of allocations to kmalloc_obj() via the existing rules in
scripts/coccinelle/api/kmalloc_objs.cocci

This catches both the set of kmalloc() uses added since the first
kmalloc_obj() conversions in v7.0 and adds a large group missed in the
first pass due to Coccinelle not interacting well with the cleanup.h
scoped_...() family of macros[1]. I worked around this with spatch's
"--macro-file" argument to a file with all the scoped_...() macros mapped
to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control
flow indicator I could find.

Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc,
riscv, and s390 with no new warnings.

Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1]
Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2]
Signed-off-by: Kees Cook <kees+treewide@kernel.org>
---
 arch/mips/ralink/Kconfig | 103 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 arch/mips/ralink/Kconfig

(limited to 'arch/mips/ralink/Kconfig')

diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
new file mode 100644
index 000000000..910d059ec
--- /dev/null
+++ b/arch/mips/ralink/Kconfig
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+if RALINK
+
+config RALINK_ILL_ACC
+	bool
+	depends on SOC_RT305X
+	default y
+
+config IRQ_INTC
+	bool
+	default y
+	depends on !SOC_MT7621
+
+choice
+	prompt "Ralink SoC selection"
+	default SOC_RT305X
+	help
+	  Select Ralink MIPS SoC type.
+
+	config SOC_RT288X
+		bool "RT288x"
+		select MIPS_AUTO_PFN_OFFSET
+		select MIPS_L1_CACHE_SHIFT_4
+		select HAVE_PCI
+		select SOC_BUS
+
+	config SOC_RT305X
+		bool "RT305x"
+		select SOC_BUS
+
+	config SOC_RT3883
+		bool "RT3883"
+		select HAVE_PCI
+		select SOC_BUS
+
+	config SOC_MT7620
+		bool "MT7620/8"
+		select CPU_MIPSR2_IRQ_VI
+		select HAVE_PCI
+		select SOC_BUS
+
+	config SOC_MT7621
+		bool "MT7621"
+		select MIPS_CPU_SCACHE
+		select SYS_SUPPORTS_MULTITHREADING
+		select SYS_SUPPORTS_SMP
+		select SYS_SUPPORTS_MIPS_CPS
+		select SYS_SUPPORTS_HIGHMEM
+		select MIPS_GIC
+		select CLKSRC_MIPS_GIC
+		select HAVE_PCI
+		select PCI_DRIVERS_GENERIC
+		select SOC_BUS
+		select PINCTRL
+
+		help
+		  The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc
+		  dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII.
+endchoice
+
+choice
+	prompt "Devicetree selection"
+	depends on !SOC_MT7621
+	default DTB_RT_NONE
+	help
+	  Select the devicetree.
+
+	config DTB_RT_NONE
+		bool "None"
+
+	config DTB_RT2880_EVAL
+		bool "RT2880 eval kit"
+		depends on SOC_RT288X
+		select BUILTIN_DTB
+
+	config DTB_RT305X_EVAL
+		bool "RT305x eval kit"
+		depends on SOC_RT305X
+		select BUILTIN_DTB
+
+	config DTB_RT3883_EVAL
+		bool "RT3883 eval kit"
+		depends on SOC_RT3883
+		select BUILTIN_DTB
+
+	config DTB_MT7620A_EVAL
+		bool "MT7620A eval kit"
+		depends on SOC_MT7620
+		select BUILTIN_DTB
+
+	config DTB_OMEGA2P
+		bool "Onion Omega2+"
+		depends on SOC_MT7620
+		select BUILTIN_DTB
+
+	config DTB_VOCORE2
+		bool "VoCore2"
+		depends on SOC_MT7620
+		select BUILTIN_DTB
+
+endchoice
+
+endif
-- 
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