From 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 2 Sep 2026 15:31:14 -0700 Subject: treewide: refresh kmalloc_obj() conversions This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook --- arch/mips/dec/ioasic-irq.c | 109 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 arch/mips/dec/ioasic-irq.c (limited to 'arch/mips/dec/ioasic-irq.c') diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c new file mode 100644 index 000000000..c690ef333 --- /dev/null +++ b/arch/mips/dec/ioasic-irq.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DEC I/O ASIC interrupts. + * + * Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki + */ + +#include +#include +#include + +#include +#include +#include + +static int ioasic_irq_base; + +static void unmask_ioasic_irq(struct irq_data *d) +{ + u32 simr; + + simr = ioasic_read(IO_REG_SIMR); + simr |= (1 << (d->irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIMR, simr); +} + +static void mask_ioasic_irq(struct irq_data *d) +{ + u32 simr; + + simr = ioasic_read(IO_REG_SIMR); + simr &= ~(1 << (d->irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIMR, simr); +} + +static void ack_ioasic_irq(struct irq_data *d) +{ + mask_ioasic_irq(d); + fast_iob(); +} + +static struct irq_chip ioasic_irq_type = { + .name = "IO-ASIC", + .irq_ack = ack_ioasic_irq, + .irq_mask = mask_ioasic_irq, + .irq_mask_ack = ack_ioasic_irq, + .irq_unmask = unmask_ioasic_irq, +}; + +static void clear_ioasic_dma_irq(struct irq_data *d) +{ + u32 sir; + + sir = ~(1 << (d->irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIR, sir); + fast_iob(); +} + +static struct irq_chip ioasic_dma_irq_type = { + .name = "IO-ASIC-DMA", + .irq_ack = clear_ioasic_dma_irq, + .irq_mask = mask_ioasic_irq, + .irq_unmask = unmask_ioasic_irq, + .irq_eoi = clear_ioasic_dma_irq, +}; + +/* + * I/O ASIC implements two kinds of DMA interrupts, informational and + * error interrupts. + * + * The former do not stop DMA and should be cleared as soon as possible + * so that if they retrigger before the handler has completed, usually as + * a side effect of actions taken by the handler, then they are reissued. + * These use the `handle_edge_irq' handler that clears the request right + * away. + * + * The latter stop DMA and do not resume it until the interrupt has been + * cleared. This cannot be done until after a corrective action has been + * taken and this also means they will not retrigger. Therefore they use + * the `handle_fasteoi_irq' handler that only clears the request on the + * way out. + * + * This mask has `1' bits in the positions of informational interrupts. + */ +#define IO_IRQ_DMA_INFO \ + (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \ + IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \ + IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \ + IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \ + IO_IRQ_MASK(IO_INR_ASC_DMA)) + +void __init init_ioasic_irqs(int base) +{ + int i; + + /* Mask interrupts. */ + ioasic_write(IO_REG_SIMR, 0); + fast_iob(); + + for (i = base; i < base + IO_INR_DMA; i++) + irq_set_chip_and_handler(i, &ioasic_irq_type, + handle_level_irq); + for (; i < base + IO_IRQ_LINES; i++) + irq_set_chip_and_handler(i, &ioasic_dma_irq_type, + 1 << (i - base) & IO_IRQ_DMA_INFO ? + handle_edge_irq : handle_fasteoi_irq); + + ioasic_irq_base = base; +} -- cgit v1.3.1