From 0d6526f82c3cdefcca47f73f5fc08dc6f335eac6 Mon Sep 17 00:00:00 2001 From: Tim Chen Date: Mon, 21 Sep 2026 17:37:22 -0700 Subject: sched/cache: Keep nr_pref_llc_running in the runnable domain, to fix LLC mis-scheduling bug alb_break_llc() decides whether to break LLC preference during active load balance. It does so by testing that every runnable fair task on the source rq prefers its LLC: env->src_rq->nr_pref_llc_running == env->src_rq->cfs.h_nr_runnable But the two counters cover different sets. nr_pref_llc_running is updated in account_llc_enqueue()/account_llc_dequeue(), next to cfs_rq->nr_queued, so it follows queued tasks. h_nr_runnable is updated in set_delayed()/ clear_delayed() and drops delay-dequeued tasks. So under DELAY_DEQUEUE, a preferring task that goes to sleep stays counted in nr_pref_llc_running while h_nr_runnable falls. The equality then breaks, alb_break_llc() returns false, and active balance is free to pull a task off its preferred LLC. Active balance only moves runnable tasks, and this is the only LLC check it consults: once the stopper runs, LBF_ACTIVE_LB skips the per-task test in can_migrate_task(). The runnable set is the one we want. Fix it on the counter side. A task should be counted in nr_pref_llc_running exactly while it is both queued on its preferred LLC (pref_llc_queued) and runnable (!sched_delayed). Define that membership once in task_pref_llc_runnable(), and adjust the counter only through pref_llc_running_inc()/pref_llc_running_dec() from the four sites that change either input: account_llc_enqueue(), account_llc_dequeue(), set_delayed() and clear_delayed(). Gating every update on the same predicate keeps the delay, wake and dequeue paths from double-counting or underflowing; see the comments at those sites for the ordering. nr_llc_running and sd->llc_counts are not touched and stay on queued semantics. Fixes: 714059f79ff0 ("sched/cache: Handle moving single tasks to/from their preferred LLC") Closes: https://lore.kernel.org/lkml/20260827135000.735138-1-zhanxusheng@xiaomi.com/ Reported-by: Zhan Xusheng Suggested-by: Chen Yu Signed-off-by: Tim Chen Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Reviewed-by: Kayra Cizmeci Cc: # v7.2.x Link: https://patch.msgid.link/06af61afedac32e6477f57feb4d658f6c411c3af.1790035273.git.tim.c.chen@linux.intel.com --- arch/mips/cobalt/setup.c | 116 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 arch/mips/cobalt/setup.c (limited to 'arch/mips/cobalt/setup.c') diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c new file mode 100644 index 000000000..9a266bf78 --- /dev/null +++ b/arch/mips/cobalt/setup.c @@ -0,0 +1,116 @@ +/* + * Setup pointers to hardware dependent routines. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +const char *get_system_type(void) +{ + switch (cobalt_board_id) { + case COBALT_BRD_ID_QUBE1: + return "Cobalt Qube"; + case COBALT_BRD_ID_RAQ1: + return "Cobalt RaQ"; + case COBALT_BRD_ID_QUBE2: + return "Cobalt Qube2"; + case COBALT_BRD_ID_RAQ2: + return "Cobalt RaQ2"; + } + return "MIPS Cobalt"; +} + +/* + * Cobalt doesn't have PS/2 keyboard/mouse interfaces, + * keyboard controller is never used. + * Also PCI-ISA bridge DMA controller is never used. + */ +static struct resource cobalt_reserved_resources[] = { + { /* dma1 */ + .start = 0x00, + .end = 0x1f, + .name = "reserved", + .flags = IORESOURCE_BUSY | IORESOURCE_IO, + }, + { /* keyboard */ + .start = 0x60, + .end = 0x6f, + .name = "reserved", + .flags = IORESOURCE_BUSY | IORESOURCE_IO, + }, + { /* dma page reg */ + .start = 0x80, + .end = 0x8f, + .name = "reserved", + .flags = IORESOURCE_BUSY | IORESOURCE_IO, + }, + { /* dma2 */ + .start = 0xc0, + .end = 0xdf, + .name = "reserved", + .flags = IORESOURCE_BUSY | IORESOURCE_IO, + }, +}; + +void __init plat_mem_setup(void) +{ + int i; + + _machine_restart = cobalt_machine_restart; + _machine_halt = cobalt_machine_halt; + pm_power_off = cobalt_machine_halt; + + set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); + + /* I/O port resource */ + ioport_resource.end = 0x01ffffff; + + /* These resources have been reserved by VIA SuperI/O chip. */ + for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) + request_resource(&ioport_resource, cobalt_reserved_resources + i); +} + +/* + * Prom init. We read our one and only communication with the firmware. + * Grab the amount of installed memory. + * Better boot loaders (CoLo) pass a command line too :-) + */ + +void __init prom_init(void) +{ + unsigned long memsz; + int argc, i; + char **argv; + + memsz = fw_arg0 & 0x7fff0000; + argc = fw_arg0 & 0x0000ffff; + argv = (char **)fw_arg1; + + for (i = 1; i < argc; i++) { + strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE); + if (i < (argc - 1)) + strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); + } + + memblock_add(0, memsz); + + setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); +} -- cgit v1.3.1