From 0102c8c7fdfc4bd700971daff2b94470f4eafae4 Mon Sep 17 00:00:00 2001 From: Dapeng Mi Date: Thu, 17 Sep 2026 09:52:33 +0800 Subject: perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp DMR introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data. Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user & tooling confusion. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Link: https://patch.msgid.link/20260917015234.981153-12-dapeng1.mi@linux.intel.com --- arch/arm64/mm/pgd.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 arch/arm64/mm/pgd.c (limited to 'arch/arm64/mm/pgd.c') diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c new file mode 100644 index 000000000..bf5110b91 --- /dev/null +++ b/arch/arm64/mm/pgd.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PGD allocation/freeing + * + * Copyright (C) 2012 ARM Ltd. + * Author: Catalin Marinas + */ + +#include +#include +#include +#include + +#include +#include +#include + +static struct kmem_cache *pgd_cache __ro_after_init; + +static bool pgdir_is_page_size(void) +{ + if (PGD_SIZE == PAGE_SIZE) + return true; + if (CONFIG_PGTABLE_LEVELS == 4) + return !pgtable_l4_enabled(); + if (CONFIG_PGTABLE_LEVELS == 5) + return !pgtable_l5_enabled(); + return false; +} + +pgd_t *pgd_alloc(struct mm_struct *mm) +{ + gfp_t gfp = GFP_PGTABLE_USER; + + if (pgdir_is_page_size()) + return __pgd_alloc(mm, 0); + else + return kmem_cache_alloc(pgd_cache, gfp); +} + +void pgd_free(struct mm_struct *mm, pgd_t *pgd) +{ + if (pgdir_is_page_size()) + __pgd_free(mm, pgd); + else + kmem_cache_free(pgd_cache, pgd); +} + +void __init pgtable_cache_init(void) +{ + if (pgdir_is_page_size()) + return; + +#ifdef CONFIG_ARM64_PA_BITS_52 + /* + * With 52-bit physical addresses, the architecture requires the + * top-level table to be aligned to at least 64 bytes. + */ + BUILD_BUG_ON(!IS_ALIGNED(PGD_SIZE, 64)); +#endif + + /* + * Naturally aligned pgds required by the architecture. + */ + pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE, + SLAB_PANIC, NULL); +} -- cgit v1.3.1