From 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 2 Sep 2026 15:31:14 -0700 Subject: treewide: refresh kmalloc_obj() conversions This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook --- arch/arm/mach-omap1/sram.S | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 arch/arm/mach-omap1/sram.S (limited to 'arch/arm/mach-omap1/sram.S') diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S new file mode 100644 index 000000000..89f4dc1b7 --- /dev/null +++ b/arch/arm/mach-omap1/sram.S @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/arch/arm/plat-omap/sram-fn.S + * + * Functions that need to be run in internal SRAM + */ + +#include +#include + +#include + +#include "hardware.h" +#include "iomap.h" + + .text + +/* + * Reprograms ULPD and CKCTL. + */ + .align 3 +ENTRY(omap1_sram_reprogram_clock) + stmfd sp!, {r0 - r12, lr} @ save registers on stack + + mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 + orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 + orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 + + mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 + orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 + orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 + + tst r0, #1 << 4 @ want lock mode? + beq newck @ nope + bic r0, r0, #1 << 4 @ else clear lock bit + strh r0, [r2] @ set dpll into bypass mode + orr r0, r0, #1 << 4 @ set lock bit again + +newck: + strh r1, [r3] @ write new ckctl value + strh r0, [r2] @ write new dpll value + + mov r4, #0x0700 @ let the clocks settle + orr r4, r4, #0x00ff +delay: sub r4, r4, #1 + cmp r4, #0 + bne delay + +lock: ldrh r4, [r2], #0 @ read back dpll value + tst r0, #1 << 4 @ want lock mode? + beq out @ nope + tst r4, #1 << 0 @ dpll rate locked? + beq lock @ try again + +out: + ldmfd sp!, {r0 - r12, pc} @ restore regs and return +ENTRY(omap1_sram_reprogram_clock_sz) + .word . - omap1_sram_reprogram_clock -- cgit v1.3.1