From 034dd340b08be1f2f0477ad16131d609f9dbd53c Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sun, 30 Aug 2026 09:22:00 -0700 Subject: Merge tag 'trace-v7.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace Pull tracing fixes from Steven Rostedt: - Fix error output of boot instance creation failure Currently if a boot instance creation fails, instead of printing out the name of the instance that failed, it prints "(null)". That is because it prints "cur_str" that had already been processed by strsep(). Print the saved name instead. While at it, print the error code of the failure. - Fix use-after-free for same named historgrams Histograms can be named so that they can be used in multiple events. But if the named histogram has a variable attached, the second event that uses the named histogram which duplicates it and needs to free the original after duplication leaves the old variable in place and still visible. If another histogram uses than variable, it will use the stale one which will try to reference the freed duplicate histogram and crash the kernel. Free the duplicate variables along with the duplicated histogram data. - Check return value of kthread_run() in event self test The events self tests uses a kthread for testing but does not check if it succeeded in creating a kthread. If the kthread creation were to fail, the code will still try to call kthread_stop() on the error returned. - Fix race between reading trace_pipe and updating subbuffer size If a user is reading the trace_pipe file at the same time they update the ring buffer sub-buffer size, can cause the trace_pipe read to read stale data. Add trace_access_lock() around updating the ring buffer sub-buffer size. - Fix eventfs_inode on failure path in creation of the events directory In the creation of the "events" directory, if after allocating the eventfs_inode a failure is detected, it calls cleanup_ei() which calls free_ei(). The free_ei() will test if eventfs_inode being freed has no children. It is a bug if it does. But on the failure case of the creation of the "events" directory, the children lists have not yet been initialized and the free will trigger a warning because list_empty() on an uninitialized list returns false. Move the initialization into init_ei() where it makes more sense and makes sure that a created eventfs_inode has its lists initialized upon creation. - Check return value of kthread_run() in ftrace direct sample code The sample code that shows how to use the ftrace direct calls does not test the return of kthread_run() to see if it succeeds. Return a failure if the kthread_run() doesn't succeed. - Clear user events state on fork in case of alloc failure On fork, the child gets a pointer to the parent's user events state. It makes a copy of it then updates the child's pointer to it. But if the allocation fails, the duplication function leaves the child with a pointer to its parent's descriptor. When the child cleans up its data, it will free the parent's descriptor while the parent is still using it. In the duplication function, set the child's user_event_mm to NULL before testing if the allocation succeeded, and when it exits it will not free the parent's descriptor. - Fix retry exhaustion in simple ring buffer reader swap simple_ring_buffer_swap_reader_page() starts with retry set to 8 and post-decrements it only after a failed link replacement. On the final attempt, a successful replacement leaves retry at zero, while a failed replacement leaves it at -1. But the check for success expects the retry value to be non-zero and exits with an error on zero. This is the opposite result. Fix it. - Fail nicely when the remote swap_reader_page() returns an error Currently, if the swap_reader_page() of a remote buffer fails, it triggers a WARN_ON_ONCE() and continues normally. Instead, have it exit with an error and a pr_warn() print instead of a full WARNING. * tag 'trace-v7.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace: ring-buffer: Stop remote reader update when page swap fails tracing: Fix retry exhaustion in simple ring buffer reader swap tracing/user_events: Clear copied tracing state before fork duplication samples/ftrace: Fix kthread_stop() on ERR_PTR in ftrace-direct-multi-modify samples/ftrace: Fix kthread_stop() on ERR_PTR in ftrace-direct-modify eventfs: Initialize ei->children and ei->list in init_ei() tracing: Fix use-after-free in trace_pipe read on sub-buffer order change tracing: Fix crash passing ERR_PTR to kthread_stop() tracing: Fix use-after-free with same-name named triggers tracing: Fix logged instance name on creation failure --- Documentation/devicetree/bindings/serial/8250.yaml | 360 +++++++++++++++++++++ .../devicetree/bindings/serial/8250_omap.yaml | 126 ++++++++ .../bindings/serial/actions,owl-uart.yaml | 48 +++ .../devicetree/bindings/serial/altr,juart-1.0.yaml | 19 ++ .../devicetree/bindings/serial/altr,uart-1.0.yaml | 25 ++ .../bindings/serial/amlogic,meson-uart.yaml | 106 ++++++ .../devicetree/bindings/serial/arm,dcc.yaml | 30 ++ .../devicetree/bindings/serial/arm,mps2-uart.yaml | 46 +++ .../devicetree/bindings/serial/arm,sbsa-uart.yaml | 38 +++ .../bindings/serial/atmel,at91-usart.yaml | 201 ++++++++++++ .../bindings/serial/brcm,bcm2835-aux-uart.yaml | 46 +++ .../bindings/serial/brcm,bcm6345-uart.yaml | 47 +++ .../bindings/serial/brcm,bcm7271-uart.yaml | 95 ++++++ .../devicetree/bindings/serial/cdns,uart.yaml | 82 +++++ .../bindings/serial/cirrus,ep7209-uart.yaml | 56 ++++ .../bindings/serial/cnxt,cx92755-usart.yaml | 48 +++ .../devicetree/bindings/serial/esp,esp32-acm.yaml | 42 +++ .../devicetree/bindings/serial/esp,esp32-uart.yaml | 51 +++ .../bindings/serial/fsl,s32-linflexuart.yaml | 50 +++ .../devicetree/bindings/serial/fsl-imx-uart.yaml | 153 +++++++++ .../devicetree/bindings/serial/fsl-lpuart.yaml | 98 ++++++ .../devicetree/bindings/serial/fsl-mxs-auart.yaml | 94 ++++++ .../bindings/serial/google,goldfish-tty.yaml | 41 +++ .../devicetree/bindings/serial/ingenic,uart.yaml | 103 ++++++ .../devicetree/bindings/serial/lantiq,asc.yaml | 56 ++++ .../devicetree/bindings/serial/litex,liteuart.yaml | 40 +++ .../bindings/serial/marvell,armada-3700-uart.yaml | 102 ++++++ .../devicetree/bindings/serial/maxim,max310x.yaml | 162 ++++++++++ .../devicetree/bindings/serial/mediatek,uart.yaml | 126 ++++++++ .../bindings/serial/microchip,pic32mzda-uart.yaml | 53 +++ .../bindings/serial/nuvoton,ma35d1-serial.yaml | 48 +++ .../bindings/serial/nvidia,tegra194-tcu.yaml | 61 ++++ .../bindings/serial/nvidia,tegra20-hsuart.yaml | 125 +++++++ .../bindings/serial/nvidia,tegra264-utc.yaml | 73 +++++ .../bindings/serial/nxp,lpc3220-hsuart.yaml | 39 +++ .../devicetree/bindings/serial/nxp,sc16is7xx.yaml | 133 ++++++++ .../devicetree/bindings/serial/pl011.yaml | 130 ++++++++ .../bindings/serial/qca,ar9330-uart.yaml | 50 +++ .../devicetree/bindings/serial/qcom,msm-uart.yaml | 56 ++++ .../bindings/serial/qcom,msm-uartdm.yaml | 125 +++++++ .../bindings/serial/qcom,sa8255p-geni-uart.yaml | 76 +++++ .../bindings/serial/qcom,serial-geni-qcom.yaml | 87 +++++ .../bindings/serial/rda,8810pl-uart.yaml | 46 +++ .../bindings/serial/renesas,em-uart.yaml | 74 +++++ .../devicetree/bindings/serial/renesas,hscif.yaml | 158 +++++++++ .../devicetree/bindings/serial/renesas,rsci.yaml | 192 +++++++++++ .../devicetree/bindings/serial/renesas,sci.yaml | 109 +++++++ .../devicetree/bindings/serial/renesas,scif.yaml | 281 ++++++++++++++++ .../devicetree/bindings/serial/renesas,scifa.yaml | 112 +++++++ .../devicetree/bindings/serial/renesas,scifb.yaml | 103 ++++++ .../devicetree/bindings/serial/rs485.yaml | 65 ++++ .../devicetree/bindings/serial/samsung_uart.yaml | 227 +++++++++++++ .../bindings/serial/serial-peripheral-props.yaml | 41 +++ .../devicetree/bindings/serial/serial.yaml | 136 ++++++++ .../devicetree/bindings/serial/sifive-serial.yaml | 65 ++++ .../devicetree/bindings/serial/snps,arc-uart.yaml | 51 +++ .../bindings/serial/snps-dw-apb-uart.yaml | 198 ++++++++++++ .../serial/socionext,milbeaut-usio-uart.yaml | 56 ++++ .../bindings/serial/socionext,uniphier-uart.yaml | 51 +++ .../devicetree/bindings/serial/sprd-uart.yaml | 82 +++++ .../devicetree/bindings/serial/st,asc.yaml | 55 ++++ .../devicetree/bindings/serial/st,stm32-uart.yaml | 133 ++++++++ .../bindings/serial/sunplus,sp7021-uart.yaml | 56 ++++ .../bindings/serial/via,vt8500-uart.yaml | 46 +++ .../bindings/serial/xlnx,opb-uartlite.yaml | 88 +++++ 65 files changed, 5972 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/8250.yaml create mode 100644 Documentation/devicetree/bindings/serial/8250_omap.yaml create mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml create mode 100644 Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/arm,dcc.yaml create mode 100644 Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml create mode 100644 Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/cdns,uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml create mode 100644 Documentation/devicetree/bindings/serial/esp,esp32-acm.yaml create mode 100644 Documentation/devicetree/bindings/serial/esp,esp32-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml create mode 100644 Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/fsl-lpuart.yaml create mode 100644 Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml create mode 100644 Documentation/devicetree/bindings/serial/google,goldfish-tty.yaml create mode 100644 Documentation/devicetree/bindings/serial/ingenic,uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/lantiq,asc.yaml create mode 100644 Documentation/devicetree/bindings/serial/litex,liteuart.yaml create mode 100644 Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/maxim,max310x.yaml create mode 100644 Documentation/devicetree/bindings/serial/mediatek,uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml create mode 100644 Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml create mode 100644 Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml create mode 100644 Documentation/devicetree/bindings/serial/pl011.yaml create mode 100644 Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml create mode 100644 Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml create mode 100644 Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,em-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,hscif.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,rsci.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,sci.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,scif.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,scifa.yaml create mode 100644 Documentation/devicetree/bindings/serial/renesas,scifb.yaml create mode 100644 Documentation/devicetree/bindings/serial/rs485.yaml create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/serial-peripheral-props.yaml create mode 100644 Documentation/devicetree/bindings/serial/serial.yaml create mode 100644 Documentation/devicetree/bindings/serial/sifive-serial.yaml create mode 100644 Documentation/devicetree/bindings/serial/snps,arc-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/sprd-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/st,asc.yaml create mode 100644 Documentation/devicetree/bindings/serial/st,stm32-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml create mode 100644 Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml new file mode 100644 index 000000000..8c2c177fa --- /dev/null +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -0,0 +1,360 @@ +# Copyright 2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UART (Universal Asynchronous Receiver/Transmitter) + +maintainers: + - devicetree@vger.kernel.org + +allOf: + - $ref: serial.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + - if: + anyOf: + - required: + - aspeed,lpc-io-reg + - required: + - aspeed,lpc-interrupts + - required: + - aspeed,sirq-polarity-sense + then: + properties: + compatible: + contains: + const: aspeed,ast2500-vuart + - if: + properties: + compatible: + const: mrvl,mmp-uart + then: + properties: + reg-shift: + const: 2 + required: + - reg-shift + - if: + not: + properties: + compatible: + items: + - enum: + - ns8250 + - ns16450 + - ns16550 + - ns16550a + then: + oneOf: + - required: [ clock-frequency ] + - required: [ clocks ] + - if: + properties: + compatible: + contains: + const: nxp,lpc1850-uart + then: + properties: + clock-names: + items: + - const: uartclk + - const: reg + - if: + properties: + compatible: + contains: + enum: + - spacemit,k1-uart + - spacemit,k3-uart + then: + properties: + clock-names: + items: + - const: core + - const: bus + - if: + properties: + compatible: + contains: + enum: + - spacemit,k1-uart + - spacemit,k3-uart + - nxp,lpc1850-uart + then: + required: + - clocks + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +properties: + compatible: + oneOf: + - const: ns8250 + - const: ns16450 + - const: ns16550 + - const: ns16550a + - const: ns16850 + - const: aspeed,ast2400-vuart + - const: aspeed,ast2500-vuart + - const: intel,xscale-uart + - const: mrvl,pxa-uart + - const: nuvoton,wpcm450-uart + - const: nuvoton,npcm750-uart + - const: nvidia,tegra20-uart + - const: nxp,lpc3220-uart + - items: + - enum: + - exar,xr16l2552 + - exar,xr16l2551 + - exar,xr16l2550 + - const: ns8250 + - items: + - enum: + - altr,16550-FIFO32 + - altr,16550-FIFO64 + - altr,16550-FIFO128 + - fsl,16550-FIFO64 + - andestech,uart16550 + - nxp,lpc1850-uart + - opencores,uart16550-rtlsvn105 + - ti,da830-uart + - loongson,ls2k0500-uart + - loongson,ls2k1500-uart + - const: ns16550a + - items: + - enum: + - ns16750 + - fsl,ns16550 + - cavium,octeon-3860-uart + - xlnx,xps-uart16550-2.00.b + - ralink,rt2880-uart + - enum: + - ns16550 # Deprecated, unless the FIFO really is broken + - ns16550a + - items: + - enum: + - nuvoton,npcm845-uart + - const: nuvoton,npcm750-uart + - items: + - enum: + - ralink,mt7620a-uart + - ralink,rt3052-uart + - ralink,rt3883-uart + - const: ralink,rt2880-uart + - enum: + - ns16550 # Deprecated, unless the FIFO really is broken + - ns16550a + - items: + - enum: + - mediatek,mt7622-btif + - mediatek,mt7623-btif + - const: mediatek,mtk-btif + - items: + - enum: + - mrvl,mmp-uart + - spacemit,k1-uart + - spacemit,k3-uart + - const: intel,xscale-uart + - items: + - enum: + - nvidia,tegra30-uart + - nvidia,tegra114-uart + - nvidia,tegra124-uart + - nvidia,tegra210-uart + - nvidia,tegra186-uart + - nvidia,tegra194-uart + - nvidia,tegra234-uart + - const: nvidia,tegra20-uart + - items: + - enum: + - loongson,ls2k1000-uart + - const: loongson,ls2k0500-uart + - const: ns16550a + - items: + - enum: + - loongson,ls3a4000-uart + - loongson,ls3a5000-uart + - loongson,ls3a6000-uart + - loongson,ls2k2000-uart + - const: loongson,ls2k1500-uart + - const: ns16550a + - items: + - enum: + - aspeed,ast2600-vuart + - aspeed,ast2700-vuart + - const: aspeed,ast2500-vuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: true + + clocks: + minItems: 1 + items: + - description: The core function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + maxItems: 2 + oneOf: + - enum: + - main + - uart + - items: + - const: core + - const: bus + - items: + - const: uartclk + - const: reg + + dmas: + minItems: 1 + maxItems: 4 + + dma-names: + minItems: 1 + maxItems: 4 + + resets: + maxItems: 1 + + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The current active speed of the UART. + + reg-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset to apply to the mapbase from the start of the registers. + + reg-shift: + description: Quantity to shift the register offsets by. + + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed on the + device. There are some systems that require 32-bit accesses to the + UART (e.g. TI davinci). + + used-by-rtas: + type: boolean + description: | + Set to indicate that the port is in use by the OpenFirmware RTAS and + should not be registered. + + no-loopback-test: + type: boolean + description: | + Set to indicate that the port does not implement loopback test mode. + + fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The fifo size of the UART. + + auto-flow-control: + type: boolean + description: | + One way to enable automatic flow control support. The driver is + allowed to detect support for the capability even without this + property. + + tx-threshold: + description: | + Specify the TX FIFO low water indication for parts with programmable + TX FIFO thresholds. + + overrun-throttle-ms: + description: | + How long to pause uart rx when input overrun is encountered. + + rts-gpios: true + cts-gpios: true + dtr-gpios: true + dsr-gpios: true + rng-gpios: true + dcd-gpios: true + + aspeed,sirq-polarity-sense: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Phandle to aspeed,ast2500-scu compatible syscon alongside register + offset and bit number to identify how the SIRQ polarity should be + configured. One possible data source is the LPC/eSPI mode bit. Only + applicable to aspeed,ast2500-vuart. + deprecated: true + + aspeed,lpc-io-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 + description: | + The VUART LPC address. Only applicable to aspeed,ast2500-vuart. + + aspeed,lpc-interrupts: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: | + A 2-cell property describing the VUART SIRQ number and SIRQ + polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only + applicable to aspeed,ast2500-vuart. + +required: + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@80230000 { + compatible = "ns8250"; + reg = <0x80230000 0x100>; + interrupts = <10>; + reg-shift = <2>; + clock-frequency = <48000000>; + }; + - | + #include + serial@49042000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x49042000 0x400>; + interrupts = <80>; + clock-frequency = <48000000>; + cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + - | + #include + #include + serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; + no-loopback-test; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml new file mode 100644 index 000000000..aabacca2b --- /dev/null +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/8250_omap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs + +maintainers: + - Vignesh Raghavendra + +allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +properties: + compatible: + oneOf: + - enum: + - ti,am3352-uart + - ti,am4372-uart + - ti,am654-uart + - ti,dra742-uart + - ti,omap2-uart + - ti,omap3-uart + - ti,omap4-uart + - items: + - enum: + - ti,am64-uart + - ti,j721e-uart + - const: ti,am654-uart + + ti,hwmods: + description: + Must be "uart", n being the instance number (1-based) + This property is applicable only on legacy platforms mainly omap2/3 + and ti81xx and should not be used on other platforms. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + description: + First entry is module IRQ required for normal IO operation. + Second entry is optional and corresponds to system wakeup IRQ + where supported. + + clocks: + maxItems: 1 + + clock-names: + const: fclk + + rs485-rts-active-high: true + power-domains: true + clock-frequency: true + current-speed: true + overrun-throttle-ms: true + wakeup-source: true + + pinctrl-0: + description: Default pinctrl state + + pinctrl-1: + description: Wakeup pinctrl state + + pinctrl-names: + description: + When present should contain at least "default" describing the default pin + states. The second state called "wakeup" describes the pins in their + wakeup configuration required to exit sleep states. + minItems: 1 + items: + - const: default + - const: wakeup + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +if: + properties: + compatible: + contains: + enum: + - ti,omap2-uart + - ti,omap3-uart + - ti,omap4-uart + +then: + properties: + ti,hwmods: + items: + - pattern: "^uart([1-9])$" + +else: + properties: + ti,hwmods: false + +examples: + - | + serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml b/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml new file mode 100644 index 000000000..ab1c4514a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/actions,owl-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi Owl UART + +maintainers: + - Kanak Shilledar + +allOf: + - $ref: serial.yaml + +properties: + compatible: + items: + - enum: + - actions,s500-uart + - actions,s900-uart + - const: actions,owl-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + uart0: serial@b0126000 { + compatible = "actions,s500-uart", "actions,owl-uart"; + reg = <0xb0126000 0x1000>; + clocks = <&cmu CLK_UART0>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml b/Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml new file mode 100644 index 000000000..02e20fa59 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/altr,juart-1.0.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/altr,juart-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera JTAG UART + +maintainers: + - Dinh Nguyen + +properties: + compatible: + const: altr,juart-1.0 + +required: + - compatible + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml b/Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml new file mode 100644 index 000000000..72d4972e1 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/altr,uart-1.0.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/altr,uart-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera UART + +maintainers: + - Dinh Nguyen + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: altr,uart-1.0 + + clock-frequency: + description: Frequency of the clock input to the UART. + +required: + - compatible + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml new file mode 100644 index 000000000..a27023196 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson SoC UART Serial Interface + +maintainers: + - Neil Armstrong + +description: | + The Amlogic Meson SoC UART Serial Interface is present on a large range + of SoCs, and can be present either in the "Always-On" power domain or the + "Everything-Else" power domain. + + The particularity of the "Always-On" Serial Interface is that the hardware + is active since power-on and does not need any clock gating and is usable + as very early serial console. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - description: Always-on power domain UART controller + items: + - enum: + - amlogic,meson6-uart + - amlogic,meson8-uart + - amlogic,meson8b-uart + - amlogic,meson-gx-uart + - amlogic,meson-s4-uart + - amlogic,meson-a1-uart + - const: amlogic,meson-ao-uart + - description: Always-on power domain UART controller on G12A SoCs + items: + - const: amlogic,meson-g12a-uart + - const: amlogic,meson-gx-uart + - const: amlogic,meson-ao-uart + - description: Everything-Else power domain UART controller + enum: + - amlogic,meson6-uart + - amlogic,meson8-uart + - amlogic,meson8b-uart + - amlogic,meson-gx-uart + - amlogic,meson-s4-uart + - amlogic,meson-a1-uart + - description: Everything-Else power domain UART controller on G12A SoCs + items: + - const: amlogic,meson-g12a-uart + - const: amlogic,meson-gx-uart + - description: UART controller on S4 compatible SoCs + items: + - enum: + - amlogic,a4-uart + - amlogic,a9-uart + - amlogic,s6-uart + - amlogic,s7-uart + - amlogic,s7d-uart + - amlogic,t7-uart + - const: amlogic,meson-s4-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: external xtal clock identifier + - description: the bus core clock, either the clk81 clock or the gate clock + - description: the source of the baudrate generator, can be either the xtal or the pclk + + clock-names: + items: + - const: xtal + - const: pclk + - const: baud + + fifo-size: + description: The fifo size supported by the UART channel. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [64, 128] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + serial@84c0 { + compatible = "amlogic,meson-gx-uart"; + reg = <0x84c0 0x14>; + interrupts = <26>; + clocks = <&xtal>, <&pclk>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; diff --git a/Documentation/devicetree/bindings/serial/arm,dcc.yaml b/Documentation/devicetree/bindings/serial/arm,dcc.yaml new file mode 100644 index 000000000..fd0589356 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/arm,dcc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/arm,dcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM DCC (Data communication channel) serial emulation + +maintainers: + - Michal Simek + +description: | + ARM DCC (Data communication channel) serial emulation interface available + via JTAG can be also used as one of serial line tightly coupled with every + ARM CPU available in the system. + +properties: + compatible: + const: arm,dcc + +required: + - compatible + +additionalProperties: false + +examples: + - | + serial { + compatible = "arm,dcc"; + }; diff --git a/Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml b/Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml new file mode 100644 index 000000000..4a8df078e --- /dev/null +++ b/Documentation/devicetree/bindings/serial/arm,mps2-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/arm,mps2-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm MPS2 UART + +maintainers: + - Vladimir Murzin + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: arm,mps2-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: RX interrupt + - description: TX interrupt + - description: Overrun interrupt + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + serial@40004000 { + compatible = "arm,mps2-uart"; + reg = <0x40004000 0x1000>; + interrupts = <0>, <1>, <12>; + clocks = <&sysclk>; + }; diff --git a/Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml b/Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml new file mode 100644 index 000000000..68e3fd64b --- /dev/null +++ b/Documentation/devicetree/bindings/serial/arm,sbsa-uart.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/serial/arm,sbsa-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM SBSA UART + +maintainers: + - Andre Przywara + +description: + This UART uses a subset of the PL011 registers and consequently lives in the + PL011 driver. It's baudrate and other communication parameters cannot be + adjusted at runtime, so it lacks a clock specifier here. + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: arm,sbsa-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + current-speed: + description: fixed baud rate set by the firmware + +required: + - compatible + - reg + - interrupts + - current-speed + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml new file mode 100644 index 000000000..375cd50bc --- /dev/null +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +maintainers: + - Richard Genoud + +properties: + compatible: + oneOf: + - enum: + - atmel,at91rm9200-usart + - atmel,at91sam9260-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - enum: + - microchip,lan9691-usart + - microchip,sam9x60-usart + - microchip,sam9x7-usart + - microchip,sama7d65-usart + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x7-dbgu + - const: atmel,at91sam9260-dbgu + - const: microchip,sam9x7-usart + - const: atmel,at91sam9260-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + minItems: 1 + items: + - const: usart + - const: gclk + + clocks: + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must be either for SPI or + for USART (found in dt-bindings/mfd/at91-usart.h). + enum: [ 0, 1 ] + + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - atmel,usart-mode + +allOf: + - if: + properties: + atmel,usart-mode: + const: 1 + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,use-dma-rx: false + + atmel,use-dma-tx: false + + atmel,fifo-size: false + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - "#size-cells" + - "#address-cells" + + else: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + /* use PDC */ + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + atmel,usart-mode = ; + interrupts = <7>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include + #include + #include + #include + + /* use DMA */ + usart1: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + }; + + - | + #include + #include + #include + #include + + /* SPI mode */ + spi0: spi@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.yaml b/Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.yaml new file mode 100644 index 000000000..6b72459f7 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/brcm,bcm2835-aux-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/brcm,bcm2835-aux-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835 AUXILIARY UART + +maintainers: + - Pratik Farkase + - Florian Fainelli + - Stefan Wahren + +allOf: + - $ref: serial.yaml + +properties: + compatible: + const: brcm,bcm2835-aux-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + serial@7e215040 { + compatible = "brcm,bcm2835-aux-uart"; + reg = <0x7e215040 0x40>; + interrupts = <1 29>; + clocks = <&aux BCM2835_AUX_CLOCK_UART>; + }; diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.yaml b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.yaml new file mode 100644 index 000000000..a22285c43 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/brcm,bcm6345-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM63xx UART + +maintainers: + - Rafał Miłecki + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: brcm,bcm6345-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: refclk + +unevaluatedProperties: false + +required: + - reg + - interrupts + - clocks + +examples: + - | + serial@14e00520 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00520 0x18>; + interrupt-parent = <&periph_intc>; + interrupts = <2>; + clocks = <&periph_clk>; + clock-names = "refclk"; + }; diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml new file mode 100644 index 000000000..8cc848ae1 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom 8250 based serial port + +maintainers: + - Al Cooper + +allOf: + - $ref: serial.yaml# + +description: |+ + The Broadcom UART is based on the basic 8250 UART but with + enhancements for more accurate high speed baud rates and support + for DMA. + +properties: + compatible: + items: + - enum: + - brcm,bcm7271-uart + - brcm,bcm7278-uart + + reg: + minItems: 1 + maxItems: 5 + + reg-names: + description: The UART register block and optionally the DMA register blocks. + oneOf: + - items: + - const: uart + - items: + - const: uart + - const: dma_arb + - const: dma_rx + - const: dma_tx + - const: dma_intr2 + + clocks: + maxItems: 1 + + clock-names: + const: sw_baud + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + description: The UART interrupt and optionally the DMA interrupt. + minItems: 1 + items: + - const: uart + - const: dma + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + serial@840d000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x840d000 0x20>; + reg-names = "uart"; + interrupts = <0x0 0x62 0x4>; + interrupt-names = "uart"; + clocks = <&scmi_clk 190>; + clock-names = "sw_baud"; + }; + + serial@840e000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x840e000 0x20>, + <0x840e080 0x8>, + <0x840e100 0xa8>, + <0x840e200 0x4c>, + <0x840e300 0x30>; + reg-names = "uart", "dma_arb", "dma_rx", "dma_tx", "dma_intr2"; + interrupts = <0x0 0x62 0x4>, <0x0 0x75 0x4>; + interrupt-names = "uart", "dma"; + clocks = <&scmi_clk 190>; + clock-names = "sw_baud"; + }; diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml new file mode 100644 index 000000000..9d3e5c1d8 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/cdns,uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence UART Controller + +maintainers: + - Michal Simek + +properties: + compatible: + oneOf: + - description: UART controller for Zynq-7xxx SoC + items: + - const: xlnx,xuartps + - const: cdns,uart-r1p8 + - items: + - enum: + - axiado,ax3000-uart + - xlnx,zynqmp-uart + - const: cdns,uart-r1p12 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: uart_clk + - const: pclk + + cts-override: + description: | + Override the CTS modem status signal. This signal will + always be reported as active instead of being obtained + from the modem status register. Define this if your serial + port does not use this pin. + type: boolean + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: serial.yaml# + - $ref: rs485.yaml# + - if: + properties: + compatible: + contains: + const: cdns,uart-r1p8 + then: + properties: + power-domains: false + +unevaluatedProperties: false + +examples: + - | + uart0: serial@e0000000 { + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "uart_clk", "pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0 27 4>; + }; diff --git a/Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml b/Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml new file mode 100644 index 000000000..c9976e868 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cirrus,ep7209-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/cirrus,ep7209-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Alexander Shiyan + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: cirrus,ep7209-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: UART TX interrupt + - description: UART RX interrupt + + clocks: + maxItems: 1 + + syscon: + description: Phandle to SYSCON node, which contains UART control bits. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - syscon + +unevaluatedProperties: false + +examples: + - | + #include + + serial@80000480 { + compatible = "cirrus,ep7209-uart"; + reg = <0x80000480 0x80>; + interrupts = <12>, <13>; + clocks = <&clks 11>; + syscon = <&syscon1>; + cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; + dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; + dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml b/Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml new file mode 100644 index 000000000..720229455 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cnxt,cx92755-usart.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/cnxt,cx92755-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Conexant Digicolor USART + +maintainers: + - Baruch Siach + +description: > + Note: this binding is only applicable for using the USART peripheral as UART. + USART also support synchronous serial protocols like SPI and I2S. + Use the binding that matches the wiring of your system. + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: cnxt,cx92755-usart + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@f0000740 { + compatible = "cnxt,cx92755-usart"; + reg = <0xf0000740 0x20>; + clocks = <&main_clk>; + interrupts = <44>; + }; diff --git a/Documentation/devicetree/bindings/serial/esp,esp32-acm.yaml b/Documentation/devicetree/bindings/serial/esp,esp32-acm.yaml new file mode 100644 index 000000000..77fbb2c72 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/esp,esp32-acm.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/esp,esp32-acm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESP32S3 ACM gadget controller + +maintainers: + - Max Filippov + +description: + Fixed function USB CDC-ACM gadget controller of the Espressif ESP32S3 SoC. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: esp,esp32s3-acm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + serial@60038000 { + compatible = "esp,esp32s3-acm"; + reg = <0x60038000 0x1000>; + interrupts = <96 3 0>; + }; diff --git a/Documentation/devicetree/bindings/serial/esp,esp32-uart.yaml b/Documentation/devicetree/bindings/serial/esp,esp32-uart.yaml new file mode 100644 index 000000000..2a80ca997 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/esp,esp32-uart.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/esp,esp32-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESP32xx UART controllers + +maintainers: + - Max Filippov + +description: + ESP32 UART controller is a part of the ESP32 SoC. + ESP32S3 UART controller is a part of the ESP32S3 SoC. + Both SoCs are produced by Espressif Systems Co. Ltd. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + enum: + - esp,esp32-uart + - esp,esp32s3-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + serial@60000000 { + compatible = "esp,esp32s3-uart"; + reg = <0x60000000 0x80>; + interrupts = <27 1 0>; + clocks = <&serial_clk>; + }; diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml new file mode 100644 index 000000000..4171f524a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale LINFlexD UART + +description: | + The LINFlexD controller implements several LIN protocol versions, as well + as support for full-duplex UART communication through 8-bit and 9-bit + frames. See chapter 47 ("LINFlexD") in the reference manual + https://www.nxp.com/webapp/Download?colCode=S32V234RM. + +maintainers: + - Chester Lin + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - const: fsl,s32v234-linflexuart + - items: + - enum: + - nxp,s32g2-linflexuart + - nxp,s32g3-linflexuart + - const: fsl,s32v234-linflexuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@40053000 { + compatible = "fsl,s32v234-linflexuart"; + reg = <0x40053000 0x1000>; + interrupts = <0 59 4>; + }; diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml new file mode 100644 index 000000000..9c6dc16f8 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Fabio Estevam + +properties: + compatible: + oneOf: + - const: fsl,imx1-uart + - const: fsl,imx21-uart + - items: + - enum: + - fsl,imx25-uart + - fsl,imx27-uart + - fsl,imx31-uart + - fsl,imx35-uart + - fsl,imx50-uart + - fsl,imx51-uart + - fsl,imx53-uart + - fsl,imx6q-uart + - const: fsl,imx21-uart + - items: + - enum: + - fsl,imx6sl-uart + - fsl,imx6sll-uart + - fsl,imx6sx-uart + - const: fsl,imx6q-uart + - const: fsl,imx21-uart + - items: + - enum: + - fsl,imx6ul-uart + - fsl,imx7d-uart + - fsl,imx8mm-uart + - fsl,imx8mn-uart + - fsl,imx8mp-uart + - fsl,imx8mq-uart + - const: fsl,imx6q-uart + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + interrupts: + items: + - description: UART RX Interrupt + - description: UART TX Interrupt + - description: UART RTS Interrupt + minItems: 1 + + wakeup-source: true + + fsl,dte-mode: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicate the uart works in DTE mode. The uart works in DCE mode by default. + + fsl,inverted-tx: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicate that the hardware attached to the peripheral inverts the signal + transmitted, and that the peripheral should invert its output using the + INVT registers. + + fsl,inverted-rx: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Indicate that the hardware attached to the peripheral inverts the signal + received, and that the peripheral should invert its input using the + INVR registers. + + fsl,dma-info: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: | + First cell contains the size of DMA buffer chunks, second cell contains + the amount of chunks used for the device. Multiplying both numbers is + the total size of memory used for receiving data. + When not being configured the system will use default settings, which + are sensible for most use cases. If you need low latency processing on + slow connections this needs to be configured appropriately. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: serial.yaml# + - $ref: rs485.yaml# + + - if: + properties: + compatible: + contains: + const: fsl,imx1-uart + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + else: + properties: + interrupts: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include + + aliases { + serial0 = &uart1; + }; + + uart1: serial@73fbc000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fbc000 0x4000>; + interrupts = <31>; + clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, + <&clks IMX5_CLK_UART1_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; + dma-names = "rx", "tx"; + uart-has-rtscts; + fsl,dte-mode; + }; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml new file mode 100644 index 000000000..c42261b5a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale low power universal asynchronous receiver/transmitter (lpuart) + +maintainers: + - Fugang Duan + +allOf: + - $ref: rs485.yaml# + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - enum: + - fsl,vf610-lpuart + - fsl,ls1021a-lpuart + - fsl,ls1028a-lpuart + - fsl,imx7ulp-lpuart + - fsl,imx8qxp-lpuart + - fsl,imxrt1050-lpuart + - items: + - enum: + - fsl,imx8ulp-lpuart + - const: fsl,imx7ulp-lpuart + - items: + - enum: + - fsl,imx93-lpuart + - fsl,imx94-lpuart + - fsl,imx95-lpuart + - const: fsl,imx8ulp-lpuart + - const: fsl,imx7ulp-lpuart + - items: + - enum: + - fsl,imx8qm-lpuart + - fsl,imx8dxl-lpuart + - const: fsl,imx8qxp-lpuart + - items: + - const: fsl,imxrt1050-lpuart + - const: fsl,imxrt1170-lpuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ipg clock + - description: baud clock + minItems: 1 + + clock-names: + items: + - const: ipg + - const: baud + minItems: 1 + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@40027000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40027000 0x1000>; + interrupts = <0 61 0x00>; + clocks = <&clks VF610_CLK_UART0>; + clock-names = "ipg"; + dmas = <&edma0 0 2>, <&edma0 0 3>; + dma-names = "rx","tx"; + }; diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml new file mode 100644 index 000000000..da032efff --- /dev/null +++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/fsl-mxs-auart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS Application UART (AUART) + +maintainers: + - Fabio Estevam + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - const: fsl,imx23-auart + - const: alphascale,asm9260-auart + - items: + - enum: + - fsl,imx28-auart + - const: fsl,imx23-auart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + clocks: + items: + - description: mod clock + - description: ahb clock + minItems: 1 + + clock-names: + items: + - const: mod + - const: ahb + minItems: 1 + + uart-has-rtscts: true + rts-gpios: true + cts-gpios: true + dtr-gpios: true + dsr-gpios: true + rng-gpios: true + dcd-gpios: true + +if: + properties: + compatible: + contains: + enum: + - alphascale,asm9260-auart +then: + required: + - clocks + - clock-names + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + aliases { + serial0 = &auart0; + }; + + auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; + clocks = <&clks 45>; + }; diff --git a/Documentation/devicetree/bindings/serial/google,goldfish-tty.yaml b/Documentation/devicetree/bindings/serial/google,goldfish-tty.yaml new file mode 100644 index 000000000..0626ce587 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/google,goldfish-tty.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/google,goldfish-tty.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Goldfish TTY + +maintainers: + - Kuan-Wei Chiu + +allOf: + - $ref: /schemas/serial/serial.yaml# + +description: + Android goldfish TTY device generated by Android emulator. + +properties: + compatible: + const: google,goldfish-tty + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@1f004000 { + compatible = "google,goldfish-tty"; + reg = <0x1f004000 0x1000>; + interrupts = <12>; + }; diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml new file mode 100644 index 000000000..d5f153bde --- /dev/null +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/ingenic,uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs UART controller + +maintainers: + - Paul Cercueil + +allOf: + - $ref: serial.yaml# + +properties: + $nodename: + pattern: "^serial@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - ingenic,jz4740-uart + - ingenic,jz4750-uart + - ingenic,jz4760-uart + - ingenic,jz4780-uart + - ingenic,x1000-uart + - items: + - enum: + - ingenic,jz4770-uart + - ingenic,jz4775-uart + - const: ingenic,jz4760-uart + - items: + - const: ingenic,jz4725b-uart + - const: ingenic,jz4740-uart + - items: + - const: ingenic,jz4755-uart + - const: ingenic,jz4750-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Baud clock + - description: UART module clock + + clock-names: + items: + - const: baud + - const: module + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + serial@10032000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10032000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <49>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; + clock-names = "baud", "module"; + + dmas = <&dma JZ4780_DMA_UART2_RX 0xffffffff>, + <&dma JZ4780_DMA_UART2_TX 0xffffffff>; + dma-names = "rx", "tx"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>; + vbat-supply = <&wlan0_power>; + device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/lantiq,asc.yaml b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml new file mode 100644 index 000000000..96e8c79cb --- /dev/null +++ b/Documentation/devicetree/bindings/serial/lantiq,asc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/lantiq,asc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq SoC ASC serial controller + +maintainers: + - John Crispin + - Songjun Wu + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: lantiq,asc + + reg: + maxItems: 1 + + interrupts: + items: + - description: TX interrupt + - description: RX interrupt + - description: Error interrupt + + clocks: + items: + - description: Frequency clock + - description: Gate clock + + clock-names: + items: + - const: freq + - const: asc + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + serial@16600000 { + compatible = "lantiq,asc"; + reg = <0x16600000 0x100000>; + interrupts = , + , + ; + }; diff --git a/Documentation/devicetree/bindings/serial/litex,liteuart.yaml b/Documentation/devicetree/bindings/serial/litex,liteuart.yaml new file mode 100644 index 000000000..c4f1f489d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/litex,liteuart.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LiteUART serial controller + +maintainers: + - Karol Gugala + - Mateusz Holenko + +description: | + LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports + multiple CPU architectures, currently including e.g. OpenRISC and RISC-V. + +properties: + compatible: + const: litex,liteuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + uart0: serial@e0001800 { + compatible = "litex,liteuart"; + reg = <0xe0001800 0x100>; + interrupts = <2>; + }; diff --git a/Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml b/Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml new file mode 100644 index 000000000..6c7fa3d19 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/marvell,armada-3700-uart.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/marvell,armada-3700-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada-3700 UART + +maintainers: + - Pali Rohár + +description: + Marvell UART is a non standard UART used in some of Marvell EBU SoCs (e.g. + Armada-3700). + +properties: + compatible: + enum: + - marvell,armada-3700-uart + - marvell,armada-3700-uart-ext + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + UART reference clock used to derive the baud rate. If absent, only fixed + baud rate from the bootloader is supported. + + interrupts: + minItems: 2 + items: + - description: UART sum interrupt + - description: UART TX interrupt + - description: UART RX interrupt + + interrupt-names: + minItems: 2 + maxItems: 3 + +required: + - compatible + - reg + - interrupts + - interrupt-names + +unevaluatedProperties: false + +allOf: + - $ref: /schemas/serial/serial.yaml# + - if: + properties: + compatible: + const: marvell,armada-3700-uart-ext + then: + properties: + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: uart-tx + - const: uart-rx + else: + properties: + interrupts: + minItems: 3 + + interrupt-names: + items: + - const: uart-sum + - const: uart-tx + - const: uart-rx + +examples: + - | + #include + + serial@12000 { + compatible = "marvell,armada-3700-uart"; + reg = <0x12000 0x18>; + clocks = <&uartclk 0>; + interrupts = + , + , + ; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + }; + + - | + #include + + serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&uartclk 1>; + interrupts = + , + ; + interrupt-names = "uart-tx", "uart-rx"; + }; diff --git a/Documentation/devicetree/bindings/serial/maxim,max310x.yaml b/Documentation/devicetree/bindings/serial/maxim,max310x.yaml new file mode 100644 index 000000000..e598dda4d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/maxim,max310x.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/maxim,max310x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART) + +maintainers: + - Hugo Villeneuve + +description: + The MAX310X is a family of SPI/I2C UARTs with one (max3107, max3108), + two (max3109) or four (max14830) channels. Single-channel parts are + described as a serial node with RS-485 properties on the chip node; + multi-channel parts use one "serial@N" child node per channel, each + carrying its own serial/RS-485 properties. + +properties: + compatible: + enum: + - maxim,max3107 + - maxim,max3108 + - maxim,max3109 + - maxim,max14830 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: + - xtal # External crystal + - osc # External clock source + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: + minItems: 1 + maxItems: 16 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + + - if: + properties: + compatible: + contains: + enum: + - maxim,max3107 + - maxim,max3108 + then: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + + - if: + properties: + compatible: + contains: + enum: + - maxim,max3109 + - maxim,max14830 + then: + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + patternProperties: + "^serial@[0-3]$": + type: object + description: A single UART channel of the chip. + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + properties: + reg: + description: UART channel number on the chip. + maximum: 3 + required: + - reg + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: maxim,max3109 + then: + patternProperties: + "^serial@[23]$": false + +unevaluatedProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + serial@2c { + compatible = "maxim,max3107"; + reg = <0x2c>; + clocks = <&xtal4m>; + clock-names = "xtal"; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + }; + }; + + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + serial@0 { + compatible = "maxim,max14830"; + reg = <0>; + spi-max-frequency = <26000000>; + clocks = <&xtal4m>; + clock-names = "xtal"; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + serial@0 { + reg = <0>; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + }; + + serial@2 { + reg = <2>; + rs485-rts-active-low; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml new file mode 100644 index 000000000..5bd8a8853 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/mediatek,uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Matthias Brugger + +allOf: + - $ref: serial.yaml# + +description: | + The MediaTek UART is based on the basic 8250 UART and compatible + with 16550A, with enhancements for high speed baud rates and + support for DMA. + +properties: + compatible: + oneOf: + - const: mediatek,mt6577-uart + - items: + - enum: + - mediatek,mt2701-uart + - mediatek,mt2712-uart + - mediatek,mt6572-uart + - mediatek,mt6580-uart + - mediatek,mt6582-uart + - mediatek,mt6589-uart + - mediatek,mt6755-uart + - mediatek,mt6765-uart + - mediatek,mt6779-uart + - mediatek,mt6795-uart + - mediatek,mt6797-uart + - mediatek,mt6893-uart + - mediatek,mt7622-uart + - mediatek,mt7623-uart + - mediatek,mt7629-uart + - mediatek,mt7981-uart + - mediatek,mt7986-uart + - mediatek,mt7988-uart + - mediatek,mt8127-uart + - mediatek,mt8135-uart + - mediatek,mt8173-uart + - mediatek,mt8183-uart + - mediatek,mt8186-uart + - mediatek,mt8188-uart + - mediatek,mt8192-uart + - mediatek,mt8195-uart + - mediatek,mt8365-uart + - mediatek,mt8516-uart + - const: mediatek,mt6577-uart + + reg: + description: The base address of the UART register bank + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: The clock the baudrate is derived from + - description: The bus clock for register accesses + + clock-names: + minItems: 1 + items: + - const: baud + - const: bus + + dmas: + items: + - description: phandle to TX DMA + - description: phandle to RX DMA + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + description: + The UART interrupt and optionally the RX in-band wakeup interrupt. + minItems: 1 + items: + - const: uart + - const: wakeup + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + serial@11006000 { + compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; + reg = <0x11006000 0x400>; + interrupts = , + ; + interrupt-names = "uart", "wakeup"; + clocks = <&uart_clk>, <&bus_clk>; + clock-names = "baud", "bus"; + pinctrl-0 = <&uart_pin>; + pinctrl-1 = <&uart_pin_sleep>; + pinctrl-names = "default", "sleep"; + }; diff --git a/Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml b/Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml new file mode 100644 index 000000000..b176fd5b5 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/microchip,pic32mzda-uart.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/microchip,pic32mzda-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 UART + +maintainers: + - Andrei Pistirica + - Purna Chandra Mandal + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: microchip,pic32mzda-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: Fault + - description: RX + - description: TX + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822000 0x50>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, + <113 IRQ_TYPE_LEVEL_HIGH>, + <114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk PB2CLK>; + cts-gpios = <&gpio1 15 0>; + }; diff --git a/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml new file mode 100644 index 000000000..a76af0f60 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART) + +maintainers: + - Min-Jen Chen + - Jacky Huang + +allOf: + - $ref: serial.yaml + +properties: + compatible: + const: nuvoton,ma35d1-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + serial@40700000 { + compatible = "nuvoton,ma35d1-uart"; + reg = <0x40700000 0x100>; + interrupts = ; + clocks = <&clk UART0_GATE>; + }; +... diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml new file mode 100644 index 000000000..e2d111b3e --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Combined UART (TCU) + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: + The TCU is a system for sharing a hardware UART instance among multiple + systems within the Tegra SoC. It is implemented through a mailbox- + based protocol where each "virtual UART" has a pair of mailboxes, one + for transmitting and one for receiving, that is used to communicate + with the hardware implementing the TCU. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + compatible: + oneOf: + - const: nvidia,tegra194-tcu + - items: + - enum: + - nvidia,tegra234-tcu + - const: nvidia,tegra194-tcu + + mbox-names: + items: + - const: rx + - const: tx + + mboxes: + description: | + List of phandles to mailbox channels used for receiving and + transmitting data from and to the hardware UART. + items: + - description: mailbox for receiving data from hardware UART + - description: mailbox for transmitting data to hardware UART + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + #include + + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; + }; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml new file mode 100644 index 000000000..29d48da81 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra20-hsuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-hsuart + - nvidia,tegra30-hsuart + - nvidia,tegra186-hsuart + - nvidia,tegra194-hsuart + - items: + - const: nvidia,tegra124-hsuart + - const: nvidia,tegra30-hsuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: serial + + dmas: + items: + - description: DMA channel used for reception + - description: DMA channel used for transmission + + dma-names: + items: + - const: rx + - const: tx + + nvidia,enable-modem-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: Enable modem interrupts. Should be enable only if all 8 lines of UART controller + are pinmuxed. + + nvidia,adjust-baud-rates: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + List of entries providing percentage of baud rate adjustment within a range. Each entry + contains a set of 3 values: range low/high and adjusted rate. When the baud rate set on the + controller falls within the range mentioned in this field, the baud rate will be adjusted by + percentage mentioned here. + + Example: <9600 115200 200> + + Increase baud rate by 2% when set baud rate falls within range 9600 to 115200. + + Standard UART devices are expected to have tolerance for baud rate error by -4 to +4 %. All + Tegra devices till Tegra210 had this support. However, Tegra186 chip has a known hardware + issue. UART RX baud rate tolerance level is 0% to +4% in 1-stop config. Otherwise, the + received data will have corruption/invalid framing errors. Parker errata suggests adjusting + baud rate to be higher than the deviations observed in TX. + + TX deviation of connected device can be captured over scope (or noted from its spec) for + valid range and Tegra baud rate has to be set above actual TX baud rate observed. To do this + we use nvidia,adjust-baud-rates. + + As an example, consider there is deviation observed in TX for baud rates as listed below. 0 + to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expected and + Tegra UART is expected to handle it. Due to the issue stated above, baud rate on Tegra UART + should be set equal to or above deviation observed for avoiding frame errors. Property + should be set like this: + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>; + items: + items: + - description: range lower bound + - description: range upper bound + - description: adjustment (in permyriad, i.e. 0.01%) + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + - dmas + - dma-names + +allOf: + - $ref: serial.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + + serial@70006000 { + compatible = "nvidia,tegra30-hsuart"; + reg = <0x70006000 0x40>; + interrupts = ; + nvidia,enable-modem-interrupt; + clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */ + }; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml new file mode 100644 index 000000000..572cc574d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra UTC (UART Trace Controller) client + +maintainers: + - Kartik Rajput + - Thierry Reding + - Jonathan Hunter + +description: + Represents a client interface of the Tegra UTC (UART Trace Controller). The + Tegra UTC allows multiple clients within the Tegra SoC to share a physical + UART interface. It supports up to 16 clients. Each client operates as an + independent UART endpoint with a dedicated interrupt and 128-character TX/RX + FIFOs. + + The Tegra UTC clients use 8-N-1 configuration and operates on a baudrate + configured by the bootloader at the controller level. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: nvidia,tegra264-utc + + reg: + items: + - description: TX region. + - description: RX region. + + reg-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + tx-threshold: + minimum: 1 + maximum: 128 + + rx-threshold: + minimum: 1 + maximum: 128 + +required: + - compatible + - reg + - reg-names + - interrupts + - tx-threshold + - rx-threshold + +additionalProperties: false + +examples: + - | + #include + + tegra_utc: serial@c4e0000 { + compatible = "nvidia,tegra264-utc"; + reg = <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; + reg-names = "tx", "rx"; + interrupts = ; + tx-threshold = <4>; + rx-threshold = <4>; + }; diff --git a/Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml b/Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml new file mode 100644 index 000000000..ffa2ea59f --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nxp,lpc3220-hsuart.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nxp,lpc3220-hsuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx SoC High Speed UART + +maintainers: + - Vladimir Zapolskiy + - Piotr Wojtaszczyk + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: nxp,lpc3220-hsuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@40014000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40014000 0x1000>; + interrupts = <26 0>; + }; diff --git a/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml new file mode 100644 index 000000000..ab39b95da --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nxp,sc16is7xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART) + +maintainers: + - Hugo Villeneuve + +properties: + compatible: + enum: + - nxp,sc16is740 + - nxp,sc16is741 + - nxp,sc16is750 + - nxp,sc16is752 + - nxp,sc16is760 + - nxp,sc16is762 + + reg: + maxItems: 1 + + interrupts: + description: + When missing, device driver uses polling instead. + maxItems: 1 + + clocks: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + clock-frequency: + description: + When there is no clock provider visible to the platform, this + is the source crystal or external clock frequency for the IC in Hz. + minimum: 1 + maximum: 80000000 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: + minItems: 1 + maxItems: 8 + + irda-mode-ports: + description: | + An array that lists the indices of the port that should operate in IrDA + mode: + 0: port A + 1: port B + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + + nxp,modem-control-line-ports: + description: | + An array that lists the indices of the port that should have shared GPIO + lines configured as modem control lines: + 0: port A + 1: port B + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +oneOf: + - required: + - clocks + - required: + - clock-frequency + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + serial@51 { + compatible = "nxp,sc16is750"; + reg = <0x51>; + clocks = <&clk20m>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; + + serial@53 { + compatible = "nxp,sc16is752"; + reg = <0x53>; + clocks = <&clk20m>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */ + gpio-controller; /* Port 0 as GPIOs */ + #gpio-cells = <2>; + }; + + serial@54 { + compatible = "nxp,sc16is752"; + reg = <0x54>; + clocks = <&clk20m>; + reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */ + }; + }; diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml new file mode 100644 index 000000000..3fcf2d042 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/pl011.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM AMBA Primecell PL011 serial UART + +maintainers: + - Rob Herring + +allOf: + - $ref: /schemas/arm/primecell.yaml# + - $ref: serial.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - arm,pl011 + required: + - compatible + +properties: + compatible: + items: + - const: arm,pl011 + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + description: + When present, must have one state named "default", + and may contain a second name named "sleep". The former + state sets up pins for ordinary operation whereas + the latter state will put the associated pins to sleep + when the UART is unused + minItems: 1 + items: + - const: default + - const: sleep + + clocks: + description: + When present, the first clock listed must correspond to + the clock named UARTCLK on the IP block, i.e. the clock + to the external serial line, whereas the second clock + must correspond to the PCLK clocking the internal logic + of the block. Just listing one clock (the first one) is + deprecated. + maxItems: 2 + + clock-names: + items: + - const: uartclk + - const: apb_pclk + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + items: + - const: rx + - const: tx + + auto-poll: + description: + Enables polling when using RX DMA. + type: boolean + + poll-rate-ms: + description: + Rate at which poll occurs when auto-poll is set. + default 100ms. + default: 100 + + poll-timeout-ms: + description: + Poll timeout when auto-poll is set, default + 3000ms. + default: 3000 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + reg-io-width: + description: + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [1, 4] + +required: + - compatible + - reg + - interrupts + +dependencies: + poll-rate-ms: [ auto-poll ] + poll-timeout-ms: [ auto-poll ] + +unevaluatedProperties: false + +examples: + - | + serial@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 4>; + dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; + dma-names = "rx", "tx"; + clocks = <&foo_clk>, <&bar_clk>; + clock-names = "uartclk", "apb_pclk"; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml b/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml new file mode 100644 index 000000000..a644e5af1 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qca,ar9330-uart.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qca,ar9330-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR9330 High-Speed UART + +maintainers: + - Oleksij Rempel + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: qca,ar9330-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: uart + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + serial@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + clocks = <&ref>; + clock-names = "uart"; + interrupt-parent = <&intc>; + interrupts = <3>; + }; +... diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml new file mode 100644 index 000000000..bc2e48754 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM SoC Serial UART + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The MSM serial UART hardware is designed for low-speed use cases where a + dma-engine isn't needed. From a software perspective it's mostly compatible + with the MSM serial UARTDM except that it only supports reading and writing + one character at a time. + +properties: + compatible: + const: qcom,msm-uart + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +allOf: + - $ref: /schemas/serial/serial.yaml# + +unevaluatedProperties: false + +examples: + - | + serial@a9c00000 { + compatible = "qcom,msm-uart"; + reg = <0xa9c00000 0x1000>; + interrupts = <11>; + clocks = <&uart_cxc>; + clock-names = "core"; + }; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml new file mode 100644 index 000000000..bc967ead2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM Serial UARTDM + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: | + The MSM serial UARTDM hardware is designed for high-speed use cases where the + transmit and/or receive channels can be offloaded to a dma-engine. From a + software perspective it's mostly compatible with the MSM serial UART except + that it supports reading and writing multiple characters at a time. + + Note: Aliases may be defined to ensure the correct ordering of the UARTs. + The alias serialN will result in the UART being assigned port N. If any + serialN alias exists, then an alias must exist for each enabled UART. The + serialN aliases should be in a .dts file instead of in a .dtsi file. + +properties: + compatible: + items: + - enum: + - qcom,msm-uartdm-v1.1 + - qcom,msm-uartdm-v1.2 + - qcom,msm-uartdm-v1.3 + - qcom,msm-uartdm-v1.4 + - const: qcom,msm-uartdm + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: iface + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interconnects: + maxItems: 1 + + interrupts: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + + qcom,rx-crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Identificator for Client Rate Control Interface to be used with RX DMA + channel. Required when using DMA for reception with UARTDM v1.3 and + below. + + qcom,tx-crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Identificator for Client Rate Control Interface to be used with TX DMA + channel. Required when using DMA for transmission with UARTDM v1.3 and + below. + + reg: + minItems: 1 + items: + - description: Main control registers + - description: An optional second register location shall specify the GSBI control region. + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +allOf: + - $ref: /schemas/serial/serial.yaml# + + - if: + properties: + compatible: + contains: + const: qcom,msm-uartdm-v1.3 + then: + properties: + reg: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; + clock-names = "core", "iface"; + dmas = <&dma0 0>, <&dma0 1>; + dma-names = "tx", "rx"; + power-domains = <&rpmpd MSM8996_VDDCX>; + operating-points-v2 = <&uart_opp_table>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + }; diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml new file mode 100644 index 000000000..8496f822d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Praveen Talari + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + oneOf: + - enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + - items: + - const: qcom,sa8797p-geni-uart + - const: qcom,sa8255p-geni-uart + - items: + - const: qcom,sa8797p-geni-debug-uart + - const: qcom,sa8255p-geni-debug-uart + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + interrupt-names: + description: + The UART interrupt and optionally the RX in-band wakeup interrupt + as not all UART instances have a wakeup-capable interrupt routed + via the PDC. + minItems: 1 + items: + - const: uart + - const: wakeup + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + + serial@990000 { + compatible = "qcom,sa8255p-geni-uart"; + reg = <0x990000 0x4000>; + interrupts = ; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; +... diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml new file mode 100644 index 000000000..ed7b3909d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Andy Gross + - Bjorn Andersson + +allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# + +properties: + compatible: + enum: + - qcom,geni-uart + - qcom,geni-debug-uart + + clocks: + maxItems: 1 + + clock-names: + const: se + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + operating-points-v2: true + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0xa88000 0x7000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + }; +... diff --git a/Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml b/Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml new file mode 100644 index 000000000..5f4ed8221 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/rda,8810pl-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro UART Interface + +maintainers: + - Manivannan Sadhasivam + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: rda,8810pl-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + uart3: serial@20a90000 { + compatible = "rda,8810pl-uart"; + reg = <0x20a90000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + }; +... diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml new file mode 100644 index 000000000..89f1eb0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile UART Interface + +maintainers: + - Magnus Damm + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a09g011-uart # RZ/V2M + - const: renesas,em-uart # generic EMMA Mobile compatible UART + + - items: + - const: renesas,em-uart # generic EMMA Mobile compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: UART functional clock + - description: Internal clock to access the registers + + clock-names: + minItems: 1 + items: + - const: sclk + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g011-uart + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + +unevaluatedProperties: false + +examples: + - | + #include + uart0: serial@e1020000 { + compatible = "renesas,em-uart"; + reg = <0xe1020000 0x38>; + interrupts = ; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml new file mode 100644 index 000000000..4b3f98a46 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,hscif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF) + +maintainers: + - Geert Uytterhoeven + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,hscif-r8a7778 # R-Car M1 + - renesas,hscif-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-hscif # R-Car Gen1 + - const: renesas,hscif # generic HSCIF compatible UART + + - items: + - enum: + - renesas,hscif-r8a7742 # RZ/G1H + - renesas,hscif-r8a7743 # RZ/G1M + - renesas,hscif-r8a7744 # RZ/G1N + - renesas,hscif-r8a7745 # RZ/G1E + - renesas,hscif-r8a77470 # RZ/G1C + - renesas,hscif-r8a7790 # R-Car H2 + - renesas,hscif-r8a7791 # R-Car M2-W + - renesas,hscif-r8a7792 # R-Car V2H + - renesas,hscif-r8a7793 # R-Car M2-N + - renesas,hscif-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1 + - const: renesas,hscif # generic HSCIF compatible UART + + - items: + - enum: + - renesas,hscif-r8a774a1 # RZ/G2M + - renesas,hscif-r8a774b1 # RZ/G2N + - renesas,hscif-r8a774c0 # RZ/G2E + - renesas,hscif-r8a774e1 # RZ/G2H + - renesas,hscif-r8a7795 # R-Car H3 + - renesas,hscif-r8a7796 # R-Car M3-W + - renesas,hscif-r8a77961 # R-Car M3-W+ + - renesas,hscif-r8a77965 # R-Car M3-N + - renesas,hscif-r8a77970 # R-Car V3M + - renesas,hscif-r8a77980 # R-Car V3H + - renesas,hscif-r8a77990 # R-Car E3 + - renesas,hscif-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 + - const: renesas,hscif # generic HSCIF compatible UART + + - items: + - enum: + - renesas,hscif-r8a779a0 # R-Car V3U + - renesas,hscif-r8a779f0 # R-Car S4-8 + - renesas,hscif-r8a779g0 # R-Car V4H + - renesas,hscif-r8a779h0 # R-Car V4M + - const: renesas,rcar-gen4-hscif # R-Car Gen4 + - const: renesas,hscif # generic HSCIF compatible UART + + - items: + - enum: + - renesas,hscif-r8a78000 # R-Car X5H + - const: renesas,rcar-gen5-hscif # R-Car Gen5 + - const: renesas,hscif # generic HSCIF compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: + - fck # UART functional clock + - hsck # optional external clock input + - brg_int # optional internal clock source for BRG frequency divider + - scif_clk # optional external clock source for BRG frequency divider + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 4 + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-hscif + - renesas,rcar-gen3-hscif + - renesas,rcar-gen4-hscif + - renesas,rcar-gen5-hscif +then: + required: + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + aliases { + serial1 = &hscif1; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0xe6550000 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + uart-has-rtscts; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml new file mode 100644 index 000000000..85ebb3056 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,rsci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RSCI Serial Communication Interface + +maintainers: + - Geert Uytterhoeven + - Lad Prabhakar + +properties: + compatible: + oneOf: + - enum: + - renesas,r9a08g046-rsci # RZ/G3L + - renesas,r9a09g047-rsci # RZ/G3E + - renesas,r9a09g077-rsci # RZ/T2H + + - items: + - enum: + - renesas,r9a09g056-rsci # RZ/V2N + - renesas,r9a09g057-rsci # RZ/V2H(P) + - const: renesas,r9a09g047-rsci + + - items: + - const: renesas,r9a09g087-rsci # RZ/N2H + - const: renesas,r9a09g077-rsci # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + minItems: 4 + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + - description: Active edge detection interrupt + - description: Break field detection interrupt + + interrupt-names: + minItems: 4 + items: + - const: eri + - const: rxi + - const: txi + - const: tei + - const: aed + - const: bfd + + clocks: + minItems: 2 + maxItems: 6 + + clock-names: + oneOf: + - items: + - const: operation + - const: bus + - const: sck # optional external clock input + + minItems: 2 + + - items: + - const: pclk + - const: tclk + - const: tclk_div4 + - const: tclk_div16 + - const: tclk_div64 + - const: sck # optional external clock input + + minItems: 5 + + resets: + items: + - description: Input for resetting the APB clock + - description: Input for resetting TCLK + + reset-names: + items: + - const: presetn + - const: tresetn + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-rsci + then: + properties: + interrupts: + maxItems: 4 + + interrupt-names: + maxItems: 4 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + resets: false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-rsci + then: + properties: + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + clocks: + minItems: 5 + maxItems: 6 + + clock-names: + minItems: 5 + maxItems: 6 + + required: + - resets + - reset-names + + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-rsci + then: + properties: + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + required: + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0x80005000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE 13>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml new file mode 100644 index 000000000..64d3db6e5 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,sci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communication Interface + +maintainers: + - Geert Uytterhoeven + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five + - renesas,r9a07g044-sci # RZ/G2{L,LC} + - renesas,r9a07g054-sci # RZ/V2L + - const: renesas,sci # generic SCI compatible UART + + - items: + - const: renesas,sci # generic SCI compatible UART + + reg: + maxItems: 1 + + interrupts: + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + + interrupt-names: + items: + - const: eri + - const: rxi + - const: txi + - const: tei + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + + uart-has-rtscts: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-sci + - renesas,r9a07g044-sci + - renesas,r9a07g054-sci +then: + properties: + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + required: + - resets + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + + aliases { + serial0 = &sci0; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0x1004d000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml new file mode 100644 index 000000000..82f544468 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -0,0 +1,281 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,scif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communication Interface with FIFO (SCIF) + +maintainers: + - Geert Uytterhoeven + +properties: + compatible: + oneOf: + - enum: + - renesas,scif-r7s9210 # RZ/A2 + - renesas,scif-r9a07g044 # RZ/G2{L,LC} + - renesas,scif-r9a09g057 # RZ/V2H(P) + + - items: + - enum: + - renesas,scif-r7s72100 # RZ/A1H + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a7778 # R-Car M1 + - renesas,scif-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-scif # R-Car Gen1 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a7742 # RZ/G1H + - renesas,scif-r8a7743 # RZ/G1M + - renesas,scif-r8a7744 # RZ/G1N + - renesas,scif-r8a7745 # RZ/G1E + - renesas,scif-r8a77470 # RZ/G1C + - renesas,scif-r8a7790 # R-Car H2 + - renesas,scif-r8a7791 # R-Car M2-W + - renesas,scif-r8a7792 # R-Car V2H + - renesas,scif-r8a7793 # R-Car M2-N + - renesas,scif-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a774a1 # RZ/G2M + - renesas,scif-r8a774a3 # RZ/G2M v3.0 + - renesas,scif-r8a774b1 # RZ/G2N + - renesas,scif-r8a774c0 # RZ/G2E + - renesas,scif-r8a774e1 # RZ/G2H + - renesas,scif-r8a7795 # R-Car H3 + - renesas,scif-r8a7796 # R-Car M3-W + - renesas,scif-r8a77961 # R-Car M3-W+ + - renesas,scif-r8a77965 # R-Car M3-N + - renesas,scif-r8a77970 # R-Car V3M + - renesas,scif-r8a77980 # R-Car V3H + - renesas,scif-r8a77990 # R-Car E3 + - renesas,scif-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a779a0 # R-Car V3U + - renesas,scif-r8a779f0 # R-Car S4-8 + - renesas,scif-r8a779g0 # R-Car V4H + - renesas,scif-r8a779h0 # R-Car V4M + - const: renesas,rcar-gen4-scif # R-Car Gen4 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r8a78000 # R-Car X5H + - const: renesas,rcar-gen5-scif # R-Car Gen5 + - const: renesas,scif # generic SCIF compatible UART + + - items: + - enum: + - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five + - renesas,scif-r9a07g054 # RZ/V2L + - renesas,scif-r9a08g045 # RZ/G3S + - renesas,scif-r9a08g046 # RZ/G3L + - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback + + - items: + - enum: + - renesas,scif-r9a09g047 # RZ/G3E + - renesas,scif-r9a09g056 # RZ/V2N + - const: renesas,scif-r9a09g057 # RZ/V2H fallback + + reg: + maxItems: 1 + + interrupts: + oneOf: + - items: + - description: A combined interrupt + - items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Break interrupt + - description: Data Ready interrupt + - description: Transmit End interrupt + - description: Transmit End/Data Ready interrupt + - description: Receive buffer full interrupt (EDGE trigger) + - description: Transmit buffer empty interrupt (EDGE trigger) + minItems: 4 + + interrupt-names: + minItems: 4 + items: + - const: eri + - const: rxi + - const: txi + - const: bri + - const: dri + - const: tei + - const: tei-dri + - const: rxi-edge + - const: txi-edge + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + - brg_int # optional internal clock source for BRG frequency divider + - scif_clk # optional external clock source for BRG frequency divider + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 4 + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scif + - renesas,rcar-gen3-scif + - renesas,rcar-gen4-scif + - renesas,rcar-gen5-scif + - renesas,scif-r9a07g044 + - renesas,scif-r9a09g057 + then: + required: + - resets + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen1-scif + - renesas,rcar-gen2-scif + - renesas,rcar-gen3-scif + - renesas,rcar-gen4-scif + - renesas,rcar-gen5-scif + then: + properties: + interrupts: + maxItems: 1 + + interrupt-names: false + else: + required: + - interrupt-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,scif-r7s72100 + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + + interrupt-names: + maxItems: 4 + + - if: + properties: + compatible: + contains: + enum: + - renesas,scif-r7s9210 + - renesas,scif-r9a07g044 + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + + interrupt-names: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: renesas,scif-r9a09g057 + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + interrupts: + minItems: 9 + + interrupt-names: + minItems: 9 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + aliases { + serial0 = &scif0; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0xe6e60000 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml new file mode 100644 index 000000000..c98657cf4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,scifa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communications Interface with FIFO A (SCIFA) + +maintainers: + - Geert Uytterhoeven + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,scifa-r8a73a4 # R-Mobile APE6 + - renesas,scifa-r8a7740 # R-Mobile A1 + - renesas,scifa-sh73a0 # SH-Mobile AG5 + - const: renesas,scifa # generic SCIFA compatible UART + + - items: + - enum: + - renesas,scifa-r8a7742 # RZ/G1H + - renesas,scifa-r8a7743 # RZ/G1M + - renesas,scifa-r8a7744 # RZ/G1N + - renesas,scifa-r8a7745 # RZ/G1E + - renesas,scifa-r8a7790 # R-Car H2 + - renesas,scifa-r8a7791 # R-Car M2-W + - renesas,scifa-r8a7793 # R-Car M2-N + - renesas,scifa-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-scifa # R-Car Gen2 and RZ/G1 + - const: renesas,scifa # generic SCIFA compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: + - fck # UART functional clock + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 4 + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scifa +then: + required: + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + aliases { + serial0 = &scifa0; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", + "renesas,scifa"; + reg = <0xe6c40000 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml new file mode 100644 index 000000000..fb695b311 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,scifb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communications Interface with FIFO B (SCIFB) + +maintainers: + - Geert Uytterhoeven + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,scifb-r8a73a4 # R-Mobile APE6 + - renesas,scifb-r8a7740 # R-Mobile A1 + - renesas,scifb-sh73a0 # SH-Mobile AG5 + - const: renesas,scifb # generic SCIFB compatible UART + + - items: + - enum: + - renesas,scifb-r8a7742 # RZ/G1H + - renesas,scifb-r8a7743 # RZ/G1M + - renesas,scifb-r8a7744 # RZ/G1N + - renesas,scifb-r8a7745 # RZ/G1E + - renesas,scifb-r8a7790 # R-Car H2 + - renesas,scifb-r8a7791 # R-Car M2-W + - renesas,scifb-r8a7793 # R-Car M2-N + - renesas,scifb-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-scifb # R-Car Gen2 and RZ/G1 + - const: renesas,scifb # generic SCIFB compatible UART + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: + - fck # UART functional clock + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 4 + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scifb +then: + required: + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + scifb: serial@e6c30000 { + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; + }; diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml new file mode 100644 index 000000000..b93254ad2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/rs485.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RS485 serial communications + +description: The RTS signal is capable of automatically controlling line + direction for the built-in half-duplex mode. The properties described + hereafter shall be given to a half-duplex capable UART node. + +maintainers: + - Rob Herring + +properties: + rs485-rts-delay: + description: prop-encoded-array + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: Delay between rts signal and beginning of data sent in + milliseconds. It corresponds to the delay before sending data. + default: 0 + maximum: 100 + - description: Delay between end of data sent and rts signal in milliseconds. + It corresponds to the delay after sending data and actual release + of the line. + default: 0 + maximum: 100 + + rs485-rts-active-high: + description: drive RTS high when sending (this is the default). + $ref: /schemas/types.yaml#/definitions/flag + + rs485-rts-active-low: + description: drive RTS low when sending (default is high). + $ref: /schemas/types.yaml#/definitions/flag + + rs485-rx-active-high: + description: Polarity of receiver enable signal (when separate from RTS). + True indicates active high (default is low). + $ref: /schemas/types.yaml#/definitions/flag + + linux,rs485-enabled-at-boot-time: + description: enables the rs485 feature at boot time. It can be disabled + later with proper ioctl. + $ref: /schemas/types.yaml#/definitions/flag + + rs485-rx-during-tx: + description: enables the receiving of data even while sending data. + $ref: /schemas/types.yaml#/definitions/flag + + rs485-term-gpios: + description: GPIO pin to enable RS485 bus termination. + maxItems: 1 + + rs485-rx-during-tx-gpios: + description: Output GPIO pin that sets the state of rs485-rx-during-tx. This + signal can be used to control the RX part of an RS485 transceiver. Thereby + the active state enables RX during TX. + maxItems: 1 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml new file mode 100644 index 000000000..75ac2a08f --- /dev/null +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/samsung_uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller + +maintainers: + - Krzysztof Kozlowski + - Greg Kroah-Hartman + +description: |+ + Each Samsung UART should have an alias correctly numbered in the "aliases" + node, according to serialN format, where N is the port number (non-negative + decimal integer) as specified by User's Manual of respective SoC. + +properties: + compatible: + oneOf: + - enum: + - apple,s5l-uart + - axis,artpec8-uart + - google,gs101-uart + - samsung,s3c6400-uart + - samsung,s5pv210-uart + - samsung,exynos4210-uart + - samsung,exynos5433-uart + - samsung,exynos850-uart + - samsung,exynos8895-uart + - items: + - enum: + - samsung,exynos2200-uart + - const: google,gs101-uart + - items: + - enum: + - samsung,exynos7-uart + - tesla,fsd-uart + - const: samsung,exynos4210-uart + - items: + - enum: + - samsung,exynos7885-uart + - const: samsung,exynos5433-uart + - items: + - enum: + - samsung,exynosautov9-uart + - samsung,exynosautov920-uart + - const: samsung,exynos850-uart + - items: + - enum: + - axis,artpec9-uart + - samsung,exynos7870-uart + - samsung,exynos8890-uart + - const: samsung,exynos8895-uart + + reg: + maxItems: 1 + + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [ 1, 4 ] + + clocks: + minItems: 2 + maxItems: 5 + + clock-names: + minItems: 2 + maxItems: 5 + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + + interrupts: + description: RX interrupt and optionally TX interrupt. + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + samsung,uart-fifosize: + description: The fifo size supported by the UART channel. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [16, 64, 256] + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + enum: + - samsung,s3c6400-uart + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: uart + - const: clk_uart_baud2 + - const: clk_uart_baud3 + + else: + properties: + clock-names: + minItems: 2 + items: + - const: uart + - const: clk_uart_baud0 + - const: clk_uart_baud1 + - const: clk_uart_baud2 + - const: clk_uart_baud3 + + - if: + properties: + compatible: + contains: + enum: + - samsung,s5pv210-uart + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + minItems: 3 + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - apple,s5l-uart + - axis,artpec8-uart + - samsung,exynos4210-uart + - samsung,exynos5433-uart + then: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - google,gs101-uart + - samsung,exynos8895-uart + then: + required: + - samsung,uart-fifosize + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - google,gs101-uart + then: + properties: + reg-io-width: false + +unevaluatedProperties: false + +examples: + - | + #include + + uart0: serial@7f005000 { + compatible = "samsung,s3c6400-uart"; + reg = <0x7f005000 0x100>; + interrupt-parent = <&vic1>; + interrupts = <5>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; + samsung,uart-fifosize = <16>; + }; + - | + #include + #include + #include + + serial_0: serial@10a00000 { + compatible = "google,gs101-uart"; + reg = <0x10a00000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart0_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + }; diff --git a/Documentation/devicetree/bindings/serial/serial-peripheral-props.yaml b/Documentation/devicetree/bindings/serial/serial-peripheral-props.yaml new file mode 100644 index 000000000..b4a73214d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/serial-peripheral-props.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/serial-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Serial-attached Devices + +maintainers: + - Rob Herring + - Greg Kroah-Hartman + +description: + Devices connected over serial/UART, expressed as children of a serial + controller, might need similar properties, e.g. for configuring the baud + rate. + +properties: + max-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum baud rate the device operates at. + This should only be present if the maximum is less than the slave + device can support. For example, a particular board has some + signal quality issue or the host processor can't support higher + baud rates. + + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The current baud rate the device operates at. + This should only be present in case a driver has no chance to know + the baud rate of the slave device. + Examples: + * device supports auto-baud + * the rate is setup by a bootloader and there is no way to reset + the device + * device baud rate is configured by its firmware but there is no + way to request the actual settings + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml new file mode 100644 index 000000000..96eb1de87 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/serial.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Serial Interface Generic + +maintainers: + - Rob Herring + - Greg Kroah-Hartman + +description: + This document lists a set of generic properties for describing UARTs in a + device tree. Whether these properties apply to a particular device depends + on the DT bindings for the actual device. + + Each enabled UART may have an optional "serialN" alias in the "aliases" node, + where N is the port number (non-negative decimal integer) as printed on the + label next to the physical port. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + label: true + + cts-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's CTS line. + + dcd-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's DCD line. + + dsr-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's DSR line. + + dtr-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's DTR line. + + rng-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's RNG line. + + rts-gpios: + maxItems: 1 + description: + Must contain a GPIO specifier, referring to the GPIO pin to be used as + the UART's RTS line. + + uart-has-rtscts: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the UART has dedicated lines + for RTS/CTS hardware flow control, and that they are available for use + (wired and enabled by pinmux configuration). This depends on both the + UART hardware and the board wiring. + + rx-tx-swap: + type: boolean + description: RX and TX pins are swapped. + + cts-rts-swap: + type: boolean + description: CTS and RTS pins are swapped. + + rx-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + RX FIFO threshold configuration (in bytes). + + tx-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + TX FIFO threshold configuration (in bytes). + + port: + $ref: /schemas/graph.yaml#/properties/port + +patternProperties: + "^(bluetooth|bluetooth-gnss|embedded-controller|gnss|gps|mcu|onewire)$": + if: + type: object + then: + additionalProperties: true + $ref: serial-peripheral-props.yaml# + description: + Serial attached devices shall be a child node of the host UART device + the slave device is attached to. It is expected that the attached + device is the only child node of the UART device. The slave device node + name shall reflect the generic type of device for the node. + + properties: + compatible: + description: + Compatible of the device connected to the serial port. + + required: + - compatible + +if: + required: + - uart-has-rtscts +then: + properties: + cts-gpios: false + rts-gpios: false + +additionalProperties: true + +examples: + - | + serial@1234 { + compatible = "ns16550a"; + reg = <0x1234 0x20>; + interrupts = <1>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + interrupt-parent = <&gpio>; + interrupts = <10>; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml new file mode 100644 index 000000000..b0df1cac4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/sifive-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive asynchronous serial interface (UART) + +maintainers: + - Pragnesh Patel + - Paul Walmsley + - Palmer Dabbelt + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + items: + - enum: + - sifive,fu540-c000-uart + - sifive,fu740-c000-uart + - canaan,k210-uarths + - const: sifive,uart0 + + description: + Should be something similar to "sifive,-uart" + for the UART as integrated on a particular chip, + and "sifive,uart" for the general UART IP + block programming model. + + UART HDL that corresponds to the IP block version + numbers can be found here - + + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + interrupt-parent = <&plic0>; + interrupts = <80>; + reg = <0x10010000 0x1000>; + clocks = <&prci FU540_PRCI_CLK_TLCLK>; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/snps,arc-uart.yaml b/Documentation/devicetree/bindings/serial/snps,arc-uart.yaml new file mode 100644 index 000000000..dd3096fbf --- /dev/null +++ b/Documentation/devicetree/bindings/serial/snps,arc-uart.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/snps,arc-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys ARC UART + +maintainers: + - Vineet Gupta + +description: + Synopsys ARC UART is a non-standard UART used in some of the ARC FPGA boards. + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: snps,arc-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + description: the input clock frequency for the UART + + current-speed: + description: baud rate for UART + +required: + - compatible + - reg + - interrupts + - clock-frequency + - current-speed + +unevaluatedProperties: false + +examples: + - | + serial@c0fc1000 { + compatible = "snps,arc-uart"; + reg = <0xc0fc1000 0x100>; + interrupts = <5>; + clock-frequency = <80000000>; + current-speed = <115200>; + }; diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml new file mode 100644 index 000000000..664305de4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare ABP UART + +maintainers: + - Rob Herring + +allOf: + - $ref: serial.yaml# + - $ref: rs485.yaml# + + - if: + properties: + compatible: + items: + - {} + - const: renesas,rzn1-uart + - const: snps,dw-apb-uart + then: + properties: + dmas: false + dma-names: false + + - if: + properties: + compatible: + contains: + const: starfive,jh7110-uart + then: + properties: + resets: + minItems: 2 + else: + properties: + resets: + maxItems: 1 + +properties: + compatible: + oneOf: + - items: + - const: renesas,r9a06g032-uart + - const: renesas,rzn1-uart + - const: snps,dw-apb-uart + - items: + - const: renesas,r9a06g032-uart + - const: renesas,rzn1-uart + - items: + - enum: + - anlogic,dr1v90-uart + - brcm,bcm11351-dw-apb-uart + - brcm,bcm21664-dw-apb-uart + - google,lga-uart + - rockchip,px30-uart + - rockchip,rk1808-uart + - rockchip,rk3036-uart + - rockchip,rk3066-uart + - rockchip,rk3128-uart + - rockchip,rk3188-uart + - rockchip,rk3288-uart + - rockchip,rk3308-uart + - rockchip,rk3328-uart + - rockchip,rk3368-uart + - rockchip,rk3399-uart + - rockchip,rk3506-uart + - rockchip,rk3528-uart + - rockchip,rk3562-uart + - rockchip,rk3568-uart + - rockchip,rk3576-uart + - rockchip,rk3588-uart + - rockchip,rv1103b-uart + - rockchip,rv1106-uart + - rockchip,rv1108-uart + - rockchip,rv1126-uart + - sophgo,sg2044-uart + - starfive,jh7100-hsuart + - starfive,jh7100-uart + - starfive,jh7110-uart + - ultrarisc,dp1000-uart + - const: snps,dw-apb-uart + - const: snps,dw-apb-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: true + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: baudclk + - const: apb_pclk + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + snps,uart-16550-compatible: + description: reflects the value of UART_16550_COMPATIBLE configuration + parameter. Define this if your UART does not implement the busy functionality. + type: boolean + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reg-shift: true + + reg-io-width: true + + dcd-override: + description: Override the DCD modem status signal. This signal will + always be reported as active instead of being obtained from the modem + status register. Define this if your serial port does not use this + pin. + type: boolean + + dsr-override: + description: Override the DTS modem status signal. This signal will + always be reported as active instead of being obtained from the modem + status register. Define this if your serial port does not use this + pin. + type: boolean + + cts-override: + description: Override the CTS modem status signal. This signal will + always be reported as active instead of being obtained from the modem + status register. Define this if your serial port does not use this + pin. + type: boolean + + ri-override: + description: Override the RI modem status signal. This signal will always + be reported as inactive instead of being obtained from the modem status + register. Define this if your serial port does not use this pin. + type: boolean + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + serial@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clock-frequency = <3686400>; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + dcd-override; + dsr-override; + cts-override; + ri-override; + }; + + - | + // Example with one clock: + serial@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clocks = <&baudclk>; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + - | + // Example with two clocks: + serial@80230000 { + compatible = "snps,dw-apb-uart"; + reg = <0x80230000 0x100>; + clocks = <&baudclk>, <&apb_pclk>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <10>; + reg-shift = <2>; + reg-io-width = <4>; + }; +... diff --git a/Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml new file mode 100644 index 000000000..34a997ca2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/socionext,milbeaut-usio-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/socionext,milbeaut-usio-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext Milbeaut UART controller + +maintainers: + - Sugaya Taichi + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + const: socionext,milbeaut-usio-uart + + reg: + maxItems: 1 + + interrupts: + items: + - description: RX interrupt specifier + - description: TX interrupt specifier + + interrupt-names: + items: + - const: rx + - const: tx + + clocks: + maxItems: 1 + + auto-flow-control: + description: Enable automatic flow control. + type: boolean + +required: + - compatible + - reg + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + serial@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + auto-flow-control; + }; diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml new file mode 100644 index 000000000..3d01cc355 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier UART controller + +maintainers: + - Masahiro Yamada + +properties: + compatible: + const: socionext,uniphier-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + auto-flow-control: + description: enable automatic flow control support. + $ref: /schemas/types.yaml#/definitions/flag + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + aliases { + serial0 = &serial0; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + }; diff --git a/Documentation/devicetree/bindings/serial/sprd-uart.yaml b/Documentation/devicetree/bindings/serial/sprd-uart.yaml new file mode 100644 index 000000000..5bf2656af --- /dev/null +++ b/Documentation/devicetree/bindings/serial/sprd-uart.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/sprd-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum serial UART + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +properties: + compatible: + oneOf: + - items: + - enum: + - sprd,ums9632-uart + - const: sprd,sc9632-uart + - items: + - enum: + - sprd,sc9860-uart + - sprd,sc9863a-uart + - sprd,ums512-uart + - sprd,ums9620-uart + - const: sprd,sc9836-uart + - enum: + - sprd,sc9632-uart + - sprd,sc9836-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + description: | + "enable" for UART module enable clock, "uart" for UART clock, "source" + for UART source (parent) clock. + items: + - const: enable + - const: uart + - const: source + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + serial@0 { + compatible = "sprd,sc9860-uart", "sprd,sc9836-uart"; + reg = <0x0 0x100>; + interrupts = ; + dma-names = "rx", "tx"; + dmas = <&ap_dma 19>, <&ap_dma 20>; + clock-names = "enable", "uart", "source"; + clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/st,asc.yaml b/Documentation/devicetree/bindings/serial/st,asc.yaml new file mode 100644 index 000000000..f2083388f --- /dev/null +++ b/Documentation/devicetree/bindings/serial/st,asc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/st,asc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi SoCs Serial Port + +maintainers: + - Patrice Chotard + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: st,asc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + st,hw-flow-ctrl: + description: When set, enable hardware flow control. + type: boolean + + st,force-m1: + description: When set, force asc to be in Mode-1. This is recommended for + high bit rates above 19.2K. + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + serial@9830000 { + compatible = "st,asc"; + reg = <0x9830000 0x2c>; + interrupts = ; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + }; +... diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml new file mode 100644 index 000000000..2ed526139 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Erwan Le Ray + +title: STMicroelectronics STM32 USART + +properties: + compatible: + enum: + - st,stm32-uart + - st,stm32f7-uart + - st,stm32h7-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + label: + description: label associated with this uart + + st,hw-flow-ctrl: + description: enable hardware flow control (deprecated) + $ref: /schemas/types.yaml#/definitions/flag + + rx-tx-swap: true + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + items: + enum: [ rx, tx ] + minItems: 1 + maxItems: 2 + +# cts-gpios and rts-gpios properties can be used instead of 'uart-has-rtscts' +# or 'st,hw-flow-ctrl' (deprecated) for making use of any gpio pins for flow +# control instead of dedicated pins. +# +# It should be noted that both cts-gpios/rts-gpios and 'uart-has-rtscts' or +# 'st,hw-flow-ctrl' (deprecated) properties cannot co-exist in a design. + cts-gpios: true + rts-gpios: true + + wakeup-source: true + + power-domains: + maxItems: 1 + + rx-threshold: + description: + If value is set to 1, RX FIFO threshold is disabled. + enum: [1, 2, 4, 8, 12, 14, 16] + default: 8 + + tx-threshold: + description: + If value is set to 1, TX FIFO threshold is disabled. + enum: [1, 2, 4, 8, 12, 14, 16] + default: 8 + + access-controllers: + minItems: 1 + maxItems: 2 + +allOf: + - $ref: rs485.yaml# + - $ref: serial.yaml# + - if: + required: + - st,hw-flow-ctrl + then: + properties: + cts-gpios: false + rts-gpios: false + - if: + properties: + compatible: + const: st,stm32-uart + then: + properties: + rx-tx-swap: false + - if: + properties: + compatible: + contains: + enum: + - st,stm32-uart + - st,stm32f7-uart + then: + properties: + rx-threshold: false + tx-threshold: false + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + usart1: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 0 164>; + dmas = <&dma2 2 4 0x414 0x0>, + <&dma2 7 4 0x414 0x0>; + dma-names = "rx", "tx"; + rx-threshold = <4>; + tx-threshold = <4>; + rs485-rts-active-low; + }; + +... diff --git a/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml new file mode 100644 index 000000000..7d0a4bcb8 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoC SP7021 UART Controller + +maintainers: + - Hammer Hsieh + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: sunplus,sp7021-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include + aliases { + serial0 = &uart0; + }; + + uart0: serial@9c000900 { + compatible = "sunplus,sp7021-uart"; + reg = <0x9c000900 0x80>; + interrupt-parent = <&intc>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 0x28>; + resets = <&rstc 0x18>; + }; +... diff --git a/Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml b/Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml new file mode 100644 index 000000000..9c6819241 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/via,vt8500-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA VT8500 and WonderMedia WM8xxx UART Controller + +maintainers: + - Alexey Charkov + +allOf: + - $ref: serial.yaml + +properties: + compatible: + enum: + - via,vt8500-uart # up to WM8850/WM8950 + - wm,wm8880-uart # for WM8880 and later + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + serial@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&clkuart0>; + }; diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml new file mode 100644 index 000000000..08dcb275d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Axi Uartlite + +maintainers: + - Peter Korsgaard + +properties: + compatible: + contains: + enum: + - xlnx,xps-uartlite-1.00.a + - xlnx,opb-uartlite-1.00.b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Set Uart port number + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The fixed baud rate that the device was configured for. + + xlnx,data-bits: + enum: [5, 6, 7, 8] + description: + The fixed number of data bits that the device was configured for. + + xlnx,use-parity: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Whether parity checking was enabled when the device was configured. + + xlnx,odd-parity: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Whether odd parity was configured. + +required: + - compatible + - reg + - interrupts + - current-speed + - xlnx,data-bits + - xlnx,use-parity + +allOf: + - $ref: serial.yaml# + - if: + properties: + xlnx,use-parity: + const: 1 + then: + required: + - xlnx,odd-parity + +unevaluatedProperties: false + +examples: + - | + serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; + current-speed = <115200>; + xlnx,data-bits = <8>; + xlnx,use-parity = <0>; + }; +... -- cgit v1.3.1