From a5bde5d8fde8a8cb28e59a672d5ddc5b9c1e7656 Mon Sep 17 00:00:00 2001 From: Breno Leitao Date: Wed, 5 Aug 2026 07:52:36 -0700 Subject: workqueue: skip the node_nr_active update for non-unbound workqueues apply_wqattrs_commit() updates node_nr_active->max unconditionally. wq->node_nr_active[] is only allocated for unbound workqueues, so guard the call before per-cpu workqueues start using this path. No functional change: only unbound workqueues reach apply_wqattrs_*() today. Signed-off-by: Breno Leitao Signed-off-by: Tejun Heo --- .../devicetree/bindings/ptp/amazon,vmclock.yaml | 46 ++++++ .../devicetree/bindings/ptp/brcm,ptp-dte.txt | 19 +++ Documentation/devicetree/bindings/ptp/fsl,ptp.yaml | 156 +++++++++++++++++++++ .../devicetree/bindings/ptp/nxp,ptp-netc.yaml | 63 +++++++++ .../devicetree/bindings/ptp/ptp-idt82p33.yaml | 45 ++++++ .../devicetree/bindings/ptp/ptp-idtcm.yaml | 69 +++++++++ Documentation/devicetree/bindings/ptp/ptp-ines.txt | 35 +++++ .../devicetree/bindings/ptp/timestamper.txt | 42 ++++++ 8 files changed, 475 insertions(+) create mode 100644 Documentation/devicetree/bindings/ptp/amazon,vmclock.yaml create mode 100644 Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt create mode 100644 Documentation/devicetree/bindings/ptp/fsl,ptp.yaml create mode 100644 Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml create mode 100644 Documentation/devicetree/bindings/ptp/ptp-idt82p33.yaml create mode 100644 Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml create mode 100644 Documentation/devicetree/bindings/ptp/ptp-ines.txt create mode 100644 Documentation/devicetree/bindings/ptp/timestamper.txt (limited to 'Documentation/devicetree/bindings/ptp') diff --git a/Documentation/devicetree/bindings/ptp/amazon,vmclock.yaml b/Documentation/devicetree/bindings/ptp/amazon,vmclock.yaml new file mode 100644 index 000000000..357790df8 --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/amazon,vmclock.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/amazon,vmclock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Virtual Machine Clock + +maintainers: + - David Woodhouse + +description: + The vmclock device provides a precise clock source and allows for + accurate timekeeping across live migration and snapshot/restore + operations. The full specification of the shared data structure is + available at https://uapi-group.org/specifications/specs/vmclock/ + +properties: + compatible: + const: amazon,vmclock + + reg: + description: + Specifies the shared memory region containing the vmclock_abi structure. + maxItems: 1 + + interrupts: + description: + Interrupt used to notify when the contents of the vmclock_abi structure + have been updated. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + ptp@80000000 { + compatible = "amazon,vmclock"; + reg = <0x80000000 0x1000>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt b/Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt new file mode 100644 index 000000000..6b1075ee8 --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/brcm,ptp-dte.txt @@ -0,0 +1,19 @@ +* Broadcom Digital Timing Engine(DTE) based PTP clock + +Required properties: +- compatible: should contain the core compatibility string + and the SoC compatibility string. The SoC + compatibility string is to handle SoC specific + hardware differences. + Core compatibility string: + "brcm,ptp-dte" + SoC compatibility strings: + "brcm,iproc-ptp-dte" - for iproc based SoC's +- reg: address and length of the DTE block's NCO registers + +Example: + +ptp: ptp-dte@180af650 { + compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte"; + reg = <0x180af650 0x10>; +}; diff --git a/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml b/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml new file mode 100644 index 000000000..42ca895f3 --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QorIQ 1588 timer based PTP clock + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - enum: + - fsl,etsec-ptp + - fsl,fman-ptp-timer + - fsl,dpaa2-ptp + - items: + - const: pci1957,ee02 + - const: fsl,enetc-ptp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + fsl,cksel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Timer reference clock source. + + Reference clock source is determined by the value, which is holded + in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the + value, which will be directly written in those bits, that is why, + according to reference manual, the next clock sources can be used: + + For eTSEC, + <0> - external high precision timer reference clock (TSEC_TMR_CLK + input is used for this purpose); + <1> - eTSEC system clock; + <2> - eTSEC1 transmit clock; + <3> - RTC clock input. + + For DPAA FMan, + <0> - external high precision timer reference clock (TMR_1588_CLK) + <1> - MAC system clock (1/2 FMan clock) + <2> - reserved + <3> - RTC clock oscillator + + fsl,tclk-period: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Timer reference clock period in nanoseconds. + + fsl,tmr-prsc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Prescaler, divides the output clock. + + fsl,tmr-add: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Frequency compensation value. + + fsl,tmr-fiper1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Fixed interval period pulse generator. + + fsl,tmr-fiper2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Fixed interval period pulse generator. + + fsl,tmr-fiper3: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Fixed interval period pulse generator. + Supported only on DPAA2 and ENETC hardware. + + fsl,max-adj: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum frequency adjustment in parts per billion. + + These properties set the operational parameters for the PTP + clock. You must choose these carefully for the clock to work right. + Here is how to figure good values: + + TimerOsc = selected reference clock MHz + tclk_period = desired clock period nanoseconds + NominalFreq = 1000 / tclk_period MHz + FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0) + tmr_add = ceil(2^32 / FreqDivRatio) + OutputClock = NominalFreq / tmr_prsc MHz + PulseWidth = 1 / OutputClock microseconds + FiperFreq1 = desired frequency in Hz + FiperDiv1 = 1000000 * OutputClock / FiperFreq1 + tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period + max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1 + + The calculation for tmr_fiper2 is the same as for tmr_fiper1. The + driver expects that tmr_fiper1 will be correctly set to produce a 1 + Pulse Per Second (PPS) signal, since this will be offered to the PPS + subsystem to synchronize the Linux clock. + + When this attribute is not used, the IEEE 1588 timer reference clock + will use the eTSEC system clock (for Gianfar) or the MAC system + clock (for DPAA). + + fsl,extts-fifo: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates hardware + support for the external trigger stamp FIFO + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates the 1588 timer + support for the external trigger stamp FIFO. + IP block is little-endian mode. The default endian mode + is big-endian. + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,enetc-ptp + then: + $ref: /schemas/pci/pci-device.yaml + +additionalProperties: false + +examples: + - | + #include + + phc@24e00 { + compatible = "fsl,etsec-ptp"; + reg = <0x24e00 0xb0>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&ipic>; + fsl,cksel = <1>; + fsl,tclk-period = <10>; + fsl,tmr-prsc = <100>; + fsl,tmr-add = <0x999999a4>; + fsl,tmr-fiper1 = <0x3b9ac9f6>; + fsl,tmr-fiper2 = <0x00018696>; + fsl,max-adj = <659999998>; + }; diff --git a/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml b/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml new file mode 100644 index 000000000..042de9d5a --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/nxp,ptp-netc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP NETC V4 Timer PTP clock + +description: + NETC V4 Timer provides current time with nanosecond resolution, precise + periodic pulse, pulse on timeout (alarm), and time capture on external + pulse support. And it supports time synchronization as required for + IEEE 1588 and IEEE 802.1AS-2020. + +maintainers: + - Wei Fang + - Clark Wang + +properties: + compatible: + enum: + - pci1131,ee02 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + The reference clock of NETC Timer, can be selected between 3 different + clock sources using an integrated hardware mux TMR_CTRL[CK_SEL]. + The "ccm" means the reference clock comes from CCM of SoC. + The "ext" means the reference clock comes from external IO pins. + If not present, indicates that the system clock of NETC IP is selected + as the reference clock. + + clock-names: + enum: + - ccm + - ext + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/pci/pci-device.yaml + +unevaluatedProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + ptp-timer@18,0 { + compatible = "pci1131,ee02"; + reg = <0x00c000 0 0 0 0>; + clocks = <&scmi_clk 18>; + clock-names = "ccm"; + }; + }; diff --git a/Documentation/devicetree/bindings/ptp/ptp-idt82p33.yaml b/Documentation/devicetree/bindings/ptp/ptp-idt82p33.yaml new file mode 100644 index 000000000..51381e4cb --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/ptp-idt82p33.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/ptp-idt82p33.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IDT 82P33 PTP Clock + +description: | + IDT 82P33XXX Synchronization Management Unit (SMU) based PTP clock + +maintainers: + - Min Li + +properties: + compatible: + enum: + - idt,82p33810 + - idt,82p33813 + - idt,82p33814 + - idt,82p33831 + - idt,82p33910 + - idt,82p33913 + - idt,82p33914 + - idt,82p33931 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + phc@51 { + compatible = "idt,82p33810"; + reg = <0x51>; + }; + }; diff --git a/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml b/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml new file mode 100644 index 000000000..7cf32663c --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/ptp-idtcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IDT ClockMatrix (TM) PTP Clock + +maintainers: + - Vincent Cheng + +properties: + compatible: + enum: + # For System Synchronizer + - idt,8a34000 + - idt,8a34001 + - idt,8a34002 + - idt,8a34003 + - idt,8a34004 + - idt,8a34005 + - idt,8a34006 + - idt,8a34007 + - idt,8a34008 + - idt,8a34009 + # For Port Synchronizer + - idt,8a34010 + - idt,8a34011 + - idt,8a34012 + - idt,8a34013 + - idt,8a34014 + - idt,8a34015 + - idt,8a34016 + - idt,8a34017 + - idt,8a34018 + - idt,8a34019 + # For Universal Frequency Translator (UFT) + - idt,8a34040 + - idt,8a34041 + - idt,8a34042 + - idt,8a34043 + - idt,8a34044 + - idt,8a34045 + - idt,8a34046 + - idt,8a34047 + - idt,8a34048 + - idt,8a34049 + + reg: + maxItems: 1 + description: + I2C slave address of the device. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + phc@5b { + compatible = "idt,8a34000"; + reg = <0x5b>; + }; + }; diff --git a/Documentation/devicetree/bindings/ptp/ptp-ines.txt b/Documentation/devicetree/bindings/ptp/ptp-ines.txt new file mode 100644 index 000000000..4c242bd1c --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/ptp-ines.txt @@ -0,0 +1,35 @@ +ZHAW InES PTP time stamping IP core + +The IP core needs two different kinds of nodes. The control node +lives somewhere in the memory map and specifies the address of the +control registers. There can be up to three port handles placed as +attributes of PHY nodes. These associate a particular MII bus with a +port index within the IP core. + +Required properties of the control node: + +- compatible: "ines,ptp-ctrl" +- reg: physical address and size of the register bank + +Required format of the port handle within the PHY node: + +- timestamper: provides control node reference and + the port channel within the IP core + +Example: + + tstamper: timestamper@60000000 { + compatible = "ines,ptp-ctrl"; + reg = <0x60000000 0x80>; + }; + + ethernet@80000000 { + ... + mdio { + ... + ethernet-phy@3 { + ... + timestamper = <&tstamper 0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/ptp/timestamper.txt b/Documentation/devicetree/bindings/ptp/timestamper.txt new file mode 100644 index 000000000..fc550ce4d --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/timestamper.txt @@ -0,0 +1,42 @@ +Time stamps from MII bus snooping devices + +This binding supports non-PHY devices that snoop the MII bus and +provide time stamps. In contrast to PHY time stamping drivers (which +can simply attach their interface directly to the PHY instance), stand +alone MII time stamping drivers use this binding to specify the +connection between the snooping device and a given network interface. + +Non-PHY MII time stamping drivers typically talk to the control +interface over another bus like I2C, SPI, UART, or via a memory mapped +peripheral. This controller device is associated with one or more +time stamping channels, each of which snoops on a MII bus. + +The "timestamper" property lives in a phy node and links a time +stamping channel from the controller device to that phy's MII bus. + +Example: + + tstamper: timestamper@10000000 { + compatible = "ines,ptp-ctrl"; + reg = <0x10000000 0x80>; + }; + + ethernet@20000000 { + mdio { + ethernet-phy@1 { + timestamper = <&tstamper 0>; + }; + }; + }; + + ethernet@30000000 { + mdio { + ethernet-phy@2 { + timestamper = <&tstamper 1>; + }; + }; + }; + +In this example, time stamps from the MII bus attached to phy@1 will +appear on time stamp channel 0 (zero), and those from phy@2 appear on +channel 1. -- cgit v1.3.1